Commit | Line | Data |
---|---|---|
eebf11a0 MCC |
1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
2 | * | |
3 | * This driver supports the memory controllers found on the Intel | |
4 | * processor family Sandy Bridge. | |
5 | * | |
6 | * This file may be distributed under the terms of the | |
7 | * GNU General Public License version 2 only. | |
8 | * | |
9 | * Copyright (c) 2011 by: | |
37e59f87 | 10 | * Mauro Carvalho Chehab |
eebf11a0 MCC |
11 | */ |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/pci_ids.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/edac.h> | |
20 | #include <linux/mmzone.h> | |
eebf11a0 MCC |
21 | #include <linux/smp.h> |
22 | #include <linux/bitmap.h> | |
5b889e37 | 23 | #include <linux/math64.h> |
2c1ea4c7 TL |
24 | #include <linux/mod_devicetable.h> |
25 | #include <asm/cpu_device_id.h> | |
eebf11a0 | 26 | #include <asm/processor.h> |
3d78c9af | 27 | #include <asm/mce.h> |
eebf11a0 MCC |
28 | |
29 | #include "edac_core.h" | |
30 | ||
31 | /* Static vars */ | |
32 | static LIST_HEAD(sbridge_edac_list); | |
eebf11a0 MCC |
33 | |
34 | /* | |
35 | * Alter this version for the module when modifications are made | |
36 | */ | |
7d375bff | 37 | #define SBRIDGE_REVISION " Ver: 1.1.1 " |
eebf11a0 MCC |
38 | #define EDAC_MOD_STR "sbridge_edac" |
39 | ||
40 | /* | |
41 | * Debug macros | |
42 | */ | |
43 | #define sbridge_printk(level, fmt, arg...) \ | |
44 | edac_printk(level, "sbridge", fmt, ##arg) | |
45 | ||
46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ | |
47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) | |
48 | ||
49 | /* | |
50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
51 | */ | |
52 | #define GET_BITFIELD(v, lo, hi) \ | |
10ef6b0d | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
eebf11a0 | 54 | |
eebf11a0 | 55 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
464f1d82 | 56 | static const u32 sbridge_dram_rule[] = { |
eebf11a0 MCC |
57 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
58 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, | |
59 | }; | |
eebf11a0 | 60 | |
4d715a80 AR |
61 | static const u32 ibridge_dram_rule[] = { |
62 | 0x60, 0x68, 0x70, 0x78, 0x80, | |
63 | 0x88, 0x90, 0x98, 0xa0, 0xa8, | |
64 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, | |
65 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, | |
66 | }; | |
eebf11a0 | 67 | |
d0cdf900 JS |
68 | static const u32 knl_dram_rule[] = { |
69 | 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */ | |
70 | 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */ | |
71 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */ | |
72 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */ | |
73 | 0x100, 0x108, 0x110, 0x118, /* 20-23 */ | |
74 | }; | |
75 | ||
eebf11a0 | 76 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) |
50d1bb93 | 77 | #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) |
eebf11a0 | 78 | |
c59f9c06 | 79 | static char *show_dram_attr(u32 attr) |
eebf11a0 | 80 | { |
c59f9c06 | 81 | switch (attr) { |
eebf11a0 MCC |
82 | case 0: |
83 | return "DRAM"; | |
84 | case 1: | |
85 | return "MMCFG"; | |
86 | case 2: | |
87 | return "NXM"; | |
88 | default: | |
89 | return "unknown"; | |
90 | } | |
91 | } | |
92 | ||
ef1ce51e | 93 | static const u32 sbridge_interleave_list[] = { |
eebf11a0 MCC |
94 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
95 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, | |
96 | }; | |
eebf11a0 | 97 | |
4d715a80 AR |
98 | static const u32 ibridge_interleave_list[] = { |
99 | 0x64, 0x6c, 0x74, 0x7c, 0x84, | |
100 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, | |
101 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, | |
102 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, | |
103 | }; | |
104 | ||
d0cdf900 JS |
105 | static const u32 knl_interleave_list[] = { |
106 | 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */ | |
107 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */ | |
108 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */ | |
109 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */ | |
110 | 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */ | |
111 | }; | |
112 | ||
cc311991 AR |
113 | struct interleave_pkg { |
114 | unsigned char start; | |
115 | unsigned char end; | |
116 | }; | |
117 | ||
118 | static const struct interleave_pkg sbridge_interleave_pkg[] = { | |
119 | { 0, 2 }, | |
120 | { 3, 5 }, | |
121 | { 8, 10 }, | |
122 | { 11, 13 }, | |
123 | { 16, 18 }, | |
124 | { 19, 21 }, | |
125 | { 24, 26 }, | |
126 | { 27, 29 }, | |
127 | }; | |
128 | ||
4d715a80 AR |
129 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
130 | { 0, 3 }, | |
131 | { 4, 7 }, | |
132 | { 8, 11 }, | |
133 | { 12, 15 }, | |
134 | { 16, 19 }, | |
135 | { 20, 23 }, | |
136 | { 24, 27 }, | |
137 | { 28, 31 }, | |
138 | }; | |
139 | ||
cc311991 AR |
140 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
141 | int interleave) | |
eebf11a0 | 142 | { |
cc311991 AR |
143 | return GET_BITFIELD(reg, table[interleave].start, |
144 | table[interleave].end); | |
eebf11a0 MCC |
145 | } |
146 | ||
147 | /* Devices 12 Function 7 */ | |
148 | ||
149 | #define TOLM 0x80 | |
d0cdf900 | 150 | #define TOHM 0x84 |
f7cf2a22 | 151 | #define HASWELL_TOLM 0xd0 |
50d1bb93 AR |
152 | #define HASWELL_TOHM_0 0xd4 |
153 | #define HASWELL_TOHM_1 0xd8 | |
d0cdf900 JS |
154 | #define KNL_TOLM 0xd0 |
155 | #define KNL_TOHM_0 0xd4 | |
156 | #define KNL_TOHM_1 0xd8 | |
eebf11a0 MCC |
157 | |
158 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) | |
159 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) | |
160 | ||
161 | /* Device 13 Function 6 */ | |
162 | ||
163 | #define SAD_TARGET 0xf0 | |
164 | ||
165 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) | |
166 | ||
d0cdf900 JS |
167 | #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14) |
168 | ||
eebf11a0 MCC |
169 | #define SAD_CONTROL 0xf4 |
170 | ||
eebf11a0 MCC |
171 | /* Device 14 function 0 */ |
172 | ||
173 | static const u32 tad_dram_rule[] = { | |
174 | 0x40, 0x44, 0x48, 0x4c, | |
175 | 0x50, 0x54, 0x58, 0x5c, | |
176 | 0x60, 0x64, 0x68, 0x6c, | |
177 | }; | |
178 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) | |
179 | ||
180 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) | |
181 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) | |
182 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) | |
183 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) | |
184 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) | |
185 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) | |
186 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) | |
187 | ||
188 | /* Device 15, function 0 */ | |
189 | ||
190 | #define MCMTR 0x7c | |
d0cdf900 | 191 | #define KNL_MCMTR 0x624 |
eebf11a0 MCC |
192 | |
193 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) | |
194 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) | |
195 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) | |
196 | ||
197 | /* Device 15, function 1 */ | |
198 | ||
199 | #define RASENABLES 0xac | |
200 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) | |
201 | ||
202 | /* Device 15, functions 2-5 */ | |
203 | ||
204 | static const int mtr_regs[] = { | |
205 | 0x80, 0x84, 0x88, | |
206 | }; | |
207 | ||
d0cdf900 JS |
208 | static const int knl_mtr_reg = 0xb60; |
209 | ||
eebf11a0 MCC |
210 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) |
211 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) | |
212 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) | |
213 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) | |
214 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) | |
215 | ||
216 | static const u32 tad_ch_nilv_offset[] = { | |
217 | 0x90, 0x94, 0x98, 0x9c, | |
218 | 0xa0, 0xa4, 0xa8, 0xac, | |
219 | 0xb0, 0xb4, 0xb8, 0xbc, | |
220 | }; | |
221 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) | |
222 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) | |
223 | ||
224 | static const u32 rir_way_limit[] = { | |
225 | 0x108, 0x10c, 0x110, 0x114, 0x118, | |
226 | }; | |
227 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) | |
228 | ||
229 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) | |
230 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) | |
eebf11a0 MCC |
231 | |
232 | #define MAX_RIR_WAY 8 | |
233 | ||
234 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { | |
235 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, | |
236 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, | |
237 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, | |
238 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, | |
239 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
240 | }; | |
241 | ||
242 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) | |
243 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) | |
244 | ||
245 | /* Device 16, functions 2-7 */ | |
246 | ||
247 | /* | |
248 | * FIXME: Implement the error count reads directly | |
249 | */ | |
250 | ||
251 | static const u32 correrrcnt[] = { | |
252 | 0x104, 0x108, 0x10c, 0x110, | |
253 | }; | |
254 | ||
255 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) | |
256 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) | |
257 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) | |
258 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) | |
259 | ||
260 | static const u32 correrrthrsld[] = { | |
261 | 0x11c, 0x120, 0x124, 0x128, | |
262 | }; | |
263 | ||
264 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) | |
265 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) | |
266 | ||
267 | ||
268 | /* Device 17, function 0 */ | |
269 | ||
ef1e8d03 | 270 | #define SB_RANK_CFG_A 0x0328 |
eebf11a0 | 271 | |
4d715a80 | 272 | #define IB_RANK_CFG_A 0x0320 |
eebf11a0 | 273 | |
eebf11a0 MCC |
274 | /* |
275 | * sbridge structs | |
276 | */ | |
277 | ||
7d375bff | 278 | #define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */ |
351fc4a9 | 279 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
d0cdf900 JS |
280 | #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */ |
281 | #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */ | |
282 | #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */ | |
351fc4a9 | 283 | #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ |
eebf11a0 | 284 | |
4d715a80 AR |
285 | enum type { |
286 | SANDY_BRIDGE, | |
287 | IVY_BRIDGE, | |
50d1bb93 | 288 | HASWELL, |
1f39581a | 289 | BROADWELL, |
d0cdf900 | 290 | KNIGHTS_LANDING, |
4d715a80 AR |
291 | }; |
292 | ||
fb79a509 | 293 | struct sbridge_pvt; |
eebf11a0 | 294 | struct sbridge_info { |
4d715a80 | 295 | enum type type; |
464f1d82 AR |
296 | u32 mcmtr; |
297 | u32 rankcfgr; | |
298 | u64 (*get_tolm)(struct sbridge_pvt *pvt); | |
299 | u64 (*get_tohm)(struct sbridge_pvt *pvt); | |
b976bcf2 | 300 | u64 (*rir_limit)(u32 reg); |
c59f9c06 JS |
301 | u64 (*sad_limit)(u32 reg); |
302 | u32 (*interleave_mode)(u32 reg); | |
303 | char* (*show_interleave_mode)(u32 reg); | |
304 | u32 (*dram_attr)(u32 reg); | |
464f1d82 | 305 | const u32 *dram_rule; |
ef1ce51e | 306 | const u32 *interleave_list; |
cc311991 | 307 | const struct interleave_pkg *interleave_pkg; |
464f1d82 | 308 | u8 max_sad; |
ef1ce51e | 309 | u8 max_interleave; |
f14d6892 | 310 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
9e375446 | 311 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
12f0721c | 312 | enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); |
50d1bb93 | 313 | struct pci_dev *pci_vtd; |
eebf11a0 MCC |
314 | }; |
315 | ||
316 | struct sbridge_channel { | |
317 | u32 ranks; | |
318 | u32 dimms; | |
319 | }; | |
320 | ||
321 | struct pci_id_descr { | |
c41afdca | 322 | int dev_id; |
eebf11a0 MCC |
323 | int optional; |
324 | }; | |
325 | ||
326 | struct pci_id_table { | |
327 | const struct pci_id_descr *descr; | |
328 | int n_devs; | |
329 | }; | |
330 | ||
331 | struct sbridge_dev { | |
332 | struct list_head list; | |
333 | u8 bus, mc; | |
334 | u8 node_id, source_id; | |
335 | struct pci_dev **pdev; | |
336 | int n_devs; | |
337 | struct mem_ctl_info *mci; | |
338 | }; | |
339 | ||
d0cdf900 JS |
340 | struct knl_pvt { |
341 | struct pci_dev *pci_cha[KNL_MAX_CHAS]; | |
342 | struct pci_dev *pci_channel[KNL_MAX_CHANNELS]; | |
343 | struct pci_dev *pci_mc0; | |
344 | struct pci_dev *pci_mc1; | |
345 | struct pci_dev *pci_mc0_misc; | |
346 | struct pci_dev *pci_mc1_misc; | |
347 | struct pci_dev *pci_mc_info; /* tolm, tohm */ | |
348 | }; | |
349 | ||
eebf11a0 MCC |
350 | struct sbridge_pvt { |
351 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; | |
4d715a80 AR |
352 | struct pci_dev *pci_sad0, *pci_sad1; |
353 | struct pci_dev *pci_ha0, *pci_ha1; | |
354 | struct pci_dev *pci_br0, *pci_br1; | |
50d1bb93 | 355 | struct pci_dev *pci_ha1_ta; |
eebf11a0 MCC |
356 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
357 | ||
358 | struct sbridge_dev *sbridge_dev; | |
359 | ||
360 | struct sbridge_info info; | |
361 | struct sbridge_channel channel[NUM_CHANNELS]; | |
362 | ||
eebf11a0 MCC |
363 | /* Memory type detection */ |
364 | bool is_mirrored, is_lockstep, is_close_pg; | |
ea5dfb5f | 365 | bool is_chan_hash; |
eebf11a0 | 366 | |
eebf11a0 MCC |
367 | /* Memory description */ |
368 | u64 tolm, tohm; | |
d0cdf900 | 369 | struct knl_pvt knl; |
eebf11a0 MCC |
370 | }; |
371 | ||
dbc954dd AR |
372 | #define PCI_DESCR(device_id, opt) \ |
373 | .dev_id = (device_id), \ | |
de4772c6 | 374 | .optional = opt |
eebf11a0 MCC |
375 | |
376 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { | |
377 | /* Processor Home Agent */ | |
dbc954dd | 378 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
eebf11a0 MCC |
379 | |
380 | /* Memory controller */ | |
dbc954dd AR |
381 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
382 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, | |
383 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, | |
384 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, | |
385 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, | |
386 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, | |
387 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, | |
eebf11a0 MCC |
388 | |
389 | /* System Address Decoder */ | |
dbc954dd AR |
390 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
391 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, | |
eebf11a0 MCC |
392 | |
393 | /* Broadcast Registers */ | |
dbc954dd | 394 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
eebf11a0 MCC |
395 | }; |
396 | ||
397 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } | |
398 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { | |
399 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), | |
400 | {0,} /* 0 terminated list. */ | |
401 | }; | |
402 | ||
4d715a80 AR |
403 | /* This changes depending if 1HA or 2HA: |
404 | * 1HA: | |
405 | * 0x0eb8 (17.0) is DDRIO0 | |
406 | * 2HA: | |
407 | * 0x0ebc (17.4) is DDRIO0 | |
408 | */ | |
409 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 | |
410 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc | |
411 | ||
412 | /* pci ids */ | |
413 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 | |
414 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 | |
415 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 | |
416 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa | |
417 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab | |
418 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac | |
419 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead | |
420 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 | |
421 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 | |
422 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca | |
423 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 | |
424 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 | |
425 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 | |
426 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a | |
427 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b | |
7d375bff TL |
428 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c |
429 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d | |
4d715a80 AR |
430 | |
431 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { | |
432 | /* Processor Home Agent */ | |
dbc954dd | 433 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, |
4d715a80 AR |
434 | |
435 | /* Memory controller */ | |
dbc954dd AR |
436 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, |
437 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, | |
438 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, | |
439 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, | |
440 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, | |
441 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, | |
4d715a80 AR |
442 | |
443 | /* System Address Decoder */ | |
dbc954dd | 444 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, |
4d715a80 AR |
445 | |
446 | /* Broadcast Registers */ | |
dbc954dd AR |
447 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, |
448 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, | |
4d715a80 AR |
449 | |
450 | /* Optional, mode 2HA */ | |
dbc954dd | 451 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, |
4d715a80 | 452 | #if 0 |
dbc954dd AR |
453 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, |
454 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, | |
4d715a80 | 455 | #endif |
dbc954dd AR |
456 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, |
457 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, | |
7d375bff TL |
458 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) }, |
459 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) }, | |
4d715a80 | 460 | |
dbc954dd AR |
461 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, |
462 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, | |
4d715a80 AR |
463 | }; |
464 | ||
465 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { | |
466 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), | |
467 | {0,} /* 0 terminated list. */ | |
468 | }; | |
469 | ||
50d1bb93 AR |
470 | /* Haswell support */ |
471 | /* EN processor: | |
472 | * - 1 IMC | |
473 | * - 3 DDR3 channels, 2 DPC per channel | |
474 | * EP processor: | |
475 | * - 1 or 2 IMC | |
476 | * - 4 DDR4 channels, 3 DPC per channel | |
477 | * EP 4S processor: | |
478 | * - 2 IMC | |
479 | * - 4 DDR4 channels, 3 DPC per channel | |
480 | * EX processor: | |
481 | * - 2 IMC | |
482 | * - each IMC interfaces with a SMI 2 channel | |
483 | * - each SMI channel interfaces with a scalable memory buffer | |
484 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
485 | */ | |
1f39581a | 486 | #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ |
50d1bb93 AR |
487 | #define HASWELL_HASYSDEFEATURE2 0x84 |
488 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 | |
489 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 | |
490 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 | |
491 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 | |
492 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 | |
493 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 | |
494 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 | |
495 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc | |
496 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd | |
497 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa | |
498 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab | |
499 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac | |
500 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad | |
501 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a | |
502 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b | |
503 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c | |
504 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d | |
505 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd | |
7179385a AR |
506 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf |
507 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9 | |
508 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb | |
50d1bb93 AR |
509 | static const struct pci_id_descr pci_dev_descr_haswell[] = { |
510 | /* first item must be the HA */ | |
511 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, | |
512 | ||
513 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, | |
514 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, | |
515 | ||
516 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, | |
517 | ||
518 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, | |
519 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, | |
520 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, | |
521 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, | |
522 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, | |
523 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, | |
524 | ||
525 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, | |
7179385a AR |
526 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) }, |
527 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) }, | |
528 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) }, | |
50d1bb93 AR |
529 | |
530 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, | |
531 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, | |
532 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, | |
533 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, | |
534 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) }, | |
535 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) }, | |
536 | }; | |
537 | ||
538 | static const struct pci_id_table pci_dev_descr_haswell_table[] = { | |
539 | PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell), | |
540 | {0,} /* 0 terminated list. */ | |
541 | }; | |
542 | ||
d0cdf900 JS |
543 | /* Knight's Landing Support */ |
544 | /* | |
545 | * KNL's memory channels are swizzled between memory controllers. | |
546 | * MC0 is mapped to CH3,5,6 and MC1 is mapped to CH0,1,2 | |
547 | */ | |
548 | #define knl_channel_remap(channel) ((channel + 3) % 6) | |
549 | ||
550 | /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ | |
551 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840 | |
552 | /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ | |
553 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL 0x7843 | |
554 | /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ | |
555 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844 | |
556 | /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ | |
557 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a | |
558 | /* SAD target - 1-29-1 (1 of these) */ | |
559 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b | |
560 | /* Caching / Home Agent */ | |
561 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c | |
562 | /* Device with TOLM and TOHM, 0-5-0 (1 of these) */ | |
563 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810 | |
564 | ||
565 | /* | |
566 | * KNL differs from SB, IB, and Haswell in that it has multiple | |
567 | * instances of the same device with the same device ID, so we handle that | |
568 | * by creating as many copies in the table as we expect to find. | |
569 | * (Like device ID must be grouped together.) | |
570 | */ | |
571 | ||
572 | static const struct pci_id_descr pci_dev_descr_knl[] = { | |
573 | [0] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) }, | |
574 | [1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) }, | |
575 | [2 ... 3] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)}, | |
576 | [4 ... 41] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) }, | |
577 | [42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) }, | |
578 | [48] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) }, | |
579 | [49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) }, | |
580 | }; | |
581 | ||
582 | static const struct pci_id_table pci_dev_descr_knl_table[] = { | |
583 | PCI_ID_TABLE_ENTRY(pci_dev_descr_knl), | |
584 | {0,} | |
585 | }; | |
586 | ||
1f39581a TL |
587 | /* |
588 | * Broadwell support | |
589 | * | |
590 | * DE processor: | |
591 | * - 1 IMC | |
592 | * - 2 DDR3 channels, 2 DPC per channel | |
fa2ce64f TL |
593 | * EP processor: |
594 | * - 1 or 2 IMC | |
595 | * - 4 DDR4 channels, 3 DPC per channel | |
596 | * EP 4S processor: | |
597 | * - 2 IMC | |
598 | * - 4 DDR4 channels, 3 DPC per channel | |
599 | * EX processor: | |
600 | * - 2 IMC | |
601 | * - each IMC interfaces with a SMI 2 channel | |
602 | * - each SMI channel interfaces with a scalable memory buffer | |
603 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
1f39581a TL |
604 | */ |
605 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 | |
606 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 | |
fa2ce64f | 607 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 |
1f39581a TL |
608 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 |
609 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71 | |
fa2ce64f TL |
610 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 |
611 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79 | |
1f39581a TL |
612 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc |
613 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd | |
614 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa | |
615 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab | |
616 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac | |
617 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad | |
fa2ce64f TL |
618 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a |
619 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b | |
620 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c | |
621 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d | |
1f39581a TL |
622 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf |
623 | ||
624 | static const struct pci_id_descr pci_dev_descr_broadwell[] = { | |
625 | /* first item must be the HA */ | |
626 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) }, | |
627 | ||
628 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) }, | |
629 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) }, | |
630 | ||
fa2ce64f TL |
631 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) }, |
632 | ||
1f39581a TL |
633 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) }, |
634 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) }, | |
635 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) }, | |
636 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) }, | |
fa2ce64f TL |
637 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) }, |
638 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) }, | |
639 | ||
1f39581a | 640 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) }, |
fa2ce64f TL |
641 | |
642 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) }, | |
643 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) }, | |
644 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) }, | |
645 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) }, | |
646 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) }, | |
647 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) }, | |
1f39581a TL |
648 | }; |
649 | ||
650 | static const struct pci_id_table pci_dev_descr_broadwell_table[] = { | |
651 | PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell), | |
652 | {0,} /* 0 terminated list. */ | |
653 | }; | |
654 | ||
eebf11a0 MCC |
655 | |
656 | /**************************************************************************** | |
15ed103a | 657 | Ancillary status routines |
eebf11a0 MCC |
658 | ****************************************************************************/ |
659 | ||
50d1bb93 | 660 | static inline int numrank(enum type type, u32 mtr) |
eebf11a0 MCC |
661 | { |
662 | int ranks = (1 << RANK_CNT_BITS(mtr)); | |
50d1bb93 AR |
663 | int max = 4; |
664 | ||
d0cdf900 | 665 | if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING) |
50d1bb93 | 666 | max = 8; |
eebf11a0 | 667 | |
50d1bb93 AR |
668 | if (ranks > max) { |
669 | edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", | |
670 | ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); | |
eebf11a0 MCC |
671 | return -EINVAL; |
672 | } | |
673 | ||
674 | return ranks; | |
675 | } | |
676 | ||
677 | static inline int numrow(u32 mtr) | |
678 | { | |
679 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | |
680 | ||
681 | if (rows < 13 || rows > 18) { | |
956b9ba1 JP |
682 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
683 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
684 | return -EINVAL; |
685 | } | |
686 | ||
687 | return 1 << rows; | |
688 | } | |
689 | ||
690 | static inline int numcol(u32 mtr) | |
691 | { | |
692 | int cols = (COL_WIDTH_BITS(mtr) + 10); | |
693 | ||
694 | if (cols > 12) { | |
956b9ba1 JP |
695 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
696 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
697 | return -EINVAL; |
698 | } | |
699 | ||
700 | return 1 << cols; | |
701 | } | |
702 | ||
c1979ba2 | 703 | static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus) |
eebf11a0 MCC |
704 | { |
705 | struct sbridge_dev *sbridge_dev; | |
706 | ||
c1979ba2 JS |
707 | /* |
708 | * If we have devices scattered across several busses that pertain | |
709 | * to the same memory controller, we'll lump them all together. | |
710 | */ | |
711 | if (multi_bus) { | |
712 | return list_first_entry_or_null(&sbridge_edac_list, | |
713 | struct sbridge_dev, list); | |
714 | } | |
715 | ||
eebf11a0 MCC |
716 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
717 | if (sbridge_dev->bus == bus) | |
718 | return sbridge_dev; | |
719 | } | |
720 | ||
721 | return NULL; | |
722 | } | |
723 | ||
724 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, | |
725 | const struct pci_id_table *table) | |
726 | { | |
727 | struct sbridge_dev *sbridge_dev; | |
728 | ||
729 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); | |
730 | if (!sbridge_dev) | |
731 | return NULL; | |
732 | ||
733 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, | |
734 | GFP_KERNEL); | |
735 | if (!sbridge_dev->pdev) { | |
736 | kfree(sbridge_dev); | |
737 | return NULL; | |
738 | } | |
739 | ||
740 | sbridge_dev->bus = bus; | |
741 | sbridge_dev->n_devs = table->n_devs; | |
742 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); | |
743 | ||
744 | return sbridge_dev; | |
745 | } | |
746 | ||
747 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) | |
748 | { | |
749 | list_del(&sbridge_dev->list); | |
750 | kfree(sbridge_dev->pdev); | |
751 | kfree(sbridge_dev); | |
752 | } | |
753 | ||
fb79a509 AR |
754 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
755 | { | |
756 | u32 reg; | |
757 | ||
758 | /* Address range is 32:28 */ | |
759 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); | |
760 | return GET_TOLM(reg); | |
761 | } | |
762 | ||
8fd6a43a AR |
763 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
764 | { | |
765 | u32 reg; | |
766 | ||
767 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); | |
768 | return GET_TOHM(reg); | |
769 | } | |
770 | ||
4d715a80 AR |
771 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
772 | { | |
773 | u32 reg; | |
774 | ||
775 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); | |
776 | ||
777 | return GET_TOLM(reg); | |
778 | } | |
779 | ||
780 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) | |
781 | { | |
782 | u32 reg; | |
783 | ||
784 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); | |
785 | ||
786 | return GET_TOHM(reg); | |
787 | } | |
788 | ||
b976bcf2 AR |
789 | static u64 rir_limit(u32 reg) |
790 | { | |
791 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; | |
792 | } | |
793 | ||
c59f9c06 JS |
794 | static u64 sad_limit(u32 reg) |
795 | { | |
796 | return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; | |
797 | } | |
798 | ||
799 | static u32 interleave_mode(u32 reg) | |
800 | { | |
801 | return GET_BITFIELD(reg, 1, 1); | |
802 | } | |
803 | ||
804 | char *show_interleave_mode(u32 reg) | |
805 | { | |
806 | return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]"; | |
807 | } | |
808 | ||
809 | static u32 dram_attr(u32 reg) | |
810 | { | |
811 | return GET_BITFIELD(reg, 2, 3); | |
812 | } | |
813 | ||
d0cdf900 JS |
814 | static u64 knl_sad_limit(u32 reg) |
815 | { | |
816 | return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff; | |
817 | } | |
818 | ||
819 | static u32 knl_interleave_mode(u32 reg) | |
820 | { | |
821 | return GET_BITFIELD(reg, 1, 2); | |
822 | } | |
823 | ||
824 | static char *knl_show_interleave_mode(u32 reg) | |
825 | { | |
826 | char *s; | |
827 | ||
828 | switch (knl_interleave_mode(reg)) { | |
829 | case 0: | |
830 | s = "use address bits [8:6]"; | |
831 | break; | |
832 | case 1: | |
833 | s = "use address bits [10:8]"; | |
834 | break; | |
835 | case 2: | |
836 | s = "use address bits [14:12]"; | |
837 | break; | |
838 | case 3: | |
839 | s = "use address bits [32:30]"; | |
840 | break; | |
841 | default: | |
842 | WARN_ON(1); | |
843 | break; | |
844 | } | |
845 | ||
846 | return s; | |
847 | } | |
848 | ||
849 | static u32 dram_attr_knl(u32 reg) | |
850 | { | |
851 | return GET_BITFIELD(reg, 3, 4); | |
852 | } | |
853 | ||
854 | ||
9e375446 AR |
855 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
856 | { | |
857 | u32 reg; | |
858 | enum mem_type mtype; | |
859 | ||
860 | if (pvt->pci_ddrio) { | |
861 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, | |
862 | ®); | |
863 | if (GET_BITFIELD(reg, 11, 11)) | |
864 | /* FIXME: Can also be LRDIMM */ | |
865 | mtype = MEM_RDDR3; | |
866 | else | |
867 | mtype = MEM_DDR3; | |
868 | } else | |
869 | mtype = MEM_UNKNOWN; | |
870 | ||
871 | return mtype; | |
872 | } | |
873 | ||
50d1bb93 AR |
874 | static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) |
875 | { | |
876 | u32 reg; | |
877 | bool registered = false; | |
878 | enum mem_type mtype = MEM_UNKNOWN; | |
879 | ||
880 | if (!pvt->pci_ddrio) | |
881 | goto out; | |
882 | ||
883 | pci_read_config_dword(pvt->pci_ddrio, | |
884 | HASWELL_DDRCRCLKCONTROLS, ®); | |
885 | /* Is_Rdimm */ | |
886 | if (GET_BITFIELD(reg, 16, 16)) | |
887 | registered = true; | |
888 | ||
889 | pci_read_config_dword(pvt->pci_ta, MCMTR, ®); | |
890 | if (GET_BITFIELD(reg, 14, 14)) { | |
891 | if (registered) | |
892 | mtype = MEM_RDDR4; | |
893 | else | |
894 | mtype = MEM_DDR4; | |
895 | } else { | |
896 | if (registered) | |
897 | mtype = MEM_RDDR3; | |
898 | else | |
899 | mtype = MEM_DDR3; | |
900 | } | |
901 | ||
902 | out: | |
903 | return mtype; | |
904 | } | |
905 | ||
45f4d3ab HC |
906 | static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) |
907 | { | |
908 | /* for KNL value is fixed */ | |
909 | return DEV_X16; | |
910 | } | |
911 | ||
12f0721c AR |
912 | static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) |
913 | { | |
914 | /* there's no way to figure out */ | |
915 | return DEV_UNKNOWN; | |
916 | } | |
917 | ||
918 | static enum dev_type __ibridge_get_width(u32 mtr) | |
919 | { | |
920 | enum dev_type type; | |
921 | ||
922 | switch (mtr) { | |
923 | case 3: | |
924 | type = DEV_UNKNOWN; | |
925 | break; | |
926 | case 2: | |
927 | type = DEV_X16; | |
928 | break; | |
929 | case 1: | |
930 | type = DEV_X8; | |
931 | break; | |
932 | case 0: | |
933 | type = DEV_X4; | |
934 | break; | |
935 | } | |
936 | ||
937 | return type; | |
938 | } | |
939 | ||
940 | static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) | |
941 | { | |
942 | /* | |
943 | * ddr3_width on the documentation but also valid for DDR4 on | |
944 | * Haswell | |
945 | */ | |
946 | return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); | |
947 | } | |
948 | ||
949 | static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) | |
950 | { | |
951 | /* ddr3_width on the documentation but also valid for DDR4 */ | |
952 | return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); | |
953 | } | |
954 | ||
d0cdf900 JS |
955 | static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) |
956 | { | |
957 | /* DDR4 RDIMMS and LRDIMMS are supported */ | |
958 | return MEM_RDDR4; | |
959 | } | |
960 | ||
f14d6892 AR |
961 | static u8 get_node_id(struct sbridge_pvt *pvt) |
962 | { | |
963 | u32 reg; | |
964 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); | |
965 | return GET_BITFIELD(reg, 0, 2); | |
966 | } | |
967 | ||
50d1bb93 AR |
968 | static u8 haswell_get_node_id(struct sbridge_pvt *pvt) |
969 | { | |
970 | u32 reg; | |
971 | ||
972 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
973 | return GET_BITFIELD(reg, 0, 3); | |
974 | } | |
975 | ||
d0cdf900 JS |
976 | static u8 knl_get_node_id(struct sbridge_pvt *pvt) |
977 | { | |
978 | u32 reg; | |
979 | ||
980 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
981 | return GET_BITFIELD(reg, 0, 2); | |
982 | } | |
983 | ||
984 | ||
50d1bb93 AR |
985 | static u64 haswell_get_tolm(struct sbridge_pvt *pvt) |
986 | { | |
987 | u32 reg; | |
988 | ||
f7cf2a22 TL |
989 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); |
990 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; | |
50d1bb93 AR |
991 | } |
992 | ||
993 | static u64 haswell_get_tohm(struct sbridge_pvt *pvt) | |
994 | { | |
995 | u64 rc; | |
996 | u32 reg; | |
997 | ||
998 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); | |
999 | rc = GET_BITFIELD(reg, 26, 31); | |
1000 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); | |
1001 | rc = ((reg << 6) | rc) << 26; | |
1002 | ||
1003 | return rc | 0x1ffffff; | |
1004 | } | |
1005 | ||
d0cdf900 JS |
1006 | static u64 knl_get_tolm(struct sbridge_pvt *pvt) |
1007 | { | |
1008 | u32 reg; | |
1009 | ||
1010 | pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); | |
1011 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; | |
1012 | } | |
1013 | ||
1014 | static u64 knl_get_tohm(struct sbridge_pvt *pvt) | |
1015 | { | |
1016 | u64 rc; | |
1017 | u32 reg_lo, reg_hi; | |
1018 | ||
1019 | pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); | |
1020 | pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); | |
1021 | rc = ((u64)reg_hi << 32) | reg_lo; | |
1022 | return rc | 0x3ffffff; | |
1023 | } | |
1024 | ||
1025 | ||
50d1bb93 AR |
1026 | static u64 haswell_rir_limit(u32 reg) |
1027 | { | |
1028 | return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; | |
1029 | } | |
1030 | ||
4d715a80 AR |
1031 | static inline u8 sad_pkg_socket(u8 pkg) |
1032 | { | |
1033 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ | |
2ff3a308 | 1034 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
4d715a80 AR |
1035 | } |
1036 | ||
1037 | static inline u8 sad_pkg_ha(u8 pkg) | |
1038 | { | |
1039 | return (pkg >> 2) & 0x1; | |
1040 | } | |
1041 | ||
ea5dfb5f TL |
1042 | static int haswell_chan_hash(int idx, u64 addr) |
1043 | { | |
1044 | int i; | |
1045 | ||
1046 | /* | |
1047 | * XOR even bits from 12:26 to bit0 of idx, | |
1048 | * odd bits from 13:27 to bit1 | |
1049 | */ | |
1050 | for (i = 12; i < 28; i += 2) | |
1051 | idx ^= (addr >> i) & 3; | |
1052 | ||
1053 | return idx; | |
1054 | } | |
1055 | ||
eebf11a0 MCC |
1056 | /**************************************************************************** |
1057 | Memory check routines | |
1058 | ****************************************************************************/ | |
dbc954dd | 1059 | static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) |
eebf11a0 | 1060 | { |
dbc954dd | 1061 | struct pci_dev *pdev = NULL; |
eebf11a0 | 1062 | |
dbc954dd AR |
1063 | do { |
1064 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); | |
1065 | if (pdev && pdev->bus->number == bus) | |
1066 | break; | |
1067 | } while (pdev); | |
eebf11a0 | 1068 | |
dbc954dd | 1069 | return pdev; |
eebf11a0 MCC |
1070 | } |
1071 | ||
1072 | /** | |
c36e3e77 | 1073 | * check_if_ecc_is_active() - Checks if ECC is active |
50d1bb93 AR |
1074 | * @bus: Device bus |
1075 | * @type: Memory controller type | |
1076 | * returns: 0 in case ECC is active, -ENODEV if it can't be determined or | |
1077 | * disabled | |
eebf11a0 | 1078 | */ |
dbc954dd | 1079 | static int check_if_ecc_is_active(const u8 bus, enum type type) |
eebf11a0 MCC |
1080 | { |
1081 | struct pci_dev *pdev = NULL; | |
dbc954dd | 1082 | u32 mcmtr, id; |
eebf11a0 | 1083 | |
1f39581a TL |
1084 | switch (type) { |
1085 | case IVY_BRIDGE: | |
dbc954dd | 1086 | id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; |
1f39581a TL |
1087 | break; |
1088 | case HASWELL: | |
50d1bb93 | 1089 | id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA; |
1f39581a TL |
1090 | break; |
1091 | case SANDY_BRIDGE: | |
dbc954dd | 1092 | id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; |
1f39581a TL |
1093 | break; |
1094 | case BROADWELL: | |
1095 | id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA; | |
1096 | break; | |
d0cdf900 JS |
1097 | case KNIGHTS_LANDING: |
1098 | /* | |
1099 | * KNL doesn't group things by bus the same way | |
1100 | * SB/IB/Haswell does. | |
1101 | */ | |
1102 | id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA; | |
1103 | break; | |
1f39581a TL |
1104 | default: |
1105 | return -ENODEV; | |
1106 | } | |
dbc954dd | 1107 | |
d0cdf900 JS |
1108 | if (type != KNIGHTS_LANDING) |
1109 | pdev = get_pdev_same_bus(bus, id); | |
1110 | else | |
1111 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0); | |
1112 | ||
eebf11a0 MCC |
1113 | if (!pdev) { |
1114 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " | |
dbc954dd AR |
1115 | "%04x:%04x! on bus %02d\n", |
1116 | PCI_VENDOR_ID_INTEL, id, bus); | |
eebf11a0 MCC |
1117 | return -ENODEV; |
1118 | } | |
1119 | ||
d0cdf900 JS |
1120 | pci_read_config_dword(pdev, |
1121 | type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr); | |
eebf11a0 MCC |
1122 | if (!IS_ECC_ENABLED(mcmtr)) { |
1123 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); | |
1124 | return -ENODEV; | |
1125 | } | |
eebf11a0 MCC |
1126 | return 0; |
1127 | } | |
1128 | ||
d0cdf900 JS |
1129 | /* Low bits of TAD limit, and some metadata. */ |
1130 | static const u32 knl_tad_dram_limit_lo[] = { | |
1131 | 0x400, 0x500, 0x600, 0x700, | |
1132 | 0x800, 0x900, 0xa00, 0xb00, | |
1133 | }; | |
1134 | ||
1135 | /* Low bits of TAD offset. */ | |
1136 | static const u32 knl_tad_dram_offset_lo[] = { | |
1137 | 0x404, 0x504, 0x604, 0x704, | |
1138 | 0x804, 0x904, 0xa04, 0xb04, | |
1139 | }; | |
1140 | ||
1141 | /* High 16 bits of TAD limit and offset. */ | |
1142 | static const u32 knl_tad_dram_hi[] = { | |
1143 | 0x408, 0x508, 0x608, 0x708, | |
1144 | 0x808, 0x908, 0xa08, 0xb08, | |
1145 | }; | |
1146 | ||
1147 | /* Number of ways a tad entry is interleaved. */ | |
1148 | static const u32 knl_tad_ways[] = { | |
1149 | 8, 6, 4, 3, 2, 1, | |
1150 | }; | |
1151 | ||
1152 | /* | |
1153 | * Retrieve the n'th Target Address Decode table entry | |
1154 | * from the memory controller's TAD table. | |
1155 | * | |
1156 | * @pvt: driver private data | |
1157 | * @entry: which entry you want to retrieve | |
1158 | * @mc: which memory controller (0 or 1) | |
1159 | * @offset: output tad range offset | |
1160 | * @limit: output address of first byte above tad range | |
1161 | * @ways: output number of interleave ways | |
1162 | * | |
1163 | * The offset value has curious semantics. It's a sort of running total | |
1164 | * of the sizes of all the memory regions that aren't mapped in this | |
1165 | * tad table. | |
1166 | */ | |
1167 | static int knl_get_tad(const struct sbridge_pvt *pvt, | |
1168 | const int entry, | |
1169 | const int mc, | |
1170 | u64 *offset, | |
1171 | u64 *limit, | |
1172 | int *ways) | |
1173 | { | |
1174 | u32 reg_limit_lo, reg_offset_lo, reg_hi; | |
1175 | struct pci_dev *pci_mc; | |
1176 | int way_id; | |
1177 | ||
1178 | switch (mc) { | |
1179 | case 0: | |
1180 | pci_mc = pvt->knl.pci_mc0; | |
1181 | break; | |
1182 | case 1: | |
1183 | pci_mc = pvt->knl.pci_mc1; | |
1184 | break; | |
1185 | default: | |
1186 | WARN_ON(1); | |
1187 | return -EINVAL; | |
1188 | } | |
1189 | ||
1190 | pci_read_config_dword(pci_mc, | |
1191 | knl_tad_dram_limit_lo[entry], ®_limit_lo); | |
1192 | pci_read_config_dword(pci_mc, | |
1193 | knl_tad_dram_offset_lo[entry], ®_offset_lo); | |
1194 | pci_read_config_dword(pci_mc, | |
1195 | knl_tad_dram_hi[entry], ®_hi); | |
1196 | ||
1197 | /* Is this TAD entry enabled? */ | |
1198 | if (!GET_BITFIELD(reg_limit_lo, 0, 0)) | |
1199 | return -ENODEV; | |
1200 | ||
1201 | way_id = GET_BITFIELD(reg_limit_lo, 3, 5); | |
1202 | ||
1203 | if (way_id < ARRAY_SIZE(knl_tad_ways)) { | |
1204 | *ways = knl_tad_ways[way_id]; | |
1205 | } else { | |
1206 | *ways = 0; | |
1207 | sbridge_printk(KERN_ERR, | |
1208 | "Unexpected value %d in mc_tad_limit_lo wayness field\n", | |
1209 | way_id); | |
1210 | return -ENODEV; | |
1211 | } | |
1212 | ||
1213 | /* | |
1214 | * The least significant 6 bits of base and limit are truncated. | |
1215 | * For limit, we fill the missing bits with 1s. | |
1216 | */ | |
1217 | *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) | | |
1218 | ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32); | |
1219 | *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 | | |
1220 | ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32); | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | /* Determine which memory controller is responsible for a given channel. */ | |
1226 | static int knl_channel_mc(int channel) | |
1227 | { | |
1228 | WARN_ON(channel < 0 || channel >= 6); | |
1229 | ||
1230 | return channel < 3 ? 1 : 0; | |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * Get the Nth entry from EDC_ROUTE_TABLE register. | |
1235 | * (This is the per-tile mapping of logical interleave targets to | |
1236 | * physical EDC modules.) | |
1237 | * | |
1238 | * entry 0: 0:2 | |
1239 | * 1: 3:5 | |
1240 | * 2: 6:8 | |
1241 | * 3: 9:11 | |
1242 | * 4: 12:14 | |
1243 | * 5: 15:17 | |
1244 | * 6: 18:20 | |
1245 | * 7: 21:23 | |
1246 | * reserved: 24:31 | |
1247 | */ | |
1248 | static u32 knl_get_edc_route(int entry, u32 reg) | |
1249 | { | |
1250 | WARN_ON(entry >= KNL_MAX_EDCS); | |
1251 | return GET_BITFIELD(reg, entry*3, (entry*3)+2); | |
1252 | } | |
1253 | ||
1254 | /* | |
1255 | * Get the Nth entry from MC_ROUTE_TABLE register. | |
1256 | * (This is the per-tile mapping of logical interleave targets to | |
1257 | * physical DRAM channels modules.) | |
1258 | * | |
1259 | * entry 0: mc 0:2 channel 18:19 | |
1260 | * 1: mc 3:5 channel 20:21 | |
1261 | * 2: mc 6:8 channel 22:23 | |
1262 | * 3: mc 9:11 channel 24:25 | |
1263 | * 4: mc 12:14 channel 26:27 | |
1264 | * 5: mc 15:17 channel 28:29 | |
1265 | * reserved: 30:31 | |
1266 | * | |
1267 | * Though we have 3 bits to identify the MC, we should only see | |
1268 | * the values 0 or 1. | |
1269 | */ | |
1270 | ||
1271 | static u32 knl_get_mc_route(int entry, u32 reg) | |
1272 | { | |
1273 | int mc, chan; | |
1274 | ||
1275 | WARN_ON(entry >= KNL_MAX_CHANNELS); | |
1276 | ||
1277 | mc = GET_BITFIELD(reg, entry*3, (entry*3)+2); | |
1278 | chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1); | |
1279 | ||
1280 | return knl_channel_remap(mc*3 + chan); | |
1281 | } | |
1282 | ||
1283 | /* | |
1284 | * Render the EDC_ROUTE register in human-readable form. | |
1285 | * Output string s should be at least KNL_MAX_EDCS*2 bytes. | |
1286 | */ | |
1287 | static void knl_show_edc_route(u32 reg, char *s) | |
1288 | { | |
1289 | int i; | |
1290 | ||
1291 | for (i = 0; i < KNL_MAX_EDCS; i++) { | |
1292 | s[i*2] = knl_get_edc_route(i, reg) + '0'; | |
1293 | s[i*2+1] = '-'; | |
1294 | } | |
1295 | ||
1296 | s[KNL_MAX_EDCS*2 - 1] = '\0'; | |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * Render the MC_ROUTE register in human-readable form. | |
1301 | * Output string s should be at least KNL_MAX_CHANNELS*2 bytes. | |
1302 | */ | |
1303 | static void knl_show_mc_route(u32 reg, char *s) | |
1304 | { | |
1305 | int i; | |
1306 | ||
1307 | for (i = 0; i < KNL_MAX_CHANNELS; i++) { | |
1308 | s[i*2] = knl_get_mc_route(i, reg) + '0'; | |
1309 | s[i*2+1] = '-'; | |
1310 | } | |
1311 | ||
1312 | s[KNL_MAX_CHANNELS*2 - 1] = '\0'; | |
1313 | } | |
1314 | ||
1315 | #define KNL_EDC_ROUTE 0xb8 | |
1316 | #define KNL_MC_ROUTE 0xb4 | |
1317 | ||
1318 | /* Is this dram rule backed by regular DRAM in flat mode? */ | |
1319 | #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29) | |
1320 | ||
1321 | /* Is this dram rule cached? */ | |
1322 | #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) | |
1323 | ||
1324 | /* Is this rule backed by edc ? */ | |
1325 | #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29) | |
1326 | ||
1327 | /* Is this rule backed by DRAM, cacheable in EDRAM? */ | |
1328 | #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) | |
1329 | ||
1330 | /* Is this rule mod3? */ | |
1331 | #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27) | |
1332 | ||
1333 | /* | |
1334 | * Figure out how big our RAM modules are. | |
1335 | * | |
1336 | * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we | |
1337 | * have to figure this out from the SAD rules, interleave lists, route tables, | |
1338 | * and TAD rules. | |
1339 | * | |
1340 | * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to | |
1341 | * inspect the TAD rules to figure out how large the SAD regions really are. | |
1342 | * | |
1343 | * When we know the real size of a SAD region and how many ways it's | |
1344 | * interleaved, we know the individual contribution of each channel to | |
1345 | * TAD is size/ways. | |
1346 | * | |
1347 | * Finally, we have to check whether each channel participates in each SAD | |
1348 | * region. | |
1349 | * | |
1350 | * Fortunately, KNL only supports one DIMM per channel, so once we know how | |
1351 | * much memory the channel uses, we know the DIMM is at least that large. | |
1352 | * (The BIOS might possibly choose not to map all available memory, in which | |
1353 | * case we will underreport the size of the DIMM.) | |
1354 | * | |
1355 | * In theory, we could try to determine the EDC sizes as well, but that would | |
1356 | * only work in flat mode, not in cache mode. | |
1357 | * | |
1358 | * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS | |
1359 | * elements) | |
1360 | */ | |
1361 | static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) | |
1362 | { | |
1363 | u64 sad_base, sad_size, sad_limit = 0; | |
1364 | u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace; | |
1365 | int sad_rule = 0; | |
1366 | int tad_rule = 0; | |
1367 | int intrlv_ways, tad_ways; | |
1368 | u32 first_pkg, pkg; | |
1369 | int i; | |
1370 | u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */ | |
1371 | u32 dram_rule, interleave_reg; | |
1372 | u32 mc_route_reg[KNL_MAX_CHAS]; | |
1373 | u32 edc_route_reg[KNL_MAX_CHAS]; | |
1374 | int edram_only; | |
1375 | char edc_route_string[KNL_MAX_EDCS*2]; | |
1376 | char mc_route_string[KNL_MAX_CHANNELS*2]; | |
1377 | int cur_reg_start; | |
1378 | int mc; | |
1379 | int channel; | |
1380 | int way; | |
1381 | int participants[KNL_MAX_CHANNELS]; | |
1382 | int participant_count = 0; | |
1383 | ||
1384 | for (i = 0; i < KNL_MAX_CHANNELS; i++) | |
1385 | mc_sizes[i] = 0; | |
1386 | ||
1387 | /* Read the EDC route table in each CHA. */ | |
1388 | cur_reg_start = 0; | |
1389 | for (i = 0; i < KNL_MAX_CHAS; i++) { | |
1390 | pci_read_config_dword(pvt->knl.pci_cha[i], | |
1391 | KNL_EDC_ROUTE, &edc_route_reg[i]); | |
1392 | ||
1393 | if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { | |
1394 | knl_show_edc_route(edc_route_reg[i-1], | |
1395 | edc_route_string); | |
1396 | if (cur_reg_start == i-1) | |
1397 | edac_dbg(0, "edc route table for CHA %d: %s\n", | |
1398 | cur_reg_start, edc_route_string); | |
1399 | else | |
1400 | edac_dbg(0, "edc route table for CHA %d-%d: %s\n", | |
1401 | cur_reg_start, i-1, edc_route_string); | |
1402 | cur_reg_start = i; | |
1403 | } | |
1404 | } | |
1405 | knl_show_edc_route(edc_route_reg[i-1], edc_route_string); | |
1406 | if (cur_reg_start == i-1) | |
1407 | edac_dbg(0, "edc route table for CHA %d: %s\n", | |
1408 | cur_reg_start, edc_route_string); | |
1409 | else | |
1410 | edac_dbg(0, "edc route table for CHA %d-%d: %s\n", | |
1411 | cur_reg_start, i-1, edc_route_string); | |
1412 | ||
1413 | /* Read the MC route table in each CHA. */ | |
1414 | cur_reg_start = 0; | |
1415 | for (i = 0; i < KNL_MAX_CHAS; i++) { | |
1416 | pci_read_config_dword(pvt->knl.pci_cha[i], | |
1417 | KNL_MC_ROUTE, &mc_route_reg[i]); | |
1418 | ||
1419 | if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { | |
1420 | knl_show_mc_route(mc_route_reg[i-1], mc_route_string); | |
1421 | if (cur_reg_start == i-1) | |
1422 | edac_dbg(0, "mc route table for CHA %d: %s\n", | |
1423 | cur_reg_start, mc_route_string); | |
1424 | else | |
1425 | edac_dbg(0, "mc route table for CHA %d-%d: %s\n", | |
1426 | cur_reg_start, i-1, mc_route_string); | |
1427 | cur_reg_start = i; | |
1428 | } | |
1429 | } | |
1430 | knl_show_mc_route(mc_route_reg[i-1], mc_route_string); | |
1431 | if (cur_reg_start == i-1) | |
1432 | edac_dbg(0, "mc route table for CHA %d: %s\n", | |
1433 | cur_reg_start, mc_route_string); | |
1434 | else | |
1435 | edac_dbg(0, "mc route table for CHA %d-%d: %s\n", | |
1436 | cur_reg_start, i-1, mc_route_string); | |
1437 | ||
1438 | /* Process DRAM rules */ | |
1439 | for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { | |
1440 | /* previous limit becomes the new base */ | |
1441 | sad_base = sad_limit; | |
1442 | ||
1443 | pci_read_config_dword(pvt->pci_sad0, | |
1444 | pvt->info.dram_rule[sad_rule], &dram_rule); | |
1445 | ||
1446 | if (!DRAM_RULE_ENABLE(dram_rule)) | |
1447 | break; | |
1448 | ||
1449 | edram_only = KNL_EDRAM_ONLY(dram_rule); | |
1450 | ||
1451 | sad_limit = pvt->info.sad_limit(dram_rule)+1; | |
1452 | sad_size = sad_limit - sad_base; | |
1453 | ||
1454 | pci_read_config_dword(pvt->pci_sad0, | |
1455 | pvt->info.interleave_list[sad_rule], &interleave_reg); | |
1456 | ||
1457 | /* | |
1458 | * Find out how many ways this dram rule is interleaved. | |
1459 | * We stop when we see the first channel again. | |
1460 | */ | |
1461 | first_pkg = sad_pkg(pvt->info.interleave_pkg, | |
1462 | interleave_reg, 0); | |
1463 | for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) { | |
1464 | pkg = sad_pkg(pvt->info.interleave_pkg, | |
1465 | interleave_reg, intrlv_ways); | |
1466 | ||
1467 | if ((pkg & 0x8) == 0) { | |
1468 | /* | |
1469 | * 0 bit means memory is non-local, | |
1470 | * which KNL doesn't support | |
1471 | */ | |
1472 | edac_dbg(0, "Unexpected interleave target %d\n", | |
1473 | pkg); | |
1474 | return -1; | |
1475 | } | |
1476 | ||
1477 | if (pkg == first_pkg) | |
1478 | break; | |
1479 | } | |
1480 | if (KNL_MOD3(dram_rule)) | |
1481 | intrlv_ways *= 3; | |
1482 | ||
1483 | edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", | |
1484 | sad_rule, | |
1485 | sad_base, | |
1486 | sad_limit, | |
1487 | intrlv_ways, | |
1488 | edram_only ? ", EDRAM" : ""); | |
1489 | ||
1490 | /* | |
1491 | * Find out how big the SAD region really is by iterating | |
1492 | * over TAD tables (SAD regions may contain holes). | |
1493 | * Each memory controller might have a different TAD table, so | |
1494 | * we have to look at both. | |
1495 | * | |
1496 | * Livespace is the memory that's mapped in this TAD table, | |
1497 | * deadspace is the holes (this could be the MMIO hole, or it | |
1498 | * could be memory that's mapped by the other TAD table but | |
1499 | * not this one). | |
1500 | */ | |
1501 | for (mc = 0; mc < 2; mc++) { | |
1502 | sad_actual_size[mc] = 0; | |
1503 | tad_livespace = 0; | |
1504 | for (tad_rule = 0; | |
1505 | tad_rule < ARRAY_SIZE( | |
1506 | knl_tad_dram_limit_lo); | |
1507 | tad_rule++) { | |
1508 | if (knl_get_tad(pvt, | |
1509 | tad_rule, | |
1510 | mc, | |
1511 | &tad_deadspace, | |
1512 | &tad_limit, | |
1513 | &tad_ways)) | |
1514 | break; | |
1515 | ||
1516 | tad_size = (tad_limit+1) - | |
1517 | (tad_livespace + tad_deadspace); | |
1518 | tad_livespace += tad_size; | |
1519 | tad_base = (tad_limit+1) - tad_size; | |
1520 | ||
1521 | if (tad_base < sad_base) { | |
1522 | if (tad_limit > sad_base) | |
1523 | edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n"); | |
1524 | } else if (tad_base < sad_limit) { | |
1525 | if (tad_limit+1 > sad_limit) { | |
1526 | edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n"); | |
1527 | } else { | |
1528 | /* TAD region is completely inside SAD region */ | |
1529 | edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", | |
1530 | tad_rule, tad_base, | |
1531 | tad_limit, tad_size, | |
1532 | mc); | |
1533 | sad_actual_size[mc] += tad_size; | |
1534 | } | |
1535 | } | |
1536 | tad_base = tad_limit+1; | |
1537 | } | |
1538 | } | |
1539 | ||
1540 | for (mc = 0; mc < 2; mc++) { | |
1541 | edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n", | |
1542 | mc, sad_actual_size[mc], sad_actual_size[mc]); | |
1543 | } | |
1544 | ||
1545 | /* Ignore EDRAM rule */ | |
1546 | if (edram_only) | |
1547 | continue; | |
1548 | ||
1549 | /* Figure out which channels participate in interleave. */ | |
1550 | for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) | |
1551 | participants[channel] = 0; | |
1552 | ||
1553 | /* For each channel, does at least one CHA have | |
1554 | * this channel mapped to the given target? | |
1555 | */ | |
1556 | for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { | |
1557 | for (way = 0; way < intrlv_ways; way++) { | |
1558 | int target; | |
1559 | int cha; | |
1560 | ||
1561 | if (KNL_MOD3(dram_rule)) | |
1562 | target = way; | |
1563 | else | |
1564 | target = 0x7 & sad_pkg( | |
1565 | pvt->info.interleave_pkg, interleave_reg, way); | |
1566 | ||
1567 | for (cha = 0; cha < KNL_MAX_CHAS; cha++) { | |
1568 | if (knl_get_mc_route(target, | |
1569 | mc_route_reg[cha]) == channel | |
83bdaad4 | 1570 | && !participants[channel]) { |
d0cdf900 JS |
1571 | participant_count++; |
1572 | participants[channel] = 1; | |
1573 | break; | |
1574 | } | |
1575 | } | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | if (participant_count != intrlv_ways) | |
1580 | edac_dbg(0, "participant_count (%d) != interleave_ways (%d): DIMM size may be incorrect\n", | |
1581 | participant_count, intrlv_ways); | |
1582 | ||
1583 | for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { | |
1584 | mc = knl_channel_mc(channel); | |
1585 | if (participants[channel]) { | |
1586 | edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n", | |
1587 | channel, | |
1588 | sad_actual_size[mc]/intrlv_ways, | |
1589 | sad_rule); | |
1590 | mc_sizes[channel] += | |
1591 | sad_actual_size[mc]/intrlv_ways; | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
084a4fcc | 1599 | static int get_dimm_config(struct mem_ctl_info *mci) |
eebf11a0 MCC |
1600 | { |
1601 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 1602 | struct dimm_info *dimm; |
deb09dda MCC |
1603 | unsigned i, j, banks, ranks, rows, cols, npages; |
1604 | u64 size; | |
eebf11a0 MCC |
1605 | u32 reg; |
1606 | enum edac_type mode; | |
c6e13b52 | 1607 | enum mem_type mtype; |
d0cdf900 JS |
1608 | int channels = pvt->info.type == KNIGHTS_LANDING ? |
1609 | KNL_MAX_CHANNELS : NUM_CHANNELS; | |
1610 | u64 knl_mc_sizes[KNL_MAX_CHANNELS]; | |
eebf11a0 | 1611 | |
ea5dfb5f TL |
1612 | if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { |
1613 | pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, ®); | |
1614 | pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); | |
1615 | } | |
d0cdf900 JS |
1616 | if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || |
1617 | pvt->info.type == KNIGHTS_LANDING) | |
50d1bb93 AR |
1618 | pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); |
1619 | else | |
1620 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); | |
1621 | ||
d0cdf900 JS |
1622 | if (pvt->info.type == KNIGHTS_LANDING) |
1623 | pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); | |
1624 | else | |
1625 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); | |
eebf11a0 | 1626 | |
f14d6892 | 1627 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
956b9ba1 JP |
1628 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
1629 | pvt->sbridge_dev->mc, | |
1630 | pvt->sbridge_dev->node_id, | |
1631 | pvt->sbridge_dev->source_id); | |
eebf11a0 | 1632 | |
d0cdf900 JS |
1633 | /* KNL doesn't support mirroring or lockstep, |
1634 | * and is always closed page | |
1635 | */ | |
1636 | if (pvt->info.type == KNIGHTS_LANDING) { | |
1637 | mode = EDAC_S4ECD4ED; | |
eebf11a0 | 1638 | pvt->is_mirrored = false; |
eebf11a0 | 1639 | |
d0cdf900 JS |
1640 | if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) |
1641 | return -1; | |
eebf11a0 | 1642 | } else { |
d0cdf900 JS |
1643 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); |
1644 | if (IS_MIRROR_ENABLED(reg)) { | |
1645 | edac_dbg(0, "Memory mirror is enabled\n"); | |
1646 | pvt->is_mirrored = true; | |
1647 | } else { | |
1648 | edac_dbg(0, "Memory mirror is disabled\n"); | |
1649 | pvt->is_mirrored = false; | |
1650 | } | |
1651 | ||
1652 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); | |
1653 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { | |
1654 | edac_dbg(0, "Lockstep is enabled\n"); | |
1655 | mode = EDAC_S8ECD8ED; | |
1656 | pvt->is_lockstep = true; | |
1657 | } else { | |
1658 | edac_dbg(0, "Lockstep is disabled\n"); | |
1659 | mode = EDAC_S4ECD4ED; | |
1660 | pvt->is_lockstep = false; | |
1661 | } | |
1662 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | |
1663 | edac_dbg(0, "address map is on closed page mode\n"); | |
1664 | pvt->is_close_pg = true; | |
1665 | } else { | |
1666 | edac_dbg(0, "address map is on open page mode\n"); | |
1667 | pvt->is_close_pg = false; | |
1668 | } | |
eebf11a0 MCC |
1669 | } |
1670 | ||
9e375446 | 1671 | mtype = pvt->info.get_memory_type(pvt); |
50d1bb93 | 1672 | if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) |
9e375446 AR |
1673 | edac_dbg(0, "Memory is registered\n"); |
1674 | else if (mtype == MEM_UNKNOWN) | |
de4772c6 | 1675 | edac_dbg(0, "Cannot determine memory type\n"); |
9e375446 AR |
1676 | else |
1677 | edac_dbg(0, "Memory is unregistered\n"); | |
eebf11a0 | 1678 | |
fec53af5 | 1679 | if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) |
50d1bb93 AR |
1680 | banks = 16; |
1681 | else | |
1682 | banks = 8; | |
eebf11a0 | 1683 | |
d0cdf900 | 1684 | for (i = 0; i < channels; i++) { |
eebf11a0 MCC |
1685 | u32 mtr; |
1686 | ||
d0cdf900 JS |
1687 | int max_dimms_per_channel; |
1688 | ||
1689 | if (pvt->info.type == KNIGHTS_LANDING) { | |
1690 | max_dimms_per_channel = 1; | |
1691 | if (!pvt->knl.pci_channel[i]) | |
1692 | continue; | |
1693 | } else { | |
1694 | max_dimms_per_channel = ARRAY_SIZE(mtr_regs); | |
1695 | if (!pvt->pci_tad[i]) | |
1696 | continue; | |
1697 | } | |
1698 | ||
1699 | for (j = 0; j < max_dimms_per_channel; j++) { | |
c36e3e77 MCC |
1700 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
1701 | i, j, 0); | |
d0cdf900 JS |
1702 | if (pvt->info.type == KNIGHTS_LANDING) { |
1703 | pci_read_config_dword(pvt->knl.pci_channel[i], | |
1704 | knl_mtr_reg, &mtr); | |
1705 | } else { | |
1706 | pci_read_config_dword(pvt->pci_tad[i], | |
1707 | mtr_regs[j], &mtr); | |
1708 | } | |
956b9ba1 | 1709 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
eebf11a0 MCC |
1710 | if (IS_DIMM_PRESENT(mtr)) { |
1711 | pvt->channel[i].dimms++; | |
1712 | ||
50d1bb93 | 1713 | ranks = numrank(pvt->info.type, mtr); |
d0cdf900 JS |
1714 | |
1715 | if (pvt->info.type == KNIGHTS_LANDING) { | |
1716 | /* For DDR4, this is fixed. */ | |
1717 | cols = 1 << 10; | |
1718 | rows = knl_mc_sizes[i] / | |
1719 | ((u64) cols * ranks * banks * 8); | |
1720 | } else { | |
1721 | rows = numrow(mtr); | |
1722 | cols = numcol(mtr); | |
1723 | } | |
eebf11a0 | 1724 | |
deb09dda | 1725 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
eebf11a0 MCC |
1726 | npages = MiB_TO_PAGES(size); |
1727 | ||
7d375bff TL |
1728 | edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
1729 | pvt->sbridge_dev->mc, i/4, i%4, j, | |
956b9ba1 JP |
1730 | size, npages, |
1731 | banks, ranks, rows, cols); | |
eebf11a0 | 1732 | |
a895bf8b | 1733 | dimm->nr_pages = npages; |
084a4fcc | 1734 | dimm->grain = 32; |
12f0721c | 1735 | dimm->dtype = pvt->info.get_width(pvt, mtr); |
084a4fcc MCC |
1736 | dimm->mtype = mtype; |
1737 | dimm->edac_mode = mode; | |
1738 | snprintf(dimm->label, sizeof(dimm->label), | |
7d375bff TL |
1739 | "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", |
1740 | pvt->sbridge_dev->source_id, i/4, i%4, j); | |
eebf11a0 MCC |
1741 | } |
1742 | } | |
1743 | } | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
1748 | static void get_memory_layout(const struct mem_ctl_info *mci) | |
1749 | { | |
1750 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1751 | int i, j, k, n_sads, n_tads, sad_interl; | |
1752 | u32 reg; | |
1753 | u64 limit, prv = 0; | |
1754 | u64 tmp_mb; | |
8c009100 | 1755 | u32 gb, mb; |
eebf11a0 MCC |
1756 | u32 rir_way; |
1757 | ||
1758 | /* | |
1759 | * Step 1) Get TOLM/TOHM ranges | |
1760 | */ | |
1761 | ||
fb79a509 | 1762 | pvt->tolm = pvt->info.get_tolm(pvt); |
eebf11a0 MCC |
1763 | tmp_mb = (1 + pvt->tolm) >> 20; |
1764 | ||
8c009100 JS |
1765 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
1766 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", | |
1767 | gb, (mb*1000)/1024, (u64)pvt->tolm); | |
eebf11a0 MCC |
1768 | |
1769 | /* Address range is already 45:25 */ | |
8fd6a43a | 1770 | pvt->tohm = pvt->info.get_tohm(pvt); |
eebf11a0 MCC |
1771 | tmp_mb = (1 + pvt->tohm) >> 20; |
1772 | ||
8c009100 JS |
1773 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
1774 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", | |
1775 | gb, (mb*1000)/1024, (u64)pvt->tohm); | |
eebf11a0 MCC |
1776 | |
1777 | /* | |
1778 | * Step 2) Get SAD range and SAD Interleave list | |
1779 | * TAD registers contain the interleave wayness. However, it | |
1780 | * seems simpler to just discover it indirectly, with the | |
1781 | * algorithm bellow. | |
1782 | */ | |
1783 | prv = 0; | |
464f1d82 | 1784 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
eebf11a0 | 1785 | /* SAD_LIMIT Address range is 45:26 */ |
464f1d82 | 1786 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
eebf11a0 | 1787 | ®); |
c59f9c06 | 1788 | limit = pvt->info.sad_limit(reg); |
eebf11a0 MCC |
1789 | |
1790 | if (!DRAM_RULE_ENABLE(reg)) | |
1791 | continue; | |
1792 | ||
1793 | if (limit <= prv) | |
1794 | break; | |
1795 | ||
1796 | tmp_mb = (limit + 1) >> 20; | |
8c009100 | 1797 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1798 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
1799 | n_sads, | |
c59f9c06 | 1800 | show_dram_attr(pvt->info.dram_attr(reg)), |
8c009100 | 1801 | gb, (mb*1000)/1024, |
956b9ba1 | 1802 | ((u64)tmp_mb) << 20L, |
c59f9c06 | 1803 | pvt->info.show_interleave_mode(reg), |
956b9ba1 | 1804 | reg); |
eebf11a0 MCC |
1805 | prv = limit; |
1806 | ||
ef1ce51e | 1807 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1808 | ®); |
cc311991 | 1809 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 1810 | for (j = 0; j < 8; j++) { |
cc311991 AR |
1811 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
1812 | if (j > 0 && sad_interl == pkg) | |
eebf11a0 MCC |
1813 | break; |
1814 | ||
956b9ba1 | 1815 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
cc311991 | 1816 | n_sads, j, pkg); |
eebf11a0 MCC |
1817 | } |
1818 | } | |
1819 | ||
d0cdf900 JS |
1820 | if (pvt->info.type == KNIGHTS_LANDING) |
1821 | return; | |
1822 | ||
eebf11a0 MCC |
1823 | /* |
1824 | * Step 3) Get TAD range | |
1825 | */ | |
1826 | prv = 0; | |
1827 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
1828 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], | |
1829 | ®); | |
1830 | limit = TAD_LIMIT(reg); | |
1831 | if (limit <= prv) | |
1832 | break; | |
1833 | tmp_mb = (limit + 1) >> 20; | |
1834 | ||
8c009100 | 1835 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 | 1836 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
8c009100 | 1837 | n_tads, gb, (mb*1000)/1024, |
956b9ba1 | 1838 | ((u64)tmp_mb) << 20L, |
eb1af3b7 LT |
1839 | (u32)(1 << TAD_SOCK(reg)), |
1840 | (u32)TAD_CH(reg) + 1, | |
956b9ba1 JP |
1841 | (u32)TAD_TGT0(reg), |
1842 | (u32)TAD_TGT1(reg), | |
1843 | (u32)TAD_TGT2(reg), | |
1844 | (u32)TAD_TGT3(reg), | |
1845 | reg); | |
7fae0db4 | 1846 | prv = limit; |
eebf11a0 MCC |
1847 | } |
1848 | ||
1849 | /* | |
1850 | * Step 4) Get TAD offsets, per each channel | |
1851 | */ | |
1852 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1853 | if (!pvt->channel[i].dimms) | |
1854 | continue; | |
1855 | for (j = 0; j < n_tads; j++) { | |
1856 | pci_read_config_dword(pvt->pci_tad[i], | |
1857 | tad_ch_nilv_offset[j], | |
1858 | ®); | |
1859 | tmp_mb = TAD_OFFSET(reg) >> 20; | |
8c009100 | 1860 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1861 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
1862 | i, j, | |
8c009100 | 1863 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1864 | ((u64)tmp_mb) << 20L, |
1865 | reg); | |
eebf11a0 MCC |
1866 | } |
1867 | } | |
1868 | ||
1869 | /* | |
1870 | * Step 6) Get RIR Wayness/Limit, per each channel | |
1871 | */ | |
1872 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1873 | if (!pvt->channel[i].dimms) | |
1874 | continue; | |
1875 | for (j = 0; j < MAX_RIR_RANGES; j++) { | |
1876 | pci_read_config_dword(pvt->pci_tad[i], | |
1877 | rir_way_limit[j], | |
1878 | ®); | |
1879 | ||
1880 | if (!IS_RIR_VALID(reg)) | |
1881 | continue; | |
1882 | ||
b976bcf2 | 1883 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
eebf11a0 | 1884 | rir_way = 1 << RIR_WAY(reg); |
8c009100 | 1885 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1886 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
1887 | i, j, | |
8c009100 | 1888 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1889 | ((u64)tmp_mb) << 20L, |
1890 | rir_way, | |
1891 | reg); | |
eebf11a0 MCC |
1892 | |
1893 | for (k = 0; k < rir_way; k++) { | |
1894 | pci_read_config_dword(pvt->pci_tad[i], | |
1895 | rir_offset[j][k], | |
1896 | ®); | |
1897 | tmp_mb = RIR_OFFSET(reg) << 6; | |
1898 | ||
8c009100 | 1899 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1900 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
1901 | i, j, k, | |
8c009100 | 1902 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1903 | ((u64)tmp_mb) << 20L, |
1904 | (u32)RIR_RNK_TGT(reg), | |
1905 | reg); | |
eebf11a0 MCC |
1906 | } |
1907 | } | |
1908 | } | |
1909 | } | |
1910 | ||
8112c0cd | 1911 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
eebf11a0 MCC |
1912 | { |
1913 | struct sbridge_dev *sbridge_dev; | |
1914 | ||
1915 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
1916 | if (sbridge_dev->node_id == node_id) | |
1917 | return sbridge_dev->mci; | |
1918 | } | |
1919 | return NULL; | |
1920 | } | |
1921 | ||
1922 | static int get_memory_error_data(struct mem_ctl_info *mci, | |
1923 | u64 addr, | |
7d375bff | 1924 | u8 *socket, u8 *ha, |
eebf11a0 MCC |
1925 | long *channel_mask, |
1926 | u8 *rank, | |
e17a2f42 | 1927 | char **area_type, char *msg) |
eebf11a0 MCC |
1928 | { |
1929 | struct mem_ctl_info *new_mci; | |
1930 | struct sbridge_pvt *pvt = mci->pvt_info; | |
4d715a80 | 1931 | struct pci_dev *pci_ha; |
c41afdca | 1932 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
eebf11a0 | 1933 | int sad_interl, idx, base_ch; |
50d1bb93 | 1934 | int interleave_mode, shiftup = 0; |
ef1ce51e | 1935 | unsigned sad_interleave[pvt->info.max_interleave]; |
50d1bb93 | 1936 | u32 reg, dram_rule; |
7d375bff | 1937 | u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0; |
eebf11a0 MCC |
1938 | u32 tad_offset; |
1939 | u32 rir_way; | |
8c009100 | 1940 | u32 mb, gb; |
bd4b9683 | 1941 | u64 ch_addr, offset, limit = 0, prv = 0; |
eebf11a0 MCC |
1942 | |
1943 | ||
1944 | /* | |
1945 | * Step 0) Check if the address is at special memory ranges | |
1946 | * The check bellow is probably enough to fill all cases where | |
1947 | * the error is not inside a memory, except for the legacy | |
1948 | * range (e. g. VGA addresses). It is unlikely, however, that the | |
1949 | * memory controller would generate an error on that range. | |
1950 | */ | |
5b889e37 | 1951 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
eebf11a0 | 1952 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
eebf11a0 MCC |
1953 | return -EINVAL; |
1954 | } | |
1955 | if (addr >= (u64)pvt->tohm) { | |
1956 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); | |
eebf11a0 MCC |
1957 | return -EINVAL; |
1958 | } | |
1959 | ||
1960 | /* | |
1961 | * Step 1) Get socket | |
1962 | */ | |
464f1d82 AR |
1963 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
1964 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], | |
eebf11a0 MCC |
1965 | ®); |
1966 | ||
1967 | if (!DRAM_RULE_ENABLE(reg)) | |
1968 | continue; | |
1969 | ||
c59f9c06 | 1970 | limit = pvt->info.sad_limit(reg); |
eebf11a0 MCC |
1971 | if (limit <= prv) { |
1972 | sprintf(msg, "Can't discover the memory socket"); | |
eebf11a0 MCC |
1973 | return -EINVAL; |
1974 | } | |
1975 | if (addr <= limit) | |
1976 | break; | |
1977 | prv = limit; | |
1978 | } | |
464f1d82 | 1979 | if (n_sads == pvt->info.max_sad) { |
eebf11a0 | 1980 | sprintf(msg, "Can't discover the memory socket"); |
eebf11a0 MCC |
1981 | return -EINVAL; |
1982 | } | |
50d1bb93 | 1983 | dram_rule = reg; |
c59f9c06 JS |
1984 | *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); |
1985 | interleave_mode = pvt->info.interleave_mode(dram_rule); | |
eebf11a0 | 1986 | |
ef1ce51e | 1987 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1988 | ®); |
4d715a80 AR |
1989 | |
1990 | if (pvt->info.type == SANDY_BRIDGE) { | |
1991 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); | |
1992 | for (sad_way = 0; sad_way < 8; sad_way++) { | |
1993 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); | |
1994 | if (sad_way > 0 && sad_interl == pkg) | |
1995 | break; | |
1996 | sad_interleave[sad_way] = pkg; | |
1997 | edac_dbg(0, "SAD interleave #%d: %d\n", | |
1998 | sad_way, sad_interleave[sad_way]); | |
1999 | } | |
2000 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", | |
2001 | pvt->sbridge_dev->mc, | |
2002 | n_sads, | |
2003 | addr, | |
2004 | limit, | |
2005 | sad_way + 7, | |
2006 | !interleave_mode ? "" : "XOR[18:16]"); | |
2007 | if (interleave_mode) | |
2008 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | |
2009 | else | |
2010 | idx = (addr >> 6) & 7; | |
2011 | switch (sad_way) { | |
2012 | case 1: | |
2013 | idx = 0; | |
eebf11a0 | 2014 | break; |
4d715a80 AR |
2015 | case 2: |
2016 | idx = idx & 1; | |
2017 | break; | |
2018 | case 4: | |
2019 | idx = idx & 3; | |
2020 | break; | |
2021 | case 8: | |
2022 | break; | |
2023 | default: | |
2024 | sprintf(msg, "Can't discover socket interleave"); | |
2025 | return -EINVAL; | |
2026 | } | |
2027 | *socket = sad_interleave[idx]; | |
2028 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", | |
2029 | idx, sad_way, *socket); | |
1f39581a | 2030 | } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { |
50d1bb93 AR |
2031 | int bits, a7mode = A7MODE(dram_rule); |
2032 | ||
2033 | if (a7mode) { | |
2034 | /* A7 mode swaps P9 with P6 */ | |
2035 | bits = GET_BITFIELD(addr, 7, 8) << 1; | |
2036 | bits |= GET_BITFIELD(addr, 9, 9); | |
2037 | } else | |
bb89e714 | 2038 | bits = GET_BITFIELD(addr, 6, 8); |
50d1bb93 | 2039 | |
bb89e714 | 2040 | if (interleave_mode == 0) { |
50d1bb93 AR |
2041 | /* interleave mode will XOR {8,7,6} with {18,17,16} */ |
2042 | idx = GET_BITFIELD(addr, 16, 18); | |
2043 | idx ^= bits; | |
2044 | } else | |
2045 | idx = bits; | |
2046 | ||
2047 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); | |
2048 | *socket = sad_pkg_socket(pkg); | |
2049 | sad_ha = sad_pkg_ha(pkg); | |
7d375bff TL |
2050 | if (sad_ha) |
2051 | ch_add = 4; | |
50d1bb93 AR |
2052 | |
2053 | if (a7mode) { | |
2054 | /* MCChanShiftUpEnable */ | |
2055 | pci_read_config_dword(pvt->pci_ha0, | |
2056 | HASWELL_HASYSDEFEATURE2, ®); | |
2057 | shiftup = GET_BITFIELD(reg, 22, 22); | |
2058 | } | |
2059 | ||
2060 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", | |
2061 | idx, *socket, sad_ha, shiftup); | |
4d715a80 AR |
2062 | } else { |
2063 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ | |
eebf11a0 | 2064 | idx = (addr >> 6) & 7; |
4d715a80 AR |
2065 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
2066 | *socket = sad_pkg_socket(pkg); | |
2067 | sad_ha = sad_pkg_ha(pkg); | |
7d375bff TL |
2068 | if (sad_ha) |
2069 | ch_add = 4; | |
4d715a80 AR |
2070 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", |
2071 | idx, *socket, sad_ha); | |
eebf11a0 | 2072 | } |
eebf11a0 | 2073 | |
7d375bff TL |
2074 | *ha = sad_ha; |
2075 | ||
eebf11a0 MCC |
2076 | /* |
2077 | * Move to the proper node structure, in order to access the | |
2078 | * right PCI registers | |
2079 | */ | |
2080 | new_mci = get_mci_for_node_id(*socket); | |
2081 | if (!new_mci) { | |
2082 | sprintf(msg, "Struct for socket #%u wasn't initialized", | |
2083 | *socket); | |
eebf11a0 MCC |
2084 | return -EINVAL; |
2085 | } | |
2086 | mci = new_mci; | |
2087 | pvt = mci->pvt_info; | |
2088 | ||
2089 | /* | |
2090 | * Step 2) Get memory channel | |
2091 | */ | |
2092 | prv = 0; | |
4d715a80 AR |
2093 | if (pvt->info.type == SANDY_BRIDGE) |
2094 | pci_ha = pvt->pci_ha0; | |
2095 | else { | |
2096 | if (sad_ha) | |
2097 | pci_ha = pvt->pci_ha1; | |
2098 | else | |
2099 | pci_ha = pvt->pci_ha0; | |
2100 | } | |
eebf11a0 | 2101 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
4d715a80 | 2102 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
eebf11a0 MCC |
2103 | limit = TAD_LIMIT(reg); |
2104 | if (limit <= prv) { | |
2105 | sprintf(msg, "Can't discover the memory channel"); | |
eebf11a0 MCC |
2106 | return -EINVAL; |
2107 | } | |
2108 | if (addr <= limit) | |
2109 | break; | |
2110 | prv = limit; | |
2111 | } | |
4d715a80 AR |
2112 | if (n_tads == MAX_TAD) { |
2113 | sprintf(msg, "Can't discover the memory channel"); | |
2114 | return -EINVAL; | |
2115 | } | |
2116 | ||
eebf11a0 | 2117 | ch_way = TAD_CH(reg) + 1; |
ff15e95c | 2118 | sck_way = TAD_SOCK(reg); |
eebf11a0 MCC |
2119 | |
2120 | if (ch_way == 3) | |
2121 | idx = addr >> 6; | |
ea5dfb5f | 2122 | else { |
50d1bb93 | 2123 | idx = (addr >> (6 + sck_way + shiftup)) & 0x3; |
ea5dfb5f TL |
2124 | if (pvt->is_chan_hash) |
2125 | idx = haswell_chan_hash(idx, addr); | |
2126 | } | |
eebf11a0 MCC |
2127 | idx = idx % ch_way; |
2128 | ||
2129 | /* | |
2130 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? | |
2131 | */ | |
2132 | switch (idx) { | |
2133 | case 0: | |
2134 | base_ch = TAD_TGT0(reg); | |
2135 | break; | |
2136 | case 1: | |
2137 | base_ch = TAD_TGT1(reg); | |
2138 | break; | |
2139 | case 2: | |
2140 | base_ch = TAD_TGT2(reg); | |
2141 | break; | |
2142 | case 3: | |
2143 | base_ch = TAD_TGT3(reg); | |
2144 | break; | |
2145 | default: | |
2146 | sprintf(msg, "Can't discover the TAD target"); | |
eebf11a0 MCC |
2147 | return -EINVAL; |
2148 | } | |
2149 | *channel_mask = 1 << base_ch; | |
2150 | ||
7d375bff | 2151 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
4d715a80 AR |
2152 | tad_ch_nilv_offset[n_tads], |
2153 | &tad_offset); | |
2154 | ||
eebf11a0 MCC |
2155 | if (pvt->is_mirrored) { |
2156 | *channel_mask |= 1 << ((base_ch + 2) % 4); | |
2157 | switch(ch_way) { | |
2158 | case 2: | |
2159 | case 4: | |
ff15e95c | 2160 | sck_xch = (1 << sck_way) * (ch_way >> 1); |
eebf11a0 MCC |
2161 | break; |
2162 | default: | |
2163 | sprintf(msg, "Invalid mirror set. Can't decode addr"); | |
eebf11a0 MCC |
2164 | return -EINVAL; |
2165 | } | |
2166 | } else | |
2167 | sck_xch = (1 << sck_way) * ch_way; | |
2168 | ||
2169 | if (pvt->is_lockstep) | |
2170 | *channel_mask |= 1 << ((base_ch + 1) % 4); | |
2171 | ||
2172 | offset = TAD_OFFSET(tad_offset); | |
2173 | ||
956b9ba1 JP |
2174 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
2175 | n_tads, | |
2176 | addr, | |
2177 | limit, | |
eb1af3b7 | 2178 | sck_way, |
956b9ba1 JP |
2179 | ch_way, |
2180 | offset, | |
2181 | idx, | |
2182 | base_ch, | |
2183 | *channel_mask); | |
eebf11a0 MCC |
2184 | |
2185 | /* Calculate channel address */ | |
2186 | /* Remove the TAD offset */ | |
2187 | ||
2188 | if (offset > addr) { | |
2189 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", | |
2190 | offset, addr); | |
eebf11a0 MCC |
2191 | return -EINVAL; |
2192 | } | |
eb1af3b7 LT |
2193 | |
2194 | ch_addr = addr - offset; | |
2195 | ch_addr >>= (6 + shiftup); | |
ff15e95c | 2196 | ch_addr /= sck_xch; |
eb1af3b7 LT |
2197 | ch_addr <<= (6 + shiftup); |
2198 | ch_addr |= addr & ((1 << (6 + shiftup)) - 1); | |
eebf11a0 MCC |
2199 | |
2200 | /* | |
2201 | * Step 3) Decode rank | |
2202 | */ | |
2203 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { | |
7d375bff | 2204 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
eebf11a0 MCC |
2205 | rir_way_limit[n_rir], |
2206 | ®); | |
2207 | ||
2208 | if (!IS_RIR_VALID(reg)) | |
2209 | continue; | |
2210 | ||
b976bcf2 | 2211 | limit = pvt->info.rir_limit(reg); |
8c009100 | 2212 | gb = div_u64_rem(limit >> 20, 1024, &mb); |
956b9ba1 JP |
2213 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
2214 | n_rir, | |
8c009100 | 2215 | gb, (mb*1000)/1024, |
956b9ba1 JP |
2216 | limit, |
2217 | 1 << RIR_WAY(reg)); | |
eebf11a0 MCC |
2218 | if (ch_addr <= limit) |
2219 | break; | |
2220 | } | |
2221 | if (n_rir == MAX_RIR_RANGES) { | |
2222 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", | |
2223 | ch_addr); | |
eebf11a0 MCC |
2224 | return -EINVAL; |
2225 | } | |
2226 | rir_way = RIR_WAY(reg); | |
50d1bb93 | 2227 | |
eebf11a0 MCC |
2228 | if (pvt->is_close_pg) |
2229 | idx = (ch_addr >> 6); | |
2230 | else | |
2231 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ | |
2232 | idx %= 1 << rir_way; | |
2233 | ||
7d375bff | 2234 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
eebf11a0 MCC |
2235 | rir_offset[n_rir][idx], |
2236 | ®); | |
2237 | *rank = RIR_RNK_TGT(reg); | |
2238 | ||
956b9ba1 JP |
2239 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
2240 | n_rir, | |
2241 | ch_addr, | |
2242 | limit, | |
2243 | rir_way, | |
2244 | idx); | |
eebf11a0 MCC |
2245 | |
2246 | return 0; | |
2247 | } | |
2248 | ||
2249 | /**************************************************************************** | |
2250 | Device initialization routines: put/get, init/exit | |
2251 | ****************************************************************************/ | |
2252 | ||
2253 | /* | |
2254 | * sbridge_put_all_devices 'put' all the devices that we have | |
2255 | * reserved via 'get' | |
2256 | */ | |
2257 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |
2258 | { | |
2259 | int i; | |
2260 | ||
956b9ba1 | 2261 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
2262 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
2263 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | |
2264 | if (!pdev) | |
2265 | continue; | |
956b9ba1 JP |
2266 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
2267 | pdev->bus->number, | |
2268 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
eebf11a0 MCC |
2269 | pci_dev_put(pdev); |
2270 | } | |
2271 | } | |
2272 | ||
2273 | static void sbridge_put_all_devices(void) | |
2274 | { | |
2275 | struct sbridge_dev *sbridge_dev, *tmp; | |
2276 | ||
2277 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { | |
2278 | sbridge_put_devices(sbridge_dev); | |
2279 | free_sbridge_dev(sbridge_dev); | |
2280 | } | |
2281 | } | |
2282 | ||
eebf11a0 MCC |
2283 | static int sbridge_get_onedevice(struct pci_dev **prev, |
2284 | u8 *num_mc, | |
2285 | const struct pci_id_table *table, | |
c1979ba2 JS |
2286 | const unsigned devno, |
2287 | const int multi_bus) | |
eebf11a0 MCC |
2288 | { |
2289 | struct sbridge_dev *sbridge_dev; | |
2290 | const struct pci_id_descr *dev_descr = &table->descr[devno]; | |
eebf11a0 MCC |
2291 | struct pci_dev *pdev = NULL; |
2292 | u8 bus = 0; | |
2293 | ||
ec5a0b38 | 2294 | sbridge_printk(KERN_DEBUG, |
dbc954dd | 2295 | "Seeking for: PCI ID %04x:%04x\n", |
eebf11a0 MCC |
2296 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2297 | ||
2298 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
2299 | dev_descr->dev_id, *prev); | |
2300 | ||
2301 | if (!pdev) { | |
2302 | if (*prev) { | |
2303 | *prev = pdev; | |
2304 | return 0; | |
2305 | } | |
2306 | ||
2307 | if (dev_descr->optional) | |
2308 | return 0; | |
2309 | ||
dbc954dd | 2310 | /* if the HA wasn't found */ |
eebf11a0 MCC |
2311 | if (devno == 0) |
2312 | return -ENODEV; | |
2313 | ||
2314 | sbridge_printk(KERN_INFO, | |
dbc954dd | 2315 | "Device not found: %04x:%04x\n", |
eebf11a0 MCC |
2316 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2317 | ||
2318 | /* End of list, leave */ | |
2319 | return -ENODEV; | |
2320 | } | |
2321 | bus = pdev->bus->number; | |
2322 | ||
c1979ba2 | 2323 | sbridge_dev = get_sbridge_dev(bus, multi_bus); |
eebf11a0 MCC |
2324 | if (!sbridge_dev) { |
2325 | sbridge_dev = alloc_sbridge_dev(bus, table); | |
2326 | if (!sbridge_dev) { | |
2327 | pci_dev_put(pdev); | |
2328 | return -ENOMEM; | |
2329 | } | |
2330 | (*num_mc)++; | |
2331 | } | |
2332 | ||
2333 | if (sbridge_dev->pdev[devno]) { | |
2334 | sbridge_printk(KERN_ERR, | |
dbc954dd | 2335 | "Duplicated device for %04x:%04x\n", |
eebf11a0 MCC |
2336 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2337 | pci_dev_put(pdev); | |
2338 | return -ENODEV; | |
2339 | } | |
2340 | ||
2341 | sbridge_dev->pdev[devno] = pdev; | |
2342 | ||
eebf11a0 MCC |
2343 | /* Be sure that the device is enabled */ |
2344 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
2345 | sbridge_printk(KERN_ERR, | |
dbc954dd | 2346 | "Couldn't enable %04x:%04x\n", |
eebf11a0 MCC |
2347 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2348 | return -ENODEV; | |
2349 | } | |
2350 | ||
dbc954dd | 2351 | edac_dbg(0, "Detected %04x:%04x\n", |
956b9ba1 | 2352 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
eebf11a0 MCC |
2353 | |
2354 | /* | |
2355 | * As stated on drivers/pci/search.c, the reference count for | |
2356 | * @from is always decremented if it is not %NULL. So, as we need | |
2357 | * to get all devices up to null, we need to do a get for the device | |
2358 | */ | |
2359 | pci_dev_get(pdev); | |
2360 | ||
2361 | *prev = pdev; | |
2362 | ||
2363 | return 0; | |
2364 | } | |
2365 | ||
5153a0f9 AR |
2366 | /* |
2367 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's | |
dbc954dd | 2368 | * devices we want to reference for this driver. |
5153a0f9 | 2369 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
c41afdca | 2370 | * of success. |
5153a0f9 | 2371 | * @table: model specific table |
c1979ba2 JS |
2372 | * @allow_dups: allow for multiple devices to exist with the same device id |
2373 | * (as implemented, this isn't expected to work correctly in the | |
2374 | * multi-socket case). | |
2375 | * @multi_bus: don't assume devices on different buses belong to different | |
2376 | * memory controllers. | |
5153a0f9 AR |
2377 | * |
2378 | * returns 0 in case of success or error code | |
2379 | */ | |
c1979ba2 JS |
2380 | static int sbridge_get_all_devices_full(u8 *num_mc, |
2381 | const struct pci_id_table *table, | |
2382 | int allow_dups, | |
2383 | int multi_bus) | |
eebf11a0 MCC |
2384 | { |
2385 | int i, rc; | |
2386 | struct pci_dev *pdev = NULL; | |
eebf11a0 MCC |
2387 | |
2388 | while (table && table->descr) { | |
2389 | for (i = 0; i < table->n_devs; i++) { | |
c1979ba2 JS |
2390 | if (!allow_dups || i == 0 || |
2391 | table->descr[i].dev_id != | |
2392 | table->descr[i-1].dev_id) { | |
2393 | pdev = NULL; | |
2394 | } | |
eebf11a0 MCC |
2395 | do { |
2396 | rc = sbridge_get_onedevice(&pdev, num_mc, | |
c1979ba2 | 2397 | table, i, multi_bus); |
eebf11a0 MCC |
2398 | if (rc < 0) { |
2399 | if (i == 0) { | |
2400 | i = table->n_devs; | |
2401 | break; | |
2402 | } | |
2403 | sbridge_put_all_devices(); | |
2404 | return -ENODEV; | |
2405 | } | |
c1979ba2 | 2406 | } while (pdev && !allow_dups); |
eebf11a0 MCC |
2407 | } |
2408 | table++; | |
2409 | } | |
2410 | ||
2411 | return 0; | |
2412 | } | |
2413 | ||
c1979ba2 JS |
2414 | #define sbridge_get_all_devices(num_mc, table) \ |
2415 | sbridge_get_all_devices_full(num_mc, table, 0, 0) | |
d0cdf900 JS |
2416 | #define sbridge_get_all_devices_knl(num_mc, table) \ |
2417 | sbridge_get_all_devices_full(num_mc, table, 1, 1) | |
c1979ba2 | 2418 | |
ea779b5a AR |
2419 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
2420 | struct sbridge_dev *sbridge_dev) | |
eebf11a0 MCC |
2421 | { |
2422 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2423 | struct pci_dev *pdev; | |
2900ea60 | 2424 | u8 saw_chan_mask = 0; |
dbc954dd | 2425 | int i; |
eebf11a0 MCC |
2426 | |
2427 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2428 | pdev = sbridge_dev->pdev[i]; | |
2429 | if (!pdev) | |
2430 | continue; | |
dbc954dd AR |
2431 | |
2432 | switch (pdev->device) { | |
2433 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: | |
2434 | pvt->pci_sad0 = pdev; | |
eebf11a0 | 2435 | break; |
dbc954dd AR |
2436 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
2437 | pvt->pci_sad1 = pdev; | |
eebf11a0 | 2438 | break; |
dbc954dd AR |
2439 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
2440 | pvt->pci_br0 = pdev; | |
eebf11a0 | 2441 | break; |
dbc954dd AR |
2442 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
2443 | pvt->pci_ha0 = pdev; | |
eebf11a0 | 2444 | break; |
dbc954dd AR |
2445 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
2446 | pvt->pci_ta = pdev; | |
2447 | break; | |
2448 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: | |
2449 | pvt->pci_ras = pdev; | |
2450 | break; | |
2451 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: | |
2452 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: | |
2453 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: | |
2454 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: | |
2455 | { | |
2456 | int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; | |
2457 | pvt->pci_tad[id] = pdev; | |
2900ea60 | 2458 | saw_chan_mask |= 1 << id; |
dbc954dd AR |
2459 | } |
2460 | break; | |
2461 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: | |
2462 | pvt->pci_ddrio = pdev; | |
eebf11a0 MCC |
2463 | break; |
2464 | default: | |
2465 | goto error; | |
2466 | } | |
2467 | ||
dbc954dd AR |
2468 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
2469 | pdev->vendor, pdev->device, | |
956b9ba1 | 2470 | sbridge_dev->bus, |
956b9ba1 | 2471 | pdev); |
eebf11a0 MCC |
2472 | } |
2473 | ||
2474 | /* Check if everything were registered */ | |
2475 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || | |
de4772c6 | 2476 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
eebf11a0 MCC |
2477 | goto enodev; |
2478 | ||
2900ea60 SJ |
2479 | if (saw_chan_mask != 0x0f) |
2480 | goto enodev; | |
eebf11a0 MCC |
2481 | return 0; |
2482 | ||
2483 | enodev: | |
2484 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2485 | return -ENODEV; | |
2486 | ||
2487 | error: | |
dbc954dd AR |
2488 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
2489 | PCI_VENDOR_ID_INTEL, pdev->device); | |
eebf11a0 MCC |
2490 | return -EINVAL; |
2491 | } | |
2492 | ||
4d715a80 AR |
2493 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
2494 | struct sbridge_dev *sbridge_dev) | |
2495 | { | |
2496 | struct sbridge_pvt *pvt = mci->pvt_info; | |
7d375bff TL |
2497 | struct pci_dev *pdev; |
2498 | u8 saw_chan_mask = 0; | |
dbc954dd | 2499 | int i; |
4d715a80 AR |
2500 | |
2501 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2502 | pdev = sbridge_dev->pdev[i]; | |
2503 | if (!pdev) | |
2504 | continue; | |
4d715a80 | 2505 | |
dbc954dd AR |
2506 | switch (pdev->device) { |
2507 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: | |
2508 | pvt->pci_ha0 = pdev; | |
2509 | break; | |
2510 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
2511 | pvt->pci_ta = pdev; | |
2512 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: | |
2513 | pvt->pci_ras = pdev; | |
2514 | break; | |
dbc954dd AR |
2515 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: |
2516 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: | |
7d375bff TL |
2517 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: |
2518 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: | |
dbc954dd AR |
2519 | { |
2520 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; | |
2521 | pvt->pci_tad[id] = pdev; | |
7d375bff | 2522 | saw_chan_mask |= 1 << id; |
dbc954dd | 2523 | } |
4d715a80 | 2524 | break; |
dbc954dd AR |
2525 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
2526 | pvt->pci_ddrio = pdev; | |
2527 | break; | |
2528 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: | |
7d375bff | 2529 | pvt->pci_ddrio = pdev; |
4d715a80 | 2530 | break; |
dbc954dd AR |
2531 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
2532 | pvt->pci_sad0 = pdev; | |
2533 | break; | |
2534 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: | |
2535 | pvt->pci_br0 = pdev; | |
2536 | break; | |
2537 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: | |
2538 | pvt->pci_br1 = pdev; | |
2539 | break; | |
2540 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: | |
2541 | pvt->pci_ha1 = pdev; | |
2542 | break; | |
2543 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: | |
2544 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: | |
7d375bff TL |
2545 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: |
2546 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: | |
dbc954dd | 2547 | { |
7d375bff | 2548 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4; |
dbc954dd | 2549 | pvt->pci_tad[id] = pdev; |
7d375bff | 2550 | saw_chan_mask |= 1 << id; |
dbc954dd AR |
2551 | } |
2552 | break; | |
4d715a80 AR |
2553 | default: |
2554 | goto error; | |
2555 | } | |
2556 | ||
2557 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2558 | sbridge_dev->bus, | |
2559 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2560 | pdev); | |
2561 | } | |
2562 | ||
2563 | /* Check if everything were registered */ | |
2564 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || | |
2565 | !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || | |
2566 | !pvt->pci_ta) | |
2567 | goto enodev; | |
2568 | ||
7d375bff TL |
2569 | if (saw_chan_mask != 0x0f && /* -EN */ |
2570 | saw_chan_mask != 0x33 && /* -EP */ | |
2571 | saw_chan_mask != 0xff) /* -EX */ | |
2572 | goto enodev; | |
4d715a80 AR |
2573 | return 0; |
2574 | ||
2575 | enodev: | |
2576 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2577 | return -ENODEV; | |
2578 | ||
2579 | error: | |
2580 | sbridge_printk(KERN_ERR, | |
dbc954dd AR |
2581 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
2582 | pdev->device); | |
4d715a80 AR |
2583 | return -EINVAL; |
2584 | } | |
2585 | ||
50d1bb93 AR |
2586 | static int haswell_mci_bind_devs(struct mem_ctl_info *mci, |
2587 | struct sbridge_dev *sbridge_dev) | |
2588 | { | |
2589 | struct sbridge_pvt *pvt = mci->pvt_info; | |
7d375bff TL |
2590 | struct pci_dev *pdev; |
2591 | u8 saw_chan_mask = 0; | |
50d1bb93 | 2592 | int i; |
50d1bb93 AR |
2593 | |
2594 | /* there's only one device per system; not tied to any bus */ | |
2595 | if (pvt->info.pci_vtd == NULL) | |
2596 | /* result will be checked later */ | |
2597 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
2598 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, | |
2599 | NULL); | |
2600 | ||
2601 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2602 | pdev = sbridge_dev->pdev[i]; | |
2603 | if (!pdev) | |
2604 | continue; | |
2605 | ||
2606 | switch (pdev->device) { | |
2607 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: | |
2608 | pvt->pci_sad0 = pdev; | |
2609 | break; | |
2610 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: | |
2611 | pvt->pci_sad1 = pdev; | |
2612 | break; | |
2613 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
2614 | pvt->pci_ha0 = pdev; | |
2615 | break; | |
2616 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: | |
2617 | pvt->pci_ta = pdev; | |
2618 | break; | |
2619 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: | |
2620 | pvt->pci_ras = pdev; | |
2621 | break; | |
2622 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: | |
50d1bb93 | 2623 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: |
50d1bb93 | 2624 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: |
50d1bb93 | 2625 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: |
7d375bff TL |
2626 | { |
2627 | int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0; | |
2628 | ||
2629 | pvt->pci_tad[id] = pdev; | |
2630 | saw_chan_mask |= 1 << id; | |
2631 | } | |
2632 | break; | |
2633 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: | |
2634 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: | |
2635 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: | |
2636 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: | |
2637 | { | |
2638 | int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4; | |
2639 | ||
2640 | pvt->pci_tad[id] = pdev; | |
2641 | saw_chan_mask |= 1 << id; | |
2642 | } | |
50d1bb93 AR |
2643 | break; |
2644 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: | |
7179385a AR |
2645 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1: |
2646 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2: | |
2647 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3: | |
2648 | if (!pvt->pci_ddrio) | |
2649 | pvt->pci_ddrio = pdev; | |
50d1bb93 AR |
2650 | break; |
2651 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: | |
2652 | pvt->pci_ha1 = pdev; | |
2653 | break; | |
2654 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: | |
2655 | pvt->pci_ha1_ta = pdev; | |
2656 | break; | |
50d1bb93 AR |
2657 | default: |
2658 | break; | |
2659 | } | |
2660 | ||
2661 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2662 | sbridge_dev->bus, | |
2663 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2664 | pdev); | |
2665 | } | |
2666 | ||
2667 | /* Check if everything were registered */ | |
2668 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || | |
2669 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) | |
2670 | goto enodev; | |
2671 | ||
7d375bff TL |
2672 | if (saw_chan_mask != 0x0f && /* -EN */ |
2673 | saw_chan_mask != 0x33 && /* -EP */ | |
2674 | saw_chan_mask != 0xff) /* -EX */ | |
2675 | goto enodev; | |
50d1bb93 AR |
2676 | return 0; |
2677 | ||
2678 | enodev: | |
2679 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2680 | return -ENODEV; | |
2681 | } | |
2682 | ||
1f39581a TL |
2683 | static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, |
2684 | struct sbridge_dev *sbridge_dev) | |
2685 | { | |
2686 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2687 | struct pci_dev *pdev; | |
fa2ce64f | 2688 | u8 saw_chan_mask = 0; |
1f39581a TL |
2689 | int i; |
2690 | ||
2691 | /* there's only one device per system; not tied to any bus */ | |
2692 | if (pvt->info.pci_vtd == NULL) | |
2693 | /* result will be checked later */ | |
2694 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
2695 | PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, | |
2696 | NULL); | |
2697 | ||
2698 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2699 | pdev = sbridge_dev->pdev[i]; | |
2700 | if (!pdev) | |
2701 | continue; | |
2702 | ||
2703 | switch (pdev->device) { | |
2704 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: | |
2705 | pvt->pci_sad0 = pdev; | |
2706 | break; | |
2707 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: | |
2708 | pvt->pci_sad1 = pdev; | |
2709 | break; | |
2710 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: | |
2711 | pvt->pci_ha0 = pdev; | |
2712 | break; | |
2713 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: | |
2714 | pvt->pci_ta = pdev; | |
2715 | break; | |
2716 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL: | |
2717 | pvt->pci_ras = pdev; | |
2718 | break; | |
2719 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: | |
1f39581a | 2720 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: |
1f39581a | 2721 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: |
1f39581a | 2722 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: |
fa2ce64f TL |
2723 | { |
2724 | int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0; | |
2725 | pvt->pci_tad[id] = pdev; | |
2726 | saw_chan_mask |= 1 << id; | |
2727 | } | |
2728 | break; | |
2729 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0: | |
2730 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1: | |
2731 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2: | |
2732 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3: | |
2733 | { | |
2734 | int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4; | |
2735 | pvt->pci_tad[id] = pdev; | |
2736 | saw_chan_mask |= 1 << id; | |
2737 | } | |
1f39581a TL |
2738 | break; |
2739 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: | |
2740 | pvt->pci_ddrio = pdev; | |
2741 | break; | |
fa2ce64f TL |
2742 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1: |
2743 | pvt->pci_ha1 = pdev; | |
2744 | break; | |
2745 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA: | |
2746 | pvt->pci_ha1_ta = pdev; | |
2747 | break; | |
1f39581a TL |
2748 | default: |
2749 | break; | |
2750 | } | |
2751 | ||
2752 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2753 | sbridge_dev->bus, | |
2754 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2755 | pdev); | |
2756 | } | |
2757 | ||
2758 | /* Check if everything were registered */ | |
2759 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || | |
2760 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) | |
2761 | goto enodev; | |
2762 | ||
fa2ce64f TL |
2763 | if (saw_chan_mask != 0x0f && /* -EN */ |
2764 | saw_chan_mask != 0x33 && /* -EP */ | |
2765 | saw_chan_mask != 0xff) /* -EX */ | |
2766 | goto enodev; | |
1f39581a TL |
2767 | return 0; |
2768 | ||
2769 | enodev: | |
2770 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2771 | return -ENODEV; | |
2772 | } | |
2773 | ||
d0cdf900 JS |
2774 | static int knl_mci_bind_devs(struct mem_ctl_info *mci, |
2775 | struct sbridge_dev *sbridge_dev) | |
2776 | { | |
2777 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2778 | struct pci_dev *pdev; | |
2779 | int dev, func; | |
2780 | ||
2781 | int i; | |
2782 | int devidx; | |
2783 | ||
2784 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2785 | pdev = sbridge_dev->pdev[i]; | |
2786 | if (!pdev) | |
2787 | continue; | |
2788 | ||
2789 | /* Extract PCI device and function. */ | |
2790 | dev = (pdev->devfn >> 3) & 0x1f; | |
2791 | func = pdev->devfn & 0x7; | |
2792 | ||
2793 | switch (pdev->device) { | |
2794 | case PCI_DEVICE_ID_INTEL_KNL_IMC_MC: | |
2795 | if (dev == 8) | |
2796 | pvt->knl.pci_mc0 = pdev; | |
2797 | else if (dev == 9) | |
2798 | pvt->knl.pci_mc1 = pdev; | |
2799 | else { | |
2800 | sbridge_printk(KERN_ERR, | |
2801 | "Memory controller in unexpected place! (dev %d, fn %d)\n", | |
2802 | dev, func); | |
2803 | continue; | |
2804 | } | |
2805 | break; | |
2806 | ||
2807 | case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0: | |
2808 | pvt->pci_sad0 = pdev; | |
2809 | break; | |
2810 | ||
2811 | case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1: | |
2812 | pvt->pci_sad1 = pdev; | |
2813 | break; | |
2814 | ||
2815 | case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA: | |
2816 | /* There are one of these per tile, and range from | |
2817 | * 1.14.0 to 1.18.5. | |
2818 | */ | |
2819 | devidx = ((dev-14)*8)+func; | |
2820 | ||
2821 | if (devidx < 0 || devidx >= KNL_MAX_CHAS) { | |
2822 | sbridge_printk(KERN_ERR, | |
2823 | "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n", | |
2824 | dev, func); | |
2825 | continue; | |
2826 | } | |
2827 | ||
2828 | WARN_ON(pvt->knl.pci_cha[devidx] != NULL); | |
2829 | ||
2830 | pvt->knl.pci_cha[devidx] = pdev; | |
2831 | break; | |
2832 | ||
2833 | case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL: | |
2834 | devidx = -1; | |
2835 | ||
2836 | /* | |
2837 | * MC0 channels 0-2 are device 9 function 2-4, | |
2838 | * MC1 channels 3-5 are device 8 function 2-4. | |
2839 | */ | |
2840 | ||
2841 | if (dev == 9) | |
2842 | devidx = func-2; | |
2843 | else if (dev == 8) | |
2844 | devidx = 3 + (func-2); | |
2845 | ||
2846 | if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) { | |
2847 | sbridge_printk(KERN_ERR, | |
2848 | "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n", | |
2849 | dev, func); | |
2850 | continue; | |
2851 | } | |
2852 | ||
2853 | WARN_ON(pvt->knl.pci_channel[devidx] != NULL); | |
2854 | pvt->knl.pci_channel[devidx] = pdev; | |
2855 | break; | |
2856 | ||
2857 | case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM: | |
2858 | pvt->knl.pci_mc_info = pdev; | |
2859 | break; | |
2860 | ||
2861 | case PCI_DEVICE_ID_INTEL_KNL_IMC_TA: | |
2862 | pvt->pci_ta = pdev; | |
2863 | break; | |
2864 | ||
2865 | default: | |
2866 | sbridge_printk(KERN_ERR, "Unexpected device %d\n", | |
2867 | pdev->device); | |
2868 | break; | |
2869 | } | |
2870 | } | |
2871 | ||
2872 | if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || | |
2873 | !pvt->pci_sad0 || !pvt->pci_sad1 || | |
2874 | !pvt->pci_ta) { | |
2875 | goto enodev; | |
2876 | } | |
2877 | ||
2878 | for (i = 0; i < KNL_MAX_CHANNELS; i++) { | |
2879 | if (!pvt->knl.pci_channel[i]) { | |
2880 | sbridge_printk(KERN_ERR, "Missing channel %d\n", i); | |
2881 | goto enodev; | |
2882 | } | |
2883 | } | |
2884 | ||
2885 | for (i = 0; i < KNL_MAX_CHAS; i++) { | |
2886 | if (!pvt->knl.pci_cha[i]) { | |
2887 | sbridge_printk(KERN_ERR, "Missing CHA %d\n", i); | |
2888 | goto enodev; | |
2889 | } | |
2890 | } | |
2891 | ||
2892 | return 0; | |
2893 | ||
2894 | enodev: | |
2895 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2896 | return -ENODEV; | |
2897 | } | |
2898 | ||
eebf11a0 MCC |
2899 | /**************************************************************************** |
2900 | Error check routines | |
2901 | ****************************************************************************/ | |
2902 | ||
2903 | /* | |
2904 | * While Sandy Bridge has error count registers, SMI BIOS read values from | |
2905 | * and resets the counters. So, they are not reliable for the OS to read | |
2906 | * from them. So, we have no option but to just trust on whatever MCE is | |
2907 | * telling us about the errors. | |
2908 | */ | |
2909 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |
2910 | const struct mce *m) | |
2911 | { | |
2912 | struct mem_ctl_info *new_mci; | |
2913 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 2914 | enum hw_event_mc_err_type tp_event; |
e17a2f42 | 2915 | char *type, *optype, msg[256]; |
eebf11a0 MCC |
2916 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
2917 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
2918 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
4d715a80 | 2919 | bool recoverable; |
eebf11a0 MCC |
2920 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
2921 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
2922 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
2923 | u32 channel = GET_BITFIELD(m->status, 0, 3); | |
2924 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
2925 | long channel_mask, first_channel; | |
7d375bff | 2926 | u8 rank, socket, ha; |
c36e3e77 | 2927 | int rc, dimm; |
e17a2f42 | 2928 | char *area_type = NULL; |
eebf11a0 | 2929 | |
fa2ce64f | 2930 | if (pvt->info.type != SANDY_BRIDGE) |
4d715a80 AR |
2931 | recoverable = true; |
2932 | else | |
2933 | recoverable = GET_BITFIELD(m->status, 56, 56); | |
2934 | ||
c36e3e77 MCC |
2935 | if (uncorrected_error) { |
2936 | if (ripv) { | |
2937 | type = "FATAL"; | |
2938 | tp_event = HW_EVENT_ERR_FATAL; | |
2939 | } else { | |
2940 | type = "NON_FATAL"; | |
2941 | tp_event = HW_EVENT_ERR_UNCORRECTED; | |
2942 | } | |
2943 | } else { | |
2944 | type = "CORRECTED"; | |
2945 | tp_event = HW_EVENT_ERR_CORRECTED; | |
2946 | } | |
eebf11a0 MCC |
2947 | |
2948 | /* | |
15ed103a | 2949 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
eebf11a0 MCC |
2950 | * memory errors should fit in this mask: |
2951 | * 000f 0000 1mmm cccc (binary) | |
2952 | * where: | |
2953 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
2954 | * won't be shown | |
2955 | * mmm = error type | |
2956 | * cccc = channel | |
2957 | * If the mask doesn't match, report an error to the parsing logic | |
2958 | */ | |
2959 | if (! ((errcode & 0xef80) == 0x80)) { | |
2960 | optype = "Can't parse: it is not a mem"; | |
2961 | } else { | |
2962 | switch (optypenum) { | |
2963 | case 0: | |
c36e3e77 | 2964 | optype = "generic undef request error"; |
eebf11a0 MCC |
2965 | break; |
2966 | case 1: | |
c36e3e77 | 2967 | optype = "memory read error"; |
eebf11a0 MCC |
2968 | break; |
2969 | case 2: | |
c36e3e77 | 2970 | optype = "memory write error"; |
eebf11a0 MCC |
2971 | break; |
2972 | case 3: | |
c36e3e77 | 2973 | optype = "addr/cmd error"; |
eebf11a0 MCC |
2974 | break; |
2975 | case 4: | |
c36e3e77 | 2976 | optype = "memory scrubbing error"; |
eebf11a0 MCC |
2977 | break; |
2978 | default: | |
2979 | optype = "reserved"; | |
2980 | break; | |
2981 | } | |
2982 | } | |
2983 | ||
be3036d2 AR |
2984 | /* Only decode errors with an valid address (ADDRV) */ |
2985 | if (!GET_BITFIELD(m->status, 58, 58)) | |
2986 | return; | |
2987 | ||
d0cdf900 JS |
2988 | if (pvt->info.type == KNIGHTS_LANDING) { |
2989 | if (channel == 14) { | |
2990 | edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n", | |
2991 | overflow ? " OVERFLOW" : "", | |
2992 | (uncorrected_error && recoverable) | |
2993 | ? " recoverable" : "", | |
2994 | mscod, errcode, | |
2995 | m->bank); | |
2996 | } else { | |
2997 | char A = *("A"); | |
2998 | ||
2999 | channel = knl_channel_remap(channel); | |
3000 | channel_mask = 1 << channel; | |
3001 | snprintf(msg, sizeof(msg), | |
3002 | "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)", | |
3003 | overflow ? " OVERFLOW" : "", | |
3004 | (uncorrected_error && recoverable) | |
3005 | ? " recoverable" : " ", | |
3006 | mscod, errcode, channel, A + channel); | |
3007 | edac_mc_handle_error(tp_event, mci, core_err_cnt, | |
3008 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, | |
3009 | channel, 0, -1, | |
3010 | optype, msg); | |
3011 | } | |
3012 | return; | |
3013 | } else { | |
3014 | rc = get_memory_error_data(mci, m->addr, &socket, &ha, | |
3015 | &channel_mask, &rank, &area_type, msg); | |
3016 | } | |
3017 | ||
eebf11a0 | 3018 | if (rc < 0) |
c36e3e77 | 3019 | goto err_parsing; |
eebf11a0 MCC |
3020 | new_mci = get_mci_for_node_id(socket); |
3021 | if (!new_mci) { | |
c36e3e77 MCC |
3022 | strcpy(msg, "Error: socket got corrupted!"); |
3023 | goto err_parsing; | |
eebf11a0 MCC |
3024 | } |
3025 | mci = new_mci; | |
3026 | pvt = mci->pvt_info; | |
3027 | ||
3028 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); | |
3029 | ||
3030 | if (rank < 4) | |
3031 | dimm = 0; | |
3032 | else if (rank < 8) | |
3033 | dimm = 1; | |
3034 | else | |
3035 | dimm = 2; | |
3036 | ||
eebf11a0 MCC |
3037 | |
3038 | /* | |
e17a2f42 MCC |
3039 | * FIXME: On some memory configurations (mirror, lockstep), the |
3040 | * Memory Controller can't point the error to a single DIMM. The | |
3041 | * EDAC core should be handling the channel mask, in order to point | |
3042 | * to the group of dimm's where the error may be happening. | |
eebf11a0 | 3043 | */ |
d7c660b7 AR |
3044 | if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) |
3045 | channel = first_channel; | |
3046 | ||
c36e3e77 | 3047 | snprintf(msg, sizeof(msg), |
7d375bff | 3048 | "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d", |
e17a2f42 MCC |
3049 | overflow ? " OVERFLOW" : "", |
3050 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
3051 | area_type, | |
3052 | mscod, errcode, | |
7d375bff | 3053 | socket, ha, |
e17a2f42 MCC |
3054 | channel_mask, |
3055 | rank); | |
eebf11a0 | 3056 | |
956b9ba1 | 3057 | edac_dbg(0, "%s\n", msg); |
eebf11a0 | 3058 | |
c36e3e77 MCC |
3059 | /* FIXME: need support for channel mask */ |
3060 | ||
351fc4a9 SJ |
3061 | if (channel == CHANNEL_UNSPECIFIED) |
3062 | channel = -1; | |
3063 | ||
eebf11a0 | 3064 | /* Call the helper to output message */ |
c1053839 | 3065 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
c36e3e77 | 3066 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
7d375bff | 3067 | 4*ha+channel, dimm, -1, |
03f7eae8 | 3068 | optype, msg); |
c36e3e77 MCC |
3069 | return; |
3070 | err_parsing: | |
c1053839 | 3071 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
c36e3e77 | 3072 | -1, -1, -1, |
03f7eae8 | 3073 | msg, ""); |
eebf11a0 | 3074 | |
eebf11a0 MCC |
3075 | } |
3076 | ||
3077 | /* | |
ad08c4e9 TL |
3078 | * Check that logging is enabled and that this is the right type |
3079 | * of error for us to handle. | |
eebf11a0 | 3080 | */ |
3d78c9af MCC |
3081 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
3082 | void *data) | |
eebf11a0 | 3083 | { |
3d78c9af MCC |
3084 | struct mce *mce = (struct mce *)data; |
3085 | struct mem_ctl_info *mci; | |
3086 | struct sbridge_pvt *pvt; | |
cf40f80c | 3087 | char *type; |
3d78c9af | 3088 | |
fd521039 CG |
3089 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
3090 | return NOTIFY_DONE; | |
3091 | ||
3d78c9af MCC |
3092 | mci = get_mci_for_node_id(mce->socketid); |
3093 | if (!mci) | |
c4fc1956 | 3094 | return NOTIFY_DONE; |
3d78c9af | 3095 | pvt = mci->pvt_info; |
eebf11a0 MCC |
3096 | |
3097 | /* | |
3098 | * Just let mcelog handle it if the error is | |
3099 | * outside the memory controller. A memory error | |
3100 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. | |
3101 | * bit 12 has an special meaning. | |
3102 | */ | |
3103 | if ((mce->status & 0xefff) >> 7 != 1) | |
3d78c9af | 3104 | return NOTIFY_DONE; |
eebf11a0 | 3105 | |
cf40f80c AR |
3106 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
3107 | type = "Exception"; | |
3108 | else | |
3109 | type = "Event"; | |
3110 | ||
49856dc9 | 3111 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
eebf11a0 | 3112 | |
49856dc9 AR |
3113 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
3114 | "Bank %d: %016Lx\n", mce->extcpu, type, | |
3115 | mce->mcgstatus, mce->bank, mce->status); | |
3116 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); | |
3117 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); | |
3118 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); | |
eebf11a0 | 3119 | |
49856dc9 AR |
3120 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
3121 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, | |
3122 | mce->time, mce->socketid, mce->apicid); | |
eebf11a0 | 3123 | |
ad08c4e9 | 3124 | sbridge_mce_output_error(mci, mce); |
eebf11a0 MCC |
3125 | |
3126 | /* Advice mcelog that the error were handled */ | |
3d78c9af | 3127 | return NOTIFY_STOP; |
eebf11a0 MCC |
3128 | } |
3129 | ||
3d78c9af MCC |
3130 | static struct notifier_block sbridge_mce_dec = { |
3131 | .notifier_call = sbridge_mce_check_error, | |
3132 | }; | |
3133 | ||
eebf11a0 MCC |
3134 | /**************************************************************************** |
3135 | EDAC register/unregister logic | |
3136 | ****************************************************************************/ | |
3137 | ||
3138 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |
3139 | { | |
3140 | struct mem_ctl_info *mci = sbridge_dev->mci; | |
3141 | struct sbridge_pvt *pvt; | |
3142 | ||
3143 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 3144 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
eebf11a0 MCC |
3145 | |
3146 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
3147 | return; | |
3148 | } | |
3149 | ||
3150 | pvt = mci->pvt_info; | |
3151 | ||
956b9ba1 JP |
3152 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
3153 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 | 3154 | |
eebf11a0 | 3155 | /* Remove MC sysfs nodes */ |
fd687502 | 3156 | edac_mc_del_mc(mci->pdev); |
eebf11a0 | 3157 | |
956b9ba1 | 3158 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
eebf11a0 MCC |
3159 | kfree(mci->ctl_name); |
3160 | edac_mc_free(mci); | |
3161 | sbridge_dev->mci = NULL; | |
3162 | } | |
3163 | ||
4d715a80 | 3164 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
eebf11a0 MCC |
3165 | { |
3166 | struct mem_ctl_info *mci; | |
c36e3e77 | 3167 | struct edac_mc_layer layers[2]; |
eebf11a0 | 3168 | struct sbridge_pvt *pvt; |
4d715a80 | 3169 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
c36e3e77 | 3170 | int rc; |
eebf11a0 MCC |
3171 | |
3172 | /* Check the number of active and not disabled channels */ | |
dbc954dd | 3173 | rc = check_if_ecc_is_active(sbridge_dev->bus, type); |
eebf11a0 MCC |
3174 | if (unlikely(rc < 0)) |
3175 | return rc; | |
3176 | ||
3177 | /* allocate a new MC control structure */ | |
c36e3e77 | 3178 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
d0cdf900 JS |
3179 | layers[0].size = type == KNIGHTS_LANDING ? |
3180 | KNL_MAX_CHANNELS : NUM_CHANNELS; | |
c36e3e77 MCC |
3181 | layers[0].is_virt_csrow = false; |
3182 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
d0cdf900 | 3183 | layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; |
c36e3e77 | 3184 | layers[1].is_virt_csrow = true; |
ca0907b9 | 3185 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
c36e3e77 MCC |
3186 | sizeof(*pvt)); |
3187 | ||
eebf11a0 MCC |
3188 | if (unlikely(!mci)) |
3189 | return -ENOMEM; | |
3190 | ||
956b9ba1 | 3191 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
4d715a80 | 3192 | mci, &pdev->dev); |
eebf11a0 MCC |
3193 | |
3194 | pvt = mci->pvt_info; | |
3195 | memset(pvt, 0, sizeof(*pvt)); | |
3196 | ||
3197 | /* Associate sbridge_dev and mci for future usage */ | |
3198 | pvt->sbridge_dev = sbridge_dev; | |
3199 | sbridge_dev->mci = mci; | |
3200 | ||
d0cdf900 JS |
3201 | mci->mtype_cap = type == KNIGHTS_LANDING ? |
3202 | MEM_FLAG_DDR4 : MEM_FLAG_DDR3; | |
eebf11a0 MCC |
3203 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
3204 | mci->edac_cap = EDAC_FLAG_NONE; | |
3205 | mci->mod_name = "sbridge_edac.c"; | |
3206 | mci->mod_ver = SBRIDGE_REVISION; | |
4d715a80 | 3207 | mci->dev_name = pci_name(pdev); |
eebf11a0 MCC |
3208 | mci->ctl_page_to_phys = NULL; |
3209 | ||
4d715a80 | 3210 | pvt->info.type = type; |
50d1bb93 AR |
3211 | switch (type) { |
3212 | case IVY_BRIDGE: | |
4d715a80 AR |
3213 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
3214 | pvt->info.get_tolm = ibridge_get_tolm; | |
3215 | pvt->info.get_tohm = ibridge_get_tohm; | |
3216 | pvt->info.dram_rule = ibridge_dram_rule; | |
9e375446 | 3217 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 3218 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 3219 | pvt->info.rir_limit = rir_limit; |
c59f9c06 JS |
3220 | pvt->info.sad_limit = sad_limit; |
3221 | pvt->info.interleave_mode = interleave_mode; | |
3222 | pvt->info.show_interleave_mode = show_interleave_mode; | |
3223 | pvt->info.dram_attr = dram_attr; | |
4d715a80 AR |
3224 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
3225 | pvt->info.interleave_list = ibridge_interleave_list; | |
3226 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
3227 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
12f0721c | 3228 | pvt->info.get_width = ibridge_get_width; |
4d715a80 AR |
3229 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx); |
3230 | ||
3231 | /* Store pci devices at mci for faster access */ | |
3232 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); | |
3233 | if (unlikely(rc < 0)) | |
3234 | goto fail0; | |
50d1bb93 AR |
3235 | break; |
3236 | case SANDY_BRIDGE: | |
4d715a80 AR |
3237 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
3238 | pvt->info.get_tolm = sbridge_get_tolm; | |
3239 | pvt->info.get_tohm = sbridge_get_tohm; | |
3240 | pvt->info.dram_rule = sbridge_dram_rule; | |
9e375446 | 3241 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 3242 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 3243 | pvt->info.rir_limit = rir_limit; |
c59f9c06 JS |
3244 | pvt->info.sad_limit = sad_limit; |
3245 | pvt->info.interleave_mode = interleave_mode; | |
3246 | pvt->info.show_interleave_mode = show_interleave_mode; | |
3247 | pvt->info.dram_attr = dram_attr; | |
4d715a80 AR |
3248 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
3249 | pvt->info.interleave_list = sbridge_interleave_list; | |
3250 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); | |
3251 | pvt->info.interleave_pkg = sbridge_interleave_pkg; | |
12f0721c | 3252 | pvt->info.get_width = sbridge_get_width; |
4d715a80 AR |
3253 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); |
3254 | ||
3255 | /* Store pci devices at mci for faster access */ | |
3256 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); | |
3257 | if (unlikely(rc < 0)) | |
3258 | goto fail0; | |
50d1bb93 AR |
3259 | break; |
3260 | case HASWELL: | |
3261 | /* rankcfgr isn't used */ | |
3262 | pvt->info.get_tolm = haswell_get_tolm; | |
3263 | pvt->info.get_tohm = haswell_get_tohm; | |
3264 | pvt->info.dram_rule = ibridge_dram_rule; | |
3265 | pvt->info.get_memory_type = haswell_get_memory_type; | |
3266 | pvt->info.get_node_id = haswell_get_node_id; | |
3267 | pvt->info.rir_limit = haswell_rir_limit; | |
c59f9c06 JS |
3268 | pvt->info.sad_limit = sad_limit; |
3269 | pvt->info.interleave_mode = interleave_mode; | |
3270 | pvt->info.show_interleave_mode = show_interleave_mode; | |
3271 | pvt->info.dram_attr = dram_attr; | |
50d1bb93 AR |
3272 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
3273 | pvt->info.interleave_list = ibridge_interleave_list; | |
3274 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
3275 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
12f0721c | 3276 | pvt->info.get_width = ibridge_get_width; |
50d1bb93 | 3277 | mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx); |
4d715a80 | 3278 | |
50d1bb93 AR |
3279 | /* Store pci devices at mci for faster access */ |
3280 | rc = haswell_mci_bind_devs(mci, sbridge_dev); | |
3281 | if (unlikely(rc < 0)) | |
3282 | goto fail0; | |
3283 | break; | |
1f39581a TL |
3284 | case BROADWELL: |
3285 | /* rankcfgr isn't used */ | |
3286 | pvt->info.get_tolm = haswell_get_tolm; | |
3287 | pvt->info.get_tohm = haswell_get_tohm; | |
3288 | pvt->info.dram_rule = ibridge_dram_rule; | |
3289 | pvt->info.get_memory_type = haswell_get_memory_type; | |
3290 | pvt->info.get_node_id = haswell_get_node_id; | |
3291 | pvt->info.rir_limit = haswell_rir_limit; | |
c59f9c06 JS |
3292 | pvt->info.sad_limit = sad_limit; |
3293 | pvt->info.interleave_mode = interleave_mode; | |
3294 | pvt->info.show_interleave_mode = show_interleave_mode; | |
3295 | pvt->info.dram_attr = dram_attr; | |
1f39581a TL |
3296 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
3297 | pvt->info.interleave_list = ibridge_interleave_list; | |
3298 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
3299 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
12f0721c | 3300 | pvt->info.get_width = broadwell_get_width; |
1f39581a TL |
3301 | mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx); |
3302 | ||
3303 | /* Store pci devices at mci for faster access */ | |
3304 | rc = broadwell_mci_bind_devs(mci, sbridge_dev); | |
3305 | if (unlikely(rc < 0)) | |
3306 | goto fail0; | |
3307 | break; | |
d0cdf900 JS |
3308 | case KNIGHTS_LANDING: |
3309 | /* pvt->info.rankcfgr == ??? */ | |
3310 | pvt->info.get_tolm = knl_get_tolm; | |
3311 | pvt->info.get_tohm = knl_get_tohm; | |
3312 | pvt->info.dram_rule = knl_dram_rule; | |
3313 | pvt->info.get_memory_type = knl_get_memory_type; | |
3314 | pvt->info.get_node_id = knl_get_node_id; | |
3315 | pvt->info.rir_limit = NULL; | |
3316 | pvt->info.sad_limit = knl_sad_limit; | |
3317 | pvt->info.interleave_mode = knl_interleave_mode; | |
3318 | pvt->info.show_interleave_mode = knl_show_interleave_mode; | |
3319 | pvt->info.dram_attr = dram_attr_knl; | |
3320 | pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); | |
3321 | pvt->info.interleave_list = knl_interleave_list; | |
3322 | pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list); | |
3323 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
45f4d3ab | 3324 | pvt->info.get_width = knl_get_width; |
d0cdf900 JS |
3325 | mci->ctl_name = kasprintf(GFP_KERNEL, |
3326 | "Knights Landing Socket#%d", mci->mc_idx); | |
3327 | ||
3328 | rc = knl_mci_bind_devs(mci, sbridge_dev); | |
3329 | if (unlikely(rc < 0)) | |
3330 | goto fail0; | |
3331 | break; | |
50d1bb93 | 3332 | } |
eebf11a0 MCC |
3333 | |
3334 | /* Get dimm basic config and the memory layout */ | |
3335 | get_dimm_config(mci); | |
3336 | get_memory_layout(mci); | |
3337 | ||
3338 | /* record ptr to the generic device */ | |
4d715a80 | 3339 | mci->pdev = &pdev->dev; |
eebf11a0 MCC |
3340 | |
3341 | /* add this new MC control structure to EDAC's list of MCs */ | |
3342 | if (unlikely(edac_mc_add_mc(mci))) { | |
956b9ba1 | 3343 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
eebf11a0 MCC |
3344 | rc = -EINVAL; |
3345 | goto fail0; | |
3346 | } | |
3347 | ||
eebf11a0 | 3348 | return 0; |
eebf11a0 MCC |
3349 | |
3350 | fail0: | |
3351 | kfree(mci->ctl_name); | |
3352 | edac_mc_free(mci); | |
3353 | sbridge_dev->mci = NULL; | |
3354 | return rc; | |
3355 | } | |
3356 | ||
2c1ea4c7 TL |
3357 | #define ICPU(model, table) \ |
3358 | { X86_VENDOR_INTEL, 6, model, 0, (unsigned long)&table } | |
3359 | ||
3360 | /* Order here must match "enum type" */ | |
3361 | static const struct x86_cpu_id sbridge_cpuids[] = { | |
3362 | ICPU(0x2d, pci_dev_descr_sbridge_table), /* SANDY_BRIDGE */ | |
3363 | ICPU(0x3e, pci_dev_descr_ibridge_table), /* IVY_BRIDGE */ | |
3364 | ICPU(0x3f, pci_dev_descr_haswell_table), /* HASWELL */ | |
3365 | ICPU(0x4f, pci_dev_descr_broadwell_table), /* BROADWELL */ | |
3366 | ICPU(0x57, pci_dev_descr_knl_table), /* KNIGHTS_LANDING */ | |
3367 | { } | |
3368 | }; | |
3369 | MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids); | |
3370 | ||
eebf11a0 | 3371 | /* |
2c1ea4c7 | 3372 | * sbridge_probe Get all devices and register memory controllers |
eebf11a0 MCC |
3373 | * present. |
3374 | * return: | |
3375 | * 0 for FOUND a device | |
3376 | * < 0 for error code | |
3377 | */ | |
3378 | ||
2c1ea4c7 | 3379 | static int sbridge_probe(const struct x86_cpu_id *id) |
eebf11a0 | 3380 | { |
50d1bb93 | 3381 | int rc = -ENODEV; |
eebf11a0 MCC |
3382 | u8 mc, num_mc = 0; |
3383 | struct sbridge_dev *sbridge_dev; | |
2c1ea4c7 | 3384 | struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; |
eebf11a0 MCC |
3385 | |
3386 | /* get the pci devices we want to reserve for our use */ | |
2c1ea4c7 | 3387 | rc = sbridge_get_all_devices(&num_mc, ptable); |
eebf11a0 | 3388 | |
11249e73 | 3389 | if (unlikely(rc < 0)) { |
2c1ea4c7 | 3390 | edac_dbg(0, "couldn't get all devices\n"); |
eebf11a0 | 3391 | goto fail0; |
11249e73 BP |
3392 | } |
3393 | ||
eebf11a0 MCC |
3394 | mc = 0; |
3395 | ||
3396 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
956b9ba1 JP |
3397 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
3398 | mc, mc + 1, num_mc); | |
50d1bb93 | 3399 | |
eebf11a0 | 3400 | sbridge_dev->mc = mc++; |
2c1ea4c7 | 3401 | rc = sbridge_register_mci(sbridge_dev, id - sbridge_cpuids); |
eebf11a0 MCC |
3402 | if (unlikely(rc < 0)) |
3403 | goto fail1; | |
3404 | } | |
3405 | ||
11249e73 | 3406 | sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); |
eebf11a0 | 3407 | |
eebf11a0 MCC |
3408 | return 0; |
3409 | ||
3410 | fail1: | |
3411 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
3412 | sbridge_unregister_mci(sbridge_dev); | |
3413 | ||
3414 | sbridge_put_all_devices(); | |
3415 | fail0: | |
eebf11a0 MCC |
3416 | return rc; |
3417 | } | |
3418 | ||
3419 | /* | |
2c1ea4c7 | 3420 | * sbridge_remove cleanup |
eebf11a0 MCC |
3421 | * |
3422 | */ | |
2c1ea4c7 | 3423 | static void sbridge_remove(void) |
eebf11a0 MCC |
3424 | { |
3425 | struct sbridge_dev *sbridge_dev; | |
3426 | ||
956b9ba1 | 3427 | edac_dbg(0, "\n"); |
eebf11a0 | 3428 | |
eebf11a0 MCC |
3429 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
3430 | sbridge_unregister_mci(sbridge_dev); | |
3431 | ||
3432 | /* Release PCI resources */ | |
3433 | sbridge_put_all_devices(); | |
eebf11a0 MCC |
3434 | } |
3435 | ||
eebf11a0 MCC |
3436 | /* |
3437 | * sbridge_init Module entry function | |
3438 | * Try to initialize this module for its devices | |
3439 | */ | |
3440 | static int __init sbridge_init(void) | |
3441 | { | |
2c1ea4c7 TL |
3442 | const struct x86_cpu_id *id; |
3443 | int rc; | |
eebf11a0 | 3444 | |
956b9ba1 | 3445 | edac_dbg(2, "\n"); |
eebf11a0 | 3446 | |
2c1ea4c7 TL |
3447 | id = x86_match_cpu(sbridge_cpuids); |
3448 | if (!id) | |
3449 | return -ENODEV; | |
3450 | ||
eebf11a0 MCC |
3451 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
3452 | opstate_init(); | |
3453 | ||
2c1ea4c7 TL |
3454 | rc = sbridge_probe(id); |
3455 | ||
3456 | if (rc >= 0) { | |
e35fca47 | 3457 | mce_register_decode_chain(&sbridge_mce_dec); |
fd521039 CG |
3458 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
3459 | sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); | |
eebf11a0 | 3460 | return 0; |
e35fca47 | 3461 | } |
eebf11a0 MCC |
3462 | |
3463 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2c1ea4c7 | 3464 | rc); |
eebf11a0 | 3465 | |
2c1ea4c7 | 3466 | return rc; |
eebf11a0 MCC |
3467 | } |
3468 | ||
3469 | /* | |
3470 | * sbridge_exit() Module exit function | |
3471 | * Unregister the driver | |
3472 | */ | |
3473 | static void __exit sbridge_exit(void) | |
3474 | { | |
956b9ba1 | 3475 | edac_dbg(2, "\n"); |
2c1ea4c7 | 3476 | sbridge_remove(); |
e35fca47 | 3477 | mce_unregister_decode_chain(&sbridge_mce_dec); |
eebf11a0 MCC |
3478 | } |
3479 | ||
3480 | module_init(sbridge_init); | |
3481 | module_exit(sbridge_exit); | |
3482 | ||
3483 | module_param(edac_op_state, int, 0444); | |
3484 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
3485 | ||
3486 | MODULE_LICENSE("GPL"); | |
37e59f87 | 3487 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
eebf11a0 | 3488 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
4d715a80 | 3489 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
eebf11a0 | 3490 | SBRIDGE_REVISION); |