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edac: move nr_pages to dimm struct
[deliverable/linux.git] / drivers / edac / sb_edac.c
CommitLineData
eebf11a0
MCC		 1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
eebf11a0
MCC		 21#include <linux/smp.h>
22#include <linux/bitmap.h>
5b889e37 23#include <linux/math64.h>
eebf11a0 24#include <asm/processor.h>
3d78c9af 25#include <asm/mce.h>
eebf11a0
MCC		 26
27#include "edac_core.h"
28
29/* Static vars */
30static LIST_HEAD(sbridge_edac_list);
31static DEFINE_MUTEX(sbridge_edac_lock);
32static int probed;
33
34/*
35 * Alter this version for the module when modifications are made
36 */
37#define SBRIDGE_REVISION " Ver: 1.0.0 "
38#define EDAC_MOD_STR "sbridge_edac"
39
40/*
41 * Debug macros
42 */
43#define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46#define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49/*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52#define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
54
55/*
56 * sbridge Memory Controller Registers
57 */
58
59/*
60 * FIXME: For now, let's order by device function, as it makes
61 * easier for driver's development proccess. This table should be
62 * moved to pci_id.h when submitted upstream
63 */
64#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
75
76 /*
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
79 */
80#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
84
85/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86static const u32 dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
89};
90#define MAX_SAD ARRAY_SIZE(dram_rule)
91
92#define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
96
97static char *get_dram_attr(u32 reg)
98{
99 switch(DRAM_ATTR(reg)) {
100 case 0:
101 return "DRAM";
102 case 1:
103 return "MMCFG";
104 case 2:
105 return "NXM";
106 default:
107 return "unknown";
108 }
109}
110
111static const u32 interleave_list[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
114};
115#define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
116
117#define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118#define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119#define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120#define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121#define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122#define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123#define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124#define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
125
126static inline int sad_pkg(u32 reg, int interleave)
127{
128 switch (interleave) {
129 case 0:
130 return SAD_PKG0(reg);
131 case 1:
132 return SAD_PKG1(reg);
133 case 2:
134 return SAD_PKG2(reg);
135 case 3:
136 return SAD_PKG3(reg);
137 case 4:
138 return SAD_PKG4(reg);
139 case 5:
140 return SAD_PKG5(reg);
141 case 6:
142 return SAD_PKG6(reg);
143 case 7:
144 return SAD_PKG7(reg);
145 default:
146 return -EINVAL;
147 }
148}
149
150/* Devices 12 Function 7 */
151
152#define TOLM 0x80
153#define TOHM 0x84
154
155#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
157
158/* Device 13 Function 6 */
159
160#define SAD_TARGET 0xf0
161
162#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
163
164#define SAD_CONTROL 0xf4
165
166#define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
167
168/* Device 14 function 0 */
169
170static const u32 tad_dram_rule[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
174};
175#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
176
177#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
184
185/* Device 15, function 0 */
186
187#define MCMTR 0x7c
188
189#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
192
193/* Device 15, function 1 */
194
195#define RASENABLES 0xac
196#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
197
198/* Device 15, functions 2-5 */
199
200static const int mtr_regs[] = {
201 0x80, 0x84, 0x88,
202};
203
204#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
209
210static const u32 tad_ch_nilv_offset[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
214};
215#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
217
218static const u32 rir_way_limit[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
220};
221#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
222
223#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225#define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
226
227#define MAX_RIR_WAY 8
228
229static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
235};
236
237#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
239
240/* Device 16, functions 2-7 */
241
242/*
243 * FIXME: Implement the error count reads directly
244 */
245
246static const u32 correrrcnt[] = {
247 0x104, 0x108, 0x10c, 0x110,
248};
249
250#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
254
255static const u32 correrrthrsld[] = {
256 0x11c, 0x120, 0x124, 0x128,
257};
258
259#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
261
262
263/* Device 17, function 0 */
264
265#define RANK_CFG_A 0x0328
266
267#define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
268
269/*
270 * sbridge structs
271 */
272
273#define NUM_CHANNELS 4
274#define MAX_DIMMS 3 /* Max DIMMS per channel */
275
276struct sbridge_info {
277 u32 mcmtr;
278};
279
280struct sbridge_channel {
281 u32 ranks;
282 u32 dimms;
283};
284
285struct pci_id_descr {
286 int dev;
287 int func;
288 int dev_id;
289 int optional;
290};
291
292struct pci_id_table {
293 const struct pci_id_descr *descr;
294 int n_devs;
295};
296
297struct sbridge_dev {
298 struct list_head list;
299 u8 bus, mc;
300 u8 node_id, source_id;
301 struct pci_dev **pdev;
302 int n_devs;
303 struct mem_ctl_info *mci;
304};
305
306struct sbridge_pvt {
307 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
308 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
309 struct pci_dev *pci_br;
310 struct pci_dev *pci_tad[NUM_CHANNELS];
311
312 struct sbridge_dev *sbridge_dev;
313
314 struct sbridge_info info;
315 struct sbridge_channel channel[NUM_CHANNELS];
316
317 int csrow_map[NUM_CHANNELS][MAX_DIMMS];
318
319 /* Memory type detection */
320 bool is_mirrored, is_lockstep, is_close_pg;
321
eebf11a0
MCC		 322 /* Fifo double buffers */
323 struct mce mce_entry[MCE_LOG_LEN];
324 struct mce mce_outentry[MCE_LOG_LEN];
325
326 /* Fifo in/out counters */
327 unsigned mce_in, mce_out;
328
329 /* Count indicator to show errors not got */
330 unsigned mce_overrun;
331
332 /* Memory description */
333 u64 tolm, tohm;
334};
335
336#define PCI_DESCR(device, function, device_id) \
337 .dev = (device), \
338 .func = (function), \
339 .dev_id = (device_id)
340
341static const struct pci_id_descr pci_dev_descr_sbridge[] = {
342 /* Processor Home Agent */
343 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
344
345 /* Memory controller */
346 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
347 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
348 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
349 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
350 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
351 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
352 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
353
354 /* System Address Decoder */
355 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
356 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
357
358 /* Broadcast Registers */
359 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
360};
361
362#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
363static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
364 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
365 {0,} /* 0 terminated list. */
366};
367
368/*
369 * pci_device_id table for which devices we are looking for
370 */
36c46f31 371static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
eebf11a0
MCC		 372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
373 {0,} /* 0 terminated list. */
374};
375
376
377/****************************************************************************
378 Anciliary status routines
379 ****************************************************************************/
380
381static inline int numrank(u32 mtr)
382{
383 int ranks = (1 << RANK_CNT_BITS(mtr));
384
385 if (ranks > 4) {
386 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)",
387 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
388 return -EINVAL;
389 }
390
391 return ranks;
392}
393
394static inline int numrow(u32 mtr)
395{
396 int rows = (RANK_WIDTH_BITS(mtr) + 12);
397
398 if (rows < 13 || rows > 18) {
399 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)",
400 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
401 return -EINVAL;
402 }
403
404 return 1 << rows;
405}
406
407static inline int numcol(u32 mtr)
408{
409 int cols = (COL_WIDTH_BITS(mtr) + 10);
410
411 if (cols > 12) {
412 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)",
413 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
414 return -EINVAL;
415 }
416
417 return 1 << cols;
418}
419
420static struct sbridge_dev *get_sbridge_dev(u8 bus)
421{
422 struct sbridge_dev *sbridge_dev;
423
424 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
425 if (sbridge_dev->bus == bus)
426 return sbridge_dev;
427 }
428
429 return NULL;
430}
431
432static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
433 const struct pci_id_table *table)
434{
435 struct sbridge_dev *sbridge_dev;
436
437 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
438 if (!sbridge_dev)
439 return NULL;
440
441 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
442 GFP_KERNEL);
443 if (!sbridge_dev->pdev) {
444 kfree(sbridge_dev);
445 return NULL;
446 }
447
448 sbridge_dev->bus = bus;
449 sbridge_dev->n_devs = table->n_devs;
450 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
451
452 return sbridge_dev;
453}
454
455static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
456{
457 list_del(&sbridge_dev->list);
458 kfree(sbridge_dev->pdev);
459 kfree(sbridge_dev);
460}
461
462/****************************************************************************
463 Memory check routines
464 ****************************************************************************/
465static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
466 unsigned func)
467{
468 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
469 int i;
470
471 if (!sbridge_dev)
472 return NULL;
473
474 for (i = 0; i < sbridge_dev->n_devs; i++) {
475 if (!sbridge_dev->pdev[i])
476 continue;
477
478 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
479 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
480 debugf1("Associated %02x.%02x.%d with %p\n",
481 bus, slot, func, sbridge_dev->pdev[i]);
482 return sbridge_dev->pdev[i];
483 }
484 }
485
486 return NULL;
487}
488
489/**
490 * sbridge_get_active_channels() - gets the number of channels and csrows
491 * bus: Device bus
492 * @channels: Number of channels that will be returned
493 * @csrows: Number of csrows found
494 *
495 * Since EDAC core needs to know in advance the number of available channels
496 * and csrows, in order to allocate memory for csrows/channels, it is needed
497 * to run two similar steps. At the first step, implemented on this function,
498 * it checks the number of csrows/channels present at one socket, identified
499 * by the associated PCI bus.
500 * this is used in order to properly allocate the size of mci components.
501 * Note: one csrow is one dimm.
502 */
503static int sbridge_get_active_channels(const u8 bus, unsigned *channels,
504 unsigned *csrows)
505{
506 struct pci_dev *pdev = NULL;
507 int i, j;
508 u32 mcmtr;
509
510 *channels = 0;
511 *csrows = 0;
512
513 pdev = get_pdev_slot_func(bus, 15, 0);
514 if (!pdev) {
515 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
516 "%2x.%02d.%d!!!\n",
517 bus, 15, 0);
518 return -ENODEV;
519 }
520
521 pci_read_config_dword(pdev, MCMTR, &mcmtr);
522 if (!IS_ECC_ENABLED(mcmtr)) {
523 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
524 return -ENODEV;
525 }
526
527 for (i = 0; i < NUM_CHANNELS; i++) {
528 u32 mtr;
529
530 /* Device 15 functions 2 - 5 */
531 pdev = get_pdev_slot_func(bus, 15, 2 + i);
532 if (!pdev) {
533 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
534 "%2x.%02d.%d!!!\n",
535 bus, 15, 2 + i);
536 return -ENODEV;
537 }
538 (*channels)++;
539
540 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
541 pci_read_config_dword(pdev, mtr_regs[j], &mtr);
542 debugf1("Bus#%02x channel #%d MTR%d = %x\n", bus, i, j, mtr);
543 if (IS_DIMM_PRESENT(mtr))
544 (*csrows)++;
545 }
546 }
547
548 debugf0("Number of active channels: %d, number of active dimms: %d\n",
549 *channels, *csrows);
550
551 return 0;
552}
553
084a4fcc 554static int get_dimm_config(struct mem_ctl_info *mci)
eebf11a0
MCC		 555{
556 struct sbridge_pvt *pvt = mci->pvt_info;
557 struct csrow_info *csr;
558 int i, j, banks, ranks, rows, cols, size, npages;
559 int csrow = 0;
560 unsigned long last_page = 0;
561 u32 reg;
562 enum edac_type mode;
c6e13b52 563 enum mem_type mtype;
eebf11a0
MCC		 564
565 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
566 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
567
568 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
569 pvt->sbridge_dev->node_id = NODE_ID(reg);
570 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
571 pvt->sbridge_dev->mc,
572 pvt->sbridge_dev->node_id,
573 pvt->sbridge_dev->source_id);
574
575 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
576 if (IS_MIRROR_ENABLED(reg)) {
577 debugf0("Memory mirror is enabled\n");
578 pvt->is_mirrored = true;
579 } else {
580 debugf0("Memory mirror is disabled\n");
581 pvt->is_mirrored = false;
582 }
583
584 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
585 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
586 debugf0("Lockstep is enabled\n");
587 mode = EDAC_S8ECD8ED;
588 pvt->is_lockstep = true;
589 } else {
590 debugf0("Lockstep is disabled\n");
591 mode = EDAC_S4ECD4ED;
592 pvt->is_lockstep = false;
593 }
594 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
595 debugf0("address map is on closed page mode\n");
596 pvt->is_close_pg = true;
597 } else {
598 debugf0("address map is on open page mode\n");
599 pvt->is_close_pg = false;
600 }
601
602 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, &reg);
603 if (IS_RDIMM_ENABLED(reg)) {
604 /* FIXME: Can also be LRDIMM */
605 debugf0("Memory is registered\n");
c6e13b52 606 mtype = MEM_RDDR3;
eebf11a0
MCC		 607 } else {
608 debugf0("Memory is unregistered\n");
c6e13b52 609 mtype = MEM_DDR3;
eebf11a0
MCC		 610 }
611
612 /* On all supported DDR3 DIMM types, there are 8 banks available */
613 banks = 8;
614
615 for (i = 0; i < NUM_CHANNELS; i++) {
616 u32 mtr;
617
618 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
a895bf8b 619 struct dimm_info *dimm = &mci->dimms[j];
eebf11a0
MCC		 620 pci_read_config_dword(pvt->pci_tad[i],
621 mtr_regs[j], &mtr);
622 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
623 if (IS_DIMM_PRESENT(mtr)) {
624 pvt->channel[i].dimms++;
625
626 ranks = numrank(mtr);
627 rows = numrow(mtr);
628 cols = numcol(mtr);
629
630 /* DDR3 has 8 I/O banks */
631 size = (rows * cols * banks * ranks) >> (20 - 3);
632 npages = MiB_TO_PAGES(size);
633
634 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
635 pvt->sbridge_dev->mc, i, j,
636 size, npages,
637 banks, ranks, rows, cols);
eebf11a0 638
084a4fcc
MCC		 639 /*
640 * Fake stuff. This controller doesn't see
641 * csrows.
642 */
643 csr = &mci->csrows[csrow];
eebf11a0 644 pvt->csrow_map[i][j] = csrow;
eebf11a0
MCC		 645 last_page += npages;
646 csrow++;
084a4fcc
MCC		 647
648 csr->channels[0].dimm = dimm;
a895bf8b 649 dimm->nr_pages = npages;
084a4fcc
MCC		 650 dimm->grain = 32;
651 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
652 dimm->mtype = mtype;
653 dimm->edac_mode = mode;
654 snprintf(dimm->label, sizeof(dimm->label),
655 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
656 pvt->sbridge_dev->source_id, i, j);
eebf11a0
MCC		 657 }
658 }
659 }
660
661 return 0;
662}
663
664static void get_memory_layout(const struct mem_ctl_info *mci)
665{
666 struct sbridge_pvt *pvt = mci->pvt_info;
667 int i, j, k, n_sads, n_tads, sad_interl;
668 u32 reg;
669 u64 limit, prv = 0;
670 u64 tmp_mb;
5b889e37 671 u32 mb, kb;
eebf11a0
MCC		 672 u32 rir_way;
673
674 /*
675 * Step 1) Get TOLM/TOHM ranges
676 */
677
678 /* Address range is 32:28 */
679 pci_read_config_dword(pvt->pci_sad1, TOLM,
680 &reg);
681 pvt->tolm = GET_TOLM(reg);
682 tmp_mb = (1 + pvt->tolm) >> 20;
683
5b889e37
MCC		 684 mb = div_u64_rem(tmp_mb, 1000, &kb);
685 debugf0("TOLM: %u.%03u GB (0x%016Lx)\n",
686 mb, kb, (u64)pvt->tolm);
eebf11a0
MCC		 687
688 /* Address range is already 45:25 */
689 pci_read_config_dword(pvt->pci_sad1, TOHM,
690 &reg);
691 pvt->tohm = GET_TOHM(reg);
692 tmp_mb = (1 + pvt->tohm) >> 20;
693
5b889e37
MCC		 694 mb = div_u64_rem(tmp_mb, 1000, &kb);
695 debugf0("TOHM: %u.%03u GB (0x%016Lx)",
696 mb, kb, (u64)pvt->tohm);
eebf11a0
MCC		 697
698 /*
699 * Step 2) Get SAD range and SAD Interleave list
700 * TAD registers contain the interleave wayness. However, it
701 * seems simpler to just discover it indirectly, with the
702 * algorithm bellow.
703 */
704 prv = 0;
705 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
706 /* SAD_LIMIT Address range is 45:26 */
707 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
708 &reg);
709 limit = SAD_LIMIT(reg);
710
711 if (!DRAM_RULE_ENABLE(reg))
712 continue;
713
714 if (limit <= prv)
715 break;
716
717 tmp_mb = (limit + 1) >> 20;
5b889e37
MCC		 718 mb = div_u64_rem(tmp_mb, 1000, &kb);
719 debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n",
eebf11a0
MCC		 720 n_sads,
721 get_dram_attr(reg),
5b889e37 722 mb, kb,
eebf11a0
MCC		 723 ((u64)tmp_mb) << 20L,
724 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
725 reg);
726 prv = limit;
727
728 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
729 &reg);
730 sad_interl = sad_pkg(reg, 0);
731 for (j = 0; j < 8; j++) {
732 if (j > 0 && sad_interl == sad_pkg(reg, j))
733 break;
734
735 debugf0("SAD#%d, interleave #%d: %d\n",
736 n_sads, j, sad_pkg(reg, j));
737 }
738 }
739
740 /*
741 * Step 3) Get TAD range
742 */
743 prv = 0;
744 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
745 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
746 &reg);
747 limit = TAD_LIMIT(reg);
748 if (limit <= prv)
749 break;
750 tmp_mb = (limit + 1) >> 20;
751
5b889e37
MCC		 752 mb = div_u64_rem(tmp_mb, 1000, &kb);
753 debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
754 n_tads, mb, kb,
eebf11a0
MCC		 755 ((u64)tmp_mb) << 20L,
756 (u32)TAD_SOCK(reg),
757 (u32)TAD_CH(reg),
758 (u32)TAD_TGT0(reg),
759 (u32)TAD_TGT1(reg),
760 (u32)TAD_TGT2(reg),
761 (u32)TAD_TGT3(reg),
762 reg);
7fae0db4 763 prv = limit;
eebf11a0
MCC		 764 }
765
766 /*
767 * Step 4) Get TAD offsets, per each channel
768 */
769 for (i = 0; i < NUM_CHANNELS; i++) {
770 if (!pvt->channel[i].dimms)
771 continue;
772 for (j = 0; j < n_tads; j++) {
773 pci_read_config_dword(pvt->pci_tad[i],
774 tad_ch_nilv_offset[j],
775 &reg);
776 tmp_mb = TAD_OFFSET(reg) >> 20;
5b889e37
MCC		 777 mb = div_u64_rem(tmp_mb, 1000, &kb);
778 debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
eebf11a0 779 i, j,
5b889e37 780 mb, kb,
eebf11a0
MCC		 781 ((u64)tmp_mb) << 20L,
782 reg);
783 }
784 }
785
786 /*
787 * Step 6) Get RIR Wayness/Limit, per each channel
788 */
789 for (i = 0; i < NUM_CHANNELS; i++) {
790 if (!pvt->channel[i].dimms)
791 continue;
792 for (j = 0; j < MAX_RIR_RANGES; j++) {
793 pci_read_config_dword(pvt->pci_tad[i],
794 rir_way_limit[j],
795 &reg);
796
797 if (!IS_RIR_VALID(reg))
798 continue;
799
800 tmp_mb = RIR_LIMIT(reg) >> 20;
801 rir_way = 1 << RIR_WAY(reg);
5b889e37
MCC		 802 mb = div_u64_rem(tmp_mb, 1000, &kb);
803 debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
eebf11a0 804 i, j,
5b889e37 805 mb, kb,
eebf11a0
MCC		 806 ((u64)tmp_mb) << 20L,
807 rir_way,
808 reg);
809
810 for (k = 0; k < rir_way; k++) {
811 pci_read_config_dword(pvt->pci_tad[i],
812 rir_offset[j][k],
813 &reg);
814 tmp_mb = RIR_OFFSET(reg) << 6;
815
5b889e37
MCC		 816 mb = div_u64_rem(tmp_mb, 1000, &kb);
817 debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
eebf11a0 818 i, j, k,
5b889e37 819 mb, kb,
eebf11a0
MCC		 820 ((u64)tmp_mb) << 20L,
821 (u32)RIR_RNK_TGT(reg),
822 reg);
823 }
824 }
825 }
826}
827
828struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
829{
830 struct sbridge_dev *sbridge_dev;
831
832 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
833 if (sbridge_dev->node_id == node_id)
834 return sbridge_dev->mci;
835 }
836 return NULL;
837}
838
839static int get_memory_error_data(struct mem_ctl_info *mci,
840 u64 addr,
841 u8 *socket,
842 long *channel_mask,
843 u8 *rank,
844 char *area_type)
845{
846 struct mem_ctl_info *new_mci;
847 struct sbridge_pvt *pvt = mci->pvt_info;
848 char msg[256];
849 int n_rir, n_sads, n_tads, sad_way, sck_xch;
850 int sad_interl, idx, base_ch;
851 int interleave_mode;
852 unsigned sad_interleave[MAX_INTERLEAVE];
853 u32 reg;
854 u8 ch_way,sck_way;
855 u32 tad_offset;
856 u32 rir_way;
5b889e37 857 u32 mb, kb;
eebf11a0
MCC		 858 u64 ch_addr, offset, limit, prv = 0;
859
860
861 /*
862 * Step 0) Check if the address is at special memory ranges
863 * The check bellow is probably enough to fill all cases where
864 * the error is not inside a memory, except for the legacy
865 * range (e. g. VGA addresses). It is unlikely, however, that the
866 * memory controller would generate an error on that range.
867 */
5b889e37 868 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
eebf11a0
MCC		 869 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
870 edac_mc_handle_ce_no_info(mci, msg);
871 return -EINVAL;
872 }
873 if (addr >= (u64)pvt->tohm) {
874 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
875 edac_mc_handle_ce_no_info(mci, msg);
876 return -EINVAL;
877 }
878
879 /*
880 * Step 1) Get socket
881 */
882 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
883 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
884 &reg);
885
886 if (!DRAM_RULE_ENABLE(reg))
887 continue;
888
889 limit = SAD_LIMIT(reg);
890 if (limit <= prv) {
891 sprintf(msg, "Can't discover the memory socket");
892 edac_mc_handle_ce_no_info(mci, msg);
893 return -EINVAL;
894 }
895 if (addr <= limit)
896 break;
897 prv = limit;
898 }
899 if (n_sads == MAX_SAD) {
900 sprintf(msg, "Can't discover the memory socket");
901 edac_mc_handle_ce_no_info(mci, msg);
902 return -EINVAL;
903 }
904 area_type = get_dram_attr(reg);
905 interleave_mode = INTERLEAVE_MODE(reg);
906
907 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
908 &reg);
909 sad_interl = sad_pkg(reg, 0);
910 for (sad_way = 0; sad_way < 8; sad_way++) {
911 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
912 break;
913 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
914 debugf0("SAD interleave #%d: %d\n",
915 sad_way, sad_interleave[sad_way]);
916 }
917 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
918 pvt->sbridge_dev->mc,
919 n_sads,
920 addr,
921 limit,
922 sad_way + 7,
ad9c40b7 923 interleave_mode ? "" : "XOR[18:16]");
eebf11a0
MCC		 924 if (interleave_mode)
925 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
926 else
927 idx = (addr >> 6) & 7;
928 switch (sad_way) {
929 case 1:
930 idx = 0;
931 break;
932 case 2:
933 idx = idx & 1;
934 break;
935 case 4:
936 idx = idx & 3;
937 break;
938 case 8:
939 break;
940 default:
941 sprintf(msg, "Can't discover socket interleave");
942 edac_mc_handle_ce_no_info(mci, msg);
943 return -EINVAL;
944 }
945 *socket = sad_interleave[idx];
946 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n",
947 idx, sad_way, *socket);
948
949 /*
950 * Move to the proper node structure, in order to access the
951 * right PCI registers
952 */
953 new_mci = get_mci_for_node_id(*socket);
954 if (!new_mci) {
955 sprintf(msg, "Struct for socket #%u wasn't initialized",
956 *socket);
957 edac_mc_handle_ce_no_info(mci, msg);
958 return -EINVAL;
959 }
960 mci = new_mci;
961 pvt = mci->pvt_info;
962
963 /*
964 * Step 2) Get memory channel
965 */
966 prv = 0;
967 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
968 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
969 &reg);
970 limit = TAD_LIMIT(reg);
971 if (limit <= prv) {
972 sprintf(msg, "Can't discover the memory channel");
973 edac_mc_handle_ce_no_info(mci, msg);
974 return -EINVAL;
975 }
976 if (addr <= limit)
977 break;
978 prv = limit;
979 }
980 ch_way = TAD_CH(reg) + 1;
981 sck_way = TAD_SOCK(reg) + 1;
982 /*
983 * FIXME: Is it right to always use channel 0 for offsets?
984 */
985 pci_read_config_dword(pvt->pci_tad[0],
986 tad_ch_nilv_offset[n_tads],
987 &tad_offset);
988
989 if (ch_way == 3)
990 idx = addr >> 6;
991 else
992 idx = addr >> (6 + sck_way);
993 idx = idx % ch_way;
994
995 /*
996 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
997 */
998 switch (idx) {
999 case 0:
1000 base_ch = TAD_TGT0(reg);
1001 break;
1002 case 1:
1003 base_ch = TAD_TGT1(reg);
1004 break;
1005 case 2:
1006 base_ch = TAD_TGT2(reg);
1007 break;
1008 case 3:
1009 base_ch = TAD_TGT3(reg);
1010 break;
1011 default:
1012 sprintf(msg, "Can't discover the TAD target");
1013 edac_mc_handle_ce_no_info(mci, msg);
1014 return -EINVAL;
1015 }
1016 *channel_mask = 1 << base_ch;
1017
1018 if (pvt->is_mirrored) {
1019 *channel_mask |= 1 << ((base_ch + 2) % 4);
1020 switch(ch_way) {
1021 case 2:
1022 case 4:
1023 sck_xch = 1 << sck_way * (ch_way >> 1);
1024 break;
1025 default:
1026 sprintf(msg, "Invalid mirror set. Can't decode addr");
1027 edac_mc_handle_ce_no_info(mci, msg);
1028 return -EINVAL;
1029 }
1030 } else
1031 sck_xch = (1 << sck_way) * ch_way;
1032
1033 if (pvt->is_lockstep)
1034 *channel_mask |= 1 << ((base_ch + 1) % 4);
1035
1036 offset = TAD_OFFSET(tad_offset);
1037
1038 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1039 n_tads,
1040 addr,
1041 limit,
1042 (u32)TAD_SOCK(reg),
1043 ch_way,
1044 offset,
1045 idx,
1046 base_ch,
1047 *channel_mask);
1048
1049 /* Calculate channel address */
1050 /* Remove the TAD offset */
1051
1052 if (offset > addr) {
1053 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1054 offset, addr);
1055 edac_mc_handle_ce_no_info(mci, msg);
1056 return -EINVAL;
1057 }
1058 addr -= offset;
1059 /* Store the low bits [0:6] of the addr */
1060 ch_addr = addr & 0x7f;
1061 /* Remove socket wayness and remove 6 bits */
1062 addr >>= 6;
5b889e37 1063 addr = div_u64(addr, sck_xch);
eebf11a0
MCC		 1064#if 0
1065 /* Divide by channel way */
1066 addr = addr / ch_way;
1067#endif
1068 /* Recover the last 6 bits */
1069 ch_addr |= addr << 6;
1070
1071 /*
1072 * Step 3) Decode rank
1073 */
1074 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1075 pci_read_config_dword(pvt->pci_tad[base_ch],
1076 rir_way_limit[n_rir],
1077 &reg);
1078
1079 if (!IS_RIR_VALID(reg))
1080 continue;
1081
1082 limit = RIR_LIMIT(reg);
5b889e37
MCC		 1083 mb = div_u64_rem(limit >> 20, 1000, &kb);
1084 debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
eebf11a0 1085 n_rir,
5b889e37 1086 mb, kb,
eebf11a0
MCC		 1087 limit,
1088 1 << RIR_WAY(reg));
1089 if (ch_addr <= limit)
1090 break;
1091 }
1092 if (n_rir == MAX_RIR_RANGES) {
1093 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1094 ch_addr);
1095 edac_mc_handle_ce_no_info(mci, msg);
1096 return -EINVAL;
1097 }
1098 rir_way = RIR_WAY(reg);
1099 if (pvt->is_close_pg)
1100 idx = (ch_addr >> 6);
1101 else
1102 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1103 idx %= 1 << rir_way;
1104
1105 pci_read_config_dword(pvt->pci_tad[base_ch],
1106 rir_offset[n_rir][idx],
1107 &reg);
1108 *rank = RIR_RNK_TGT(reg);
1109
1110 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1111 n_rir,
1112 ch_addr,
1113 limit,
1114 rir_way,
1115 idx);
1116
1117 return 0;
1118}
1119
1120/****************************************************************************
1121 Device initialization routines: put/get, init/exit
1122 ****************************************************************************/
1123
1124/*
1125 * sbridge_put_all_devices 'put' all the devices that we have
1126 * reserved via 'get'
1127 */
1128static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1129{
1130 int i;
1131
1132 debugf0(__FILE__ ": %s()\n", __func__);
1133 for (i = 0; i < sbridge_dev->n_devs; i++) {
1134 struct pci_dev *pdev = sbridge_dev->pdev[i];
1135 if (!pdev)
1136 continue;
1137 debugf0("Removing dev %02x:%02x.%d\n",
1138 pdev->bus->number,
1139 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1140 pci_dev_put(pdev);
1141 }
1142}
1143
1144static void sbridge_put_all_devices(void)
1145{
1146 struct sbridge_dev *sbridge_dev, *tmp;
1147
1148 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1149 sbridge_put_devices(sbridge_dev);
1150 free_sbridge_dev(sbridge_dev);
1151 }
1152}
1153
1154/*
1155 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1156 * device/functions we want to reference for this driver
1157 *
1158 * Need to 'get' device 16 func 1 and func 2
1159 */
1160static int sbridge_get_onedevice(struct pci_dev **prev,
1161 u8 *num_mc,
1162 const struct pci_id_table *table,
1163 const unsigned devno)
1164{
1165 struct sbridge_dev *sbridge_dev;
1166 const struct pci_id_descr *dev_descr = &table->descr[devno];
1167
1168 struct pci_dev *pdev = NULL;
1169 u8 bus = 0;
1170
1171 sbridge_printk(KERN_INFO,
1172 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1173 dev_descr->dev, dev_descr->func,
1174 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1175
1176 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1177 dev_descr->dev_id, *prev);
1178
1179 if (!pdev) {
1180 if (*prev) {
1181 *prev = pdev;
1182 return 0;
1183 }
1184
1185 if (dev_descr->optional)
1186 return 0;
1187
1188 if (devno == 0)
1189 return -ENODEV;
1190
1191 sbridge_printk(KERN_INFO,
1192 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1193 dev_descr->dev, dev_descr->func,
1194 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1195
1196 /* End of list, leave */
1197 return -ENODEV;
1198 }
1199 bus = pdev->bus->number;
1200
1201 sbridge_dev = get_sbridge_dev(bus);
1202 if (!sbridge_dev) {
1203 sbridge_dev = alloc_sbridge_dev(bus, table);
1204 if (!sbridge_dev) {
1205 pci_dev_put(pdev);
1206 return -ENOMEM;
1207 }
1208 (*num_mc)++;
1209 }
1210
1211 if (sbridge_dev->pdev[devno]) {
1212 sbridge_printk(KERN_ERR,
1213 "Duplicated device for "
1214 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1215 bus, dev_descr->dev, dev_descr->func,
1216 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1217 pci_dev_put(pdev);
1218 return -ENODEV;
1219 }
1220
1221 sbridge_dev->pdev[devno] = pdev;
1222
1223 /* Sanity check */
1224 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1225 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1226 sbridge_printk(KERN_ERR,
1227 "Device PCI ID %04x:%04x "
1228 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1229 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1230 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1231 bus, dev_descr->dev, dev_descr->func);
1232 return -ENODEV;
1233 }
1234
1235 /* Be sure that the device is enabled */
1236 if (unlikely(pci_enable_device(pdev) < 0)) {
1237 sbridge_printk(KERN_ERR,
1238 "Couldn't enable "
1239 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1240 bus, dev_descr->dev, dev_descr->func,
1241 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1242 return -ENODEV;
1243 }
1244
1245 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1246 bus, dev_descr->dev,
1247 dev_descr->func,
1248 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1249
1250 /*
1251 * As stated on drivers/pci/search.c, the reference count for
1252 * @from is always decremented if it is not %NULL. So, as we need
1253 * to get all devices up to null, we need to do a get for the device
1254 */
1255 pci_dev_get(pdev);
1256
1257 *prev = pdev;
1258
1259 return 0;
1260}
1261
1262static int sbridge_get_all_devices(u8 *num_mc)
1263{
1264 int i, rc;
1265 struct pci_dev *pdev = NULL;
1266 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1267
1268 while (table && table->descr) {
1269 for (i = 0; i < table->n_devs; i++) {
1270 pdev = NULL;
1271 do {
1272 rc = sbridge_get_onedevice(&pdev, num_mc,
1273 table, i);
1274 if (rc < 0) {
1275 if (i == 0) {
1276 i = table->n_devs;
1277 break;
1278 }
1279 sbridge_put_all_devices();
1280 return -ENODEV;
1281 }
1282 } while (pdev);
1283 }
1284 table++;
1285 }
1286
1287 return 0;
1288}
1289
1290static int mci_bind_devs(struct mem_ctl_info *mci,
1291 struct sbridge_dev *sbridge_dev)
1292{
1293 struct sbridge_pvt *pvt = mci->pvt_info;
1294 struct pci_dev *pdev;
1295 int i, func, slot;
1296
1297 for (i = 0; i < sbridge_dev->n_devs; i++) {
1298 pdev = sbridge_dev->pdev[i];
1299 if (!pdev)
1300 continue;
1301 slot = PCI_SLOT(pdev->devfn);
1302 func = PCI_FUNC(pdev->devfn);
1303 switch (slot) {
1304 case 12:
1305 switch (func) {
1306 case 6:
1307 pvt->pci_sad0 = pdev;
1308 break;
1309 case 7:
1310 pvt->pci_sad1 = pdev;
1311 break;
1312 default:
1313 goto error;
1314 }
1315 break;
1316 case 13:
1317 switch (func) {
1318 case 6:
1319 pvt->pci_br = pdev;
1320 break;
1321 default:
1322 goto error;
1323 }
1324 break;
1325 case 14:
1326 switch (func) {
1327 case 0:
1328 pvt->pci_ha0 = pdev;
1329 break;
1330 default:
1331 goto error;
1332 }
1333 break;
1334 case 15:
1335 switch (func) {
1336 case 0:
1337 pvt->pci_ta = pdev;
1338 break;
1339 case 1:
1340 pvt->pci_ras = pdev;
1341 break;
1342 case 2:
1343 case 3:
1344 case 4:
1345 case 5:
1346 pvt->pci_tad[func - 2] = pdev;
1347 break;
1348 default:
1349 goto error;
1350 }
1351 break;
1352 case 17:
1353 switch (func) {
1354 case 0:
1355 pvt->pci_ddrio = pdev;
1356 break;
1357 default:
1358 goto error;
1359 }
1360 break;
1361 default:
1362 goto error;
1363 }
1364
1365 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n",
1366 sbridge_dev->bus,
1367 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1368 pdev);
1369 }
1370
1371 /* Check if everything were registered */
1372 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1373 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1374 !pvt->pci_ddrio)
1375 goto enodev;
1376
1377 for (i = 0; i < NUM_CHANNELS; i++) {
1378 if (!pvt->pci_tad[i])
1379 goto enodev;
1380 }
1381 return 0;
1382
1383enodev:
1384 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1385 return -ENODEV;
1386
1387error:
1388 sbridge_printk(KERN_ERR, "Device %d, function %d "
1389 "is out of the expected range\n",
1390 slot, func);
1391 return -EINVAL;
1392}
1393
1394/****************************************************************************
1395 Error check routines
1396 ****************************************************************************/
1397
1398/*
1399 * While Sandy Bridge has error count registers, SMI BIOS read values from
1400 * and resets the counters. So, they are not reliable for the OS to read
1401 * from them. So, we have no option but to just trust on whatever MCE is
1402 * telling us about the errors.
1403 */
1404static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1405 const struct mce *m)
1406{
1407 struct mem_ctl_info *new_mci;
1408 struct sbridge_pvt *pvt = mci->pvt_info;
1409 char *type, *optype, *msg, *recoverable_msg;
1410 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1411 bool overflow = GET_BITFIELD(m->status, 62, 62);
1412 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1413 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1414 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1415 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1416 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1417 u32 channel = GET_BITFIELD(m->status, 0, 3);
1418 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1419 long channel_mask, first_channel;
1420 u8 rank, socket;
1421 int csrow, rc, dimm;
1422 char *area_type = "Unknown";
1423
1424 if (ripv)
1425 type = "NON_FATAL";
1426 else
1427 type = "FATAL";
1428
1429 /*
1430 * According with Table 15-9 of the Intel Archictecture spec vol 3A,
1431 * memory errors should fit in this mask:
1432 * 000f 0000 1mmm cccc (binary)
1433 * where:
1434 * f = Correction Report Filtering Bit. If 1, subsequent errors
1435 * won't be shown
1436 * mmm = error type
1437 * cccc = channel
1438 * If the mask doesn't match, report an error to the parsing logic
1439 */
1440 if (! ((errcode & 0xef80) == 0x80)) {
1441 optype = "Can't parse: it is not a mem";
1442 } else {
1443 switch (optypenum) {
1444 case 0:
1445 optype = "generic undef request";
1446 break;
1447 case 1:
1448 optype = "memory read";
1449 break;
1450 case 2:
1451 optype = "memory write";
1452 break;
1453 case 3:
1454 optype = "addr/cmd";
1455 break;
1456 case 4:
1457 optype = "memory scrubbing";
1458 break;
1459 default:
1460 optype = "reserved";
1461 break;
1462 }
1463 }
1464
1465 rc = get_memory_error_data(mci, m->addr, &socket,
1466 &channel_mask, &rank, area_type);
1467 if (rc < 0)
1468 return;
1469 new_mci = get_mci_for_node_id(socket);
1470 if (!new_mci) {
1471 edac_mc_handle_ce_no_info(mci, "Error: socket got corrupted!");
1472 return;
1473 }
1474 mci = new_mci;
1475 pvt = mci->pvt_info;
1476
1477 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1478
1479 if (rank < 4)
1480 dimm = 0;
1481 else if (rank < 8)
1482 dimm = 1;
1483 else
1484 dimm = 2;
1485
1486 csrow = pvt->csrow_map[first_channel][dimm];
1487
1488 if (uncorrected_error && recoverable)
1489 recoverable_msg = " recoverable";
1490 else
1491 recoverable_msg = "";
1492
1493 /*
1494 * FIXME: What should we do with "channel" information on mcelog?
1495 * Probably, we can just discard it, as the channel information
1496 * comes from the get_memory_error_data() address decoding
1497 */
1498 msg = kasprintf(GFP_ATOMIC,
1499 "%d %s error(s): %s on %s area %s%s: cpu=%d Err=%04x:%04x (ch=%d), "
1500 "addr = 0x%08llx => socket=%d, Channel=%ld(mask=%ld), rank=%d\n",
1501 core_err_cnt,
1502 area_type,
1503 optype,
1504 type,
1505 recoverable_msg,
1506 overflow ? "OVERFLOW" : "",
1507 m->cpu,
1508 mscod, errcode,
1509 channel, /* 1111b means not specified */
1510 (long long) m->addr,
1511 socket,
1512 first_channel, /* This is the real channel on SB */
1513 channel_mask,
1514 rank);
1515
1516 debugf0("%s", msg);
1517
1518 /* Call the helper to output message */
1519 if (uncorrected_error)
1520 edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg);
1521 else
1522 edac_mc_handle_fbd_ce(mci, csrow, 0, msg);
1523
1524 kfree(msg);
1525}
1526
1527/*
1528 * sbridge_check_error Retrieve and process errors reported by the
1529 * hardware. Called by the Core module.
1530 */
1531static void sbridge_check_error(struct mem_ctl_info *mci)
1532{
1533 struct sbridge_pvt *pvt = mci->pvt_info;
1534 int i;
1535 unsigned count = 0;
1536 struct mce *m;
1537
1538 /*
1539 * MCE first step: Copy all mce errors into a temporary buffer
1540 * We use a double buffering here, to reduce the risk of
1541 * loosing an error.
1542 */
1543 smp_rmb();
1544 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1545 % MCE_LOG_LEN;
1546 if (!count)
1547 return;
1548
1549 m = pvt->mce_outentry;
1550 if (pvt->mce_in + count > MCE_LOG_LEN) {
1551 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1552
1553 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1554 smp_wmb();
1555 pvt->mce_in = 0;
1556 count -= l;
1557 m += l;
1558 }
1559 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1560 smp_wmb();
1561 pvt->mce_in += count;
1562
1563 smp_rmb();
1564 if (pvt->mce_overrun) {
1565 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1566 pvt->mce_overrun);
1567 smp_wmb();
1568 pvt->mce_overrun = 0;
1569 }
1570
1571 /*
1572 * MCE second step: parse errors and display
1573 */
1574 for (i = 0; i < count; i++)
1575 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1576}
1577
1578/*
1579 * sbridge_mce_check_error Replicates mcelog routine to get errors
1580 * This routine simply queues mcelog errors, and
1581 * return. The error itself should be handled later
1582 * by sbridge_check_error.
1583 * WARNING: As this routine should be called at NMI time, extra care should
1584 * be taken to avoid deadlocks, and to be as fast as possible.
1585 */
3d78c9af
MCC		 1586static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1587 void *data)
eebf11a0 1588{
3d78c9af
MCC		 1589 struct mce *mce = (struct mce *)data;
1590 struct mem_ctl_info *mci;
1591 struct sbridge_pvt *pvt;
1592
1593 mci = get_mci_for_node_id(mce->socketid);
1594 if (!mci)
1595 return NOTIFY_BAD;
1596 pvt = mci->pvt_info;
eebf11a0
MCC		 1597
1598 /*
1599 * Just let mcelog handle it if the error is
1600 * outside the memory controller. A memory error
1601 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1602 * bit 12 has an special meaning.
1603 */
1604 if ((mce->status & 0xefff) >> 7 != 1)
3d78c9af 1605 return NOTIFY_DONE;
eebf11a0
MCC		 1606
1607 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1608
1609 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1610 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1611 printk("TSC %llx ", mce->tsc);
1612 printk("ADDR %llx ", mce->addr);
1613 printk("MISC %llx ", mce->misc);
1614
1615 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1616 mce->cpuvendor, mce->cpuid, mce->time,
1617 mce->socketid, mce->apicid);
1618
eebf11a0
MCC		 1619 /* Only handle if it is the right mc controller */
1620 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
3d78c9af 1621 return NOTIFY_DONE;
eebf11a0
MCC		 1622
1623 smp_rmb();
1624 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1625 smp_wmb();
1626 pvt->mce_overrun++;
3d78c9af 1627 return NOTIFY_DONE;
eebf11a0
MCC		 1628 }
1629
1630 /* Copy memory error at the ringbuffer */
1631 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1632 smp_wmb();
1633 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1634
1635 /* Handle fatal errors immediately */
1636 if (mce->mcgstatus & 1)
1637 sbridge_check_error(mci);
1638
1639 /* Advice mcelog that the error were handled */
3d78c9af 1640 return NOTIFY_STOP;
eebf11a0
MCC		 1641}
1642
3d78c9af
MCC		 1643static struct notifier_block sbridge_mce_dec = {
1644 .notifier_call = sbridge_mce_check_error,
1645};
1646
eebf11a0
MCC		 1647/****************************************************************************
1648 EDAC register/unregister logic
1649 ****************************************************************************/
1650
1651static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1652{
1653 struct mem_ctl_info *mci = sbridge_dev->mci;
1654 struct sbridge_pvt *pvt;
1655
1656 if (unlikely(!mci || !mci->pvt_info)) {
1657 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
1658 __func__, &sbridge_dev->pdev[0]->dev);
1659
1660 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1661 return;
1662 }
1663
1664 pvt = mci->pvt_info;
1665
1666 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1667 __func__, mci, &sbridge_dev->pdev[0]->dev);
1668
3653ada5 1669 mce_unregister_decode_chain(&sbridge_mce_dec);
eebf11a0
MCC		 1670
1671 /* Remove MC sysfs nodes */
1672 edac_mc_del_mc(mci->dev);
1673
1674 debugf1("%s: free mci struct\n", mci->ctl_name);
1675 kfree(mci->ctl_name);
1676 edac_mc_free(mci);
1677 sbridge_dev->mci = NULL;
1678}
1679
1680static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1681{
1682 struct mem_ctl_info *mci;
1683 struct sbridge_pvt *pvt;
1684 int rc, channels, csrows;
1685
1686 /* Check the number of active and not disabled channels */
1687 rc = sbridge_get_active_channels(sbridge_dev->bus, &channels, &csrows);
1688 if (unlikely(rc < 0))
1689 return rc;
1690
1691 /* allocate a new MC control structure */
1692 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, sbridge_dev->mc);
1693 if (unlikely(!mci))
1694 return -ENOMEM;
1695
1696 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1697 __func__, mci, &sbridge_dev->pdev[0]->dev);
1698
1699 pvt = mci->pvt_info;
1700 memset(pvt, 0, sizeof(*pvt));
1701
1702 /* Associate sbridge_dev and mci for future usage */
1703 pvt->sbridge_dev = sbridge_dev;
1704 sbridge_dev->mci = mci;
1705
1706 mci->mtype_cap = MEM_FLAG_DDR3;
1707 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1708 mci->edac_cap = EDAC_FLAG_NONE;
1709 mci->mod_name = "sbridge_edac.c";
1710 mci->mod_ver = SBRIDGE_REVISION;
1711 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1712 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1713 mci->ctl_page_to_phys = NULL;
1714
1715 /* Set the function pointer to an actual operation function */
1716 mci->edac_check = sbridge_check_error;
1717
1718 /* Store pci devices at mci for faster access */
1719 rc = mci_bind_devs(mci, sbridge_dev);
1720 if (unlikely(rc < 0))
1721 goto fail0;
1722
1723 /* Get dimm basic config and the memory layout */
1724 get_dimm_config(mci);
1725 get_memory_layout(mci);
1726
1727 /* record ptr to the generic device */
1728 mci->dev = &sbridge_dev->pdev[0]->dev;
1729
1730 /* add this new MC control structure to EDAC's list of MCs */
1731 if (unlikely(edac_mc_add_mc(mci))) {
1732 debugf0("MC: " __FILE__
1733 ": %s(): failed edac_mc_add_mc()\n", __func__);
1734 rc = -EINVAL;
1735 goto fail0;
1736 }
1737
3653ada5 1738 mce_register_decode_chain(&sbridge_mce_dec);
eebf11a0 1739 return 0;
eebf11a0
MCC		 1740
1741fail0:
1742 kfree(mci->ctl_name);
1743 edac_mc_free(mci);
1744 sbridge_dev->mci = NULL;
1745 return rc;
1746}
1747
1748/*
1749 * sbridge_probe Probe for ONE instance of device to see if it is
1750 * present.
1751 * return:
1752 * 0 for FOUND a device
1753 * < 0 for error code
1754 */
1755
1756static int __devinit sbridge_probe(struct pci_dev *pdev,
1757 const struct pci_device_id *id)
1758{
1759 int rc;
1760 u8 mc, num_mc = 0;
1761 struct sbridge_dev *sbridge_dev;
1762
1763 /* get the pci devices we want to reserve for our use */
1764 mutex_lock(&sbridge_edac_lock);
1765
1766 /*
1767 * All memory controllers are allocated at the first pass.
1768 */
1769 if (unlikely(probed >= 1)) {
1770 mutex_unlock(&sbridge_edac_lock);
1771 return -ENODEV;
1772 }
1773 probed++;
1774
1775 rc = sbridge_get_all_devices(&num_mc);
1776 if (unlikely(rc < 0))
1777 goto fail0;
1778 mc = 0;
1779
1780 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1781 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc);
1782 sbridge_dev->mc = mc++;
1783 rc = sbridge_register_mci(sbridge_dev);
1784 if (unlikely(rc < 0))
1785 goto fail1;
1786 }
1787
1788 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1789
1790 mutex_unlock(&sbridge_edac_lock);
1791 return 0;
1792
1793fail1:
1794 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1795 sbridge_unregister_mci(sbridge_dev);
1796
1797 sbridge_put_all_devices();
1798fail0:
1799 mutex_unlock(&sbridge_edac_lock);
1800 return rc;
1801}
1802
1803/*
1804 * sbridge_remove destructor for one instance of device
1805 *
1806 */
1807static void __devexit sbridge_remove(struct pci_dev *pdev)
1808{
1809 struct sbridge_dev *sbridge_dev;
1810
1811 debugf0(__FILE__ ": %s()\n", __func__);
1812
1813 /*
1814 * we have a trouble here: pdev value for removal will be wrong, since
1815 * it will point to the X58 register used to detect that the machine
1816 * is a Nehalem or upper design. However, due to the way several PCI
1817 * devices are grouped together to provide MC functionality, we need
1818 * to use a different method for releasing the devices
1819 */
1820
1821 mutex_lock(&sbridge_edac_lock);
1822
1823 if (unlikely(!probed)) {
1824 mutex_unlock(&sbridge_edac_lock);
1825 return;
1826 }
1827
1828 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1829 sbridge_unregister_mci(sbridge_dev);
1830
1831 /* Release PCI resources */
1832 sbridge_put_all_devices();
1833
1834 probed--;
1835
1836 mutex_unlock(&sbridge_edac_lock);
1837}
1838
1839MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1840
1841/*
1842 * sbridge_driver pci_driver structure for this module
1843 *
1844 */
1845static struct pci_driver sbridge_driver = {
1846 .name = "sbridge_edac",
1847 .probe = sbridge_probe,
1848 .remove = __devexit_p(sbridge_remove),
1849 .id_table = sbridge_pci_tbl,
1850};
1851
1852/*
1853 * sbridge_init Module entry function
1854 * Try to initialize this module for its devices
1855 */
1856static int __init sbridge_init(void)
1857{
1858 int pci_rc;
1859
1860 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1861
1862 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1863 opstate_init();
1864
1865 pci_rc = pci_register_driver(&sbridge_driver);
1866
1867 if (pci_rc >= 0)
1868 return 0;
1869
1870 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1871 pci_rc);
1872
1873 return pci_rc;
1874}
1875
1876/*
1877 * sbridge_exit() Module exit function
1878 * Unregister the driver
1879 */
1880static void __exit sbridge_exit(void)
1881{
1882 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1883 pci_unregister_driver(&sbridge_driver);
1884}
1885
1886module_init(sbridge_init);
1887module_exit(sbridge_exit);
1888
1889module_param(edac_op_state, int, 0444);
1890MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1891
1892MODULE_LICENSE("GPL");
1893MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1894MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1895MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "
1896 SBRIDGE_REVISION);
Linux kernel - Deliverables
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