[deliverable/linux.git] / drivers / edac / tile_edac.c

/*
 * Copyright 2011 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 * Tilera-specific EDAC driver.
 *
 * This source code is derived from the following driver:
 *
 * Cell MIC driver for ECC counting
 *
 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
 *                <benh@kernel.crashing.org>
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/edac.h>
#include <hv/hypervisor.h>
#include <hv/drv_mshim_intf.h>

#include "edac_core.h"

#define DRV_NAME	"tile-edac"

/* Number of cs_rows needed per memory controller on TILEPro. */
#define TILE_EDAC_NR_CSROWS	1

/* Number of channels per memory controller on TILEPro. */
#define TILE_EDAC_NR_CHANS	1

/* Granularity of reported error in bytes on TILEPro. */
#define TILE_EDAC_ERROR_GRAIN	8

/* TILE processor has multiple independent memory controllers. */
struct platform_device *mshim_pdev[TILE_MAX_MSHIMS];

struct tile_edac_priv {
	int		hv_devhdl;	/* Hypervisor device handle. */
	int		node;		/* Memory controller instance #. */
	unsigned int	ce_count;	/*
					 * Correctable-error counter
					 * kept by the driver.
					 */
};

static void tile_edac_check(struct mem_ctl_info *mci)
{
	struct tile_edac_priv	*priv = mci->pvt_info;
	struct mshim_mem_error	mem_error;

	if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error,
		sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) !=
		sizeof(struct mshim_mem_error)) {
		pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure.\n");
		return;
	}

	/* Check if the current error count is different from the saved one. */
	if (mem_error.sbe_count != priv->ce_count) {
		dev_dbg(mci->dev, "ECC CE err on node %d\n", priv->node);
		priv->ce_count = mem_error.sbe_count;
		edac_mc_handle_ce(mci, 0, 0, 0, 0, 0, mci->ctl_name);
	}
}

/*
 * Initialize the 'csrows' table within the mci control structure with the
 * addressing of memory.
 */
static int __devinit tile_edac_init_csrows(struct mem_ctl_info *mci)
{
	struct csrow_info	*csrow = &mci->csrows[0];
	struct tile_edac_priv	*priv = mci->pvt_info;
	struct mshim_mem_info	mem_info;
	struct dimm_info *dimm = csrow->channels[0].dimm;

	if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
		sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
		sizeof(struct mshim_mem_info)) {
		pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure.\n");
		return -1;
	}

	if (mem_info.mem_ecc)
		dimm->edac_mode = EDAC_SECDED;
	else
		dimm->edac_mode = EDAC_NONE;
	switch (mem_info.mem_type) {
	case DDR2:
		dimm->mtype = MEM_DDR2;
		break;

	case DDR3:
		dimm->mtype = MEM_DDR3;
		break;

	default:
		return -1;
	}

	dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
	dimm->grain = TILE_EDAC_ERROR_GRAIN;
	dimm->dtype = DEV_UNKNOWN;

	return 0;
}

static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
{
	char			hv_file[32];
	int			hv_devhdl;
	struct mem_ctl_info	*mci;
	struct tile_edac_priv	*priv;
	int			rc;

	sprintf(hv_file, "mshim/%d", pdev->id);
	hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0);
	if (hv_devhdl < 0)
		return -EINVAL;

	/* A TILE MC has a single channel and one chip-select row. */
	mci = edac_mc_alloc(sizeof(struct tile_edac_priv),
		TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id);
	if (mci == NULL)
		return -ENOMEM;
	priv = mci->pvt_info;
	priv->node = pdev->id;
	priv->hv_devhdl = hv_devhdl;

	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR2;
	mci->edac_ctl_cap = EDAC_FLAG_SECDED;

	mci->mod_name = DRV_NAME;
#ifdef __tilegx__
	mci->ctl_name = "TILEGx_Memory_Controller";
#else
	mci->ctl_name = "TILEPro_Memory_Controller";
#endif
	mci->dev_name = dev_name(&pdev->dev);
	mci->edac_check = tile_edac_check;

	/*
	 * Initialize the MC control structure 'csrows' table
	 * with the mapping and control information.
	 */
	if (tile_edac_init_csrows(mci)) {
		/* No csrows found. */
		mci->edac_cap = EDAC_FLAG_NONE;
	} else {
		mci->edac_cap = EDAC_FLAG_SECDED;
	}

	platform_set_drvdata(pdev, mci);

	/* Register with EDAC core */
	rc = edac_mc_add_mc(mci);
	if (rc) {
		dev_err(&pdev->dev, "failed to register with EDAC core\n");
		edac_mc_free(mci);
		return rc;
	}

	return 0;
}

static int __devexit tile_edac_mc_remove(struct platform_device *pdev)
{
	struct mem_ctl_info *mci = platform_get_drvdata(pdev);

	edac_mc_del_mc(&pdev->dev);
	if (mci)
		edac_mc_free(mci);
	return 0;
}

static struct platform_driver tile_edac_mc_driver = {
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
	.probe		= tile_edac_mc_probe,
	.remove		= __devexit_p(tile_edac_mc_remove),
};

/*
 * Driver init routine.
 */
static int __init tile_edac_init(void)
{
	char	hv_file[32];
	struct platform_device *pdev;
	int i, err, num = 0;

	/* Only support POLL mode. */
	edac_op_state = EDAC_OPSTATE_POLL;

	err = platform_driver_register(&tile_edac_mc_driver);
	if (err)
		return err;

	for (i = 0; i < TILE_MAX_MSHIMS; i++) {
		/*
		 * Not all memory controllers are configured such as in the
		 * case of a simulator. So we register only those mshims
		 * that are configured by the hypervisor.
		 */
		sprintf(hv_file, "mshim/%d", i);
		if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0)
			continue;

		pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0);
		if (IS_ERR(pdev))
			continue;
		mshim_pdev[i] = pdev;
		num++;
	}

	if (num == 0) {
		platform_driver_unregister(&tile_edac_mc_driver);
		return -ENODEV;
	}
	return 0;
}

/*
 * Driver cleanup routine.
 */
static void __exit tile_edac_exit(void)
{
	int i;

	for (i = 0; i < TILE_MAX_MSHIMS; i++) {
		struct platform_device *pdev = mshim_pdev[i];
		if (!pdev)
			continue;

		platform_set_drvdata(pdev, NULL);
		platform_device_unregister(pdev);
	}
	platform_driver_unregister(&tile_edac_mc_driver);
}

module_init(tile_edac_init);
module_exit(tile_edac_exit);
Commit	Line	Data
5c770755 CM	1	/*
	2	* Copyright 2011 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	* Tilera-specific EDAC driver.
	14	*
	15	* This source code is derived from the following driver:
	16	*
	17	* Cell MIC driver for ECC counting
	18	*
	19	* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
	20	* <benh@kernel.crashing.org>
	21	*
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/init.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/io.h>
	28	#include <linux/uaccess.h>
	29	#include <linux/edac.h>
	30	#include <hv/hypervisor.h>
	31	#include <hv/drv_mshim_intf.h>
	32
	33	#include "edac_core.h"
	34
	35	#define DRV_NAME "tile-edac"
	36
	37	/* Number of cs_rows needed per memory controller on TILEPro. */
	38	#define TILE_EDAC_NR_CSROWS 1
	39
	40	/* Number of channels per memory controller on TILEPro. */
	41	#define TILE_EDAC_NR_CHANS 1
	42
	43	/* Granularity of reported error in bytes on TILEPro. */
	44	#define TILE_EDAC_ERROR_GRAIN 8
	45
	46	/* TILE processor has multiple independent memory controllers. */
	47	struct platform_device *mshim_pdev[TILE_MAX_MSHIMS];
	48
	49	struct tile_edac_priv {
	50	int hv_devhdl; /* Hypervisor device handle. */
	51	int node; /* Memory controller instance #. */
	52	unsigned int ce_count; /*
	53	* Correctable-error counter
	54	* kept by the driver.
	55	*/
	56	};
	57
	58	static void tile_edac_check(struct mem_ctl_info *mci)
	59	{
	60	struct tile_edac_priv *priv = mci->pvt_info;
	61	struct mshim_mem_error mem_error;
	62
	63	if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error,
	64	sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) !=
65	sizeof(struct mshim_mem_error)) {
66	pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure.\n");
67	return;
68	}
69
70	/* Check if the current error count is different from the saved one. */
71	if (mem_error.sbe_count != priv->ce_count) {
72	dev_dbg(mci->dev, "ECC CE err on node %d\n", priv->node);
73	priv->ce_count = mem_error.sbe_count;
74	edac_mc_handle_ce(mci, 0, 0, 0, 0, 0, mci->ctl_name);
75	}
76	}
77
78	/*
79	* Initialize the 'csrows' table within the mci control structure with the
80	* addressing of memory.
81	*/
82	static int __devinit tile_edac_init_csrows(struct mem_ctl_info *mci)
83	{
84	struct csrow_info *csrow = &mci->csrows[0];
85	struct tile_edac_priv *priv = mci->pvt_info;
86	struct mshim_mem_info mem_info;
084a4fcc	87	struct dimm_info *dimm = csrow->channels[0].dimm;
5c770755 CM	88
	89	if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
	90	sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
	91	sizeof(struct mshim_mem_info)) {
	92	pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure.\n");
	93	return -1;
	94	}
	95
	96	if (mem_info.mem_ecc)
084a4fcc	97	dimm->edac_mode = EDAC_SECDED;
5c770755	98	else
084a4fcc	99	dimm->edac_mode = EDAC_NONE;
5c770755 CM	100	switch (mem_info.mem_type) {
5c770755 CM	101	case DDR2:
084a4fcc	102	dimm->mtype = MEM_DDR2;
5c770755 CM	103	break;
	104
	105	case DDR3:
084a4fcc	106	dimm->mtype = MEM_DDR3;
5c770755 CM	107	break;
	108
	109	default:
	110	return -1;
	111	}
	112
a895bf8b	113	dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
084a4fcc MCC	114	dimm->grain = TILE_EDAC_ERROR_GRAIN;
084a4fcc MCC	115	dimm->dtype = DEV_UNKNOWN;
5c770755 CM	116
	117	return 0;
	118	}
	119
	120	static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
	121	{
	122	char hv_file[32];
	123	int hv_devhdl;
	124	struct mem_ctl_info *mci;
	125	struct tile_edac_priv *priv;
	126	int rc;
	127
	128	sprintf(hv_file, "mshim/%d", pdev->id);
	129	hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0);
	130	if (hv_devhdl < 0)
	131	return -EINVAL;
	132
	133	/* A TILE MC has a single channel and one chip-select row. */
	134	mci = edac_mc_alloc(sizeof(struct tile_edac_priv),
	135	TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id);
	136	if (mci == NULL)
	137	return -ENOMEM;
	138	priv = mci->pvt_info;
	139	priv->node = pdev->id;
	140	priv->hv_devhdl = hv_devhdl;
	141
	142	mci->dev = &pdev->dev;
	143	mci->mtype_cap = MEM_FLAG_DDR2;
	144	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	145
	146	mci->mod_name = DRV_NAME;
e2e110d7 CM	147	#ifdef __tilegx__
	148	mci->ctl_name = "TILEGx_Memory_Controller";
	149	#else
5c770755	150	mci->ctl_name = "TILEPro_Memory_Controller";
e2e110d7	151	#endif
5c770755 CM	152	mci->dev_name = dev_name(&pdev->dev);
	153	mci->edac_check = tile_edac_check;
	154
	155	/*
	156	* Initialize the MC control structure 'csrows' table
	157	* with the mapping and control information.
	158	*/
	159	if (tile_edac_init_csrows(mci)) {
	160	/* No csrows found. */
	161	mci->edac_cap = EDAC_FLAG_NONE;
	162	} else {
	163	mci->edac_cap = EDAC_FLAG_SECDED;
	164	}
	165
	166	platform_set_drvdata(pdev, mci);
	167
	168	/* Register with EDAC core */
	169	rc = edac_mc_add_mc(mci);
	170	if (rc) {
	171	dev_err(&pdev->dev, "failed to register with EDAC core\n");
	172	edac_mc_free(mci);
	173	return rc;
	174	}
	175
	176	return 0;
	177	}
	178
	179	static int __devexit tile_edac_mc_remove(struct platform_device *pdev)
	180	{
	181	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
	182
	183	edac_mc_del_mc(&pdev->dev);
	184	if (mci)
	185	edac_mc_free(mci);
	186	return 0;
	187	}
	188
	189	static struct platform_driver tile_edac_mc_driver = {
	190	.driver = {
	191	.name = DRV_NAME,
	192	.owner = THIS_MODULE,
	193	},
	194	.probe = tile_edac_mc_probe,
	195	.remove = __devexit_p(tile_edac_mc_remove),
	196	};
	197
	198	/*
	199	* Driver init routine.
	200	*/
	201	static int __init tile_edac_init(void)
	202	{
	203	char hv_file[32];
	204	struct platform_device *pdev;
	205	int i, err, num = 0;
	206
	207	/* Only support POLL mode. */
	208	edac_op_state = EDAC_OPSTATE_POLL;
	209
	210	err = platform_driver_register(&tile_edac_mc_driver);
	211	if (err)
	212	return err;
	213
	214	for (i = 0; i < TILE_MAX_MSHIMS; i++) {
	215	/*
216	* Not all memory controllers are configured such as in the
217	* case of a simulator. So we register only those mshims
218	* that are configured by the hypervisor.
219	*/
220	sprintf(hv_file, "mshim/%d", i);
221	if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0)
222	continue;
223
224	pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0);
225	if (IS_ERR(pdev))
226	continue;
227	mshim_pdev[i] = pdev;
228	num++;
229	}
230
231	if (num == 0) {
232	platform_driver_unregister(&tile_edac_mc_driver);
233	return -ENODEV;
234	}
235	return 0;
236	}
237
238	/*
239	* Driver cleanup routine.
240	*/
241	static void __exit tile_edac_exit(void)
242	{
243	int i;
244
245	for (i = 0; i < TILE_MAX_MSHIMS; i++) {
246	struct platform_device *pdev = mshim_pdev[i];
247	if (!pdev)
248	continue;
249
250	platform_set_drvdata(pdev, NULL);
251	platform_device_unregister(pdev);
252	}
253	platform_driver_unregister(&tile_edac_mc_driver);
254	}
255
256	module_init(tile_edac_init);
257	module_exit(tile_edac_exit);