Commit | Line | Data |
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c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
e524f616 | 21 | #include <linux/compiler.h> |
ed568912 | 22 | #include <linux/delay.h> |
cf3e72fd | 23 | #include <linux/dma-mapping.h> |
c26f0234 | 24 | #include <linux/gfp.h> |
a7fb60db SR |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/kernel.h> | |
faa2fb4e | 28 | #include <linux/mm.h> |
a7fb60db | 29 | #include <linux/module.h> |
ad3c0fe8 | 30 | #include <linux/moduleparam.h> |
a7fb60db | 31 | #include <linux/pci.h> |
c26f0234 | 32 | #include <linux/spinlock.h> |
cf3e72fd | 33 | |
c26f0234 | 34 | #include <asm/page.h> |
ee71c2f9 | 35 | #include <asm/system.h> |
ed568912 | 36 | |
ea8d006b SR |
37 | #ifdef CONFIG_PPC_PMAC |
38 | #include <asm/pmac_feature.h> | |
39 | #endif | |
40 | ||
ed568912 | 41 | #include "fw-ohci.h" |
a7fb60db | 42 | #include "fw-transaction.h" |
ed568912 | 43 | |
a77754a7 KH |
44 | #define DESCRIPTOR_OUTPUT_MORE 0 |
45 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
46 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
47 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
48 | #define DESCRIPTOR_STATUS (1 << 11) | |
49 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
50 | #define DESCRIPTOR_PING (1 << 7) | |
51 | #define DESCRIPTOR_YY (1 << 6) | |
52 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
53 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
54 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
55 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
56 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
57 | |
58 | struct descriptor { | |
59 | __le16 req_count; | |
60 | __le16 control; | |
61 | __le32 data_address; | |
62 | __le32 branch_address; | |
63 | __le16 res_count; | |
64 | __le16 transfer_status; | |
65 | } __attribute__((aligned(16))); | |
66 | ||
295e3feb KH |
67 | struct db_descriptor { |
68 | __le16 first_size; | |
69 | __le16 control; | |
70 | __le16 second_req_count; | |
71 | __le16 first_req_count; | |
72 | __le32 branch_address; | |
73 | __le16 second_res_count; | |
74 | __le16 first_res_count; | |
75 | __le32 reserved0; | |
76 | __le32 first_buffer; | |
77 | __le32 second_buffer; | |
78 | __le32 reserved1; | |
79 | } __attribute__((aligned(16))); | |
80 | ||
a77754a7 KH |
81 | #define CONTROL_SET(regs) (regs) |
82 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
83 | #define COMMAND_PTR(regs) ((regs) + 12) | |
84 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 85 | |
32b46093 | 86 | struct ar_buffer { |
ed568912 | 87 | struct descriptor descriptor; |
32b46093 KH |
88 | struct ar_buffer *next; |
89 | __le32 data[0]; | |
90 | }; | |
ed568912 | 91 | |
32b46093 KH |
92 | struct ar_context { |
93 | struct fw_ohci *ohci; | |
94 | struct ar_buffer *current_buffer; | |
95 | struct ar_buffer *last_buffer; | |
96 | void *pointer; | |
72e318e0 | 97 | u32 regs; |
ed568912 KH |
98 | struct tasklet_struct tasklet; |
99 | }; | |
100 | ||
30200739 KH |
101 | struct context; |
102 | ||
103 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
104 | struct descriptor *d, | |
105 | struct descriptor *last); | |
fe5ca634 DM |
106 | |
107 | /* | |
108 | * A buffer that contains a block of DMA-able coherent memory used for | |
109 | * storing a portion of a DMA descriptor program. | |
110 | */ | |
111 | struct descriptor_buffer { | |
112 | struct list_head list; | |
113 | dma_addr_t buffer_bus; | |
114 | size_t buffer_size; | |
115 | size_t used; | |
116 | struct descriptor buffer[0]; | |
117 | }; | |
118 | ||
30200739 | 119 | struct context { |
373b2edd | 120 | struct fw_ohci *ohci; |
30200739 | 121 | u32 regs; |
fe5ca634 | 122 | int total_allocation; |
373b2edd | 123 | |
fe5ca634 DM |
124 | /* |
125 | * List of page-sized buffers for storing DMA descriptors. | |
126 | * Head of list contains buffers in use and tail of list contains | |
127 | * free buffers. | |
128 | */ | |
129 | struct list_head buffer_list; | |
130 | ||
131 | /* | |
132 | * Pointer to a buffer inside buffer_list that contains the tail | |
133 | * end of the current DMA program. | |
134 | */ | |
135 | struct descriptor_buffer *buffer_tail; | |
136 | ||
137 | /* | |
138 | * The descriptor containing the branch address of the first | |
139 | * descriptor that has not yet been filled by the device. | |
140 | */ | |
141 | struct descriptor *last; | |
142 | ||
143 | /* | |
144 | * The last descriptor in the DMA program. It contains the branch | |
145 | * address that must be updated upon appending a new descriptor. | |
146 | */ | |
147 | struct descriptor *prev; | |
30200739 KH |
148 | |
149 | descriptor_callback_t callback; | |
150 | ||
373b2edd | 151 | struct tasklet_struct tasklet; |
30200739 | 152 | }; |
30200739 | 153 | |
a77754a7 KH |
154 | #define IT_HEADER_SY(v) ((v) << 0) |
155 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
156 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
157 | #define IT_HEADER_TAG(v) ((v) << 14) | |
158 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
159 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
160 | |
161 | struct iso_context { | |
162 | struct fw_iso_context base; | |
30200739 | 163 | struct context context; |
0642b657 | 164 | int excess_bytes; |
9b32d5f3 KH |
165 | void *header; |
166 | size_t header_length; | |
ed568912 KH |
167 | }; |
168 | ||
169 | #define CONFIG_ROM_SIZE 1024 | |
170 | ||
171 | struct fw_ohci { | |
172 | struct fw_card card; | |
173 | ||
e364cf4e | 174 | u32 version; |
ed568912 KH |
175 | __iomem char *registers; |
176 | dma_addr_t self_id_bus; | |
177 | __le32 *self_id_cpu; | |
178 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 179 | int node_id; |
ed568912 | 180 | int generation; |
e09770db | 181 | int request_generation; /* for timestamping incoming requests */ |
d60d7f1d | 182 | u32 bus_seconds; |
11bf20ad | 183 | bool old_uninorth; |
d34316a4 | 184 | bool bus_reset_packet_quirk; |
ed568912 | 185 | |
c781c06d KH |
186 | /* |
187 | * Spinlock for accessing fw_ohci data. Never call out of | |
188 | * this driver with this lock held. | |
189 | */ | |
ed568912 KH |
190 | spinlock_t lock; |
191 | u32 self_id_buffer[512]; | |
192 | ||
193 | /* Config rom buffers */ | |
194 | __be32 *config_rom; | |
195 | dma_addr_t config_rom_bus; | |
196 | __be32 *next_config_rom; | |
197 | dma_addr_t next_config_rom_bus; | |
198 | u32 next_header; | |
199 | ||
200 | struct ar_context ar_request_ctx; | |
201 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
202 | struct context at_request_ctx; |
203 | struct context at_response_ctx; | |
ed568912 KH |
204 | |
205 | u32 it_context_mask; | |
206 | struct iso_context *it_context_list; | |
207 | u32 ir_context_mask; | |
208 | struct iso_context *ir_context_list; | |
209 | }; | |
210 | ||
95688e97 | 211 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
212 | { |
213 | return container_of(card, struct fw_ohci, card); | |
214 | } | |
215 | ||
295e3feb KH |
216 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
217 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
218 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
219 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
220 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
221 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
222 | |
223 | #define CONTEXT_RUN 0x8000 | |
224 | #define CONTEXT_WAKE 0x1000 | |
225 | #define CONTEXT_DEAD 0x0800 | |
226 | #define CONTEXT_ACTIVE 0x0400 | |
227 | ||
228 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
229 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
230 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
231 | ||
232 | #define FW_OHCI_MAJOR 240 | |
233 | #define OHCI1394_REGISTER_SIZE 0x800 | |
234 | #define OHCI_LOOP_COUNT 500 | |
235 | #define OHCI1394_PCI_HCI_Control 0x40 | |
236 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 237 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 238 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 239 | |
ed568912 KH |
240 | static char ohci_driver_name[] = KBUILD_MODNAME; |
241 | ||
ad3c0fe8 SR |
242 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
243 | ||
a007bb85 | 244 | #define OHCI_PARAM_DEBUG_AT_AR 1 |
ad3c0fe8 | 245 | #define OHCI_PARAM_DEBUG_SELFIDS 2 |
a007bb85 SR |
246 | #define OHCI_PARAM_DEBUG_IRQS 4 |
247 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ | |
ad3c0fe8 SR |
248 | |
249 | static int param_debug; | |
250 | module_param_named(debug, param_debug, int, 0644); | |
251 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |
ad3c0fe8 | 252 | ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) |
a007bb85 SR |
253 | ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) |
254 | ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) | |
255 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) | |
ad3c0fe8 SR |
256 | ", or a combination, or all = -1)"); |
257 | ||
258 | static void log_irqs(u32 evt) | |
259 | { | |
a007bb85 SR |
260 | if (likely(!(param_debug & |
261 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) | |
262 | return; | |
263 | ||
264 | if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && | |
265 | !(evt & OHCI1394_busReset)) | |
ad3c0fe8 SR |
266 | return; |
267 | ||
161b96e7 SR |
268 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
269 | evt & OHCI1394_selfIDComplete ? " selfID" : "", | |
270 | evt & OHCI1394_RQPkt ? " AR_req" : "", | |
271 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | |
272 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | |
273 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | |
274 | evt & OHCI1394_isochRx ? " IR" : "", | |
275 | evt & OHCI1394_isochTx ? " IT" : "", | |
276 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | |
277 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | |
278 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", | |
279 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", | |
280 | evt & OHCI1394_busReset ? " busReset" : "", | |
281 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | |
282 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | |
283 | OHCI1394_respTxComplete | OHCI1394_isochRx | | |
284 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | |
285 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | | |
286 | OHCI1394_regAccessFail | OHCI1394_busReset) | |
ad3c0fe8 SR |
287 | ? " ?" : ""); |
288 | } | |
289 | ||
290 | static const char *speed[] = { | |
291 | [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", | |
292 | }; | |
293 | static const char *power[] = { | |
294 | [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", | |
295 | [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", | |
296 | }; | |
297 | static const char port[] = { '.', '-', 'p', 'c', }; | |
298 | ||
299 | static char _p(u32 *s, int shift) | |
300 | { | |
301 | return port[*s >> shift & 3]; | |
302 | } | |
303 | ||
08ddb2f4 | 304 | static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) |
ad3c0fe8 SR |
305 | { |
306 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | |
307 | return; | |
308 | ||
161b96e7 SR |
309 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", |
310 | self_id_count, generation, node_id); | |
ad3c0fe8 SR |
311 | |
312 | for (; self_id_count--; ++s) | |
313 | if ((*s & 1 << 23) == 0) | |
161b96e7 SR |
314 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " |
315 | "%s gc=%d %s %s%s%s\n", | |
316 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | |
317 | speed[*s >> 14 & 3], *s >> 16 & 63, | |
318 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | |
319 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | |
ad3c0fe8 | 320 | else |
161b96e7 SR |
321 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", |
322 | *s, *s >> 24 & 63, | |
323 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | |
324 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | |
ad3c0fe8 SR |
325 | } |
326 | ||
327 | static const char *evts[] = { | |
328 | [0x00] = "evt_no_status", [0x01] = "-reserved-", | |
329 | [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", | |
330 | [0x04] = "evt_underrun", [0x05] = "evt_overrun", | |
331 | [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", | |
332 | [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", | |
333 | [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", | |
334 | [0x0c] = "-reserved-", [0x0d] = "-reserved-", | |
335 | [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", | |
336 | [0x10] = "-reserved-", [0x11] = "ack_complete", | |
337 | [0x12] = "ack_pending ", [0x13] = "-reserved-", | |
338 | [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", | |
339 | [0x16] = "ack_busy_B", [0x17] = "-reserved-", | |
340 | [0x18] = "-reserved-", [0x19] = "-reserved-", | |
341 | [0x1a] = "-reserved-", [0x1b] = "ack_tardy", | |
342 | [0x1c] = "-reserved-", [0x1d] = "ack_data_error", | |
343 | [0x1e] = "ack_type_error", [0x1f] = "-reserved-", | |
344 | [0x20] = "pending/cancelled", | |
345 | }; | |
346 | static const char *tcodes[] = { | |
347 | [0x0] = "QW req", [0x1] = "BW req", | |
348 | [0x2] = "W resp", [0x3] = "-reserved-", | |
349 | [0x4] = "QR req", [0x5] = "BR req", | |
350 | [0x6] = "QR resp", [0x7] = "BR resp", | |
351 | [0x8] = "cycle start", [0x9] = "Lk req", | |
352 | [0xa] = "async stream packet", [0xb] = "Lk resp", | |
353 | [0xc] = "-reserved-", [0xd] = "-reserved-", | |
354 | [0xe] = "link internal", [0xf] = "-reserved-", | |
355 | }; | |
356 | static const char *phys[] = { | |
357 | [0x0] = "phy config packet", [0x1] = "link-on packet", | |
358 | [0x2] = "self-id packet", [0x3] = "-reserved-", | |
359 | }; | |
360 | ||
361 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |
362 | { | |
363 | int tcode = header[0] >> 4 & 0xf; | |
364 | char specific[12]; | |
365 | ||
366 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) | |
367 | return; | |
368 | ||
369 | if (unlikely(evt >= ARRAY_SIZE(evts))) | |
370 | evt = 0x1f; | |
371 | ||
08ddb2f4 | 372 | if (evt == OHCI1394_evt_bus_reset) { |
161b96e7 SR |
373 | fw_notify("A%c evt_bus_reset, generation %d\n", |
374 | dir, (header[2] >> 16) & 0xff); | |
08ddb2f4 SR |
375 | return; |
376 | } | |
377 | ||
ad3c0fe8 | 378 | if (header[0] == ~header[1]) { |
161b96e7 SR |
379 | fw_notify("A%c %s, %s, %08x\n", |
380 | dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); | |
ad3c0fe8 SR |
381 | return; |
382 | } | |
383 | ||
384 | switch (tcode) { | |
385 | case 0x0: case 0x6: case 0x8: | |
386 | snprintf(specific, sizeof(specific), " = %08x", | |
387 | be32_to_cpu((__force __be32)header[3])); | |
388 | break; | |
389 | case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: | |
390 | snprintf(specific, sizeof(specific), " %x,%x", | |
391 | header[3] >> 16, header[3] & 0xffff); | |
392 | break; | |
393 | default: | |
394 | specific[0] = '\0'; | |
395 | } | |
396 | ||
397 | switch (tcode) { | |
398 | case 0xe: case 0xa: | |
161b96e7 | 399 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); |
ad3c0fe8 SR |
400 | break; |
401 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | |
161b96e7 SR |
402 | fw_notify("A%c spd %x tl %02x, " |
403 | "%04x -> %04x, %s, " | |
404 | "%s, %04x%08x%s\n", | |
405 | dir, speed, header[0] >> 10 & 0x3f, | |
406 | header[1] >> 16, header[0] >> 16, evts[evt], | |
407 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | |
ad3c0fe8 SR |
408 | break; |
409 | default: | |
161b96e7 SR |
410 | fw_notify("A%c spd %x tl %02x, " |
411 | "%04x -> %04x, %s, " | |
412 | "%s%s\n", | |
413 | dir, speed, header[0] >> 10 & 0x3f, | |
414 | header[1] >> 16, header[0] >> 16, evts[evt], | |
415 | tcodes[tcode], specific); | |
ad3c0fe8 SR |
416 | } |
417 | } | |
418 | ||
419 | #else | |
420 | ||
421 | #define log_irqs(evt) | |
08ddb2f4 | 422 | #define log_selfids(node_id, generation, self_id_count, sid) |
ad3c0fe8 SR |
423 | #define log_ar_at_event(dir, speed, header, evt) |
424 | ||
425 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | |
426 | ||
95688e97 | 427 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
428 | { |
429 | writel(data, ohci->registers + offset); | |
430 | } | |
431 | ||
95688e97 | 432 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
433 | { |
434 | return readl(ohci->registers + offset); | |
435 | } | |
436 | ||
95688e97 | 437 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
438 | { |
439 | /* Do a dummy read to flush writes. */ | |
440 | reg_read(ohci, OHCI1394_Version); | |
441 | } | |
442 | ||
443 | static int | |
444 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
445 | int clear_bits, int set_bits) | |
446 | { | |
447 | struct fw_ohci *ohci = fw_ohci(card); | |
448 | u32 val, old; | |
449 | ||
450 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
362e901c | 451 | flush_writes(ohci); |
ed568912 KH |
452 | msleep(2); |
453 | val = reg_read(ohci, OHCI1394_PhyControl); | |
454 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
455 | fw_error("failed to set phy reg bits.\n"); | |
456 | return -EBUSY; | |
457 | } | |
458 | ||
459 | old = OHCI1394_PhyControl_ReadData(val); | |
460 | old = (old & ~clear_bits) | set_bits; | |
461 | reg_write(ohci, OHCI1394_PhyControl, | |
462 | OHCI1394_PhyControl_Write(addr, old)); | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
32b46093 | 467 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 468 | { |
32b46093 KH |
469 | struct device *dev = ctx->ohci->card.device; |
470 | struct ar_buffer *ab; | |
f5101d58 | 471 | dma_addr_t uninitialized_var(ab_bus); |
32b46093 KH |
472 | size_t offset; |
473 | ||
bde1709a | 474 | ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); |
32b46093 KH |
475 | if (ab == NULL) |
476 | return -ENOMEM; | |
477 | ||
2d826cc5 | 478 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
479 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
480 | DESCRIPTOR_STATUS | | |
481 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
482 | offset = offsetof(struct ar_buffer, data); |
483 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
484 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
485 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
486 | ab->descriptor.branch_address = 0; | |
487 | ||
ec839e43 | 488 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
489 | ctx->last_buffer->next = ab; |
490 | ctx->last_buffer = ab; | |
491 | ||
a77754a7 | 492 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 493 | flush_writes(ctx->ohci); |
32b46093 KH |
494 | |
495 | return 0; | |
ed568912 KH |
496 | } |
497 | ||
11bf20ad SR |
498 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
499 | #define cond_le32_to_cpu(v) \ | |
500 | (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v)) | |
501 | #else | |
502 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
503 | #endif | |
504 | ||
32b46093 | 505 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 506 | { |
ed568912 | 507 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
508 | struct fw_packet p; |
509 | u32 status, length, tcode; | |
43286568 | 510 | int evt; |
2639a6fb | 511 | |
11bf20ad SR |
512 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
513 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
514 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
515 | |
516 | tcode = (p.header[0] >> 4) & 0x0f; | |
517 | switch (tcode) { | |
518 | case TCODE_WRITE_QUADLET_REQUEST: | |
519 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 520 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 521 | p.header_length = 16; |
32b46093 | 522 | p.payload_length = 0; |
2639a6fb KH |
523 | break; |
524 | ||
2639a6fb | 525 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 526 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
527 | p.header_length = 16; |
528 | p.payload_length = 0; | |
529 | break; | |
530 | ||
531 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
532 | case TCODE_READ_BLOCK_RESPONSE: |
533 | case TCODE_LOCK_REQUEST: | |
534 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 535 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 536 | p.header_length = 16; |
32b46093 | 537 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
538 | break; |
539 | ||
540 | case TCODE_WRITE_RESPONSE: | |
541 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 542 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 543 | p.header_length = 12; |
32b46093 | 544 | p.payload_length = 0; |
2639a6fb | 545 | break; |
ccff9629 SR |
546 | |
547 | default: | |
548 | /* FIXME: Stop context, discard everything, and restart? */ | |
549 | p.header_length = 0; | |
550 | p.payload_length = 0; | |
2639a6fb | 551 | } |
ed568912 | 552 | |
32b46093 KH |
553 | p.payload = (void *) buffer + p.header_length; |
554 | ||
555 | /* FIXME: What to do about evt_* errors? */ | |
556 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 557 | status = cond_le32_to_cpu(buffer[length]); |
43286568 | 558 | evt = (status >> 16) & 0x1f; |
32b46093 | 559 | |
43286568 | 560 | p.ack = evt - 16; |
32b46093 KH |
561 | p.speed = (status >> 21) & 0x7; |
562 | p.timestamp = status & 0xffff; | |
563 | p.generation = ohci->request_generation; | |
ed568912 | 564 | |
43286568 | 565 | log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8 | 566 | |
c781c06d KH |
567 | /* |
568 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
569 | * the new generation number when a bus reset happens (see |
570 | * section 8.4.2.3). This helps us determine when a request | |
571 | * was received and make sure we send the response in the same | |
572 | * generation. We only need this for requests; for responses | |
573 | * we use the unique tlabel for finding the matching | |
c781c06d | 574 | * request. |
d34316a4 SR |
575 | * |
576 | * Alas some chips sometimes emit bus reset packets with a | |
577 | * wrong generation. We set the correct generation for these | |
578 | * at a slightly incorrect time (in bus_reset_tasklet). | |
c781c06d | 579 | */ |
d34316a4 SR |
580 | if (evt == OHCI1394_evt_bus_reset) { |
581 | if (!ohci->bus_reset_packet_quirk) | |
582 | ohci->request_generation = (p.header[2] >> 16) & 0xff; | |
583 | } else if (ctx == &ohci->ar_request_ctx) { | |
2639a6fb | 584 | fw_core_handle_request(&ohci->card, &p); |
d34316a4 | 585 | } else { |
2639a6fb | 586 | fw_core_handle_response(&ohci->card, &p); |
d34316a4 | 587 | } |
ed568912 | 588 | |
32b46093 KH |
589 | return buffer + length + 1; |
590 | } | |
ed568912 | 591 | |
32b46093 KH |
592 | static void ar_context_tasklet(unsigned long data) |
593 | { | |
594 | struct ar_context *ctx = (struct ar_context *)data; | |
595 | struct fw_ohci *ohci = ctx->ohci; | |
596 | struct ar_buffer *ab; | |
597 | struct descriptor *d; | |
598 | void *buffer, *end; | |
599 | ||
600 | ab = ctx->current_buffer; | |
601 | d = &ab->descriptor; | |
602 | ||
603 | if (d->res_count == 0) { | |
604 | size_t size, rest, offset; | |
6b84236d JW |
605 | dma_addr_t start_bus; |
606 | void *start; | |
32b46093 | 607 | |
c781c06d KH |
608 | /* |
609 | * This descriptor is finished and we may have a | |
32b46093 | 610 | * packet split across this and the next buffer. We |
c781c06d KH |
611 | * reuse the page for reassembling the split packet. |
612 | */ | |
32b46093 KH |
613 | |
614 | offset = offsetof(struct ar_buffer, data); | |
6b84236d JW |
615 | start = buffer = ab; |
616 | start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
32b46093 | 617 | |
32b46093 KH |
618 | ab = ab->next; |
619 | d = &ab->descriptor; | |
620 | size = buffer + PAGE_SIZE - ctx->pointer; | |
621 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
622 | memmove(buffer, ctx->pointer, size); | |
623 | memcpy(buffer + size, ab->data, rest); | |
624 | ctx->current_buffer = ab; | |
625 | ctx->pointer = (void *) ab->data + rest; | |
626 | end = buffer + size + rest; | |
627 | ||
628 | while (buffer < end) | |
629 | buffer = handle_ar_packet(ctx, buffer); | |
630 | ||
bde1709a | 631 | dma_free_coherent(ohci->card.device, PAGE_SIZE, |
6b84236d | 632 | start, start_bus); |
32b46093 KH |
633 | ar_context_add_page(ctx); |
634 | } else { | |
635 | buffer = ctx->pointer; | |
636 | ctx->pointer = end = | |
637 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
638 | ||
639 | while (buffer < end) | |
640 | buffer = handle_ar_packet(ctx, buffer); | |
641 | } | |
ed568912 KH |
642 | } |
643 | ||
644 | static int | |
72e318e0 | 645 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 646 | { |
32b46093 | 647 | struct ar_buffer ab; |
ed568912 | 648 | |
72e318e0 KH |
649 | ctx->regs = regs; |
650 | ctx->ohci = ohci; | |
651 | ctx->last_buffer = &ab; | |
ed568912 KH |
652 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
653 | ||
32b46093 KH |
654 | ar_context_add_page(ctx); |
655 | ar_context_add_page(ctx); | |
656 | ctx->current_buffer = ab.next; | |
657 | ctx->pointer = ctx->current_buffer->data; | |
658 | ||
2aef469a KH |
659 | return 0; |
660 | } | |
661 | ||
662 | static void ar_context_run(struct ar_context *ctx) | |
663 | { | |
664 | struct ar_buffer *ab = ctx->current_buffer; | |
665 | dma_addr_t ab_bus; | |
666 | size_t offset; | |
667 | ||
668 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 669 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
670 | |
671 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 672 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 673 | flush_writes(ctx->ohci); |
ed568912 | 674 | } |
373b2edd | 675 | |
a186b4a6 JW |
676 | static struct descriptor * |
677 | find_branch_descriptor(struct descriptor *d, int z) | |
678 | { | |
679 | int b, key; | |
680 | ||
681 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
682 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
683 | ||
684 | /* figure out which descriptor the branch address goes in */ | |
685 | if (z == 2 && (b == 3 || key == 2)) | |
686 | return d; | |
687 | else | |
688 | return d + z - 1; | |
689 | } | |
690 | ||
30200739 KH |
691 | static void context_tasklet(unsigned long data) |
692 | { | |
693 | struct context *ctx = (struct context *) data; | |
30200739 KH |
694 | struct descriptor *d, *last; |
695 | u32 address; | |
696 | int z; | |
fe5ca634 | 697 | struct descriptor_buffer *desc; |
30200739 | 698 | |
fe5ca634 DM |
699 | desc = list_entry(ctx->buffer_list.next, |
700 | struct descriptor_buffer, list); | |
701 | last = ctx->last; | |
30200739 | 702 | while (last->branch_address != 0) { |
fe5ca634 | 703 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
704 | address = le32_to_cpu(last->branch_address); |
705 | z = address & 0xf; | |
fe5ca634 DM |
706 | address &= ~0xf; |
707 | ||
708 | /* If the branch address points to a buffer outside of the | |
709 | * current buffer, advance to the next buffer. */ | |
710 | if (address < desc->buffer_bus || | |
711 | address >= desc->buffer_bus + desc->used) | |
712 | desc = list_entry(desc->list.next, | |
713 | struct descriptor_buffer, list); | |
714 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 715 | last = find_branch_descriptor(d, z); |
30200739 KH |
716 | |
717 | if (!ctx->callback(ctx, d, last)) | |
718 | break; | |
719 | ||
fe5ca634 DM |
720 | if (old_desc != desc) { |
721 | /* If we've advanced to the next buffer, move the | |
722 | * previous buffer to the free list. */ | |
723 | unsigned long flags; | |
724 | old_desc->used = 0; | |
725 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
726 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
727 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
728 | } | |
729 | ctx->last = last; | |
30200739 KH |
730 | } |
731 | } | |
732 | ||
fe5ca634 DM |
733 | /* |
734 | * Allocate a new buffer and add it to the list of free buffers for this | |
735 | * context. Must be called with ohci->lock held. | |
736 | */ | |
737 | static int | |
738 | context_add_buffer(struct context *ctx) | |
739 | { | |
740 | struct descriptor_buffer *desc; | |
f5101d58 | 741 | dma_addr_t uninitialized_var(bus_addr); |
fe5ca634 DM |
742 | int offset; |
743 | ||
744 | /* | |
745 | * 16MB of descriptors should be far more than enough for any DMA | |
746 | * program. This will catch run-away userspace or DoS attacks. | |
747 | */ | |
748 | if (ctx->total_allocation >= 16*1024*1024) | |
749 | return -ENOMEM; | |
750 | ||
751 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
752 | &bus_addr, GFP_ATOMIC); | |
753 | if (!desc) | |
754 | return -ENOMEM; | |
755 | ||
756 | offset = (void *)&desc->buffer - (void *)desc; | |
757 | desc->buffer_size = PAGE_SIZE - offset; | |
758 | desc->buffer_bus = bus_addr + offset; | |
759 | desc->used = 0; | |
760 | ||
761 | list_add_tail(&desc->list, &ctx->buffer_list); | |
762 | ctx->total_allocation += PAGE_SIZE; | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
30200739 KH |
767 | static int |
768 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
fe5ca634 | 769 | u32 regs, descriptor_callback_t callback) |
30200739 KH |
770 | { |
771 | ctx->ohci = ohci; | |
772 | ctx->regs = regs; | |
fe5ca634 DM |
773 | ctx->total_allocation = 0; |
774 | ||
775 | INIT_LIST_HEAD(&ctx->buffer_list); | |
776 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
777 | return -ENOMEM; |
778 | ||
fe5ca634 DM |
779 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
780 | struct descriptor_buffer, list); | |
781 | ||
30200739 KH |
782 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
783 | ctx->callback = callback; | |
784 | ||
c781c06d KH |
785 | /* |
786 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 787 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 788 | * have a descriptor to append DMA programs to. |
c781c06d | 789 | */ |
fe5ca634 DM |
790 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
791 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
792 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
793 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
794 | ctx->last = ctx->buffer_tail->buffer; | |
795 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
796 | |
797 | return 0; | |
798 | } | |
799 | ||
9b32d5f3 | 800 | static void |
30200739 KH |
801 | context_release(struct context *ctx) |
802 | { | |
803 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 804 | struct descriptor_buffer *desc, *tmp; |
30200739 | 805 | |
fe5ca634 DM |
806 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
807 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
808 | desc->buffer_bus - | |
809 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
810 | } |
811 | ||
fe5ca634 | 812 | /* Must be called with ohci->lock held */ |
30200739 KH |
813 | static struct descriptor * |
814 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
815 | { | |
fe5ca634 DM |
816 | struct descriptor *d = NULL; |
817 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
818 | ||
819 | if (z * sizeof(*d) > desc->buffer_size) | |
820 | return NULL; | |
821 | ||
822 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
823 | /* No room for the descriptor in this buffer, so advance to the | |
824 | * next one. */ | |
30200739 | 825 | |
fe5ca634 DM |
826 | if (desc->list.next == &ctx->buffer_list) { |
827 | /* If there is no free buffer next in the list, | |
828 | * allocate one. */ | |
829 | if (context_add_buffer(ctx) < 0) | |
830 | return NULL; | |
831 | } | |
832 | desc = list_entry(desc->list.next, | |
833 | struct descriptor_buffer, list); | |
834 | ctx->buffer_tail = desc; | |
835 | } | |
30200739 | 836 | |
fe5ca634 | 837 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 838 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 839 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
840 | |
841 | return d; | |
842 | } | |
843 | ||
295e3feb | 844 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
845 | { |
846 | struct fw_ohci *ohci = ctx->ohci; | |
847 | ||
a77754a7 | 848 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 849 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
850 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
851 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
852 | flush_writes(ohci); |
853 | } | |
854 | ||
855 | static void context_append(struct context *ctx, | |
856 | struct descriptor *d, int z, int extra) | |
857 | { | |
858 | dma_addr_t d_bus; | |
fe5ca634 | 859 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 860 | |
fe5ca634 | 861 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 862 | |
fe5ca634 DM |
863 | desc->used += (z + extra) * sizeof(*d); |
864 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); | |
865 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 866 | |
a77754a7 | 867 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
868 | flush_writes(ctx->ohci); |
869 | } | |
870 | ||
871 | static void context_stop(struct context *ctx) | |
872 | { | |
873 | u32 reg; | |
b8295668 | 874 | int i; |
30200739 | 875 | |
a77754a7 | 876 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 877 | flush_writes(ctx->ohci); |
30200739 | 878 | |
b8295668 | 879 | for (i = 0; i < 10; i++) { |
a77754a7 | 880 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 KH |
881 | if ((reg & CONTEXT_ACTIVE) == 0) |
882 | break; | |
883 | ||
884 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
b980f5a2 | 885 | mdelay(1); |
b8295668 | 886 | } |
30200739 | 887 | } |
ed568912 | 888 | |
f319b6a0 KH |
889 | struct driver_data { |
890 | struct fw_packet *packet; | |
891 | }; | |
ed568912 | 892 | |
c781c06d KH |
893 | /* |
894 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 895 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
896 | * generation handling and locking around packet queue manipulation. |
897 | */ | |
f319b6a0 KH |
898 | static int |
899 | at_context_queue_packet(struct context *ctx, struct fw_packet *packet) | |
ed568912 | 900 | { |
ed568912 | 901 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 902 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
903 | struct driver_data *driver_data; |
904 | struct descriptor *d, *last; | |
905 | __le32 *header; | |
ed568912 | 906 | int z, tcode; |
f319b6a0 | 907 | u32 reg; |
ed568912 | 908 | |
f319b6a0 KH |
909 | d = context_get_descriptors(ctx, 4, &d_bus); |
910 | if (d == NULL) { | |
911 | packet->ack = RCODE_SEND_ERROR; | |
912 | return -1; | |
ed568912 KH |
913 | } |
914 | ||
a77754a7 | 915 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
916 | d[0].res_count = cpu_to_le16(packet->timestamp); |
917 | ||
c781c06d KH |
918 | /* |
919 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
920 | * from the IEEE1394 layout, so shift the fields around |
921 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
922 | * which we need to prepend an extra quadlet. |
923 | */ | |
f319b6a0 KH |
924 | |
925 | header = (__le32 *) &d[1]; | |
ed568912 | 926 | if (packet->header_length > 8) { |
f319b6a0 KH |
927 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
928 | (packet->speed << 16)); | |
929 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
930 | (packet->header[0] & 0xffff0000)); | |
931 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
932 | |
933 | tcode = (packet->header[0] >> 4) & 0x0f; | |
934 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 935 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 936 | else |
f319b6a0 KH |
937 | header[3] = (__force __le32) packet->header[3]; |
938 | ||
939 | d[0].req_count = cpu_to_le16(packet->header_length); | |
ed568912 | 940 | } else { |
f319b6a0 KH |
941 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
942 | (packet->speed << 16)); | |
943 | header[1] = cpu_to_le32(packet->header[0]); | |
944 | header[2] = cpu_to_le32(packet->header[1]); | |
945 | d[0].req_count = cpu_to_le16(12); | |
ed568912 KH |
946 | } |
947 | ||
f319b6a0 KH |
948 | driver_data = (struct driver_data *) &d[3]; |
949 | driver_data->packet = packet; | |
20d11673 | 950 | packet->driver_data = driver_data; |
a186b4a6 | 951 | |
f319b6a0 KH |
952 | if (packet->payload_length > 0) { |
953 | payload_bus = | |
954 | dma_map_single(ohci->card.device, packet->payload, | |
955 | packet->payload_length, DMA_TO_DEVICE); | |
956 | if (dma_mapping_error(payload_bus)) { | |
957 | packet->ack = RCODE_SEND_ERROR; | |
958 | return -1; | |
959 | } | |
960 | ||
961 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
962 | d[2].data_address = cpu_to_le32(payload_bus); | |
963 | last = &d[2]; | |
964 | z = 3; | |
ed568912 | 965 | } else { |
f319b6a0 KH |
966 | last = &d[0]; |
967 | z = 2; | |
ed568912 | 968 | } |
ed568912 | 969 | |
a77754a7 KH |
970 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
971 | DESCRIPTOR_IRQ_ALWAYS | | |
972 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 973 | |
76f73ca1 JW |
974 | /* |
975 | * If the controller and packet generations don't match, we need to | |
976 | * bail out and try again. If IntEvent.busReset is set, the AT context | |
977 | * is halted, so appending to the context and trying to run it is | |
978 | * futile. Most controllers do the right thing and just flush the AT | |
979 | * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but | |
980 | * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind | |
981 | * up stalling out. So we just bail out in software and try again | |
982 | * later, and everyone is happy. | |
983 | * FIXME: Document how the locking works. | |
984 | */ | |
985 | if (ohci->generation != packet->generation || | |
986 | reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
ab88ca48 SR |
987 | if (packet->payload_length > 0) |
988 | dma_unmap_single(ohci->card.device, payload_bus, | |
989 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
990 | packet->ack = RCODE_GENERATION; |
991 | return -1; | |
992 | } | |
993 | ||
994 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 995 | |
f319b6a0 | 996 | /* If the context isn't already running, start it up. */ |
a77754a7 | 997 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 998 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
999 | context_run(ctx, 0); |
1000 | ||
1001 | return 0; | |
ed568912 KH |
1002 | } |
1003 | ||
f319b6a0 KH |
1004 | static int handle_at_packet(struct context *context, |
1005 | struct descriptor *d, | |
1006 | struct descriptor *last) | |
ed568912 | 1007 | { |
f319b6a0 | 1008 | struct driver_data *driver_data; |
ed568912 | 1009 | struct fw_packet *packet; |
f319b6a0 KH |
1010 | struct fw_ohci *ohci = context->ohci; |
1011 | dma_addr_t payload_bus; | |
ed568912 KH |
1012 | int evt; |
1013 | ||
f319b6a0 KH |
1014 | if (last->transfer_status == 0) |
1015 | /* This descriptor isn't done yet, stop iteration. */ | |
1016 | return 0; | |
ed568912 | 1017 | |
f319b6a0 KH |
1018 | driver_data = (struct driver_data *) &d[3]; |
1019 | packet = driver_data->packet; | |
1020 | if (packet == NULL) | |
1021 | /* This packet was cancelled, just continue. */ | |
1022 | return 1; | |
730c32f5 | 1023 | |
f319b6a0 KH |
1024 | payload_bus = le32_to_cpu(last->data_address); |
1025 | if (payload_bus != 0) | |
1026 | dma_unmap_single(ohci->card.device, payload_bus, | |
ed568912 | 1027 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 1028 | |
f319b6a0 KH |
1029 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1030 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 1031 | |
ad3c0fe8 SR |
1032 | log_ar_at_event('T', packet->speed, packet->header, evt); |
1033 | ||
f319b6a0 KH |
1034 | switch (evt) { |
1035 | case OHCI1394_evt_timeout: | |
1036 | /* Async response transmit timed out. */ | |
1037 | packet->ack = RCODE_CANCELLED; | |
1038 | break; | |
ed568912 | 1039 | |
f319b6a0 | 1040 | case OHCI1394_evt_flushed: |
c781c06d KH |
1041 | /* |
1042 | * The packet was flushed should give same error as | |
1043 | * when we try to use a stale generation count. | |
1044 | */ | |
f319b6a0 KH |
1045 | packet->ack = RCODE_GENERATION; |
1046 | break; | |
ed568912 | 1047 | |
f319b6a0 | 1048 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
1049 | /* |
1050 | * Using a valid (current) generation count, but the | |
1051 | * node is not on the bus or not sending acks. | |
1052 | */ | |
f319b6a0 KH |
1053 | packet->ack = RCODE_NO_ACK; |
1054 | break; | |
ed568912 | 1055 | |
f319b6a0 KH |
1056 | case ACK_COMPLETE + 0x10: |
1057 | case ACK_PENDING + 0x10: | |
1058 | case ACK_BUSY_X + 0x10: | |
1059 | case ACK_BUSY_A + 0x10: | |
1060 | case ACK_BUSY_B + 0x10: | |
1061 | case ACK_DATA_ERROR + 0x10: | |
1062 | case ACK_TYPE_ERROR + 0x10: | |
1063 | packet->ack = evt - 0x10; | |
1064 | break; | |
ed568912 | 1065 | |
f319b6a0 KH |
1066 | default: |
1067 | packet->ack = RCODE_SEND_ERROR; | |
1068 | break; | |
1069 | } | |
ed568912 | 1070 | |
f319b6a0 | 1071 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 1072 | |
f319b6a0 | 1073 | return 1; |
ed568912 KH |
1074 | } |
1075 | ||
a77754a7 KH |
1076 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
1077 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
1078 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
1079 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
1080 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb KH |
1081 | |
1082 | static void | |
1083 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
1084 | { | |
1085 | struct fw_packet response; | |
1086 | int tcode, length, i; | |
1087 | ||
a77754a7 | 1088 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 1089 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 1090 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
1091 | else |
1092 | length = 4; | |
1093 | ||
1094 | i = csr - CSR_CONFIG_ROM; | |
1095 | if (i + length > CONFIG_ROM_SIZE) { | |
1096 | fw_fill_response(&response, packet->header, | |
1097 | RCODE_ADDRESS_ERROR, NULL, 0); | |
1098 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
1099 | fw_fill_response(&response, packet->header, | |
1100 | RCODE_TYPE_ERROR, NULL, 0); | |
1101 | } else { | |
1102 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
1103 | (void *) ohci->config_rom + i, length); | |
1104 | } | |
1105 | ||
1106 | fw_core_handle_response(&ohci->card, &response); | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
1111 | { | |
1112 | struct fw_packet response; | |
1113 | int tcode, length, ext_tcode, sel; | |
1114 | __be32 *payload, lock_old; | |
1115 | u32 lock_arg, lock_data; | |
1116 | ||
a77754a7 KH |
1117 | tcode = HEADER_GET_TCODE(packet->header[0]); |
1118 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 1119 | payload = packet->payload; |
a77754a7 | 1120 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
1121 | |
1122 | if (tcode == TCODE_LOCK_REQUEST && | |
1123 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
1124 | lock_arg = be32_to_cpu(payload[0]); | |
1125 | lock_data = be32_to_cpu(payload[1]); | |
1126 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
1127 | lock_arg = 0; | |
1128 | lock_data = 0; | |
1129 | } else { | |
1130 | fw_fill_response(&response, packet->header, | |
1131 | RCODE_TYPE_ERROR, NULL, 0); | |
1132 | goto out; | |
1133 | } | |
1134 | ||
1135 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
1136 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
1137 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
1138 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
1139 | ||
1140 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
1141 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
1142 | else | |
1143 | fw_notify("swap not done yet\n"); | |
1144 | ||
1145 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 1146 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
1147 | out: |
1148 | fw_core_handle_response(&ohci->card, &response); | |
1149 | } | |
1150 | ||
1151 | static void | |
f319b6a0 | 1152 | handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
1153 | { |
1154 | u64 offset; | |
1155 | u32 csr; | |
1156 | ||
473d28c7 KH |
1157 | if (ctx == &ctx->ohci->at_request_ctx) { |
1158 | packet->ack = ACK_PENDING; | |
1159 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1160 | } | |
93c4cceb KH |
1161 | |
1162 | offset = | |
1163 | ((unsigned long long) | |
a77754a7 | 1164 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
1165 | packet->header[2]; |
1166 | csr = offset - CSR_REGISTER_BASE; | |
1167 | ||
1168 | /* Handle config rom reads. */ | |
1169 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
1170 | handle_local_rom(ctx->ohci, packet, csr); | |
1171 | else switch (csr) { | |
1172 | case CSR_BUS_MANAGER_ID: | |
1173 | case CSR_BANDWIDTH_AVAILABLE: | |
1174 | case CSR_CHANNELS_AVAILABLE_HI: | |
1175 | case CSR_CHANNELS_AVAILABLE_LO: | |
1176 | handle_local_lock(ctx->ohci, packet, csr); | |
1177 | break; | |
1178 | default: | |
1179 | if (ctx == &ctx->ohci->at_request_ctx) | |
1180 | fw_core_handle_request(&ctx->ohci->card, packet); | |
1181 | else | |
1182 | fw_core_handle_response(&ctx->ohci->card, packet); | |
1183 | break; | |
1184 | } | |
473d28c7 KH |
1185 | |
1186 | if (ctx == &ctx->ohci->at_response_ctx) { | |
1187 | packet->ack = ACK_COMPLETE; | |
1188 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1189 | } | |
93c4cceb | 1190 | } |
e636fe25 | 1191 | |
ed568912 | 1192 | static void |
f319b6a0 | 1193 | at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 1194 | { |
ed568912 | 1195 | unsigned long flags; |
f319b6a0 | 1196 | int retval; |
ed568912 KH |
1197 | |
1198 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1199 | ||
a77754a7 | 1200 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 1201 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
1202 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1203 | handle_local_request(ctx, packet); | |
1204 | return; | |
e636fe25 | 1205 | } |
ed568912 | 1206 | |
f319b6a0 | 1207 | retval = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1208 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1209 | ||
f319b6a0 KH |
1210 | if (retval < 0) |
1211 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
a186b4a6 | 1212 | |
ed568912 KH |
1213 | } |
1214 | ||
1215 | static void bus_reset_tasklet(unsigned long data) | |
1216 | { | |
1217 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1218 | int self_id_count, i, j, reg; |
ed568912 KH |
1219 | int generation, new_generation; |
1220 | unsigned long flags; | |
4eaff7d6 SR |
1221 | void *free_rom = NULL; |
1222 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
1223 | |
1224 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1225 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1226 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1227 | return; |
1228 | } | |
02ff8f8e SR |
1229 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1230 | fw_notify("malconfigured bus\n"); | |
1231 | return; | |
1232 | } | |
1233 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1234 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1235 | |
c8a9a498 SR |
1236 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1237 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | |
1238 | fw_notify("inconsistent self IDs\n"); | |
1239 | return; | |
1240 | } | |
c781c06d KH |
1241 | /* |
1242 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1243 | * bytes in the self ID receive buffer. Since we also receive |
1244 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1245 | * bit extra to get the actual number of self IDs. |
1246 | */ | |
c8a9a498 | 1247 | self_id_count = (reg >> 3) & 0x3ff; |
016bf3df SR |
1248 | if (self_id_count == 0) { |
1249 | fw_notify("inconsistent self IDs\n"); | |
1250 | return; | |
1251 | } | |
11bf20ad | 1252 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1253 | rmb(); |
ed568912 KH |
1254 | |
1255 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
c8a9a498 SR |
1256 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { |
1257 | fw_notify("inconsistent self IDs\n"); | |
1258 | return; | |
1259 | } | |
11bf20ad SR |
1260 | ohci->self_id_buffer[j] = |
1261 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1262 | } |
ee71c2f9 | 1263 | rmb(); |
ed568912 | 1264 | |
c781c06d KH |
1265 | /* |
1266 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1267 | * problem we face is that a new bus reset can start while we |
1268 | * read out the self IDs from the DMA buffer. If this happens, | |
1269 | * the DMA buffer will be overwritten with new self IDs and we | |
1270 | * will read out inconsistent data. The OHCI specification | |
1271 | * (section 11.2) recommends a technique similar to | |
1272 | * linux/seqlock.h, where we remember the generation of the | |
1273 | * self IDs in the buffer before reading them out and compare | |
1274 | * it to the current generation after reading them out. If | |
1275 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1276 | * of self IDs. |
1277 | */ | |
ed568912 KH |
1278 | |
1279 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1280 | if (new_generation != generation) { | |
1281 | fw_notify("recursive bus reset detected, " | |
1282 | "discarding self ids\n"); | |
1283 | return; | |
1284 | } | |
1285 | ||
1286 | /* FIXME: Document how the locking works. */ | |
1287 | spin_lock_irqsave(&ohci->lock, flags); | |
1288 | ||
1289 | ohci->generation = generation; | |
f319b6a0 KH |
1290 | context_stop(&ohci->at_request_ctx); |
1291 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1292 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1293 | ||
d34316a4 SR |
1294 | if (ohci->bus_reset_packet_quirk) |
1295 | ohci->request_generation = generation; | |
1296 | ||
c781c06d KH |
1297 | /* |
1298 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1299 | * have to do it under the spinlock also. If a new config rom |
1300 | * was set up before this reset, the old one is now no longer | |
1301 | * in use and we can free it. Update the config rom pointers | |
1302 | * to point to the current config rom and clear the | |
c781c06d KH |
1303 | * next_config_rom pointer so a new udpate can take place. |
1304 | */ | |
ed568912 KH |
1305 | |
1306 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1307 | if (ohci->next_config_rom != ohci->config_rom) { |
1308 | free_rom = ohci->config_rom; | |
1309 | free_rom_bus = ohci->config_rom_bus; | |
1310 | } | |
ed568912 KH |
1311 | ohci->config_rom = ohci->next_config_rom; |
1312 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1313 | ohci->next_config_rom = NULL; | |
1314 | ||
c781c06d KH |
1315 | /* |
1316 | * Restore config_rom image and manually update | |
ed568912 KH |
1317 | * config_rom registers. Writing the header quadlet |
1318 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1319 | * do that last. |
1320 | */ | |
ed568912 KH |
1321 | reg_write(ohci, OHCI1394_BusOptions, |
1322 | be32_to_cpu(ohci->config_rom[2])); | |
1323 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
1324 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
1325 | } | |
1326 | ||
080de8c2 SR |
1327 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1328 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); | |
1329 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); | |
1330 | #endif | |
1331 | ||
ed568912 KH |
1332 | spin_unlock_irqrestore(&ohci->lock, flags); |
1333 | ||
4eaff7d6 SR |
1334 | if (free_rom) |
1335 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1336 | free_rom, free_rom_bus); | |
1337 | ||
08ddb2f4 SR |
1338 | log_selfids(ohci->node_id, generation, |
1339 | self_id_count, ohci->self_id_buffer); | |
ad3c0fe8 | 1340 | |
e636fe25 | 1341 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1342 | self_id_count, ohci->self_id_buffer); |
1343 | } | |
1344 | ||
1345 | static irqreturn_t irq_handler(int irq, void *data) | |
1346 | { | |
1347 | struct fw_ohci *ohci = data; | |
d60d7f1d | 1348 | u32 event, iso_event, cycle_time; |
ed568912 KH |
1349 | int i; |
1350 | ||
1351 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1352 | ||
a515958d | 1353 | if (!event || !~event) |
ed568912 KH |
1354 | return IRQ_NONE; |
1355 | ||
a007bb85 SR |
1356 | /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */ |
1357 | reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); | |
ad3c0fe8 | 1358 | log_irqs(event); |
ed568912 KH |
1359 | |
1360 | if (event & OHCI1394_selfIDComplete) | |
1361 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1362 | ||
1363 | if (event & OHCI1394_RQPkt) | |
1364 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1365 | ||
1366 | if (event & OHCI1394_RSPkt) | |
1367 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1368 | ||
1369 | if (event & OHCI1394_reqTxComplete) | |
1370 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1371 | ||
1372 | if (event & OHCI1394_respTxComplete) | |
1373 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1374 | ||
c889475f | 1375 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1376 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1377 | ||
1378 | while (iso_event) { | |
1379 | i = ffs(iso_event) - 1; | |
30200739 | 1380 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1381 | iso_event &= ~(1 << i); |
1382 | } | |
1383 | ||
c889475f | 1384 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1385 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1386 | ||
1387 | while (iso_event) { | |
1388 | i = ffs(iso_event) - 1; | |
30200739 | 1389 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1390 | iso_event &= ~(1 << i); |
1391 | } | |
1392 | ||
75f7832e JW |
1393 | if (unlikely(event & OHCI1394_regAccessFail)) |
1394 | fw_error("Register access failure - " | |
1395 | "please notify linux1394-devel@lists.sf.net\n"); | |
1396 | ||
e524f616 SR |
1397 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1398 | fw_error("PCI posted write error\n"); | |
1399 | ||
bb9f2206 SR |
1400 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1401 | if (printk_ratelimit()) | |
1402 | fw_notify("isochronous cycle too long\n"); | |
1403 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1404 | OHCI1394_LinkControl_cycleMaster); | |
1405 | } | |
1406 | ||
d60d7f1d KH |
1407 | if (event & OHCI1394_cycle64Seconds) { |
1408 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1409 | if ((cycle_time & 0x80000000) == 0) | |
1410 | ohci->bus_seconds++; | |
1411 | } | |
1412 | ||
ed568912 KH |
1413 | return IRQ_HANDLED; |
1414 | } | |
1415 | ||
2aef469a KH |
1416 | static int software_reset(struct fw_ohci *ohci) |
1417 | { | |
1418 | int i; | |
1419 | ||
1420 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1421 | ||
1422 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1423 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1424 | OHCI1394_HCControl_softReset) == 0) | |
1425 | return 0; | |
1426 | msleep(1); | |
1427 | } | |
1428 | ||
1429 | return -EBUSY; | |
1430 | } | |
1431 | ||
ed568912 KH |
1432 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) |
1433 | { | |
1434 | struct fw_ohci *ohci = fw_ohci(card); | |
1435 | struct pci_dev *dev = to_pci_dev(card->device); | |
02214724 JW |
1436 | u32 lps; |
1437 | int i; | |
ed568912 | 1438 | |
2aef469a KH |
1439 | if (software_reset(ohci)) { |
1440 | fw_error("Failed to reset ohci card.\n"); | |
1441 | return -EBUSY; | |
1442 | } | |
1443 | ||
1444 | /* | |
1445 | * Now enable LPS, which we need in order to start accessing | |
1446 | * most of the registers. In fact, on some cards (ALI M5251), | |
1447 | * accessing registers in the SClk domain without LPS enabled | |
1448 | * will lock up the machine. Wait 50msec to make sure we have | |
02214724 JW |
1449 | * full link enabled. However, with some cards (well, at least |
1450 | * a JMicron PCIe card), we have to try again sometimes. | |
2aef469a KH |
1451 | */ |
1452 | reg_write(ohci, OHCI1394_HCControlSet, | |
1453 | OHCI1394_HCControl_LPS | | |
1454 | OHCI1394_HCControl_postedWriteEnable); | |
1455 | flush_writes(ohci); | |
02214724 JW |
1456 | |
1457 | for (lps = 0, i = 0; !lps && i < 3; i++) { | |
1458 | msleep(50); | |
1459 | lps = reg_read(ohci, OHCI1394_HCControlSet) & | |
1460 | OHCI1394_HCControl_LPS; | |
1461 | } | |
1462 | ||
1463 | if (!lps) { | |
1464 | fw_error("Failed to set Link Power Status\n"); | |
1465 | return -EIO; | |
1466 | } | |
2aef469a KH |
1467 | |
1468 | reg_write(ohci, OHCI1394_HCControlClear, | |
1469 | OHCI1394_HCControl_noByteSwapData); | |
1470 | ||
affc9c24 | 1471 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); |
e896ec43 SR |
1472 | reg_write(ohci, OHCI1394_LinkControlClear, |
1473 | OHCI1394_LinkControl_rcvPhyPkt); | |
2aef469a KH |
1474 | reg_write(ohci, OHCI1394_LinkControlSet, |
1475 | OHCI1394_LinkControl_rcvSelfID | | |
1476 | OHCI1394_LinkControl_cycleTimerEnable | | |
1477 | OHCI1394_LinkControl_cycleMaster); | |
1478 | ||
1479 | reg_write(ohci, OHCI1394_ATRetries, | |
1480 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1481 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1482 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1483 | ||
1484 | ar_context_run(&ohci->ar_request_ctx); | |
1485 | ar_context_run(&ohci->ar_response_ctx); | |
1486 | ||
2aef469a KH |
1487 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); |
1488 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1489 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1490 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1491 | OHCI1394_selfIDComplete | | |
1492 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1493 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1494 | OHCI1394_isochRx | OHCI1394_isochTx | | |
bb9f2206 | 1495 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
75f7832e JW |
1496 | OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | |
1497 | OHCI1394_masterIntEnable); | |
a007bb85 SR |
1498 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) |
1499 | reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); | |
2aef469a KH |
1500 | |
1501 | /* Activate link_on bit and contender bit in our self ID packets.*/ | |
1502 | if (ohci_update_phy_reg(card, 4, 0, | |
1503 | PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) | |
1504 | return -EIO; | |
1505 | ||
c781c06d KH |
1506 | /* |
1507 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1508 | * update mechanism described below in ohci_set_config_rom() |
1509 | * is not active. We have to update ConfigRomHeader and | |
1510 | * BusOptions manually, and the write to ConfigROMmap takes | |
1511 | * effect immediately. We tie this to the enabling of the | |
1512 | * link, so we have a valid config rom before enabling - the | |
1513 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1514 | * values before enabling. | |
1515 | * | |
1516 | * However, when the ConfigROMmap is written, some controllers | |
1517 | * always read back quadlets 0 and 2 from the config rom to | |
1518 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1519 | * They shouldn't do that in this initial case where the link | |
1520 | * isn't enabled. This means we have to use the same | |
1521 | * workaround here, setting the bus header to 0 and then write | |
1522 | * the right values in the bus reset tasklet. | |
1523 | */ | |
1524 | ||
0bd243c4 KH |
1525 | if (config_rom) { |
1526 | ohci->next_config_rom = | |
1527 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1528 | &ohci->next_config_rom_bus, | |
1529 | GFP_KERNEL); | |
1530 | if (ohci->next_config_rom == NULL) | |
1531 | return -ENOMEM; | |
ed568912 | 1532 | |
0bd243c4 KH |
1533 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); |
1534 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1535 | } else { | |
1536 | /* | |
1537 | * In the suspend case, config_rom is NULL, which | |
1538 | * means that we just reuse the old config rom. | |
1539 | */ | |
1540 | ohci->next_config_rom = ohci->config_rom; | |
1541 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1542 | } | |
ed568912 | 1543 | |
0bd243c4 | 1544 | ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]); |
ed568912 KH |
1545 | ohci->next_config_rom[0] = 0; |
1546 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1547 | reg_write(ohci, OHCI1394_BusOptions, |
1548 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1549 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1550 | ||
1551 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1552 | ||
1553 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1554 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1555 | fw_error("Failed to allocate shared interrupt %d.\n", |
1556 | dev->irq); | |
1557 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1558 | ohci->config_rom, ohci->config_rom_bus); | |
1559 | return -EIO; | |
1560 | } | |
1561 | ||
1562 | reg_write(ohci, OHCI1394_HCControlSet, | |
1563 | OHCI1394_HCControl_linkEnable | | |
1564 | OHCI1394_HCControl_BIBimageValid); | |
1565 | flush_writes(ohci); | |
1566 | ||
c781c06d KH |
1567 | /* |
1568 | * We are ready to go, initiate bus reset to finish the | |
1569 | * initialization. | |
1570 | */ | |
ed568912 KH |
1571 | |
1572 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1573 | ||
1574 | return 0; | |
1575 | } | |
1576 | ||
1577 | static int | |
1578 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1579 | { | |
1580 | struct fw_ohci *ohci; | |
1581 | unsigned long flags; | |
4eaff7d6 | 1582 | int retval = -EBUSY; |
ed568912 | 1583 | __be32 *next_config_rom; |
f5101d58 | 1584 | dma_addr_t uninitialized_var(next_config_rom_bus); |
ed568912 KH |
1585 | |
1586 | ohci = fw_ohci(card); | |
1587 | ||
c781c06d KH |
1588 | /* |
1589 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1590 | * mechanism is a bit tricky, but easy enough to use. See |
1591 | * section 5.5.6 in the OHCI specification. | |
1592 | * | |
1593 | * The OHCI controller caches the new config rom address in a | |
1594 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1595 | * for the changes to take place. When the bus reset is | |
1596 | * detected, the controller loads the new values for the | |
1597 | * ConfigRomHeader and BusOptions registers from the specified | |
1598 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1599 | * shadow register. All automatically and atomically. | |
1600 | * | |
1601 | * Now, there's a twist to this story. The automatic load of | |
1602 | * ConfigRomHeader and BusOptions doesn't honor the | |
1603 | * noByteSwapData bit, so with a be32 config rom, the | |
1604 | * controller will load be32 values in to these registers | |
1605 | * during the atomic update, even on litte endian | |
1606 | * architectures. The workaround we use is to put a 0 in the | |
1607 | * header quadlet; 0 is endian agnostic and means that the | |
1608 | * config rom isn't ready yet. In the bus reset tasklet we | |
1609 | * then set up the real values for the two registers. | |
1610 | * | |
1611 | * We use ohci->lock to avoid racing with the code that sets | |
1612 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1613 | */ | |
1614 | ||
1615 | next_config_rom = | |
1616 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1617 | &next_config_rom_bus, GFP_KERNEL); | |
1618 | if (next_config_rom == NULL) | |
1619 | return -ENOMEM; | |
1620 | ||
1621 | spin_lock_irqsave(&ohci->lock, flags); | |
1622 | ||
1623 | if (ohci->next_config_rom == NULL) { | |
1624 | ohci->next_config_rom = next_config_rom; | |
1625 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1626 | ||
1627 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1628 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1629 | length * 4); | |
1630 | ||
1631 | ohci->next_header = config_rom[0]; | |
1632 | ohci->next_config_rom[0] = 0; | |
1633 | ||
1634 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1635 | ohci->next_config_rom_bus); | |
4eaff7d6 | 1636 | retval = 0; |
ed568912 KH |
1637 | } |
1638 | ||
1639 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1640 | ||
c781c06d KH |
1641 | /* |
1642 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1643 | * effect. We clean up the old config rom memory and DMA |
1644 | * mappings in the bus reset tasklet, since the OHCI | |
1645 | * controller could need to access it before the bus reset | |
c781c06d KH |
1646 | * takes effect. |
1647 | */ | |
ed568912 KH |
1648 | if (retval == 0) |
1649 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
4eaff7d6 SR |
1650 | else |
1651 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1652 | next_config_rom, next_config_rom_bus); | |
ed568912 KH |
1653 | |
1654 | return retval; | |
1655 | } | |
1656 | ||
1657 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1658 | { | |
1659 | struct fw_ohci *ohci = fw_ohci(card); | |
1660 | ||
1661 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1662 | } | |
1663 | ||
1664 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1665 | { | |
1666 | struct fw_ohci *ohci = fw_ohci(card); | |
1667 | ||
1668 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1669 | } | |
1670 | ||
730c32f5 KH |
1671 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1672 | { | |
1673 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1674 | struct context *ctx = &ohci->at_request_ctx; |
1675 | struct driver_data *driver_data = packet->driver_data; | |
1676 | int retval = -ENOENT; | |
730c32f5 | 1677 | |
f319b6a0 | 1678 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1679 | |
f319b6a0 KH |
1680 | if (packet->ack != 0) |
1681 | goto out; | |
730c32f5 | 1682 | |
ad3c0fe8 | 1683 | log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a0 KH |
1684 | driver_data->packet = NULL; |
1685 | packet->ack = RCODE_CANCELLED; | |
1686 | packet->callback(packet, &ohci->card, packet->ack); | |
1687 | retval = 0; | |
730c32f5 | 1688 | |
f319b6a0 KH |
1689 | out: |
1690 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1691 | |
f319b6a0 | 1692 | return retval; |
730c32f5 KH |
1693 | } |
1694 | ||
ed568912 KH |
1695 | static int |
1696 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1697 | { | |
080de8c2 SR |
1698 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1699 | return 0; | |
1700 | #else | |
ed568912 KH |
1701 | struct fw_ohci *ohci = fw_ohci(card); |
1702 | unsigned long flags; | |
907293d7 | 1703 | int n, retval = 0; |
ed568912 | 1704 | |
c781c06d KH |
1705 | /* |
1706 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1707 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1708 | */ | |
ed568912 KH |
1709 | |
1710 | spin_lock_irqsave(&ohci->lock, flags); | |
1711 | ||
1712 | if (ohci->generation != generation) { | |
1713 | retval = -ESTALE; | |
1714 | goto out; | |
1715 | } | |
1716 | ||
c781c06d KH |
1717 | /* |
1718 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1719 | * enabled for _all_ nodes on remote buses. | |
1720 | */ | |
907293d7 SR |
1721 | |
1722 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1723 | if (n < 32) | |
1724 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1725 | else | |
1726 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1727 | ||
ed568912 | 1728 | flush_writes(ohci); |
ed568912 | 1729 | out: |
6cad95fe | 1730 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 | 1731 | return retval; |
080de8c2 | 1732 | #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed568912 | 1733 | } |
373b2edd | 1734 | |
d60d7f1d KH |
1735 | static u64 |
1736 | ohci_get_bus_time(struct fw_card *card) | |
1737 | { | |
1738 | struct fw_ohci *ohci = fw_ohci(card); | |
1739 | u32 cycle_time; | |
1740 | u64 bus_time; | |
1741 | ||
1742 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1743 | bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time; | |
1744 | ||
1745 | return bus_time; | |
1746 | } | |
1747 | ||
d2746dc1 KH |
1748 | static int handle_ir_dualbuffer_packet(struct context *context, |
1749 | struct descriptor *d, | |
1750 | struct descriptor *last) | |
ed568912 | 1751 | { |
295e3feb KH |
1752 | struct iso_context *ctx = |
1753 | container_of(context, struct iso_context, context); | |
1754 | struct db_descriptor *db = (struct db_descriptor *) d; | |
c70dc788 | 1755 | __le32 *ir_header; |
9b32d5f3 | 1756 | size_t header_length; |
c70dc788 KH |
1757 | void *p, *end; |
1758 | int i; | |
d2746dc1 | 1759 | |
efbf390a | 1760 | if (db->first_res_count != 0 && db->second_res_count != 0) { |
0642b657 DM |
1761 | if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) { |
1762 | /* This descriptor isn't done yet, stop iteration. */ | |
1763 | return 0; | |
1764 | } | |
1765 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count); | |
1766 | } | |
295e3feb | 1767 | |
c70dc788 KH |
1768 | header_length = le16_to_cpu(db->first_req_count) - |
1769 | le16_to_cpu(db->first_res_count); | |
1770 | ||
1771 | i = ctx->header_length; | |
1772 | p = db + 1; | |
1773 | end = p + header_length; | |
1774 | while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { | |
c781c06d KH |
1775 | /* |
1776 | * The iso header is byteswapped to little endian by | |
15536221 KH |
1777 | * the controller, but the remaining header quadlets |
1778 | * are big endian. We want to present all the headers | |
1779 | * as big endian, so we have to swap the first | |
c781c06d KH |
1780 | * quadlet. |
1781 | */ | |
15536221 KH |
1782 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); |
1783 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
c70dc788 | 1784 | i += ctx->base.header_size; |
0642b657 | 1785 | ctx->excess_bytes += |
efbf390a | 1786 | (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff; |
c70dc788 KH |
1787 | p += ctx->base.header_size + 4; |
1788 | } | |
c70dc788 | 1789 | ctx->header_length = i; |
9b32d5f3 | 1790 | |
0642b657 DM |
1791 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count) - |
1792 | le16_to_cpu(db->second_res_count); | |
1793 | ||
a77754a7 | 1794 | if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788 KH |
1795 | ir_header = (__le32 *) (db + 1); |
1796 | ctx->base.callback(&ctx->base, | |
1797 | le32_to_cpu(ir_header[0]) & 0xffff, | |
9b32d5f3 | 1798 | ctx->header_length, ctx->header, |
295e3feb | 1799 | ctx->base.callback_data); |
9b32d5f3 KH |
1800 | ctx->header_length = 0; |
1801 | } | |
ed568912 | 1802 | |
295e3feb | 1803 | return 1; |
ed568912 KH |
1804 | } |
1805 | ||
a186b4a6 JW |
1806 | static int handle_ir_packet_per_buffer(struct context *context, |
1807 | struct descriptor *d, | |
1808 | struct descriptor *last) | |
1809 | { | |
1810 | struct iso_context *ctx = | |
1811 | container_of(context, struct iso_context, context); | |
bcee893c | 1812 | struct descriptor *pd; |
a186b4a6 | 1813 | __le32 *ir_header; |
bcee893c DM |
1814 | void *p; |
1815 | int i; | |
a186b4a6 | 1816 | |
bcee893c DM |
1817 | for (pd = d; pd <= last; pd++) { |
1818 | if (pd->transfer_status) | |
1819 | break; | |
1820 | } | |
1821 | if (pd > last) | |
a186b4a6 JW |
1822 | /* Descriptor(s) not done yet, stop iteration */ |
1823 | return 0; | |
1824 | ||
a186b4a6 | 1825 | i = ctx->header_length; |
bcee893c | 1826 | p = last + 1; |
a186b4a6 | 1827 | |
bcee893c DM |
1828 | if (ctx->base.header_size > 0 && |
1829 | i + ctx->base.header_size <= PAGE_SIZE) { | |
a186b4a6 JW |
1830 | /* |
1831 | * The iso header is byteswapped to little endian by | |
1832 | * the controller, but the remaining header quadlets | |
1833 | * are big endian. We want to present all the headers | |
1834 | * as big endian, so we have to swap the first quadlet. | |
1835 | */ | |
1836 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
1837 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
bcee893c | 1838 | ctx->header_length += ctx->base.header_size; |
a186b4a6 JW |
1839 | } |
1840 | ||
bcee893c DM |
1841 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
1842 | ir_header = (__le32 *) p; | |
a186b4a6 JW |
1843 | ctx->base.callback(&ctx->base, |
1844 | le32_to_cpu(ir_header[0]) & 0xffff, | |
1845 | ctx->header_length, ctx->header, | |
1846 | ctx->base.callback_data); | |
1847 | ctx->header_length = 0; | |
1848 | } | |
1849 | ||
a186b4a6 JW |
1850 | return 1; |
1851 | } | |
1852 | ||
30200739 KH |
1853 | static int handle_it_packet(struct context *context, |
1854 | struct descriptor *d, | |
1855 | struct descriptor *last) | |
ed568912 | 1856 | { |
30200739 KH |
1857 | struct iso_context *ctx = |
1858 | container_of(context, struct iso_context, context); | |
373b2edd | 1859 | |
30200739 KH |
1860 | if (last->transfer_status == 0) |
1861 | /* This descriptor isn't done yet, stop iteration. */ | |
1862 | return 0; | |
1863 | ||
a77754a7 | 1864 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f3 KH |
1865 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1866 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1867 | |
1868 | return 1; | |
ed568912 KH |
1869 | } |
1870 | ||
30200739 | 1871 | static struct fw_iso_context * |
eb0306ea | 1872 | ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed568912 KH |
1873 | { |
1874 | struct fw_ohci *ohci = fw_ohci(card); | |
1875 | struct iso_context *ctx, *list; | |
30200739 | 1876 | descriptor_callback_t callback; |
295e3feb | 1877 | u32 *mask, regs; |
ed568912 | 1878 | unsigned long flags; |
9b32d5f3 | 1879 | int index, retval = -ENOMEM; |
ed568912 KH |
1880 | |
1881 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1882 | mask = &ohci->it_context_mask; | |
1883 | list = ohci->it_context_list; | |
30200739 | 1884 | callback = handle_it_packet; |
ed568912 | 1885 | } else { |
373b2edd SR |
1886 | mask = &ohci->ir_context_mask; |
1887 | list = ohci->ir_context_list; | |
a186b4a6 JW |
1888 | if (ohci->version >= OHCI_VERSION_1_1) |
1889 | callback = handle_ir_dualbuffer_packet; | |
1890 | else | |
1891 | callback = handle_ir_packet_per_buffer; | |
ed568912 KH |
1892 | } |
1893 | ||
1894 | spin_lock_irqsave(&ohci->lock, flags); | |
1895 | index = ffs(*mask) - 1; | |
1896 | if (index >= 0) | |
1897 | *mask &= ~(1 << index); | |
1898 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1899 | ||
1900 | if (index < 0) | |
1901 | return ERR_PTR(-EBUSY); | |
1902 | ||
373b2edd SR |
1903 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1904 | regs = OHCI1394_IsoXmitContextBase(index); | |
1905 | else | |
1906 | regs = OHCI1394_IsoRcvContextBase(index); | |
1907 | ||
ed568912 | 1908 | ctx = &list[index]; |
2d826cc5 | 1909 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
1910 | ctx->header_length = 0; |
1911 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1912 | if (ctx->header == NULL) | |
1913 | goto out; | |
1914 | ||
fe5ca634 | 1915 | retval = context_init(&ctx->context, ohci, regs, callback); |
9b32d5f3 KH |
1916 | if (retval < 0) |
1917 | goto out_with_header; | |
ed568912 KH |
1918 | |
1919 | return &ctx->base; | |
9b32d5f3 KH |
1920 | |
1921 | out_with_header: | |
1922 | free_page((unsigned long)ctx->header); | |
1923 | out: | |
1924 | spin_lock_irqsave(&ohci->lock, flags); | |
1925 | *mask |= 1 << index; | |
1926 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1927 | ||
1928 | return ERR_PTR(retval); | |
ed568912 KH |
1929 | } |
1930 | ||
eb0306ea KH |
1931 | static int ohci_start_iso(struct fw_iso_context *base, |
1932 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 1933 | { |
373b2edd | 1934 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1935 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 1936 | u32 control, match; |
ed568912 KH |
1937 | int index; |
1938 | ||
295e3feb KH |
1939 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1940 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
1941 | match = 0; |
1942 | if (cycle >= 0) | |
1943 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 1944 | (cycle & 0x7fff) << 16; |
21efb3cf | 1945 | |
295e3feb KH |
1946 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
1947 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 1948 | context_run(&ctx->context, match); |
295e3feb KH |
1949 | } else { |
1950 | index = ctx - ohci->ir_context_list; | |
a186b4a6 JW |
1951 | control = IR_CONTEXT_ISOCH_HEADER; |
1952 | if (ohci->version >= OHCI_VERSION_1_1) | |
1953 | control |= IR_CONTEXT_DUAL_BUFFER_MODE; | |
8a2f7d93 KH |
1954 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
1955 | if (cycle >= 0) { | |
1956 | match |= (cycle & 0x07fff) << 12; | |
1957 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
1958 | } | |
ed568912 | 1959 | |
295e3feb KH |
1960 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1961 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 1962 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 1963 | context_run(&ctx->context, control); |
295e3feb | 1964 | } |
ed568912 KH |
1965 | |
1966 | return 0; | |
1967 | } | |
1968 | ||
b8295668 KH |
1969 | static int ohci_stop_iso(struct fw_iso_context *base) |
1970 | { | |
1971 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1972 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
1973 | int index; |
1974 | ||
1975 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1976 | index = ctx - ohci->it_context_list; | |
1977 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1978 | } else { | |
1979 | index = ctx - ohci->ir_context_list; | |
1980 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1981 | } | |
1982 | flush_writes(ohci); | |
1983 | context_stop(&ctx->context); | |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
ed568912 KH |
1988 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1989 | { | |
1990 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1991 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1992 | unsigned long flags; |
1993 | int index; | |
1994 | ||
b8295668 KH |
1995 | ohci_stop_iso(base); |
1996 | context_release(&ctx->context); | |
9b32d5f3 | 1997 | free_page((unsigned long)ctx->header); |
b8295668 | 1998 | |
ed568912 KH |
1999 | spin_lock_irqsave(&ohci->lock, flags); |
2000 | ||
2001 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2002 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
2003 | ohci->it_context_mask |= 1 << index; |
2004 | } else { | |
2005 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
2006 | ohci->ir_context_mask |= 1 << index; |
2007 | } | |
ed568912 KH |
2008 | |
2009 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2010 | } | |
2011 | ||
2012 | static int | |
295e3feb KH |
2013 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
2014 | struct fw_iso_packet *packet, | |
2015 | struct fw_iso_buffer *buffer, | |
2016 | unsigned long payload) | |
ed568912 | 2017 | { |
373b2edd | 2018 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2019 | struct descriptor *d, *last, *pd; |
ed568912 KH |
2020 | struct fw_iso_packet *p; |
2021 | __le32 *header; | |
9aad8125 | 2022 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
2023 | u32 z, header_z, payload_z, irq; |
2024 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 2025 | int page, end_page, i, length, offset; |
ed568912 | 2026 | |
c781c06d KH |
2027 | /* |
2028 | * FIXME: Cycle lost behavior should be configurable: lose | |
2029 | * packet, retransmit or terminate.. | |
2030 | */ | |
ed568912 KH |
2031 | |
2032 | p = packet; | |
9aad8125 | 2033 | payload_index = payload; |
ed568912 KH |
2034 | |
2035 | if (p->skip) | |
2036 | z = 1; | |
2037 | else | |
2038 | z = 2; | |
2039 | if (p->header_length > 0) | |
2040 | z++; | |
2041 | ||
2042 | /* Determine the first page the payload isn't contained in. */ | |
2043 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
2044 | if (p->payload_length > 0) | |
2045 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
2046 | else | |
2047 | payload_z = 0; | |
2048 | ||
2049 | z += payload_z; | |
2050 | ||
2051 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 2052 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 2053 | |
30200739 KH |
2054 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
2055 | if (d == NULL) | |
2056 | return -ENOMEM; | |
ed568912 KH |
2057 | |
2058 | if (!p->skip) { | |
a77754a7 | 2059 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 KH |
2060 | d[0].req_count = cpu_to_le16(8); |
2061 | ||
2062 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
2063 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
2064 | IT_HEADER_TAG(p->tag) | | |
2065 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
2066 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
2067 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 2068 | header[1] = |
a77754a7 | 2069 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
2070 | p->payload_length)); |
2071 | } | |
2072 | ||
2073 | if (p->header_length > 0) { | |
2074 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 2075 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
2076 | memcpy(&d[z], p->header, p->header_length); |
2077 | } | |
2078 | ||
2079 | pd = d + z - payload_z; | |
2080 | payload_end_index = payload_index + p->payload_length; | |
2081 | for (i = 0; i < payload_z; i++) { | |
2082 | page = payload_index >> PAGE_SHIFT; | |
2083 | offset = payload_index & ~PAGE_MASK; | |
2084 | next_page_index = (page + 1) << PAGE_SHIFT; | |
2085 | length = | |
2086 | min(next_page_index, payload_end_index) - payload_index; | |
2087 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
2088 | |
2089 | page_bus = page_private(buffer->pages[page]); | |
2090 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
2091 | |
2092 | payload_index += length; | |
2093 | } | |
2094 | ||
ed568912 | 2095 | if (p->interrupt) |
a77754a7 | 2096 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 2097 | else |
a77754a7 | 2098 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 2099 | |
30200739 | 2100 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
2101 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
2102 | DESCRIPTOR_STATUS | | |
2103 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 2104 | irq); |
ed568912 | 2105 | |
30200739 | 2106 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
2107 | |
2108 | return 0; | |
2109 | } | |
373b2edd | 2110 | |
295e3feb | 2111 | static int |
d2746dc1 KH |
2112 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
2113 | struct fw_iso_packet *packet, | |
2114 | struct fw_iso_buffer *buffer, | |
2115 | unsigned long payload) | |
295e3feb KH |
2116 | { |
2117 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
2118 | struct db_descriptor *db = NULL; | |
2119 | struct descriptor *d; | |
2120 | struct fw_iso_packet *p; | |
2121 | dma_addr_t d_bus, page_bus; | |
2122 | u32 z, header_z, length, rest; | |
c70dc788 | 2123 | int page, offset, packet_count, header_size; |
373b2edd | 2124 | |
c781c06d KH |
2125 | /* |
2126 | * FIXME: Cycle lost behavior should be configurable: lose | |
2127 | * packet, retransmit or terminate.. | |
2128 | */ | |
295e3feb KH |
2129 | |
2130 | p = packet; | |
2131 | z = 2; | |
2132 | ||
c781c06d KH |
2133 | /* |
2134 | * The OHCI controller puts the status word in the header | |
2135 | * buffer too, so we need 4 extra bytes per packet. | |
2136 | */ | |
c70dc788 KH |
2137 | packet_count = p->header_length / ctx->base.header_size; |
2138 | header_size = packet_count * (ctx->base.header_size + 4); | |
2139 | ||
295e3feb | 2140 | /* Get header size in number of descriptors. */ |
2d826cc5 | 2141 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb KH |
2142 | page = payload >> PAGE_SHIFT; |
2143 | offset = payload & ~PAGE_MASK; | |
2144 | rest = p->payload_length; | |
2145 | ||
295e3feb KH |
2146 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ |
2147 | while (rest > 0) { | |
2148 | d = context_get_descriptors(&ctx->context, | |
2149 | z + header_z, &d_bus); | |
2150 | if (d == NULL) | |
2151 | return -ENOMEM; | |
2152 | ||
2153 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
2154 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2155 | DESCRIPTOR_BRANCH_ALWAYS); | |
c70dc788 | 2156 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
0642b657 DM |
2157 | if (p->skip && rest == p->payload_length) { |
2158 | db->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
2159 | db->first_req_count = db->first_size; | |
2160 | } else { | |
2161 | db->first_req_count = cpu_to_le16(header_size); | |
2162 | } | |
1e1d196b | 2163 | db->first_res_count = db->first_req_count; |
2d826cc5 | 2164 | db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd | 2165 | |
0642b657 DM |
2166 | if (p->skip && rest == p->payload_length) |
2167 | length = 4; | |
2168 | else if (offset + rest < PAGE_SIZE) | |
295e3feb KH |
2169 | length = rest; |
2170 | else | |
2171 | length = PAGE_SIZE - offset; | |
2172 | ||
1e1d196b KH |
2173 | db->second_req_count = cpu_to_le16(length); |
2174 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
2175 | page_bus = page_private(buffer->pages[page]); |
2176 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
2177 | ||
cb2d2cdb | 2178 | if (p->interrupt && length == rest) |
a77754a7 | 2179 | db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdb | 2180 | |
295e3feb KH |
2181 | context_append(&ctx->context, d, z, header_z); |
2182 | offset = (offset + length) & ~PAGE_MASK; | |
2183 | rest -= length; | |
0642b657 DM |
2184 | if (offset == 0) |
2185 | page++; | |
295e3feb KH |
2186 | } |
2187 | ||
d2746dc1 KH |
2188 | return 0; |
2189 | } | |
21efb3cf | 2190 | |
a186b4a6 JW |
2191 | static int |
2192 | ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, | |
2193 | struct fw_iso_packet *packet, | |
2194 | struct fw_iso_buffer *buffer, | |
2195 | unsigned long payload) | |
2196 | { | |
2197 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
2198 | struct descriptor *d = NULL, *pd = NULL; | |
bcee893c | 2199 | struct fw_iso_packet *p = packet; |
a186b4a6 JW |
2200 | dma_addr_t d_bus, page_bus; |
2201 | u32 z, header_z, rest; | |
bcee893c DM |
2202 | int i, j, length; |
2203 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
2204 | |
2205 | /* | |
2206 | * The OHCI controller puts the status word in the | |
2207 | * buffer too, so we need 4 extra bytes per packet. | |
2208 | */ | |
2209 | packet_count = p->header_length / ctx->base.header_size; | |
bcee893c | 2210 | header_size = ctx->base.header_size + 4; |
a186b4a6 JW |
2211 | |
2212 | /* Get header size in number of descriptors. */ | |
2213 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
2214 | page = payload >> PAGE_SHIFT; | |
2215 | offset = payload & ~PAGE_MASK; | |
bcee893c | 2216 | payload_per_buffer = p->payload_length / packet_count; |
a186b4a6 JW |
2217 | |
2218 | for (i = 0; i < packet_count; i++) { | |
2219 | /* d points to the header descriptor */ | |
bcee893c | 2220 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 2221 | d = context_get_descriptors(&ctx->context, |
bcee893c | 2222 | z + header_z, &d_bus); |
a186b4a6 JW |
2223 | if (d == NULL) |
2224 | return -ENOMEM; | |
2225 | ||
bcee893c DM |
2226 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2227 | DESCRIPTOR_INPUT_MORE); | |
2228 | if (p->skip && i == 0) | |
2229 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
a186b4a6 JW |
2230 | d->req_count = cpu_to_le16(header_size); |
2231 | d->res_count = d->req_count; | |
bcee893c | 2232 | d->transfer_status = 0; |
a186b4a6 JW |
2233 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
2234 | ||
bcee893c DM |
2235 | rest = payload_per_buffer; |
2236 | for (j = 1; j < z; j++) { | |
2237 | pd = d + j; | |
2238 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | | |
2239 | DESCRIPTOR_INPUT_MORE); | |
2240 | ||
2241 | if (offset + rest < PAGE_SIZE) | |
2242 | length = rest; | |
2243 | else | |
2244 | length = PAGE_SIZE - offset; | |
2245 | pd->req_count = cpu_to_le16(length); | |
2246 | pd->res_count = pd->req_count; | |
2247 | pd->transfer_status = 0; | |
2248 | ||
2249 | page_bus = page_private(buffer->pages[page]); | |
2250 | pd->data_address = cpu_to_le32(page_bus + offset); | |
2251 | ||
2252 | offset = (offset + length) & ~PAGE_MASK; | |
2253 | rest -= length; | |
2254 | if (offset == 0) | |
2255 | page++; | |
2256 | } | |
a186b4a6 JW |
2257 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2258 | DESCRIPTOR_INPUT_LAST | | |
2259 | DESCRIPTOR_BRANCH_ALWAYS); | |
bcee893c | 2260 | if (p->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2261 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2262 | ||
a186b4a6 JW |
2263 | context_append(&ctx->context, d, z, header_z); |
2264 | } | |
2265 | ||
2266 | return 0; | |
2267 | } | |
2268 | ||
295e3feb KH |
2269 | static int |
2270 | ohci_queue_iso(struct fw_iso_context *base, | |
2271 | struct fw_iso_packet *packet, | |
2272 | struct fw_iso_buffer *buffer, | |
2273 | unsigned long payload) | |
2274 | { | |
e364cf4e | 2275 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 DM |
2276 | unsigned long flags; |
2277 | int retval; | |
e364cf4e | 2278 | |
fe5ca634 | 2279 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb | 2280 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
fe5ca634 | 2281 | retval = ohci_queue_iso_transmit(base, packet, buffer, payload); |
e364cf4e | 2282 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
fe5ca634 | 2283 | retval = ohci_queue_iso_receive_dualbuffer(base, packet, |
d2746dc1 | 2284 | buffer, payload); |
e364cf4e | 2285 | else |
fe5ca634 | 2286 | retval = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
a186b4a6 JW |
2287 | buffer, |
2288 | payload); | |
fe5ca634 DM |
2289 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
2290 | ||
2291 | return retval; | |
295e3feb KH |
2292 | } |
2293 | ||
21ebcd12 | 2294 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
2295 | .name = ohci_driver_name, |
2296 | .enable = ohci_enable, | |
2297 | .update_phy_reg = ohci_update_phy_reg, | |
2298 | .set_config_rom = ohci_set_config_rom, | |
2299 | .send_request = ohci_send_request, | |
2300 | .send_response = ohci_send_response, | |
730c32f5 | 2301 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 2302 | .enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d | 2303 | .get_bus_time = ohci_get_bus_time, |
ed568912 KH |
2304 | |
2305 | .allocate_iso_context = ohci_allocate_iso_context, | |
2306 | .free_iso_context = ohci_free_iso_context, | |
2307 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 2308 | .start_iso = ohci_start_iso, |
b8295668 | 2309 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
2310 | }; |
2311 | ||
ea8d006b | 2312 | #ifdef CONFIG_PPC_PMAC |
2ed0f181 SR |
2313 | static void ohci_pmac_on(struct pci_dev *dev) |
2314 | { | |
ea8d006b SR |
2315 | if (machine_is(powermac)) { |
2316 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2317 | ||
2318 | if (ofn) { | |
2319 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
2320 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2321 | } | |
2322 | } | |
2ed0f181 SR |
2323 | } |
2324 | ||
2325 | static void ohci_pmac_off(struct pci_dev *dev) | |
2326 | { | |
2327 | if (machine_is(powermac)) { | |
2328 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2329 | ||
2330 | if (ofn) { | |
2331 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2332 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
2333 | } | |
2334 | } | |
2335 | } | |
2336 | #else | |
2337 | #define ohci_pmac_on(dev) | |
2338 | #define ohci_pmac_off(dev) | |
ea8d006b SR |
2339 | #endif /* CONFIG_PPC_PMAC */ |
2340 | ||
2ed0f181 SR |
2341 | static int __devinit |
2342 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
2343 | { | |
2344 | struct fw_ohci *ohci; | |
2345 | u32 bus_options, max_receive, link_speed; | |
2346 | u64 guid; | |
2347 | int err; | |
2348 | size_t size; | |
2349 | ||
2d826cc5 | 2350 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 KH |
2351 | if (ohci == NULL) { |
2352 | fw_error("Could not malloc fw_ohci data.\n"); | |
2353 | return -ENOMEM; | |
2354 | } | |
2355 | ||
2356 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
2357 | ||
130d5496 SR |
2358 | ohci_pmac_on(dev); |
2359 | ||
d79406dd KH |
2360 | err = pci_enable_device(dev); |
2361 | if (err) { | |
ed568912 | 2362 | fw_error("Failed to enable OHCI hardware.\n"); |
bd7dee63 | 2363 | goto fail_free; |
ed568912 KH |
2364 | } |
2365 | ||
2366 | pci_set_master(dev); | |
2367 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
2368 | pci_set_drvdata(dev, ohci); | |
2369 | ||
11bf20ad SR |
2370 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
2371 | ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE && | |
2372 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW; | |
2373 | #endif | |
d34316a4 SR |
2374 | ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI; |
2375 | ||
ed568912 KH |
2376 | spin_lock_init(&ohci->lock); |
2377 | ||
2378 | tasklet_init(&ohci->bus_reset_tasklet, | |
2379 | bus_reset_tasklet, (unsigned long)ohci); | |
2380 | ||
d79406dd KH |
2381 | err = pci_request_region(dev, 0, ohci_driver_name); |
2382 | if (err) { | |
ed568912 | 2383 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 2384 | goto fail_disable; |
ed568912 KH |
2385 | } |
2386 | ||
2387 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
2388 | if (ohci->registers == NULL) { | |
2389 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
2390 | err = -ENXIO; |
2391 | goto fail_iomem; | |
ed568912 KH |
2392 | } |
2393 | ||
ed568912 KH |
2394 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2395 | OHCI1394_AsReqRcvContextControlSet); | |
2396 | ||
2397 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2398 | OHCI1394_AsRspRcvContextControlSet); | |
2399 | ||
fe5ca634 | 2400 | context_init(&ohci->at_request_ctx, ohci, |
f319b6a0 | 2401 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed568912 | 2402 | |
fe5ca634 | 2403 | context_init(&ohci->at_response_ctx, ohci, |
f319b6a0 | 2404 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed568912 | 2405 | |
ed568912 KH |
2406 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
2407 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
2408 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
2409 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
2410 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
2411 | ||
2412 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
2413 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
2414 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
2415 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
2416 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
2417 | ||
2418 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
2419 | fw_error("Out of memory for it/ir contexts.\n"); | |
d79406dd KH |
2420 | err = -ENOMEM; |
2421 | goto fail_registers; | |
ed568912 KH |
2422 | } |
2423 | ||
2424 | /* self-id dma buffer allocation */ | |
2425 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2426 | SELF_ID_BUF_SIZE, | |
2427 | &ohci->self_id_bus, | |
2428 | GFP_KERNEL); | |
2429 | if (ohci->self_id_cpu == NULL) { | |
2430 | fw_error("Out of memory for self ID buffer.\n"); | |
d79406dd KH |
2431 | err = -ENOMEM; |
2432 | goto fail_registers; | |
ed568912 KH |
2433 | } |
2434 | ||
ed568912 KH |
2435 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2436 | max_receive = (bus_options >> 12) & 0xf; | |
2437 | link_speed = bus_options & 0x7; | |
2438 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2439 | reg_read(ohci, OHCI1394_GUIDLo); | |
2440 | ||
d79406dd KH |
2441 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
2442 | if (err < 0) | |
2443 | goto fail_self_id; | |
ed568912 | 2444 | |
e364cf4e | 2445 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 2446 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 2447 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 | 2448 | return 0; |
d79406dd KH |
2449 | |
2450 | fail_self_id: | |
2451 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2452 | ohci->self_id_cpu, ohci->self_id_bus); | |
2453 | fail_registers: | |
2454 | kfree(ohci->it_context_list); | |
2455 | kfree(ohci->ir_context_list); | |
2456 | pci_iounmap(dev, ohci->registers); | |
2457 | fail_iomem: | |
2458 | pci_release_region(dev, 0); | |
2459 | fail_disable: | |
2460 | pci_disable_device(dev); | |
bd7dee63 SR |
2461 | fail_free: |
2462 | kfree(&ohci->card); | |
130d5496 | 2463 | ohci_pmac_off(dev); |
d79406dd KH |
2464 | |
2465 | return err; | |
ed568912 KH |
2466 | } |
2467 | ||
2468 | static void pci_remove(struct pci_dev *dev) | |
2469 | { | |
2470 | struct fw_ohci *ohci; | |
2471 | ||
2472 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2473 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2474 | flush_writes(ohci); | |
ed568912 KH |
2475 | fw_core_remove_card(&ohci->card); |
2476 | ||
c781c06d KH |
2477 | /* |
2478 | * FIXME: Fail all pending packets here, now that the upper | |
2479 | * layers can't queue any more. | |
2480 | */ | |
ed568912 KH |
2481 | |
2482 | software_reset(ohci); | |
2483 | free_irq(dev->irq, ohci); | |
d79406dd KH |
2484 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2485 | ohci->self_id_cpu, ohci->self_id_bus); | |
2486 | kfree(ohci->it_context_list); | |
2487 | kfree(ohci->ir_context_list); | |
2488 | pci_iounmap(dev, ohci->registers); | |
2489 | pci_release_region(dev, 0); | |
2490 | pci_disable_device(dev); | |
bd7dee63 | 2491 | kfree(&ohci->card); |
2ed0f181 | 2492 | ohci_pmac_off(dev); |
ea8d006b | 2493 | |
ed568912 KH |
2494 | fw_notify("Removed fw-ohci device.\n"); |
2495 | } | |
2496 | ||
2aef469a | 2497 | #ifdef CONFIG_PM |
2ed0f181 | 2498 | static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a | 2499 | { |
2ed0f181 | 2500 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2501 | int err; |
2502 | ||
2503 | software_reset(ohci); | |
2ed0f181 SR |
2504 | free_irq(dev->irq, ohci); |
2505 | err = pci_save_state(dev); | |
2aef469a | 2506 | if (err) { |
8a8cea27 | 2507 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2508 | return err; |
2509 | } | |
2ed0f181 | 2510 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
55111428 SR |
2511 | if (err) |
2512 | fw_error("pci_set_power_state failed with %d\n", err); | |
2ed0f181 | 2513 | ohci_pmac_off(dev); |
ea8d006b | 2514 | |
2aef469a KH |
2515 | return 0; |
2516 | } | |
2517 | ||
2ed0f181 | 2518 | static int pci_resume(struct pci_dev *dev) |
2aef469a | 2519 | { |
2ed0f181 | 2520 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2521 | int err; |
2522 | ||
2ed0f181 SR |
2523 | ohci_pmac_on(dev); |
2524 | pci_set_power_state(dev, PCI_D0); | |
2525 | pci_restore_state(dev); | |
2526 | err = pci_enable_device(dev); | |
2aef469a | 2527 | if (err) { |
8a8cea27 | 2528 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2529 | return err; |
2530 | } | |
2531 | ||
0bd243c4 | 2532 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2533 | } |
2534 | #endif | |
2535 | ||
ed568912 KH |
2536 | static struct pci_device_id pci_table[] = { |
2537 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
2538 | { } | |
2539 | }; | |
2540 | ||
2541 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2542 | ||
2543 | static struct pci_driver fw_ohci_pci_driver = { | |
2544 | .name = ohci_driver_name, | |
2545 | .id_table = pci_table, | |
2546 | .probe = pci_probe, | |
2547 | .remove = pci_remove, | |
2aef469a KH |
2548 | #ifdef CONFIG_PM |
2549 | .resume = pci_resume, | |
2550 | .suspend = pci_suspend, | |
2551 | #endif | |
ed568912 KH |
2552 | }; |
2553 | ||
2554 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2555 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2556 | MODULE_LICENSE("GPL"); | |
2557 | ||
1e4c7b0d OH |
2558 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2559 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2560 | MODULE_ALIAS("ohci1394"); | |
2561 | #endif | |
2562 | ||
ed568912 KH |
2563 | static int __init fw_ohci_init(void) |
2564 | { | |
2565 | return pci_register_driver(&fw_ohci_pci_driver); | |
2566 | } | |
2567 | ||
2568 | static void __exit fw_ohci_cleanup(void) | |
2569 | { | |
2570 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2571 | } | |
2572 | ||
2573 | module_init(fw_ohci_init); | |
2574 | module_exit(fw_ohci_cleanup); |