firewire: fw-ohci: Fix for dualbuffer three-or-more buffers
[deliverable/linux.git] / drivers / firewire / fw-ohci.c
CommitLineData
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1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
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4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
e524f616 21#include <linux/compiler.h>
ed568912 22#include <linux/delay.h>
cf3e72fd 23#include <linux/dma-mapping.h>
c26f0234 24#include <linux/gfp.h>
a7fb60db
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25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
faa2fb4e 28#include <linux/mm.h>
a7fb60db
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29#include <linux/module.h>
30#include <linux/pci.h>
c26f0234 31#include <linux/spinlock.h>
cf3e72fd 32
c26f0234 33#include <asm/page.h>
ee71c2f9 34#include <asm/system.h>
ed568912 35
ed568912 36#include "fw-ohci.h"
a7fb60db 37#include "fw-transaction.h"
ed568912 38
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39#define DESCRIPTOR_OUTPUT_MORE 0
40#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
41#define DESCRIPTOR_INPUT_MORE (2 << 12)
42#define DESCRIPTOR_INPUT_LAST (3 << 12)
43#define DESCRIPTOR_STATUS (1 << 11)
44#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
45#define DESCRIPTOR_PING (1 << 7)
46#define DESCRIPTOR_YY (1 << 6)
47#define DESCRIPTOR_NO_IRQ (0 << 4)
48#define DESCRIPTOR_IRQ_ERROR (1 << 4)
49#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
50#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
51#define DESCRIPTOR_WAIT (3 << 0)
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52
53struct descriptor {
54 __le16 req_count;
55 __le16 control;
56 __le32 data_address;
57 __le32 branch_address;
58 __le16 res_count;
59 __le16 transfer_status;
60} __attribute__((aligned(16)));
61
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62struct db_descriptor {
63 __le16 first_size;
64 __le16 control;
65 __le16 second_req_count;
66 __le16 first_req_count;
67 __le32 branch_address;
68 __le16 second_res_count;
69 __le16 first_res_count;
70 __le32 reserved0;
71 __le32 first_buffer;
72 __le32 second_buffer;
73 __le32 reserved1;
74} __attribute__((aligned(16)));
75
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76#define CONTROL_SET(regs) (regs)
77#define CONTROL_CLEAR(regs) ((regs) + 4)
78#define COMMAND_PTR(regs) ((regs) + 12)
79#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 80
32b46093 81struct ar_buffer {
ed568912 82 struct descriptor descriptor;
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83 struct ar_buffer *next;
84 __le32 data[0];
85};
ed568912 86
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87struct ar_context {
88 struct fw_ohci *ohci;
89 struct ar_buffer *current_buffer;
90 struct ar_buffer *last_buffer;
91 void *pointer;
72e318e0 92 u32 regs;
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93 struct tasklet_struct tasklet;
94};
95
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96struct context;
97
98typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *d,
100 struct descriptor *last);
101struct context {
373b2edd 102 struct fw_ohci *ohci;
30200739 103 u32 regs;
373b2edd 104
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105 struct descriptor *buffer;
106 dma_addr_t buffer_bus;
107 size_t buffer_size;
108 struct descriptor *head_descriptor;
109 struct descriptor *tail_descriptor;
110 struct descriptor *tail_descriptor_last;
111 struct descriptor *prev_descriptor;
112
113 descriptor_callback_t callback;
114
373b2edd 115 struct tasklet_struct tasklet;
30200739 116};
30200739 117
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118#define IT_HEADER_SY(v) ((v) << 0)
119#define IT_HEADER_TCODE(v) ((v) << 4)
120#define IT_HEADER_CHANNEL(v) ((v) << 8)
121#define IT_HEADER_TAG(v) ((v) << 14)
122#define IT_HEADER_SPEED(v) ((v) << 16)
123#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
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124
125struct iso_context {
126 struct fw_iso_context base;
30200739 127 struct context context;
0642b657 128 int excess_bytes;
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129 void *header;
130 size_t header_length;
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131};
132
133#define CONFIG_ROM_SIZE 1024
134
135struct fw_ohci {
136 struct fw_card card;
137
e364cf4e 138 u32 version;
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139 __iomem char *registers;
140 dma_addr_t self_id_bus;
141 __le32 *self_id_cpu;
142 struct tasklet_struct bus_reset_tasklet;
e636fe25 143 int node_id;
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144 int generation;
145 int request_generation;
d60d7f1d 146 u32 bus_seconds;
ed568912 147
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148 /*
149 * Spinlock for accessing fw_ohci data. Never call out of
150 * this driver with this lock held.
151 */
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152 spinlock_t lock;
153 u32 self_id_buffer[512];
154
155 /* Config rom buffers */
156 __be32 *config_rom;
157 dma_addr_t config_rom_bus;
158 __be32 *next_config_rom;
159 dma_addr_t next_config_rom_bus;
160 u32 next_header;
161
162 struct ar_context ar_request_ctx;
163 struct ar_context ar_response_ctx;
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164 struct context at_request_ctx;
165 struct context at_response_ctx;
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166
167 u32 it_context_mask;
168 struct iso_context *it_context_list;
169 u32 ir_context_mask;
170 struct iso_context *ir_context_list;
171};
172
95688e97 173static inline struct fw_ohci *fw_ohci(struct fw_card *card)
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174{
175 return container_of(card, struct fw_ohci, card);
176}
177
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178#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
179#define IR_CONTEXT_BUFFER_FILL 0x80000000
180#define IR_CONTEXT_ISOCH_HEADER 0x40000000
181#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
182#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
183#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
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184
185#define CONTEXT_RUN 0x8000
186#define CONTEXT_WAKE 0x1000
187#define CONTEXT_DEAD 0x0800
188#define CONTEXT_ACTIVE 0x0400
189
190#define OHCI1394_MAX_AT_REQ_RETRIES 0x2
191#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
192#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
193
194#define FW_OHCI_MAJOR 240
195#define OHCI1394_REGISTER_SIZE 0x800
196#define OHCI_LOOP_COUNT 500
197#define OHCI1394_PCI_HCI_Control 0x40
198#define SELF_ID_BUF_SIZE 0x800
32b46093 199#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 200#define OHCI_VERSION_1_1 0x010010
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201#define ISO_BUFFER_SIZE (64 * 1024)
202#define AT_BUFFER_SIZE 4096
0edeefd9 203
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204static char ohci_driver_name[] = KBUILD_MODNAME;
205
95688e97 206static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
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207{
208 writel(data, ohci->registers + offset);
209}
210
95688e97 211static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
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212{
213 return readl(ohci->registers + offset);
214}
215
95688e97 216static inline void flush_writes(const struct fw_ohci *ohci)
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217{
218 /* Do a dummy read to flush writes. */
219 reg_read(ohci, OHCI1394_Version);
220}
221
222static int
223ohci_update_phy_reg(struct fw_card *card, int addr,
224 int clear_bits, int set_bits)
225{
226 struct fw_ohci *ohci = fw_ohci(card);
227 u32 val, old;
228
229 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
362e901c 230 flush_writes(ohci);
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231 msleep(2);
232 val = reg_read(ohci, OHCI1394_PhyControl);
233 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
234 fw_error("failed to set phy reg bits.\n");
235 return -EBUSY;
236 }
237
238 old = OHCI1394_PhyControl_ReadData(val);
239 old = (old & ~clear_bits) | set_bits;
240 reg_write(ohci, OHCI1394_PhyControl,
241 OHCI1394_PhyControl_Write(addr, old));
242
243 return 0;
244}
245
32b46093 246static int ar_context_add_page(struct ar_context *ctx)
ed568912 247{
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248 struct device *dev = ctx->ohci->card.device;
249 struct ar_buffer *ab;
250 dma_addr_t ab_bus;
251 size_t offset;
252
253 ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
254 if (ab == NULL)
255 return -ENOMEM;
256
257 ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
258 if (dma_mapping_error(ab_bus)) {
259 free_page((unsigned long) ab);
260 return -ENOMEM;
261 }
262
2d826cc5 263 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
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264 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
265 DESCRIPTOR_STATUS |
266 DESCRIPTOR_BRANCH_ALWAYS);
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267 offset = offsetof(struct ar_buffer, data);
268 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
269 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
270 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
271 ab->descriptor.branch_address = 0;
272
273 dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
274
ec839e43 275 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
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276 ctx->last_buffer->next = ab;
277 ctx->last_buffer = ab;
278
a77754a7 279 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
ed568912 280 flush_writes(ctx->ohci);
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281
282 return 0;
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283}
284
32b46093 285static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 286{
ed568912 287 struct fw_ohci *ohci = ctx->ohci;
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288 struct fw_packet p;
289 u32 status, length, tcode;
2639a6fb 290
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291 p.header[0] = le32_to_cpu(buffer[0]);
292 p.header[1] = le32_to_cpu(buffer[1]);
293 p.header[2] = le32_to_cpu(buffer[2]);
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294
295 tcode = (p.header[0] >> 4) & 0x0f;
296 switch (tcode) {
297 case TCODE_WRITE_QUADLET_REQUEST:
298 case TCODE_READ_QUADLET_RESPONSE:
32b46093 299 p.header[3] = (__force __u32) buffer[3];
2639a6fb 300 p.header_length = 16;
32b46093 301 p.payload_length = 0;
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302 break;
303
2639a6fb 304 case TCODE_READ_BLOCK_REQUEST :
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305 p.header[3] = le32_to_cpu(buffer[3]);
306 p.header_length = 16;
307 p.payload_length = 0;
308 break;
309
310 case TCODE_WRITE_BLOCK_REQUEST:
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311 case TCODE_READ_BLOCK_RESPONSE:
312 case TCODE_LOCK_REQUEST:
313 case TCODE_LOCK_RESPONSE:
32b46093 314 p.header[3] = le32_to_cpu(buffer[3]);
2639a6fb 315 p.header_length = 16;
32b46093 316 p.payload_length = p.header[3] >> 16;
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317 break;
318
319 case TCODE_WRITE_RESPONSE:
320 case TCODE_READ_QUADLET_REQUEST:
32b46093 321 case OHCI_TCODE_PHY_PACKET:
2639a6fb 322 p.header_length = 12;
32b46093 323 p.payload_length = 0;
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324 break;
325 }
ed568912 326
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327 p.payload = (void *) buffer + p.header_length;
328
329 /* FIXME: What to do about evt_* errors? */
330 length = (p.header_length + p.payload_length + 3) / 4;
331 status = le32_to_cpu(buffer[length]);
332
333 p.ack = ((status >> 16) & 0x1f) - 16;
334 p.speed = (status >> 21) & 0x7;
335 p.timestamp = status & 0xffff;
336 p.generation = ohci->request_generation;
ed568912 337
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338 /*
339 * The OHCI bus reset handler synthesizes a phy packet with
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340 * the new generation number when a bus reset happens (see
341 * section 8.4.2.3). This helps us determine when a request
342 * was received and make sure we send the response in the same
343 * generation. We only need this for requests; for responses
344 * we use the unique tlabel for finding the matching
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345 * request.
346 */
ed568912 347
2639a6fb 348 if (p.ack + 16 == 0x09)
32b46093 349 ohci->request_generation = (buffer[2] >> 16) & 0xff;
ed568912 350 else if (ctx == &ohci->ar_request_ctx)
2639a6fb 351 fw_core_handle_request(&ohci->card, &p);
ed568912 352 else
2639a6fb 353 fw_core_handle_response(&ohci->card, &p);
ed568912 354
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355 return buffer + length + 1;
356}
ed568912 357
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358static void ar_context_tasklet(unsigned long data)
359{
360 struct ar_context *ctx = (struct ar_context *)data;
361 struct fw_ohci *ohci = ctx->ohci;
362 struct ar_buffer *ab;
363 struct descriptor *d;
364 void *buffer, *end;
365
366 ab = ctx->current_buffer;
367 d = &ab->descriptor;
368
369 if (d->res_count == 0) {
370 size_t size, rest, offset;
371
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372 /*
373 * This descriptor is finished and we may have a
32b46093 374 * packet split across this and the next buffer. We
c781c06d
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375 * reuse the page for reassembling the split packet.
376 */
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377
378 offset = offsetof(struct ar_buffer, data);
379 dma_unmap_single(ohci->card.device,
0a9972ba
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380 le32_to_cpu(ab->descriptor.data_address) - offset,
381 PAGE_SIZE, DMA_BIDIRECTIONAL);
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382
383 buffer = ab;
384 ab = ab->next;
385 d = &ab->descriptor;
386 size = buffer + PAGE_SIZE - ctx->pointer;
387 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
388 memmove(buffer, ctx->pointer, size);
389 memcpy(buffer + size, ab->data, rest);
390 ctx->current_buffer = ab;
391 ctx->pointer = (void *) ab->data + rest;
392 end = buffer + size + rest;
393
394 while (buffer < end)
395 buffer = handle_ar_packet(ctx, buffer);
396
397 free_page((unsigned long)buffer);
398 ar_context_add_page(ctx);
399 } else {
400 buffer = ctx->pointer;
401 ctx->pointer = end =
402 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
403
404 while (buffer < end)
405 buffer = handle_ar_packet(ctx, buffer);
406 }
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407}
408
409static int
72e318e0 410ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
ed568912 411{
32b46093 412 struct ar_buffer ab;
ed568912 413
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414 ctx->regs = regs;
415 ctx->ohci = ohci;
416 ctx->last_buffer = &ab;
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417 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
418
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419 ar_context_add_page(ctx);
420 ar_context_add_page(ctx);
421 ctx->current_buffer = ab.next;
422 ctx->pointer = ctx->current_buffer->data;
423
2aef469a
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424 return 0;
425}
426
427static void ar_context_run(struct ar_context *ctx)
428{
429 struct ar_buffer *ab = ctx->current_buffer;
430 dma_addr_t ab_bus;
431 size_t offset;
432
433 offset = offsetof(struct ar_buffer, data);
0a9972ba 434 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
2aef469a
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435
436 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
a77754a7 437 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
32b46093 438 flush_writes(ctx->ohci);
ed568912 439}
373b2edd 440
a186b4a6
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441static struct descriptor *
442find_branch_descriptor(struct descriptor *d, int z)
443{
444 int b, key;
445
446 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
447 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
448
449 /* figure out which descriptor the branch address goes in */
450 if (z == 2 && (b == 3 || key == 2))
451 return d;
452 else
453 return d + z - 1;
454}
455
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456static void context_tasklet(unsigned long data)
457{
458 struct context *ctx = (struct context *) data;
459 struct fw_ohci *ohci = ctx->ohci;
460 struct descriptor *d, *last;
461 u32 address;
462 int z;
463
464 dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
465 ctx->buffer_size, DMA_TO_DEVICE);
466
467 d = ctx->tail_descriptor;
468 last = ctx->tail_descriptor_last;
469
470 while (last->branch_address != 0) {
471 address = le32_to_cpu(last->branch_address);
472 z = address & 0xf;
2d826cc5 473 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
a186b4a6 474 last = find_branch_descriptor(d, z);
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475
476 if (!ctx->callback(ctx, d, last))
477 break;
478
479 ctx->tail_descriptor = d;
480 ctx->tail_descriptor_last = last;
481 }
482}
483
484static int
485context_init(struct context *ctx, struct fw_ohci *ohci,
486 size_t buffer_size, u32 regs,
487 descriptor_callback_t callback)
488{
489 ctx->ohci = ohci;
490 ctx->regs = regs;
491 ctx->buffer_size = buffer_size;
492 ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
493 if (ctx->buffer == NULL)
494 return -ENOMEM;
495
496 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
497 ctx->callback = callback;
498
499 ctx->buffer_bus =
500 dma_map_single(ohci->card.device, ctx->buffer,
501 buffer_size, DMA_TO_DEVICE);
502 if (dma_mapping_error(ctx->buffer_bus)) {
503 kfree(ctx->buffer);
504 return -ENOMEM;
505 }
506
507 ctx->head_descriptor = ctx->buffer;
508 ctx->prev_descriptor = ctx->buffer;
509 ctx->tail_descriptor = ctx->buffer;
510 ctx->tail_descriptor_last = ctx->buffer;
511
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512 /*
513 * We put a dummy descriptor in the buffer that has a NULL
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514 * branch address and looks like it's been sent. That way we
515 * have a descriptor to append DMA programs to. Also, the
516 * ring buffer invariant is that it always has at least one
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517 * element so that head == tail means buffer full.
518 */
30200739 519
2d826cc5 520 memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
a77754a7 521 ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
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522 ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
523 ctx->head_descriptor++;
524
525 return 0;
526}
527
9b32d5f3 528static void
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529context_release(struct context *ctx)
530{
531 struct fw_card *card = &ctx->ohci->card;
532
533 dma_unmap_single(card->device, ctx->buffer_bus,
534 ctx->buffer_size, DMA_TO_DEVICE);
535 kfree(ctx->buffer);
536}
537
538static struct descriptor *
539context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
540{
541 struct descriptor *d, *tail, *end;
542
543 d = ctx->head_descriptor;
544 tail = ctx->tail_descriptor;
2d826cc5 545 end = ctx->buffer + ctx->buffer_size / sizeof(*d);
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546
547 if (d + z <= tail) {
548 goto has_space;
549 } else if (d > tail && d + z <= end) {
550 goto has_space;
551 } else if (d > tail && ctx->buffer + z <= tail) {
552 d = ctx->buffer;
553 goto has_space;
554 }
555
556 return NULL;
557
558 has_space:
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559 memset(d, 0, z * sizeof(*d));
560 *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
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561
562 return d;
563}
564
295e3feb 565static void context_run(struct context *ctx, u32 extra)
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566{
567 struct fw_ohci *ohci = ctx->ohci;
568
a77754a7 569 reg_write(ohci, COMMAND_PTR(ctx->regs),
30200739 570 le32_to_cpu(ctx->tail_descriptor_last->branch_address));
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571 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
572 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
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573 flush_writes(ohci);
574}
575
576static void context_append(struct context *ctx,
577 struct descriptor *d, int z, int extra)
578{
579 dma_addr_t d_bus;
580
2d826cc5 581 d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
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582
583 ctx->head_descriptor = d + z + extra;
584 ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
a186b4a6 585 ctx->prev_descriptor = find_branch_descriptor(d, z);
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586
587 dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
588 ctx->buffer_size, DMA_TO_DEVICE);
589
a77754a7 590 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
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591 flush_writes(ctx->ohci);
592}
593
594static void context_stop(struct context *ctx)
595{
596 u32 reg;
b8295668 597 int i;
30200739 598
a77754a7 599 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
b8295668 600 flush_writes(ctx->ohci);
30200739 601
b8295668 602 for (i = 0; i < 10; i++) {
a77754a7 603 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
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KH
604 if ((reg & CONTEXT_ACTIVE) == 0)
605 break;
606
607 fw_notify("context_stop: still active (0x%08x)\n", reg);
b980f5a2 608 mdelay(1);
b8295668 609 }
30200739 610}
ed568912 611
f319b6a0
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612struct driver_data {
613 struct fw_packet *packet;
614};
ed568912 615
c781c06d
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616/*
617 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 618 * Must always be called with the ochi->lock held to ensure proper
c781c06d
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619 * generation handling and locking around packet queue manipulation.
620 */
f319b6a0
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621static int
622at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
ed568912 623{
ed568912 624 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 625 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
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626 struct driver_data *driver_data;
627 struct descriptor *d, *last;
628 __le32 *header;
ed568912 629 int z, tcode;
f319b6a0 630 u32 reg;
ed568912 631
f319b6a0
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632 d = context_get_descriptors(ctx, 4, &d_bus);
633 if (d == NULL) {
634 packet->ack = RCODE_SEND_ERROR;
635 return -1;
ed568912
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636 }
637
a77754a7 638 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
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639 d[0].res_count = cpu_to_le16(packet->timestamp);
640
c781c06d
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641 /*
642 * The DMA format for asyncronous link packets is different
ed568912
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643 * from the IEEE1394 layout, so shift the fields around
644 * accordingly. If header_length is 8, it's a PHY packet, to
c781c06d
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645 * which we need to prepend an extra quadlet.
646 */
f319b6a0
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647
648 header = (__le32 *) &d[1];
ed568912 649 if (packet->header_length > 8) {
f319b6a0
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650 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
651 (packet->speed << 16));
652 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
653 (packet->header[0] & 0xffff0000));
654 header[2] = cpu_to_le32(packet->header[2]);
ed568912
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655
656 tcode = (packet->header[0] >> 4) & 0x0f;
657 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 658 header[3] = cpu_to_le32(packet->header[3]);
ed568912 659 else
f319b6a0
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660 header[3] = (__force __le32) packet->header[3];
661
662 d[0].req_count = cpu_to_le16(packet->header_length);
ed568912 663 } else {
f319b6a0
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664 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
665 (packet->speed << 16));
666 header[1] = cpu_to_le32(packet->header[0]);
667 header[2] = cpu_to_le32(packet->header[1]);
668 d[0].req_count = cpu_to_le16(12);
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669 }
670
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671 driver_data = (struct driver_data *) &d[3];
672 driver_data->packet = packet;
20d11673 673 packet->driver_data = driver_data;
a186b4a6 674
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675 if (packet->payload_length > 0) {
676 payload_bus =
677 dma_map_single(ohci->card.device, packet->payload,
678 packet->payload_length, DMA_TO_DEVICE);
679 if (dma_mapping_error(payload_bus)) {
680 packet->ack = RCODE_SEND_ERROR;
681 return -1;
682 }
683
684 d[2].req_count = cpu_to_le16(packet->payload_length);
685 d[2].data_address = cpu_to_le32(payload_bus);
686 last = &d[2];
687 z = 3;
ed568912 688 } else {
f319b6a0
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689 last = &d[0];
690 z = 2;
ed568912 691 }
ed568912 692
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693 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
694 DESCRIPTOR_IRQ_ALWAYS |
695 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 696
f319b6a0
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697 /* FIXME: Document how the locking works. */
698 if (ohci->generation != packet->generation) {
ab88ca48
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699 if (packet->payload_length > 0)
700 dma_unmap_single(ohci->card.device, payload_bus,
701 packet->payload_length, DMA_TO_DEVICE);
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702 packet->ack = RCODE_GENERATION;
703 return -1;
704 }
705
706 context_append(ctx, d, z, 4 - z);
ed568912 707
f319b6a0 708 /* If the context isn't already running, start it up. */
a77754a7 709 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
053b3080 710 if ((reg & CONTEXT_RUN) == 0)
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711 context_run(ctx, 0);
712
713 return 0;
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714}
715
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716static int handle_at_packet(struct context *context,
717 struct descriptor *d,
718 struct descriptor *last)
ed568912 719{
f319b6a0 720 struct driver_data *driver_data;
ed568912 721 struct fw_packet *packet;
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722 struct fw_ohci *ohci = context->ohci;
723 dma_addr_t payload_bus;
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724 int evt;
725
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726 if (last->transfer_status == 0)
727 /* This descriptor isn't done yet, stop iteration. */
728 return 0;
ed568912 729
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730 driver_data = (struct driver_data *) &d[3];
731 packet = driver_data->packet;
732 if (packet == NULL)
733 /* This packet was cancelled, just continue. */
734 return 1;
730c32f5 735
f319b6a0
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736 payload_bus = le32_to_cpu(last->data_address);
737 if (payload_bus != 0)
738 dma_unmap_single(ohci->card.device, payload_bus,
ed568912 739 packet->payload_length, DMA_TO_DEVICE);
ed568912 740
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741 evt = le16_to_cpu(last->transfer_status) & 0x1f;
742 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 743
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744 switch (evt) {
745 case OHCI1394_evt_timeout:
746 /* Async response transmit timed out. */
747 packet->ack = RCODE_CANCELLED;
748 break;
ed568912 749
f319b6a0 750 case OHCI1394_evt_flushed:
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751 /*
752 * The packet was flushed should give same error as
753 * when we try to use a stale generation count.
754 */
f319b6a0
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755 packet->ack = RCODE_GENERATION;
756 break;
ed568912 757
f319b6a0 758 case OHCI1394_evt_missing_ack:
c781c06d
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759 /*
760 * Using a valid (current) generation count, but the
761 * node is not on the bus or not sending acks.
762 */
f319b6a0
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763 packet->ack = RCODE_NO_ACK;
764 break;
ed568912 765
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766 case ACK_COMPLETE + 0x10:
767 case ACK_PENDING + 0x10:
768 case ACK_BUSY_X + 0x10:
769 case ACK_BUSY_A + 0x10:
770 case ACK_BUSY_B + 0x10:
771 case ACK_DATA_ERROR + 0x10:
772 case ACK_TYPE_ERROR + 0x10:
773 packet->ack = evt - 0x10;
774 break;
ed568912 775
f319b6a0
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776 default:
777 packet->ack = RCODE_SEND_ERROR;
778 break;
779 }
ed568912 780
f319b6a0 781 packet->callback(packet, &ohci->card, packet->ack);
ed568912 782
f319b6a0 783 return 1;
ed568912
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784}
785
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786#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
787#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
788#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
789#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
790#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
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791
792static void
793handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
794{
795 struct fw_packet response;
796 int tcode, length, i;
797
a77754a7 798 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 799 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 800 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
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801 else
802 length = 4;
803
804 i = csr - CSR_CONFIG_ROM;
805 if (i + length > CONFIG_ROM_SIZE) {
806 fw_fill_response(&response, packet->header,
807 RCODE_ADDRESS_ERROR, NULL, 0);
808 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
809 fw_fill_response(&response, packet->header,
810 RCODE_TYPE_ERROR, NULL, 0);
811 } else {
812 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
813 (void *) ohci->config_rom + i, length);
814 }
815
816 fw_core_handle_response(&ohci->card, &response);
817}
818
819static void
820handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
821{
822 struct fw_packet response;
823 int tcode, length, ext_tcode, sel;
824 __be32 *payload, lock_old;
825 u32 lock_arg, lock_data;
826
a77754a7
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827 tcode = HEADER_GET_TCODE(packet->header[0]);
828 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 829 payload = packet->payload;
a77754a7 830 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
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831
832 if (tcode == TCODE_LOCK_REQUEST &&
833 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
834 lock_arg = be32_to_cpu(payload[0]);
835 lock_data = be32_to_cpu(payload[1]);
836 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
837 lock_arg = 0;
838 lock_data = 0;
839 } else {
840 fw_fill_response(&response, packet->header,
841 RCODE_TYPE_ERROR, NULL, 0);
842 goto out;
843 }
844
845 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
846 reg_write(ohci, OHCI1394_CSRData, lock_data);
847 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
848 reg_write(ohci, OHCI1394_CSRControl, sel);
849
850 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
851 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
852 else
853 fw_notify("swap not done yet\n");
854
855 fw_fill_response(&response, packet->header,
2d826cc5 856 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
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857 out:
858 fw_core_handle_response(&ohci->card, &response);
859}
860
861static void
f319b6a0 862handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb
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863{
864 u64 offset;
865 u32 csr;
866
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867 if (ctx == &ctx->ohci->at_request_ctx) {
868 packet->ack = ACK_PENDING;
869 packet->callback(packet, &ctx->ohci->card, packet->ack);
870 }
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871
872 offset =
873 ((unsigned long long)
a77754a7 874 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
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875 packet->header[2];
876 csr = offset - CSR_REGISTER_BASE;
877
878 /* Handle config rom reads. */
879 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
880 handle_local_rom(ctx->ohci, packet, csr);
881 else switch (csr) {
882 case CSR_BUS_MANAGER_ID:
883 case CSR_BANDWIDTH_AVAILABLE:
884 case CSR_CHANNELS_AVAILABLE_HI:
885 case CSR_CHANNELS_AVAILABLE_LO:
886 handle_local_lock(ctx->ohci, packet, csr);
887 break;
888 default:
889 if (ctx == &ctx->ohci->at_request_ctx)
890 fw_core_handle_request(&ctx->ohci->card, packet);
891 else
892 fw_core_handle_response(&ctx->ohci->card, packet);
893 break;
894 }
473d28c7
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895
896 if (ctx == &ctx->ohci->at_response_ctx) {
897 packet->ack = ACK_COMPLETE;
898 packet->callback(packet, &ctx->ohci->card, packet->ack);
899 }
93c4cceb 900}
e636fe25 901
ed568912 902static void
f319b6a0 903at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 904{
ed568912 905 unsigned long flags;
f319b6a0 906 int retval;
ed568912
KH
907
908 spin_lock_irqsave(&ctx->ohci->lock, flags);
909
a77754a7 910 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 911 ctx->ohci->generation == packet->generation) {
93c4cceb
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912 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
913 handle_local_request(ctx, packet);
914 return;
e636fe25 915 }
ed568912 916
f319b6a0 917 retval = at_context_queue_packet(ctx, packet);
ed568912
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918 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
919
f319b6a0
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920 if (retval < 0)
921 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 922
ed568912
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923}
924
925static void bus_reset_tasklet(unsigned long data)
926{
927 struct fw_ohci *ohci = (struct fw_ohci *)data;
e636fe25 928 int self_id_count, i, j, reg;
ed568912
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929 int generation, new_generation;
930 unsigned long flags;
4eaff7d6
SR
931 void *free_rom = NULL;
932 dma_addr_t free_rom_bus = 0;
ed568912
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933
934 reg = reg_read(ohci, OHCI1394_NodeID);
935 if (!(reg & OHCI1394_NodeID_idValid)) {
02ff8f8e 936 fw_notify("node ID not valid, new bus reset in progress\n");
ed568912
KH
937 return;
938 }
02ff8f8e
SR
939 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
940 fw_notify("malconfigured bus\n");
941 return;
942 }
943 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
944 OHCI1394_NodeID_nodeNumber);
ed568912 945
c781c06d
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946 /*
947 * The count in the SelfIDCount register is the number of
ed568912
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948 * bytes in the self ID receive buffer. Since we also receive
949 * the inverted quadlets and a header quadlet, we shift one
c781c06d
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950 * bit extra to get the actual number of self IDs.
951 */
ed568912
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952
953 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
954 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 955 rmb();
ed568912
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956
957 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
958 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
959 fw_error("inconsistent self IDs\n");
960 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
961 }
ee71c2f9 962 rmb();
ed568912 963
c781c06d
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964 /*
965 * Check the consistency of the self IDs we just read. The
ed568912
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966 * problem we face is that a new bus reset can start while we
967 * read out the self IDs from the DMA buffer. If this happens,
968 * the DMA buffer will be overwritten with new self IDs and we
969 * will read out inconsistent data. The OHCI specification
970 * (section 11.2) recommends a technique similar to
971 * linux/seqlock.h, where we remember the generation of the
972 * self IDs in the buffer before reading them out and compare
973 * it to the current generation after reading them out. If
974 * the two generations match we know we have a consistent set
c781c06d
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975 * of self IDs.
976 */
ed568912
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977
978 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
979 if (new_generation != generation) {
980 fw_notify("recursive bus reset detected, "
981 "discarding self ids\n");
982 return;
983 }
984
985 /* FIXME: Document how the locking works. */
986 spin_lock_irqsave(&ohci->lock, flags);
987
988 ohci->generation = generation;
f319b6a0
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989 context_stop(&ohci->at_request_ctx);
990 context_stop(&ohci->at_response_ctx);
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991 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
992
c781c06d
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993 /*
994 * This next bit is unrelated to the AT context stuff but we
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995 * have to do it under the spinlock also. If a new config rom
996 * was set up before this reset, the old one is now no longer
997 * in use and we can free it. Update the config rom pointers
998 * to point to the current config rom and clear the
c781c06d
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999 * next_config_rom pointer so a new udpate can take place.
1000 */
ed568912
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1001
1002 if (ohci->next_config_rom != NULL) {
0bd243c4
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1003 if (ohci->next_config_rom != ohci->config_rom) {
1004 free_rom = ohci->config_rom;
1005 free_rom_bus = ohci->config_rom_bus;
1006 }
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1007 ohci->config_rom = ohci->next_config_rom;
1008 ohci->config_rom_bus = ohci->next_config_rom_bus;
1009 ohci->next_config_rom = NULL;
1010
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1011 /*
1012 * Restore config_rom image and manually update
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1013 * config_rom registers. Writing the header quadlet
1014 * will indicate that the config rom is ready, so we
c781c06d
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1015 * do that last.
1016 */
ed568912
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1017 reg_write(ohci, OHCI1394_BusOptions,
1018 be32_to_cpu(ohci->config_rom[2]));
1019 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1020 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1021 }
1022
1023 spin_unlock_irqrestore(&ohci->lock, flags);
1024
4eaff7d6
SR
1025 if (free_rom)
1026 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1027 free_rom, free_rom_bus);
1028
e636fe25 1029 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
ed568912
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1030 self_id_count, ohci->self_id_buffer);
1031}
1032
1033static irqreturn_t irq_handler(int irq, void *data)
1034{
1035 struct fw_ohci *ohci = data;
d60d7f1d 1036 u32 event, iso_event, cycle_time;
ed568912
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1037 int i;
1038
1039 event = reg_read(ohci, OHCI1394_IntEventClear);
1040
a515958d 1041 if (!event || !~event)
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1042 return IRQ_NONE;
1043
1044 reg_write(ohci, OHCI1394_IntEventClear, event);
1045
1046 if (event & OHCI1394_selfIDComplete)
1047 tasklet_schedule(&ohci->bus_reset_tasklet);
1048
1049 if (event & OHCI1394_RQPkt)
1050 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1051
1052 if (event & OHCI1394_RSPkt)
1053 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1054
1055 if (event & OHCI1394_reqTxComplete)
1056 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1057
1058 if (event & OHCI1394_respTxComplete)
1059 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1060
c889475f 1061 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
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1062 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1063
1064 while (iso_event) {
1065 i = ffs(iso_event) - 1;
30200739 1066 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
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1067 iso_event &= ~(1 << i);
1068 }
1069
c889475f 1070 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
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1071 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1072
1073 while (iso_event) {
1074 i = ffs(iso_event) - 1;
30200739 1075 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
ed568912
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1076 iso_event &= ~(1 << i);
1077 }
1078
e524f616
SR
1079 if (unlikely(event & OHCI1394_postedWriteErr))
1080 fw_error("PCI posted write error\n");
1081
d60d7f1d
KH
1082 if (event & OHCI1394_cycle64Seconds) {
1083 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1084 if ((cycle_time & 0x80000000) == 0)
1085 ohci->bus_seconds++;
1086 }
1087
ed568912
KH
1088 return IRQ_HANDLED;
1089}
1090
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1091static int software_reset(struct fw_ohci *ohci)
1092{
1093 int i;
1094
1095 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1096
1097 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1098 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1099 OHCI1394_HCControl_softReset) == 0)
1100 return 0;
1101 msleep(1);
1102 }
1103
1104 return -EBUSY;
1105}
1106
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1107static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1108{
1109 struct fw_ohci *ohci = fw_ohci(card);
1110 struct pci_dev *dev = to_pci_dev(card->device);
1111
2aef469a
KH
1112 if (software_reset(ohci)) {
1113 fw_error("Failed to reset ohci card.\n");
1114 return -EBUSY;
1115 }
1116
1117 /*
1118 * Now enable LPS, which we need in order to start accessing
1119 * most of the registers. In fact, on some cards (ALI M5251),
1120 * accessing registers in the SClk domain without LPS enabled
1121 * will lock up the machine. Wait 50msec to make sure we have
1122 * full link enabled.
1123 */
1124 reg_write(ohci, OHCI1394_HCControlSet,
1125 OHCI1394_HCControl_LPS |
1126 OHCI1394_HCControl_postedWriteEnable);
1127 flush_writes(ohci);
1128 msleep(50);
1129
1130 reg_write(ohci, OHCI1394_HCControlClear,
1131 OHCI1394_HCControl_noByteSwapData);
1132
1133 reg_write(ohci, OHCI1394_LinkControlSet,
1134 OHCI1394_LinkControl_rcvSelfID |
1135 OHCI1394_LinkControl_cycleTimerEnable |
1136 OHCI1394_LinkControl_cycleMaster);
1137
1138 reg_write(ohci, OHCI1394_ATRetries,
1139 OHCI1394_MAX_AT_REQ_RETRIES |
1140 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1141 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1142
1143 ar_context_run(&ohci->ar_request_ctx);
1144 ar_context_run(&ohci->ar_response_ctx);
1145
1146 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1147 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1148 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1149 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1150 reg_write(ohci, OHCI1394_IntMaskSet,
1151 OHCI1394_selfIDComplete |
1152 OHCI1394_RQPkt | OHCI1394_RSPkt |
1153 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1154 OHCI1394_isochRx | OHCI1394_isochTx |
e524f616
SR
1155 OHCI1394_postedWriteErr | OHCI1394_cycle64Seconds |
1156 OHCI1394_masterIntEnable);
2aef469a
KH
1157
1158 /* Activate link_on bit and contender bit in our self ID packets.*/
1159 if (ohci_update_phy_reg(card, 4, 0,
1160 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1161 return -EIO;
1162
c781c06d
KH
1163 /*
1164 * When the link is not yet enabled, the atomic config rom
ed568912
KH
1165 * update mechanism described below in ohci_set_config_rom()
1166 * is not active. We have to update ConfigRomHeader and
1167 * BusOptions manually, and the write to ConfigROMmap takes
1168 * effect immediately. We tie this to the enabling of the
1169 * link, so we have a valid config rom before enabling - the
1170 * OHCI requires that ConfigROMhdr and BusOptions have valid
1171 * values before enabling.
1172 *
1173 * However, when the ConfigROMmap is written, some controllers
1174 * always read back quadlets 0 and 2 from the config rom to
1175 * the ConfigRomHeader and BusOptions registers on bus reset.
1176 * They shouldn't do that in this initial case where the link
1177 * isn't enabled. This means we have to use the same
1178 * workaround here, setting the bus header to 0 and then write
1179 * the right values in the bus reset tasklet.
1180 */
1181
0bd243c4
KH
1182 if (config_rom) {
1183 ohci->next_config_rom =
1184 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1185 &ohci->next_config_rom_bus,
1186 GFP_KERNEL);
1187 if (ohci->next_config_rom == NULL)
1188 return -ENOMEM;
ed568912 1189
0bd243c4
KH
1190 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1191 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1192 } else {
1193 /*
1194 * In the suspend case, config_rom is NULL, which
1195 * means that we just reuse the old config rom.
1196 */
1197 ohci->next_config_rom = ohci->config_rom;
1198 ohci->next_config_rom_bus = ohci->config_rom_bus;
1199 }
ed568912 1200
0bd243c4 1201 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
ed568912
KH
1202 ohci->next_config_rom[0] = 0;
1203 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH
1204 reg_write(ohci, OHCI1394_BusOptions,
1205 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH
1206 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1207
1208 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1209
1210 if (request_irq(dev->irq, irq_handler,
65efffa8 1211 IRQF_SHARED, ohci_driver_name, ohci)) {
ed568912
KH
1212 fw_error("Failed to allocate shared interrupt %d.\n",
1213 dev->irq);
1214 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1215 ohci->config_rom, ohci->config_rom_bus);
1216 return -EIO;
1217 }
1218
1219 reg_write(ohci, OHCI1394_HCControlSet,
1220 OHCI1394_HCControl_linkEnable |
1221 OHCI1394_HCControl_BIBimageValid);
1222 flush_writes(ohci);
1223
c781c06d
KH
1224 /*
1225 * We are ready to go, initiate bus reset to finish the
1226 * initialization.
1227 */
ed568912
KH
1228
1229 fw_core_initiate_bus_reset(&ohci->card, 1);
1230
1231 return 0;
1232}
1233
1234static int
1235ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1236{
1237 struct fw_ohci *ohci;
1238 unsigned long flags;
4eaff7d6 1239 int retval = -EBUSY;
ed568912
KH
1240 __be32 *next_config_rom;
1241 dma_addr_t next_config_rom_bus;
1242
1243 ohci = fw_ohci(card);
1244
c781c06d
KH
1245 /*
1246 * When the OHCI controller is enabled, the config rom update
ed568912
KH
1247 * mechanism is a bit tricky, but easy enough to use. See
1248 * section 5.5.6 in the OHCI specification.
1249 *
1250 * The OHCI controller caches the new config rom address in a
1251 * shadow register (ConfigROMmapNext) and needs a bus reset
1252 * for the changes to take place. When the bus reset is
1253 * detected, the controller loads the new values for the
1254 * ConfigRomHeader and BusOptions registers from the specified
1255 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1256 * shadow register. All automatically and atomically.
1257 *
1258 * Now, there's a twist to this story. The automatic load of
1259 * ConfigRomHeader and BusOptions doesn't honor the
1260 * noByteSwapData bit, so with a be32 config rom, the
1261 * controller will load be32 values in to these registers
1262 * during the atomic update, even on litte endian
1263 * architectures. The workaround we use is to put a 0 in the
1264 * header quadlet; 0 is endian agnostic and means that the
1265 * config rom isn't ready yet. In the bus reset tasklet we
1266 * then set up the real values for the two registers.
1267 *
1268 * We use ohci->lock to avoid racing with the code that sets
1269 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1270 */
1271
1272 next_config_rom =
1273 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1274 &next_config_rom_bus, GFP_KERNEL);
1275 if (next_config_rom == NULL)
1276 return -ENOMEM;
1277
1278 spin_lock_irqsave(&ohci->lock, flags);
1279
1280 if (ohci->next_config_rom == NULL) {
1281 ohci->next_config_rom = next_config_rom;
1282 ohci->next_config_rom_bus = next_config_rom_bus;
1283
1284 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1285 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1286 length * 4);
1287
1288 ohci->next_header = config_rom[0];
1289 ohci->next_config_rom[0] = 0;
1290
1291 reg_write(ohci, OHCI1394_ConfigROMmap,
1292 ohci->next_config_rom_bus);
4eaff7d6 1293 retval = 0;
ed568912
KH
1294 }
1295
1296 spin_unlock_irqrestore(&ohci->lock, flags);
1297
c781c06d
KH
1298 /*
1299 * Now initiate a bus reset to have the changes take
ed568912
KH
1300 * effect. We clean up the old config rom memory and DMA
1301 * mappings in the bus reset tasklet, since the OHCI
1302 * controller could need to access it before the bus reset
c781c06d
KH
1303 * takes effect.
1304 */
ed568912
KH
1305 if (retval == 0)
1306 fw_core_initiate_bus_reset(&ohci->card, 1);
4eaff7d6
SR
1307 else
1308 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1309 next_config_rom, next_config_rom_bus);
ed568912
KH
1310
1311 return retval;
1312}
1313
1314static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1315{
1316 struct fw_ohci *ohci = fw_ohci(card);
1317
1318 at_context_transmit(&ohci->at_request_ctx, packet);
1319}
1320
1321static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1322{
1323 struct fw_ohci *ohci = fw_ohci(card);
1324
1325 at_context_transmit(&ohci->at_response_ctx, packet);
1326}
1327
730c32f5
KH
1328static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1329{
1330 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH
1331 struct context *ctx = &ohci->at_request_ctx;
1332 struct driver_data *driver_data = packet->driver_data;
1333 int retval = -ENOENT;
730c32f5 1334
f319b6a0 1335 tasklet_disable(&ctx->tasklet);
730c32f5 1336
f319b6a0
KH
1337 if (packet->ack != 0)
1338 goto out;
730c32f5 1339
f319b6a0
KH
1340 driver_data->packet = NULL;
1341 packet->ack = RCODE_CANCELLED;
1342 packet->callback(packet, &ohci->card, packet->ack);
1343 retval = 0;
730c32f5 1344
f319b6a0
KH
1345 out:
1346 tasklet_enable(&ctx->tasklet);
730c32f5 1347
f319b6a0 1348 return retval;
730c32f5
KH
1349}
1350
ed568912
KH
1351static int
1352ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1353{
1354 struct fw_ohci *ohci = fw_ohci(card);
1355 unsigned long flags;
907293d7 1356 int n, retval = 0;
ed568912 1357
c781c06d
KH
1358 /*
1359 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1360 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1361 */
ed568912
KH
1362
1363 spin_lock_irqsave(&ohci->lock, flags);
1364
1365 if (ohci->generation != generation) {
1366 retval = -ESTALE;
1367 goto out;
1368 }
1369
c781c06d
KH
1370 /*
1371 * Note, if the node ID contains a non-local bus ID, physical DMA is
1372 * enabled for _all_ nodes on remote buses.
1373 */
907293d7
SR
1374
1375 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1376 if (n < 32)
1377 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1378 else
1379 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1380
ed568912 1381 flush_writes(ohci);
ed568912 1382 out:
6cad95fe 1383 spin_unlock_irqrestore(&ohci->lock, flags);
ed568912
KH
1384 return retval;
1385}
373b2edd 1386
d60d7f1d
KH
1387static u64
1388ohci_get_bus_time(struct fw_card *card)
1389{
1390 struct fw_ohci *ohci = fw_ohci(card);
1391 u32 cycle_time;
1392 u64 bus_time;
1393
1394 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1395 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1396
1397 return bus_time;
1398}
1399
d2746dc1
KH
1400static int handle_ir_dualbuffer_packet(struct context *context,
1401 struct descriptor *d,
1402 struct descriptor *last)
ed568912 1403{
295e3feb
KH
1404 struct iso_context *ctx =
1405 container_of(context, struct iso_context, context);
1406 struct db_descriptor *db = (struct db_descriptor *) d;
c70dc788 1407 __le32 *ir_header;
9b32d5f3 1408 size_t header_length;
c70dc788
KH
1409 void *p, *end;
1410 int i;
d2746dc1 1411
0642b657
DM
1412 if (db->first_res_count > 0 && db->second_res_count > 0) {
1413 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1414 /* This descriptor isn't done yet, stop iteration. */
1415 return 0;
1416 }
1417 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1418 }
295e3feb 1419
c70dc788
KH
1420 header_length = le16_to_cpu(db->first_req_count) -
1421 le16_to_cpu(db->first_res_count);
1422
1423 i = ctx->header_length;
1424 p = db + 1;
1425 end = p + header_length;
1426 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
c781c06d
KH
1427 /*
1428 * The iso header is byteswapped to little endian by
15536221
KH
1429 * the controller, but the remaining header quadlets
1430 * are big endian. We want to present all the headers
1431 * as big endian, so we have to swap the first
c781c06d
KH
1432 * quadlet.
1433 */
15536221
KH
1434 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1435 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
c70dc788 1436 i += ctx->base.header_size;
0642b657
DM
1437 ctx->excess_bytes +=
1438 (le32_to_cpu(*(u32 *)(p + 4)) >> 16) & 0xffff;
c70dc788
KH
1439 p += ctx->base.header_size + 4;
1440 }
c70dc788 1441 ctx->header_length = i;
9b32d5f3 1442
0642b657
DM
1443 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1444 le16_to_cpu(db->second_res_count);
1445
a77754a7 1446 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
c70dc788
KH
1447 ir_header = (__le32 *) (db + 1);
1448 ctx->base.callback(&ctx->base,
1449 le32_to_cpu(ir_header[0]) & 0xffff,
9b32d5f3 1450 ctx->header_length, ctx->header,
295e3feb 1451 ctx->base.callback_data);
9b32d5f3
KH
1452 ctx->header_length = 0;
1453 }
ed568912 1454
295e3feb 1455 return 1;
ed568912
KH
1456}
1457
a186b4a6
JW
1458static int handle_ir_packet_per_buffer(struct context *context,
1459 struct descriptor *d,
1460 struct descriptor *last)
1461{
1462 struct iso_context *ctx =
1463 container_of(context, struct iso_context, context);
1464 struct descriptor *pd = d + 1;
1465 __le32 *ir_header;
1466 size_t header_length;
1467 void *p, *end;
1468 int i, z;
1469
1470 if (pd->res_count == pd->req_count)
1471 /* Descriptor(s) not done yet, stop iteration */
1472 return 0;
1473
1474 header_length = le16_to_cpu(d->req_count);
1475
1476 i = ctx->header_length;
1477 z = le32_to_cpu(pd->branch_address) & 0xf;
1478 p = d + z;
1479 end = p + header_length;
1480
1481 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1482 /*
1483 * The iso header is byteswapped to little endian by
1484 * the controller, but the remaining header quadlets
1485 * are big endian. We want to present all the headers
1486 * as big endian, so we have to swap the first quadlet.
1487 */
1488 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1489 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1490 i += ctx->base.header_size;
1491 p += ctx->base.header_size + 4;
1492 }
1493
1494 ctx->header_length = i;
1495
1496 if (le16_to_cpu(pd->control) & DESCRIPTOR_IRQ_ALWAYS) {
1497 ir_header = (__le32 *) (d + z);
1498 ctx->base.callback(&ctx->base,
1499 le32_to_cpu(ir_header[0]) & 0xffff,
1500 ctx->header_length, ctx->header,
1501 ctx->base.callback_data);
1502 ctx->header_length = 0;
1503 }
1504
1505
1506 return 1;
1507}
1508
30200739
KH
1509static int handle_it_packet(struct context *context,
1510 struct descriptor *d,
1511 struct descriptor *last)
ed568912 1512{
30200739
KH
1513 struct iso_context *ctx =
1514 container_of(context, struct iso_context, context);
373b2edd 1515
30200739
KH
1516 if (last->transfer_status == 0)
1517 /* This descriptor isn't done yet, stop iteration. */
1518 return 0;
1519
a77754a7 1520 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
9b32d5f3
KH
1521 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1522 0, NULL, ctx->base.callback_data);
30200739
KH
1523
1524 return 1;
ed568912
KH
1525}
1526
30200739 1527static struct fw_iso_context *
eb0306ea 1528ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
ed568912
KH
1529{
1530 struct fw_ohci *ohci = fw_ohci(card);
1531 struct iso_context *ctx, *list;
30200739 1532 descriptor_callback_t callback;
295e3feb 1533 u32 *mask, regs;
ed568912 1534 unsigned long flags;
9b32d5f3 1535 int index, retval = -ENOMEM;
ed568912
KH
1536
1537 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1538 mask = &ohci->it_context_mask;
1539 list = ohci->it_context_list;
30200739 1540 callback = handle_it_packet;
ed568912 1541 } else {
373b2edd
SR
1542 mask = &ohci->ir_context_mask;
1543 list = ohci->ir_context_list;
a186b4a6
JW
1544 if (ohci->version >= OHCI_VERSION_1_1)
1545 callback = handle_ir_dualbuffer_packet;
1546 else
1547 callback = handle_ir_packet_per_buffer;
ed568912
KH
1548 }
1549
1550 spin_lock_irqsave(&ohci->lock, flags);
1551 index = ffs(*mask) - 1;
1552 if (index >= 0)
1553 *mask &= ~(1 << index);
1554 spin_unlock_irqrestore(&ohci->lock, flags);
1555
1556 if (index < 0)
1557 return ERR_PTR(-EBUSY);
1558
373b2edd
SR
1559 if (type == FW_ISO_CONTEXT_TRANSMIT)
1560 regs = OHCI1394_IsoXmitContextBase(index);
1561 else
1562 regs = OHCI1394_IsoRcvContextBase(index);
1563
ed568912 1564 ctx = &list[index];
2d826cc5 1565 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH
1566 ctx->header_length = 0;
1567 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1568 if (ctx->header == NULL)
1569 goto out;
1570
30200739 1571 retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
295e3feb 1572 regs, callback);
9b32d5f3
KH
1573 if (retval < 0)
1574 goto out_with_header;
ed568912
KH
1575
1576 return &ctx->base;
9b32d5f3
KH
1577
1578 out_with_header:
1579 free_page((unsigned long)ctx->header);
1580 out:
1581 spin_lock_irqsave(&ohci->lock, flags);
1582 *mask |= 1 << index;
1583 spin_unlock_irqrestore(&ohci->lock, flags);
1584
1585 return ERR_PTR(retval);
ed568912
KH
1586}
1587
eb0306ea
KH
1588static int ohci_start_iso(struct fw_iso_context *base,
1589 s32 cycle, u32 sync, u32 tags)
ed568912 1590{
373b2edd 1591 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 1592 struct fw_ohci *ohci = ctx->context.ohci;
8a2f7d93 1593 u32 control, match;
ed568912
KH
1594 int index;
1595
295e3feb
KH
1596 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1597 index = ctx - ohci->it_context_list;
8a2f7d93
KH
1598 match = 0;
1599 if (cycle >= 0)
1600 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 1601 (cycle & 0x7fff) << 16;
21efb3cf 1602
295e3feb
KH
1603 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1604 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 1605 context_run(&ctx->context, match);
295e3feb
KH
1606 } else {
1607 index = ctx - ohci->ir_context_list;
a186b4a6
JW
1608 control = IR_CONTEXT_ISOCH_HEADER;
1609 if (ohci->version >= OHCI_VERSION_1_1)
1610 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
8a2f7d93
KH
1611 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1612 if (cycle >= 0) {
1613 match |= (cycle & 0x07fff) << 12;
1614 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1615 }
ed568912 1616
295e3feb
KH
1617 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1618 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 1619 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 1620 context_run(&ctx->context, control);
295e3feb 1621 }
ed568912
KH
1622
1623 return 0;
1624}
1625
b8295668
KH
1626static int ohci_stop_iso(struct fw_iso_context *base)
1627{
1628 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 1629 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH
1630 int index;
1631
1632 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1633 index = ctx - ohci->it_context_list;
1634 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1635 } else {
1636 index = ctx - ohci->ir_context_list;
1637 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1638 }
1639 flush_writes(ohci);
1640 context_stop(&ctx->context);
1641
1642 return 0;
1643}
1644
ed568912
KH
1645static void ohci_free_iso_context(struct fw_iso_context *base)
1646{
1647 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 1648 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH
1649 unsigned long flags;
1650 int index;
1651
b8295668
KH
1652 ohci_stop_iso(base);
1653 context_release(&ctx->context);
9b32d5f3 1654 free_page((unsigned long)ctx->header);
b8295668 1655
ed568912
KH
1656 spin_lock_irqsave(&ohci->lock, flags);
1657
1658 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1659 index = ctx - ohci->it_context_list;
ed568912
KH
1660 ohci->it_context_mask |= 1 << index;
1661 } else {
1662 index = ctx - ohci->ir_context_list;
ed568912
KH
1663 ohci->ir_context_mask |= 1 << index;
1664 }
ed568912
KH
1665
1666 spin_unlock_irqrestore(&ohci->lock, flags);
1667}
1668
1669static int
295e3feb
KH
1670ohci_queue_iso_transmit(struct fw_iso_context *base,
1671 struct fw_iso_packet *packet,
1672 struct fw_iso_buffer *buffer,
1673 unsigned long payload)
ed568912 1674{
373b2edd 1675 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 1676 struct descriptor *d, *last, *pd;
ed568912
KH
1677 struct fw_iso_packet *p;
1678 __le32 *header;
9aad8125 1679 dma_addr_t d_bus, page_bus;
ed568912
KH
1680 u32 z, header_z, payload_z, irq;
1681 u32 payload_index, payload_end_index, next_page_index;
30200739 1682 int page, end_page, i, length, offset;
ed568912 1683
c781c06d
KH
1684 /*
1685 * FIXME: Cycle lost behavior should be configurable: lose
1686 * packet, retransmit or terminate..
1687 */
ed568912
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1688
1689 p = packet;
9aad8125 1690 payload_index = payload;
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KH
1691
1692 if (p->skip)
1693 z = 1;
1694 else
1695 z = 2;
1696 if (p->header_length > 0)
1697 z++;
1698
1699 /* Determine the first page the payload isn't contained in. */
1700 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1701 if (p->payload_length > 0)
1702 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1703 else
1704 payload_z = 0;
1705
1706 z += payload_z;
1707
1708 /* Get header size in number of descriptors. */
2d826cc5 1709 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 1710
30200739
KH
1711 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1712 if (d == NULL)
1713 return -ENOMEM;
ed568912
KH
1714
1715 if (!p->skip) {
a77754a7 1716 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
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KH
1717 d[0].req_count = cpu_to_le16(8);
1718
1719 header = (__le32 *) &d[1];
a77754a7
KH
1720 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1721 IT_HEADER_TAG(p->tag) |
1722 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1723 IT_HEADER_CHANNEL(ctx->base.channel) |
1724 IT_HEADER_SPEED(ctx->base.speed));
ed568912 1725 header[1] =
a77754a7 1726 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH
1727 p->payload_length));
1728 }
1729
1730 if (p->header_length > 0) {
1731 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 1732 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH
1733 memcpy(&d[z], p->header, p->header_length);
1734 }
1735
1736 pd = d + z - payload_z;
1737 payload_end_index = payload_index + p->payload_length;
1738 for (i = 0; i < payload_z; i++) {
1739 page = payload_index >> PAGE_SHIFT;
1740 offset = payload_index & ~PAGE_MASK;
1741 next_page_index = (page + 1) << PAGE_SHIFT;
1742 length =
1743 min(next_page_index, payload_end_index) - payload_index;
1744 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH
1745
1746 page_bus = page_private(buffer->pages[page]);
1747 pd[i].data_address = cpu_to_le32(page_bus + offset);
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KH
1748
1749 payload_index += length;
1750 }
1751
ed568912 1752 if (p->interrupt)
a77754a7 1753 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 1754 else
a77754a7 1755 irq = DESCRIPTOR_NO_IRQ;
ed568912 1756
30200739 1757 last = z == 2 ? d : d + z - 1;
a77754a7
KH
1758 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1759 DESCRIPTOR_STATUS |
1760 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 1761 irq);
ed568912 1762
30200739 1763 context_append(&ctx->context, d, z, header_z);
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KH
1764
1765 return 0;
1766}
373b2edd 1767
295e3feb 1768static int
d2746dc1
KH
1769ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1770 struct fw_iso_packet *packet,
1771 struct fw_iso_buffer *buffer,
1772 unsigned long payload)
295e3feb
KH
1773{
1774 struct iso_context *ctx = container_of(base, struct iso_context, base);
1775 struct db_descriptor *db = NULL;
1776 struct descriptor *d;
1777 struct fw_iso_packet *p;
1778 dma_addr_t d_bus, page_bus;
1779 u32 z, header_z, length, rest;
c70dc788 1780 int page, offset, packet_count, header_size;
373b2edd 1781
c781c06d
KH
1782 /*
1783 * FIXME: Cycle lost behavior should be configurable: lose
1784 * packet, retransmit or terminate..
1785 */
295e3feb
KH
1786
1787 p = packet;
1788 z = 2;
1789
c781c06d
KH
1790 /*
1791 * The OHCI controller puts the status word in the header
1792 * buffer too, so we need 4 extra bytes per packet.
1793 */
c70dc788
KH
1794 packet_count = p->header_length / ctx->base.header_size;
1795 header_size = packet_count * (ctx->base.header_size + 4);
1796
295e3feb 1797 /* Get header size in number of descriptors. */
2d826cc5 1798 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
295e3feb
KH
1799 page = payload >> PAGE_SHIFT;
1800 offset = payload & ~PAGE_MASK;
1801 rest = p->payload_length;
1802
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KH
1803 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1804 while (rest > 0) {
1805 d = context_get_descriptors(&ctx->context,
1806 z + header_z, &d_bus);
1807 if (d == NULL)
1808 return -ENOMEM;
1809
1810 db = (struct db_descriptor *) d;
a77754a7
KH
1811 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1812 DESCRIPTOR_BRANCH_ALWAYS);
c70dc788 1813 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
0642b657
DM
1814 if (p->skip && rest == p->payload_length) {
1815 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
1816 db->first_req_count = db->first_size;
1817 } else {
1818 db->first_req_count = cpu_to_le16(header_size);
1819 }
1e1d196b 1820 db->first_res_count = db->first_req_count;
2d826cc5 1821 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
373b2edd 1822
0642b657
DM
1823 if (p->skip && rest == p->payload_length)
1824 length = 4;
1825 else if (offset + rest < PAGE_SIZE)
295e3feb
KH
1826 length = rest;
1827 else
1828 length = PAGE_SIZE - offset;
1829
1e1d196b
KH
1830 db->second_req_count = cpu_to_le16(length);
1831 db->second_res_count = db->second_req_count;
295e3feb
KH
1832 page_bus = page_private(buffer->pages[page]);
1833 db->second_buffer = cpu_to_le32(page_bus + offset);
1834
cb2d2cdb 1835 if (p->interrupt && length == rest)
a77754a7 1836 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
cb2d2cdb 1837
295e3feb
KH
1838 context_append(&ctx->context, d, z, header_z);
1839 offset = (offset + length) & ~PAGE_MASK;
1840 rest -= length;
0642b657
DM
1841 if (offset == 0)
1842 page++;
295e3feb
KH
1843 }
1844
d2746dc1
KH
1845 return 0;
1846}
21efb3cf 1847
a186b4a6
JW
1848static int
1849ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
1850 struct fw_iso_packet *packet,
1851 struct fw_iso_buffer *buffer,
1852 unsigned long payload)
1853{
1854 struct iso_context *ctx = container_of(base, struct iso_context, base);
1855 struct descriptor *d = NULL, *pd = NULL;
1856 struct fw_iso_packet *p;
1857 dma_addr_t d_bus, page_bus;
1858 u32 z, header_z, rest;
1859 int i, page, offset, packet_count, header_size;
1860
1861 if (packet->skip) {
1862 d = context_get_descriptors(&ctx->context, 1, &d_bus);
1863 if (d == NULL)
1864 return -ENOMEM;
1865
1866 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
1867 DESCRIPTOR_INPUT_LAST |
1868 DESCRIPTOR_BRANCH_ALWAYS |
1869 DESCRIPTOR_WAIT);
1870 context_append(&ctx->context, d, 1, 0);
1871 }
1872
1873 /* one descriptor for header, one for payload */
1874 /* FIXME: handle cases where we need multiple desc. for payload */
1875 z = 2;
1876 p = packet;
1877
1878 /*
1879 * The OHCI controller puts the status word in the
1880 * buffer too, so we need 4 extra bytes per packet.
1881 */
1882 packet_count = p->header_length / ctx->base.header_size;
1883 header_size = packet_count * (ctx->base.header_size + 4);
1884
1885 /* Get header size in number of descriptors. */
1886 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1887 page = payload >> PAGE_SHIFT;
1888 offset = payload & ~PAGE_MASK;
1889 rest = p->payload_length;
1890
1891 for (i = 0; i < packet_count; i++) {
1892 /* d points to the header descriptor */
1893 d = context_get_descriptors(&ctx->context,
1894 z + header_z, &d_bus);
1895 if (d == NULL)
1896 return -ENOMEM;
1897
1898 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE);
1899 d->req_count = cpu_to_le16(header_size);
1900 d->res_count = d->req_count;
1901 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
1902
1903 /* pd points to the payload descriptor */
1904 pd = d + 1;
1905 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
1906 DESCRIPTOR_INPUT_LAST |
1907 DESCRIPTOR_BRANCH_ALWAYS);
1908 if (p->interrupt)
1909 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1910
1911 pd->req_count = cpu_to_le16(rest);
1912 pd->res_count = pd->req_count;
1913
1914 page_bus = page_private(buffer->pages[page]);
1915 pd->data_address = cpu_to_le32(page_bus + offset);
1916
1917 context_append(&ctx->context, d, z, header_z);
1918 }
1919
1920 return 0;
1921}
1922
295e3feb
KH
1923static int
1924ohci_queue_iso(struct fw_iso_context *base,
1925 struct fw_iso_packet *packet,
1926 struct fw_iso_buffer *buffer,
1927 unsigned long payload)
1928{
e364cf4e
KH
1929 struct iso_context *ctx = container_of(base, struct iso_context, base);
1930
295e3feb
KH
1931 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1932 return ohci_queue_iso_transmit(base, packet, buffer, payload);
e364cf4e 1933 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
d2746dc1
KH
1934 return ohci_queue_iso_receive_dualbuffer(base, packet,
1935 buffer, payload);
e364cf4e 1936 else
a186b4a6
JW
1937 return ohci_queue_iso_receive_packet_per_buffer(base, packet,
1938 buffer,
1939 payload);
295e3feb
KH
1940}
1941
21ebcd12 1942static const struct fw_card_driver ohci_driver = {
ed568912
KH
1943 .name = ohci_driver_name,
1944 .enable = ohci_enable,
1945 .update_phy_reg = ohci_update_phy_reg,
1946 .set_config_rom = ohci_set_config_rom,
1947 .send_request = ohci_send_request,
1948 .send_response = ohci_send_response,
730c32f5 1949 .cancel_packet = ohci_cancel_packet,
ed568912 1950 .enable_phys_dma = ohci_enable_phys_dma,
d60d7f1d 1951 .get_bus_time = ohci_get_bus_time,
ed568912
KH
1952
1953 .allocate_iso_context = ohci_allocate_iso_context,
1954 .free_iso_context = ohci_free_iso_context,
1955 .queue_iso = ohci_queue_iso,
69cdb726 1956 .start_iso = ohci_start_iso,
b8295668 1957 .stop_iso = ohci_stop_iso,
ed568912
KH
1958};
1959
ed568912
KH
1960static int __devinit
1961pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1962{
1963 struct fw_ohci *ohci;
e364cf4e 1964 u32 bus_options, max_receive, link_speed;
ed568912 1965 u64 guid;
d79406dd 1966 int err;
ed568912
KH
1967 size_t size;
1968
2d826cc5 1969 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912
KH
1970 if (ohci == NULL) {
1971 fw_error("Could not malloc fw_ohci data.\n");
1972 return -ENOMEM;
1973 }
1974
1975 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1976
d79406dd
KH
1977 err = pci_enable_device(dev);
1978 if (err) {
ed568912 1979 fw_error("Failed to enable OHCI hardware.\n");
d79406dd 1980 goto fail_put_card;
ed568912
KH
1981 }
1982
1983 pci_set_master(dev);
1984 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1985 pci_set_drvdata(dev, ohci);
1986
1987 spin_lock_init(&ohci->lock);
1988
1989 tasklet_init(&ohci->bus_reset_tasklet,
1990 bus_reset_tasklet, (unsigned long)ohci);
1991
d79406dd
KH
1992 err = pci_request_region(dev, 0, ohci_driver_name);
1993 if (err) {
ed568912 1994 fw_error("MMIO resource unavailable\n");
d79406dd 1995 goto fail_disable;
ed568912
KH
1996 }
1997
1998 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1999 if (ohci->registers == NULL) {
2000 fw_error("Failed to remap registers\n");
d79406dd
KH
2001 err = -ENXIO;
2002 goto fail_iomem;
ed568912
KH
2003 }
2004
ed568912
KH
2005 ar_context_init(&ohci->ar_request_ctx, ohci,
2006 OHCI1394_AsReqRcvContextControlSet);
2007
2008 ar_context_init(&ohci->ar_response_ctx, ohci,
2009 OHCI1394_AsRspRcvContextControlSet);
2010
f319b6a0
KH
2011 context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
2012 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
ed568912 2013
f319b6a0
KH
2014 context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
2015 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
ed568912 2016
ed568912
KH
2017 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2018 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2019 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2020 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2021 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2022
2023 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2024 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2025 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2026 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2027 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2028
2029 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2030 fw_error("Out of memory for it/ir contexts.\n");
d79406dd
KH
2031 err = -ENOMEM;
2032 goto fail_registers;
ed568912
KH
2033 }
2034
2035 /* self-id dma buffer allocation */
2036 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2037 SELF_ID_BUF_SIZE,
2038 &ohci->self_id_bus,
2039 GFP_KERNEL);
2040 if (ohci->self_id_cpu == NULL) {
2041 fw_error("Out of memory for self ID buffer.\n");
d79406dd
KH
2042 err = -ENOMEM;
2043 goto fail_registers;
ed568912
KH
2044 }
2045
ed568912
KH
2046 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2047 max_receive = (bus_options >> 12) & 0xf;
2048 link_speed = bus_options & 0x7;
2049 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2050 reg_read(ohci, OHCI1394_GUIDLo);
2051
d79406dd
KH
2052 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2053 if (err < 0)
2054 goto fail_self_id;
ed568912 2055
e364cf4e 2056 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
500be725 2057 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
e364cf4e 2058 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
ed568912 2059 return 0;
d79406dd
KH
2060
2061 fail_self_id:
2062 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2063 ohci->self_id_cpu, ohci->self_id_bus);
2064 fail_registers:
2065 kfree(ohci->it_context_list);
2066 kfree(ohci->ir_context_list);
2067 pci_iounmap(dev, ohci->registers);
2068 fail_iomem:
2069 pci_release_region(dev, 0);
2070 fail_disable:
2071 pci_disable_device(dev);
2072 fail_put_card:
2073 fw_card_put(&ohci->card);
2074
2075 return err;
ed568912
KH
2076}
2077
2078static void pci_remove(struct pci_dev *dev)
2079{
2080 struct fw_ohci *ohci;
2081
2082 ohci = pci_get_drvdata(dev);
e254a4b4
KH
2083 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2084 flush_writes(ohci);
ed568912
KH
2085 fw_core_remove_card(&ohci->card);
2086
c781c06d
KH
2087 /*
2088 * FIXME: Fail all pending packets here, now that the upper
2089 * layers can't queue any more.
2090 */
ed568912
KH
2091
2092 software_reset(ohci);
2093 free_irq(dev->irq, ohci);
d79406dd
KH
2094 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2095 ohci->self_id_cpu, ohci->self_id_bus);
2096 kfree(ohci->it_context_list);
2097 kfree(ohci->ir_context_list);
2098 pci_iounmap(dev, ohci->registers);
2099 pci_release_region(dev, 0);
2100 pci_disable_device(dev);
2101 fw_card_put(&ohci->card);
ed568912
KH
2102
2103 fw_notify("Removed fw-ohci device.\n");
2104}
2105
2aef469a
KH
2106#ifdef CONFIG_PM
2107static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
2108{
2109 struct fw_ohci *ohci = pci_get_drvdata(pdev);
2110 int err;
2111
2112 software_reset(ohci);
2113 free_irq(pdev->irq, ohci);
2114 err = pci_save_state(pdev);
2115 if (err) {
8a8cea27 2116 fw_error("pci_save_state failed\n");
2aef469a
KH
2117 return err;
2118 }
2119 err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
55111428
SR
2120 if (err)
2121 fw_error("pci_set_power_state failed with %d\n", err);
2aef469a
KH
2122
2123 return 0;
2124}
2125
2126static int pci_resume(struct pci_dev *pdev)
2127{
2128 struct fw_ohci *ohci = pci_get_drvdata(pdev);
2129 int err;
2130
2131 pci_set_power_state(pdev, PCI_D0);
2132 pci_restore_state(pdev);
2133 err = pci_enable_device(pdev);
2134 if (err) {
8a8cea27 2135 fw_error("pci_enable_device failed\n");
2aef469a
KH
2136 return err;
2137 }
2138
0bd243c4 2139 return ohci_enable(&ohci->card, NULL, 0);
2aef469a
KH
2140}
2141#endif
2142
ed568912
KH
2143static struct pci_device_id pci_table[] = {
2144 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2145 { }
2146};
2147
2148MODULE_DEVICE_TABLE(pci, pci_table);
2149
2150static struct pci_driver fw_ohci_pci_driver = {
2151 .name = ohci_driver_name,
2152 .id_table = pci_table,
2153 .probe = pci_probe,
2154 .remove = pci_remove,
2aef469a
KH
2155#ifdef CONFIG_PM
2156 .resume = pci_resume,
2157 .suspend = pci_suspend,
2158#endif
ed568912
KH
2159};
2160
2161MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2162MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2163MODULE_LICENSE("GPL");
2164
1e4c7b0d
OH
2165/* Provide a module alias so root-on-sbp2 initrds don't break. */
2166#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2167MODULE_ALIAS("ohci1394");
2168#endif
2169
ed568912
KH
2170static int __init fw_ohci_init(void)
2171{
2172 return pci_register_driver(&fw_ohci_pci_driver);
2173}
2174
2175static void __exit fw_ohci_cleanup(void)
2176{
2177 pci_unregister_driver(&fw_ohci_pci_driver);
2178}
2179
2180module_init(fw_ohci_init);
2181module_exit(fw_ohci_cleanup);
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