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ed568912 KH |
1 | /* -*- c-basic-offset: 8 -*- |
2 | * | |
3 | * fw-ohci.c - Driver for OHCI 1394 boards | |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd AM |
28 | #include <linux/dma-mapping.h> |
29 | ||
ed568912 KH |
30 | #include <asm/uaccess.h> |
31 | #include <asm/semaphore.h> | |
32 | ||
33 | #include "fw-transaction.h" | |
34 | #include "fw-ohci.h" | |
35 | ||
36 | #define descriptor_output_more 0 | |
37 | #define descriptor_output_last (1 << 12) | |
38 | #define descriptor_input_more (2 << 12) | |
39 | #define descriptor_input_last (3 << 12) | |
40 | #define descriptor_status (1 << 11) | |
41 | #define descriptor_key_immediate (2 << 8) | |
42 | #define descriptor_ping (1 << 7) | |
43 | #define descriptor_yy (1 << 6) | |
44 | #define descriptor_no_irq (0 << 4) | |
45 | #define descriptor_irq_error (1 << 4) | |
46 | #define descriptor_irq_always (3 << 4) | |
47 | #define descriptor_branch_always (3 << 2) | |
295e3feb | 48 | #define descriptor_wait (3 << 0) |
ed568912 KH |
49 | |
50 | struct descriptor { | |
51 | __le16 req_count; | |
52 | __le16 control; | |
53 | __le32 data_address; | |
54 | __le32 branch_address; | |
55 | __le16 res_count; | |
56 | __le16 transfer_status; | |
57 | } __attribute__((aligned(16))); | |
58 | ||
295e3feb KH |
59 | struct db_descriptor { |
60 | __le16 first_size; | |
61 | __le16 control; | |
62 | __le16 second_req_count; | |
63 | __le16 first_req_count; | |
64 | __le32 branch_address; | |
65 | __le16 second_res_count; | |
66 | __le16 first_res_count; | |
67 | __le32 reserved0; | |
68 | __le32 first_buffer; | |
69 | __le32 second_buffer; | |
70 | __le32 reserved1; | |
71 | } __attribute__((aligned(16))); | |
72 | ||
72e318e0 KH |
73 | #define control_set(regs) (regs) |
74 | #define control_clear(regs) ((regs) + 4) | |
75 | #define command_ptr(regs) ((regs) + 12) | |
76 | #define context_match(regs) ((regs) + 16) | |
77 | ||
32b46093 | 78 | struct ar_buffer { |
ed568912 | 79 | struct descriptor descriptor; |
32b46093 KH |
80 | struct ar_buffer *next; |
81 | __le32 data[0]; | |
82 | }; | |
ed568912 | 83 | |
32b46093 KH |
84 | struct ar_context { |
85 | struct fw_ohci *ohci; | |
86 | struct ar_buffer *current_buffer; | |
87 | struct ar_buffer *last_buffer; | |
88 | void *pointer; | |
72e318e0 | 89 | u32 regs; |
ed568912 KH |
90 | struct tasklet_struct tasklet; |
91 | }; | |
92 | ||
30200739 KH |
93 | struct context; |
94 | ||
95 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
96 | struct descriptor *d, | |
97 | struct descriptor *last); | |
98 | struct context { | |
99 | struct fw_ohci *ohci; | |
100 | u32 regs; | |
101 | ||
102 | struct descriptor *buffer; | |
103 | dma_addr_t buffer_bus; | |
104 | size_t buffer_size; | |
105 | struct descriptor *head_descriptor; | |
106 | struct descriptor *tail_descriptor; | |
107 | struct descriptor *tail_descriptor_last; | |
108 | struct descriptor *prev_descriptor; | |
109 | ||
110 | descriptor_callback_t callback; | |
111 | ||
112 | struct tasklet_struct tasklet; | |
113 | }; | |
114 | ||
115 | ||
116 | ||
ed568912 KH |
117 | struct at_context { |
118 | struct fw_ohci *ohci; | |
119 | dma_addr_t descriptor_bus; | |
120 | dma_addr_t buffer_bus; | |
730c32f5 | 121 | struct fw_packet *current_packet; |
ed568912 KH |
122 | |
123 | struct list_head list; | |
124 | ||
125 | struct { | |
126 | struct descriptor more; | |
127 | __le32 header[4]; | |
128 | struct descriptor last; | |
129 | } d; | |
130 | ||
72e318e0 | 131 | u32 regs; |
ed568912 KH |
132 | |
133 | struct tasklet_struct tasklet; | |
134 | }; | |
135 | ||
136 | #define it_header_sy(v) ((v) << 0) | |
137 | #define it_header_tcode(v) ((v) << 4) | |
138 | #define it_header_channel(v) ((v) << 8) | |
139 | #define it_header_tag(v) ((v) << 14) | |
140 | #define it_header_speed(v) ((v) << 16) | |
141 | #define it_header_data_length(v) ((v) << 16) | |
142 | ||
143 | struct iso_context { | |
144 | struct fw_iso_context base; | |
30200739 | 145 | struct context context; |
9b32d5f3 KH |
146 | void *header; |
147 | size_t header_length; | |
ed568912 KH |
148 | }; |
149 | ||
150 | #define CONFIG_ROM_SIZE 1024 | |
151 | ||
152 | struct fw_ohci { | |
153 | struct fw_card card; | |
154 | ||
e364cf4e | 155 | u32 version; |
ed568912 KH |
156 | __iomem char *registers; |
157 | dma_addr_t self_id_bus; | |
158 | __le32 *self_id_cpu; | |
159 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 160 | int node_id; |
ed568912 KH |
161 | int generation; |
162 | int request_generation; | |
163 | ||
164 | /* Spinlock for accessing fw_ohci data. Never call out of | |
165 | * this driver with this lock held. */ | |
166 | spinlock_t lock; | |
167 | u32 self_id_buffer[512]; | |
168 | ||
169 | /* Config rom buffers */ | |
170 | __be32 *config_rom; | |
171 | dma_addr_t config_rom_bus; | |
172 | __be32 *next_config_rom; | |
173 | dma_addr_t next_config_rom_bus; | |
174 | u32 next_header; | |
175 | ||
176 | struct ar_context ar_request_ctx; | |
177 | struct ar_context ar_response_ctx; | |
178 | struct at_context at_request_ctx; | |
179 | struct at_context at_response_ctx; | |
180 | ||
181 | u32 it_context_mask; | |
182 | struct iso_context *it_context_list; | |
183 | u32 ir_context_mask; | |
184 | struct iso_context *ir_context_list; | |
185 | }; | |
186 | ||
95688e97 | 187 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
188 | { |
189 | return container_of(card, struct fw_ohci, card); | |
190 | } | |
191 | ||
295e3feb KH |
192 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
193 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
194 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
195 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
196 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
197 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
198 | |
199 | #define CONTEXT_RUN 0x8000 | |
200 | #define CONTEXT_WAKE 0x1000 | |
201 | #define CONTEXT_DEAD 0x0800 | |
202 | #define CONTEXT_ACTIVE 0x0400 | |
203 | ||
204 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
205 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
206 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
207 | ||
208 | #define FW_OHCI_MAJOR 240 | |
209 | #define OHCI1394_REGISTER_SIZE 0x800 | |
210 | #define OHCI_LOOP_COUNT 500 | |
211 | #define OHCI1394_PCI_HCI_Control 0x40 | |
212 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 213 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 214 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 215 | |
ed568912 KH |
216 | static char ohci_driver_name[] = KBUILD_MODNAME; |
217 | ||
95688e97 | 218 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
219 | { |
220 | writel(data, ohci->registers + offset); | |
221 | } | |
222 | ||
95688e97 | 223 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
224 | { |
225 | return readl(ohci->registers + offset); | |
226 | } | |
227 | ||
95688e97 | 228 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
229 | { |
230 | /* Do a dummy read to flush writes. */ | |
231 | reg_read(ohci, OHCI1394_Version); | |
232 | } | |
233 | ||
234 | static int | |
235 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
236 | int clear_bits, int set_bits) | |
237 | { | |
238 | struct fw_ohci *ohci = fw_ohci(card); | |
239 | u32 val, old; | |
240 | ||
241 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
242 | msleep(2); | |
243 | val = reg_read(ohci, OHCI1394_PhyControl); | |
244 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
245 | fw_error("failed to set phy reg bits.\n"); | |
246 | return -EBUSY; | |
247 | } | |
248 | ||
249 | old = OHCI1394_PhyControl_ReadData(val); | |
250 | old = (old & ~clear_bits) | set_bits; | |
251 | reg_write(ohci, OHCI1394_PhyControl, | |
252 | OHCI1394_PhyControl_Write(addr, old)); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
32b46093 | 257 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 258 | { |
32b46093 KH |
259 | struct device *dev = ctx->ohci->card.device; |
260 | struct ar_buffer *ab; | |
261 | dma_addr_t ab_bus; | |
262 | size_t offset; | |
263 | ||
264 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
265 | if (ab == NULL) | |
266 | return -ENOMEM; | |
267 | ||
268 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
269 | if (dma_mapping_error(ab_bus)) { | |
270 | free_page((unsigned long) ab); | |
271 | return -ENOMEM; | |
272 | } | |
273 | ||
274 | memset(&ab->descriptor, 0, sizeof ab->descriptor); | |
275 | ab->descriptor.control = cpu_to_le16(descriptor_input_more | | |
276 | descriptor_status | | |
277 | descriptor_branch_always); | |
278 | offset = offsetof(struct ar_buffer, data); | |
279 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
280 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
281 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
282 | ab->descriptor.branch_address = 0; | |
283 | ||
284 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
285 | ||
286 | ctx->last_buffer->descriptor.branch_address = ab_bus | 1; | |
287 | ctx->last_buffer->next = ab; | |
288 | ctx->last_buffer = ab; | |
289 | ||
72e318e0 | 290 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE); |
ed568912 | 291 | flush_writes(ctx->ohci); |
32b46093 KH |
292 | |
293 | return 0; | |
ed568912 KH |
294 | } |
295 | ||
32b46093 | 296 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 297 | { |
ed568912 | 298 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
299 | struct fw_packet p; |
300 | u32 status, length, tcode; | |
2639a6fb | 301 | |
32b46093 KH |
302 | p.header[0] = le32_to_cpu(buffer[0]); |
303 | p.header[1] = le32_to_cpu(buffer[1]); | |
304 | p.header[2] = le32_to_cpu(buffer[2]); | |
2639a6fb KH |
305 | |
306 | tcode = (p.header[0] >> 4) & 0x0f; | |
307 | switch (tcode) { | |
308 | case TCODE_WRITE_QUADLET_REQUEST: | |
309 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 310 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 311 | p.header_length = 16; |
32b46093 | 312 | p.payload_length = 0; |
2639a6fb KH |
313 | break; |
314 | ||
2639a6fb | 315 | case TCODE_READ_BLOCK_REQUEST : |
32b46093 KH |
316 | p.header[3] = le32_to_cpu(buffer[3]); |
317 | p.header_length = 16; | |
318 | p.payload_length = 0; | |
319 | break; | |
320 | ||
321 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
322 | case TCODE_READ_BLOCK_RESPONSE: |
323 | case TCODE_LOCK_REQUEST: | |
324 | case TCODE_LOCK_RESPONSE: | |
32b46093 | 325 | p.header[3] = le32_to_cpu(buffer[3]); |
2639a6fb | 326 | p.header_length = 16; |
32b46093 | 327 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
328 | break; |
329 | ||
330 | case TCODE_WRITE_RESPONSE: | |
331 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 332 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 333 | p.header_length = 12; |
32b46093 | 334 | p.payload_length = 0; |
2639a6fb KH |
335 | break; |
336 | } | |
ed568912 | 337 | |
32b46093 KH |
338 | p.payload = (void *) buffer + p.header_length; |
339 | ||
340 | /* FIXME: What to do about evt_* errors? */ | |
341 | length = (p.header_length + p.payload_length + 3) / 4; | |
342 | status = le32_to_cpu(buffer[length]); | |
343 | ||
344 | p.ack = ((status >> 16) & 0x1f) - 16; | |
345 | p.speed = (status >> 21) & 0x7; | |
346 | p.timestamp = status & 0xffff; | |
347 | p.generation = ohci->request_generation; | |
ed568912 KH |
348 | |
349 | /* The OHCI bus reset handler synthesizes a phy packet with | |
350 | * the new generation number when a bus reset happens (see | |
351 | * section 8.4.2.3). This helps us determine when a request | |
352 | * was received and make sure we send the response in the same | |
353 | * generation. We only need this for requests; for responses | |
354 | * we use the unique tlabel for finding the matching | |
355 | * request. */ | |
356 | ||
2639a6fb | 357 | if (p.ack + 16 == 0x09) |
32b46093 | 358 | ohci->request_generation = (buffer[2] >> 16) & 0xff; |
ed568912 | 359 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 360 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 361 | else |
2639a6fb | 362 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 363 | |
32b46093 KH |
364 | return buffer + length + 1; |
365 | } | |
ed568912 | 366 | |
32b46093 KH |
367 | static void ar_context_tasklet(unsigned long data) |
368 | { | |
369 | struct ar_context *ctx = (struct ar_context *)data; | |
370 | struct fw_ohci *ohci = ctx->ohci; | |
371 | struct ar_buffer *ab; | |
372 | struct descriptor *d; | |
373 | void *buffer, *end; | |
374 | ||
375 | ab = ctx->current_buffer; | |
376 | d = &ab->descriptor; | |
377 | ||
378 | if (d->res_count == 0) { | |
379 | size_t size, rest, offset; | |
380 | ||
381 | /* This descriptor is finished and we may have a | |
382 | * packet split across this and the next buffer. We | |
383 | * reuse the page for reassembling the split packet. */ | |
384 | ||
385 | offset = offsetof(struct ar_buffer, data); | |
386 | dma_unmap_single(ohci->card.device, | |
387 | ab->descriptor.data_address - offset, | |
388 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
389 | ||
390 | buffer = ab; | |
391 | ab = ab->next; | |
392 | d = &ab->descriptor; | |
393 | size = buffer + PAGE_SIZE - ctx->pointer; | |
394 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
395 | memmove(buffer, ctx->pointer, size); | |
396 | memcpy(buffer + size, ab->data, rest); | |
397 | ctx->current_buffer = ab; | |
398 | ctx->pointer = (void *) ab->data + rest; | |
399 | end = buffer + size + rest; | |
400 | ||
401 | while (buffer < end) | |
402 | buffer = handle_ar_packet(ctx, buffer); | |
403 | ||
404 | free_page((unsigned long)buffer); | |
405 | ar_context_add_page(ctx); | |
406 | } else { | |
407 | buffer = ctx->pointer; | |
408 | ctx->pointer = end = | |
409 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
410 | ||
411 | while (buffer < end) | |
412 | buffer = handle_ar_packet(ctx, buffer); | |
413 | } | |
ed568912 KH |
414 | } |
415 | ||
416 | static int | |
72e318e0 | 417 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 418 | { |
32b46093 | 419 | struct ar_buffer ab; |
ed568912 | 420 | |
72e318e0 KH |
421 | ctx->regs = regs; |
422 | ctx->ohci = ohci; | |
423 | ctx->last_buffer = &ab; | |
ed568912 KH |
424 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
425 | ||
32b46093 KH |
426 | ar_context_add_page(ctx); |
427 | ar_context_add_page(ctx); | |
428 | ctx->current_buffer = ab.next; | |
429 | ctx->pointer = ctx->current_buffer->data; | |
430 | ||
72e318e0 KH |
431 | reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address); |
432 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN); | |
32b46093 | 433 | flush_writes(ctx->ohci); |
ed568912 KH |
434 | |
435 | return 0; | |
436 | } | |
30200739 KH |
437 | |
438 | static void context_tasklet(unsigned long data) | |
439 | { | |
440 | struct context *ctx = (struct context *) data; | |
441 | struct fw_ohci *ohci = ctx->ohci; | |
442 | struct descriptor *d, *last; | |
443 | u32 address; | |
444 | int z; | |
445 | ||
446 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
447 | ctx->buffer_size, DMA_TO_DEVICE); | |
448 | ||
449 | d = ctx->tail_descriptor; | |
450 | last = ctx->tail_descriptor_last; | |
451 | ||
452 | while (last->branch_address != 0) { | |
453 | address = le32_to_cpu(last->branch_address); | |
454 | z = address & 0xf; | |
455 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d; | |
456 | last = (z == 2) ? d : d + z - 1; | |
457 | ||
458 | if (!ctx->callback(ctx, d, last)) | |
459 | break; | |
460 | ||
461 | ctx->tail_descriptor = d; | |
462 | ctx->tail_descriptor_last = last; | |
463 | } | |
464 | } | |
465 | ||
466 | static int | |
467 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
468 | size_t buffer_size, u32 regs, | |
469 | descriptor_callback_t callback) | |
470 | { | |
471 | ctx->ohci = ohci; | |
472 | ctx->regs = regs; | |
473 | ctx->buffer_size = buffer_size; | |
474 | ctx->buffer = kmalloc(buffer_size, GFP_KERNEL); | |
475 | if (ctx->buffer == NULL) | |
476 | return -ENOMEM; | |
477 | ||
478 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); | |
479 | ctx->callback = callback; | |
480 | ||
481 | ctx->buffer_bus = | |
482 | dma_map_single(ohci->card.device, ctx->buffer, | |
483 | buffer_size, DMA_TO_DEVICE); | |
484 | if (dma_mapping_error(ctx->buffer_bus)) { | |
485 | kfree(ctx->buffer); | |
486 | return -ENOMEM; | |
487 | } | |
488 | ||
489 | ctx->head_descriptor = ctx->buffer; | |
490 | ctx->prev_descriptor = ctx->buffer; | |
491 | ctx->tail_descriptor = ctx->buffer; | |
492 | ctx->tail_descriptor_last = ctx->buffer; | |
493 | ||
494 | /* We put a dummy descriptor in the buffer that has a NULL | |
495 | * branch address and looks like it's been sent. That way we | |
496 | * have a descriptor to append DMA programs to. Also, the | |
497 | * ring buffer invariant is that it always has at least one | |
498 | * element so that head == tail means buffer full. */ | |
499 | ||
500 | memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); | |
501 | ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); | |
502 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); | |
503 | ctx->head_descriptor++; | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
9b32d5f3 | 508 | static void |
30200739 KH |
509 | context_release(struct context *ctx) |
510 | { | |
511 | struct fw_card *card = &ctx->ohci->card; | |
512 | ||
513 | dma_unmap_single(card->device, ctx->buffer_bus, | |
514 | ctx->buffer_size, DMA_TO_DEVICE); | |
515 | kfree(ctx->buffer); | |
516 | } | |
517 | ||
518 | static struct descriptor * | |
519 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
520 | { | |
521 | struct descriptor *d, *tail, *end; | |
522 | ||
523 | d = ctx->head_descriptor; | |
524 | tail = ctx->tail_descriptor; | |
525 | end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor); | |
526 | ||
527 | if (d + z <= tail) { | |
528 | goto has_space; | |
529 | } else if (d > tail && d + z <= end) { | |
530 | goto has_space; | |
531 | } else if (d > tail && ctx->buffer + z <= tail) { | |
532 | d = ctx->buffer; | |
533 | goto has_space; | |
534 | } | |
535 | ||
536 | return NULL; | |
537 | ||
538 | has_space: | |
539 | memset(d, 0, z * sizeof *d); | |
540 | *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
541 | ||
542 | return d; | |
543 | } | |
544 | ||
295e3feb | 545 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
546 | { |
547 | struct fw_ohci *ohci = ctx->ohci; | |
548 | ||
549 | reg_write(ohci, command_ptr(ctx->regs), | |
550 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); | |
551 | reg_write(ohci, control_clear(ctx->regs), ~0); | |
295e3feb | 552 | reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra); |
30200739 KH |
553 | flush_writes(ohci); |
554 | } | |
555 | ||
556 | static void context_append(struct context *ctx, | |
557 | struct descriptor *d, int z, int extra) | |
558 | { | |
559 | dma_addr_t d_bus; | |
560 | ||
561 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
562 | ||
563 | ctx->head_descriptor = d + z + extra; | |
564 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
565 | ctx->prev_descriptor = z == 2 ? d : d + z - 1; | |
566 | ||
567 | dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus, | |
568 | ctx->buffer_size, DMA_TO_DEVICE); | |
569 | ||
570 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE); | |
571 | flush_writes(ctx->ohci); | |
572 | } | |
573 | ||
574 | static void context_stop(struct context *ctx) | |
575 | { | |
576 | u32 reg; | |
b8295668 | 577 | int i; |
30200739 KH |
578 | |
579 | reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN); | |
b8295668 | 580 | flush_writes(ctx->ohci); |
30200739 | 581 | |
b8295668 KH |
582 | for (i = 0; i < 10; i++) { |
583 | reg = reg_read(ctx->ohci, control_set(ctx->regs)); | |
584 | if ((reg & CONTEXT_ACTIVE) == 0) | |
585 | break; | |
586 | ||
587 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
588 | msleep(1); | |
589 | } | |
30200739 | 590 | } |
ed568912 KH |
591 | |
592 | static void | |
593 | do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list) | |
594 | { | |
595 | struct fw_packet *p, *next; | |
596 | ||
597 | list_for_each_entry_safe(p, next, list, link) | |
2639a6fb | 598 | p->callback(p, &ohci->card, p->ack); |
ed568912 KH |
599 | } |
600 | ||
601 | static void | |
602 | complete_transmission(struct fw_packet *packet, | |
2639a6fb | 603 | int ack, struct list_head *list) |
ed568912 KH |
604 | { |
605 | list_move_tail(&packet->link, list); | |
2639a6fb | 606 | packet->ack = ack; |
ed568912 KH |
607 | } |
608 | ||
609 | /* This function prepares the first packet in the context queue for | |
610 | * transmission. Must always be called with the ochi->lock held to | |
611 | * ensure proper generation handling and locking around packet queue | |
612 | * manipulation. */ | |
613 | static void | |
614 | at_context_setup_packet(struct at_context *ctx, struct list_head *list) | |
615 | { | |
616 | struct fw_packet *packet; | |
617 | struct fw_ohci *ohci = ctx->ohci; | |
618 | int z, tcode; | |
619 | ||
620 | packet = fw_packet(ctx->list.next); | |
621 | ||
622 | memset(&ctx->d, 0, sizeof ctx->d); | |
623 | if (packet->payload_length > 0) { | |
624 | packet->payload_bus = dma_map_single(ohci->card.device, | |
625 | packet->payload, | |
626 | packet->payload_length, | |
627 | DMA_TO_DEVICE); | |
82eff9db | 628 | if (dma_mapping_error(packet->payload_bus)) { |
e5f49c3b | 629 | complete_transmission(packet, RCODE_SEND_ERROR, list); |
ed568912 KH |
630 | return; |
631 | } | |
632 | ||
633 | ctx->d.more.control = | |
634 | cpu_to_le16(descriptor_output_more | | |
635 | descriptor_key_immediate); | |
636 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
637 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
638 | ctx->d.last.control = | |
639 | cpu_to_le16(descriptor_output_last | | |
640 | descriptor_irq_always | | |
641 | descriptor_branch_always); | |
642 | ctx->d.last.req_count = cpu_to_le16(packet->payload_length); | |
643 | ctx->d.last.data_address = cpu_to_le32(packet->payload_bus); | |
644 | z = 3; | |
645 | } else { | |
646 | ctx->d.more.control = | |
647 | cpu_to_le16(descriptor_output_last | | |
648 | descriptor_key_immediate | | |
649 | descriptor_irq_always | | |
650 | descriptor_branch_always); | |
651 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
652 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
653 | z = 2; | |
654 | } | |
655 | ||
656 | /* The DMA format for asyncronous link packets is different | |
657 | * from the IEEE1394 layout, so shift the fields around | |
658 | * accordingly. If header_length is 8, it's a PHY packet, to | |
659 | * which we need to prepend an extra quadlet. */ | |
660 | if (packet->header_length > 8) { | |
661 | ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
662 | (packet->speed << 16)); | |
663 | ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
664 | (packet->header[0] & 0xffff0000)); | |
665 | ctx->d.header[2] = cpu_to_le32(packet->header[2]); | |
666 | ||
667 | tcode = (packet->header[0] >> 4) & 0x0f; | |
668 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
669 | ctx->d.header[3] = cpu_to_le32(packet->header[3]); | |
670 | else | |
671 | ctx->d.header[3] = packet->header[3]; | |
672 | } else { | |
673 | ctx->d.header[0] = | |
674 | cpu_to_le32((OHCI1394_phy_tcode << 4) | | |
675 | (packet->speed << 16)); | |
676 | ctx->d.header[1] = cpu_to_le32(packet->header[0]); | |
677 | ctx->d.header[2] = cpu_to_le32(packet->header[1]); | |
678 | ctx->d.more.req_count = cpu_to_le16(12); | |
679 | } | |
680 | ||
681 | /* FIXME: Document how the locking works. */ | |
682 | if (ohci->generation == packet->generation) { | |
72e318e0 | 683 | reg_write(ctx->ohci, command_ptr(ctx->regs), |
ed568912 | 684 | ctx->descriptor_bus | z); |
72e318e0 | 685 | reg_write(ctx->ohci, control_set(ctx->regs), |
ed568912 | 686 | CONTEXT_RUN | CONTEXT_WAKE); |
730c32f5 | 687 | ctx->current_packet = packet; |
ed568912 KH |
688 | } else { |
689 | /* We dont return error codes from this function; all | |
690 | * transmission errors are reported through the | |
691 | * callback. */ | |
e5f49c3b | 692 | complete_transmission(packet, RCODE_GENERATION, list); |
ed568912 KH |
693 | } |
694 | } | |
695 | ||
696 | static void at_context_stop(struct at_context *ctx) | |
697 | { | |
698 | u32 reg; | |
699 | ||
72e318e0 | 700 | reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN); |
ed568912 | 701 | |
72e318e0 | 702 | reg = reg_read(ctx->ohci, control_set(ctx->regs)); |
ed568912 KH |
703 | if (reg & CONTEXT_ACTIVE) |
704 | fw_notify("Tried to stop context, but it is still active " | |
705 | "(0x%08x).\n", reg); | |
706 | } | |
707 | ||
708 | static void at_context_tasklet(unsigned long data) | |
709 | { | |
710 | struct at_context *ctx = (struct at_context *)data; | |
711 | struct fw_ohci *ohci = ctx->ohci; | |
712 | struct fw_packet *packet; | |
713 | LIST_HEAD(list); | |
714 | unsigned long flags; | |
715 | int evt; | |
716 | ||
717 | spin_lock_irqsave(&ohci->lock, flags); | |
718 | ||
719 | packet = fw_packet(ctx->list.next); | |
720 | ||
721 | at_context_stop(ctx); | |
722 | ||
730c32f5 KH |
723 | /* If the head of the list isn't the packet that just got |
724 | * transmitted, the packet got cancelled before we finished | |
725 | * transmitting it. */ | |
726 | if (ctx->current_packet != packet) | |
727 | goto skip_to_next; | |
728 | ||
ed568912 KH |
729 | if (packet->payload_length > 0) { |
730 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
731 | packet->payload_length, DMA_TO_DEVICE); | |
732 | evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f; | |
733 | packet->timestamp = le16_to_cpu(ctx->d.last.res_count); | |
734 | } | |
735 | else { | |
736 | evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f; | |
737 | packet->timestamp = le16_to_cpu(ctx->d.more.res_count); | |
738 | } | |
739 | ||
740 | if (evt < 16) { | |
741 | switch (evt) { | |
742 | case OHCI1394_evt_timeout: | |
743 | /* Async response transmit timed out. */ | |
e5f49c3b | 744 | complete_transmission(packet, RCODE_CANCELLED, &list); |
ed568912 KH |
745 | break; |
746 | ||
747 | case OHCI1394_evt_flushed: | |
748 | /* The packet was flushed should give same | |
749 | * error as when we try to use a stale | |
750 | * generation count. */ | |
e5f49c3b KH |
751 | complete_transmission(packet, |
752 | RCODE_GENERATION, &list); | |
ed568912 KH |
753 | break; |
754 | ||
755 | case OHCI1394_evt_missing_ack: | |
e5f49c3b KH |
756 | /* Using a valid (current) generation count, |
757 | * but the node is not on the bus or not | |
758 | * sending acks. */ | |
759 | complete_transmission(packet, RCODE_NO_ACK, &list); | |
ed568912 KH |
760 | break; |
761 | ||
762 | default: | |
e5f49c3b | 763 | complete_transmission(packet, RCODE_SEND_ERROR, &list); |
ed568912 KH |
764 | break; |
765 | } | |
766 | } else | |
767 | complete_transmission(packet, evt - 16, &list); | |
768 | ||
730c32f5 | 769 | skip_to_next: |
ed568912 KH |
770 | /* If more packets are queued, set up the next one. */ |
771 | if (!list_empty(&ctx->list)) | |
772 | at_context_setup_packet(ctx, &list); | |
773 | ||
774 | spin_unlock_irqrestore(&ohci->lock, flags); | |
775 | ||
776 | do_packet_callbacks(ohci, &list); | |
777 | } | |
778 | ||
779 | static int | |
72e318e0 | 780 | at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 KH |
781 | { |
782 | INIT_LIST_HEAD(&ctx->list); | |
783 | ||
784 | ctx->descriptor_bus = | |
785 | dma_map_single(ohci->card.device, &ctx->d, | |
786 | sizeof ctx->d, DMA_TO_DEVICE); | |
82eff9db | 787 | if (dma_mapping_error(ctx->descriptor_bus)) |
ed568912 KH |
788 | return -ENOMEM; |
789 | ||
72e318e0 KH |
790 | ctx->regs = regs; |
791 | ctx->ohci = ohci; | |
ed568912 KH |
792 | |
793 | tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx); | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
e636fe25 | 798 | #define header_get_destination(q) (((q) >> 16) & 0xffff) |
93c4cceb KH |
799 | #define header_get_tcode(q) (((q) >> 4) & 0x0f) |
800 | #define header_get_offset_high(q) (((q) >> 0) & 0xffff) | |
801 | #define header_get_data_length(q) (((q) >> 16) & 0xffff) | |
802 | #define header_get_extended_tcode(q) (((q) >> 0) & 0xffff) | |
803 | ||
804 | static void | |
805 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
806 | { | |
807 | struct fw_packet response; | |
808 | int tcode, length, i; | |
809 | ||
810 | tcode = header_get_tcode(packet->header[0]); | |
811 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
812 | length = header_get_data_length(packet->header[3]); | |
813 | else | |
814 | length = 4; | |
815 | ||
816 | i = csr - CSR_CONFIG_ROM; | |
817 | if (i + length > CONFIG_ROM_SIZE) { | |
818 | fw_fill_response(&response, packet->header, | |
819 | RCODE_ADDRESS_ERROR, NULL, 0); | |
820 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
821 | fw_fill_response(&response, packet->header, | |
822 | RCODE_TYPE_ERROR, NULL, 0); | |
823 | } else { | |
824 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
825 | (void *) ohci->config_rom + i, length); | |
826 | } | |
827 | ||
828 | fw_core_handle_response(&ohci->card, &response); | |
829 | } | |
830 | ||
831 | static void | |
832 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
833 | { | |
834 | struct fw_packet response; | |
835 | int tcode, length, ext_tcode, sel; | |
836 | __be32 *payload, lock_old; | |
837 | u32 lock_arg, lock_data; | |
838 | ||
839 | tcode = header_get_tcode(packet->header[0]); | |
840 | length = header_get_data_length(packet->header[3]); | |
841 | payload = packet->payload; | |
842 | ext_tcode = header_get_extended_tcode(packet->header[3]); | |
843 | ||
844 | if (tcode == TCODE_LOCK_REQUEST && | |
845 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
846 | lock_arg = be32_to_cpu(payload[0]); | |
847 | lock_data = be32_to_cpu(payload[1]); | |
848 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
849 | lock_arg = 0; | |
850 | lock_data = 0; | |
851 | } else { | |
852 | fw_fill_response(&response, packet->header, | |
853 | RCODE_TYPE_ERROR, NULL, 0); | |
854 | goto out; | |
855 | } | |
856 | ||
857 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
858 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
859 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
860 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
861 | ||
862 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
863 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
864 | else | |
865 | fw_notify("swap not done yet\n"); | |
866 | ||
867 | fw_fill_response(&response, packet->header, | |
868 | RCODE_COMPLETE, &lock_old, sizeof lock_old); | |
869 | out: | |
870 | fw_core_handle_response(&ohci->card, &response); | |
871 | } | |
872 | ||
873 | static void | |
874 | handle_local_request(struct at_context *ctx, struct fw_packet *packet) | |
875 | { | |
876 | u64 offset; | |
877 | u32 csr; | |
878 | ||
879 | packet->ack = ACK_PENDING; | |
880 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
881 | ||
882 | offset = | |
883 | ((unsigned long long) | |
884 | header_get_offset_high(packet->header[1]) << 32) | | |
885 | packet->header[2]; | |
886 | csr = offset - CSR_REGISTER_BASE; | |
887 | ||
888 | /* Handle config rom reads. */ | |
889 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
890 | handle_local_rom(ctx->ohci, packet, csr); | |
891 | else switch (csr) { | |
892 | case CSR_BUS_MANAGER_ID: | |
893 | case CSR_BANDWIDTH_AVAILABLE: | |
894 | case CSR_CHANNELS_AVAILABLE_HI: | |
895 | case CSR_CHANNELS_AVAILABLE_LO: | |
896 | handle_local_lock(ctx->ohci, packet, csr); | |
897 | break; | |
898 | default: | |
899 | if (ctx == &ctx->ohci->at_request_ctx) | |
900 | fw_core_handle_request(&ctx->ohci->card, packet); | |
901 | else | |
902 | fw_core_handle_response(&ctx->ohci->card, packet); | |
903 | break; | |
904 | } | |
905 | } | |
e636fe25 | 906 | |
ed568912 KH |
907 | static void |
908 | at_context_transmit(struct at_context *ctx, struct fw_packet *packet) | |
909 | { | |
910 | LIST_HEAD(list); | |
911 | unsigned long flags; | |
ed568912 KH |
912 | |
913 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
914 | ||
e636fe25 KH |
915 | if (header_get_destination(packet->header[0]) == ctx->ohci->node_id && |
916 | ctx->ohci->generation == packet->generation) { | |
93c4cceb KH |
917 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
918 | handle_local_request(ctx, packet); | |
919 | return; | |
e636fe25 | 920 | } |
ed568912 | 921 | |
93c4cceb KH |
922 | list_add_tail(&packet->link, &ctx->list); |
923 | if (ctx->list.next == &packet->link) | |
924 | at_context_setup_packet(ctx, &list); | |
925 | ||
ed568912 KH |
926 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
927 | ||
928 | do_packet_callbacks(ctx->ohci, &list); | |
929 | } | |
930 | ||
931 | static void bus_reset_tasklet(unsigned long data) | |
932 | { | |
933 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 934 | int self_id_count, i, j, reg; |
ed568912 KH |
935 | int generation, new_generation; |
936 | unsigned long flags; | |
937 | ||
938 | reg = reg_read(ohci, OHCI1394_NodeID); | |
939 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
940 | fw_error("node ID not valid, new bus reset in progress\n"); | |
941 | return; | |
942 | } | |
e636fe25 | 943 | ohci->node_id = reg & 0xffff; |
ed568912 KH |
944 | |
945 | /* The count in the SelfIDCount register is the number of | |
946 | * bytes in the self ID receive buffer. Since we also receive | |
947 | * the inverted quadlets and a header quadlet, we shift one | |
948 | * bit extra to get the actual number of self IDs. */ | |
949 | ||
950 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
951 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
952 | ||
953 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
954 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
955 | fw_error("inconsistent self IDs\n"); | |
956 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
957 | } | |
958 | ||
959 | /* Check the consistency of the self IDs we just read. The | |
960 | * problem we face is that a new bus reset can start while we | |
961 | * read out the self IDs from the DMA buffer. If this happens, | |
962 | * the DMA buffer will be overwritten with new self IDs and we | |
963 | * will read out inconsistent data. The OHCI specification | |
964 | * (section 11.2) recommends a technique similar to | |
965 | * linux/seqlock.h, where we remember the generation of the | |
966 | * self IDs in the buffer before reading them out and compare | |
967 | * it to the current generation after reading them out. If | |
968 | * the two generations match we know we have a consistent set | |
969 | * of self IDs. */ | |
970 | ||
971 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
972 | if (new_generation != generation) { | |
973 | fw_notify("recursive bus reset detected, " | |
974 | "discarding self ids\n"); | |
975 | return; | |
976 | } | |
977 | ||
978 | /* FIXME: Document how the locking works. */ | |
979 | spin_lock_irqsave(&ohci->lock, flags); | |
980 | ||
981 | ohci->generation = generation; | |
982 | at_context_stop(&ohci->at_request_ctx); | |
983 | at_context_stop(&ohci->at_response_ctx); | |
984 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
985 | ||
986 | /* This next bit is unrelated to the AT context stuff but we | |
987 | * have to do it under the spinlock also. If a new config rom | |
988 | * was set up before this reset, the old one is now no longer | |
989 | * in use and we can free it. Update the config rom pointers | |
990 | * to point to the current config rom and clear the | |
991 | * next_config_rom pointer so a new udpate can take place. */ | |
992 | ||
993 | if (ohci->next_config_rom != NULL) { | |
994 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
995 | ohci->config_rom, ohci->config_rom_bus); | |
996 | ohci->config_rom = ohci->next_config_rom; | |
997 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
998 | ohci->next_config_rom = NULL; | |
999 | ||
1000 | /* Restore config_rom image and manually update | |
1001 | * config_rom registers. Writing the header quadlet | |
1002 | * will indicate that the config rom is ready, so we | |
1003 | * do that last. */ | |
1004 | reg_write(ohci, OHCI1394_BusOptions, | |
1005 | be32_to_cpu(ohci->config_rom[2])); | |
1006 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
1007 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
1008 | } | |
1009 | ||
1010 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1011 | ||
e636fe25 | 1012 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1013 | self_id_count, ohci->self_id_buffer); |
1014 | } | |
1015 | ||
1016 | static irqreturn_t irq_handler(int irq, void *data) | |
1017 | { | |
1018 | struct fw_ohci *ohci = data; | |
1019 | u32 event, iso_event; | |
1020 | int i; | |
1021 | ||
1022 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1023 | ||
1024 | if (!event) | |
1025 | return IRQ_NONE; | |
1026 | ||
1027 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
1028 | ||
1029 | if (event & OHCI1394_selfIDComplete) | |
1030 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1031 | ||
1032 | if (event & OHCI1394_RQPkt) | |
1033 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1034 | ||
1035 | if (event & OHCI1394_RSPkt) | |
1036 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1037 | ||
1038 | if (event & OHCI1394_reqTxComplete) | |
1039 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1040 | ||
1041 | if (event & OHCI1394_respTxComplete) | |
1042 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1043 | ||
c889475f | 1044 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1045 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1046 | ||
1047 | while (iso_event) { | |
1048 | i = ffs(iso_event) - 1; | |
30200739 | 1049 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1050 | iso_event &= ~(1 << i); |
1051 | } | |
1052 | ||
c889475f | 1053 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1054 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1055 | ||
1056 | while (iso_event) { | |
1057 | i = ffs(iso_event) - 1; | |
30200739 | 1058 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1059 | iso_event &= ~(1 << i); |
1060 | } | |
1061 | ||
1062 | return IRQ_HANDLED; | |
1063 | } | |
1064 | ||
1065 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |
1066 | { | |
1067 | struct fw_ohci *ohci = fw_ohci(card); | |
1068 | struct pci_dev *dev = to_pci_dev(card->device); | |
1069 | ||
1070 | /* When the link is not yet enabled, the atomic config rom | |
1071 | * update mechanism described below in ohci_set_config_rom() | |
1072 | * is not active. We have to update ConfigRomHeader and | |
1073 | * BusOptions manually, and the write to ConfigROMmap takes | |
1074 | * effect immediately. We tie this to the enabling of the | |
1075 | * link, so we have a valid config rom before enabling - the | |
1076 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1077 | * values before enabling. | |
1078 | * | |
1079 | * However, when the ConfigROMmap is written, some controllers | |
1080 | * always read back quadlets 0 and 2 from the config rom to | |
1081 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1082 | * They shouldn't do that in this initial case where the link | |
1083 | * isn't enabled. This means we have to use the same | |
1084 | * workaround here, setting the bus header to 0 and then write | |
1085 | * the right values in the bus reset tasklet. | |
1086 | */ | |
1087 | ||
1088 | ohci->next_config_rom = | |
1089 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1090 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
1091 | if (ohci->next_config_rom == NULL) | |
1092 | return -ENOMEM; | |
1093 | ||
1094 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1095 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1096 | ||
1097 | ohci->next_header = config_rom[0]; | |
1098 | ohci->next_config_rom[0] = 0; | |
1099 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
1100 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
1101 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
1102 | ||
1103 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1104 | ||
1105 | if (request_irq(dev->irq, irq_handler, | |
1106 | SA_SHIRQ, ohci_driver_name, ohci)) { | |
1107 | fw_error("Failed to allocate shared interrupt %d.\n", | |
1108 | dev->irq); | |
1109 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1110 | ohci->config_rom, ohci->config_rom_bus); | |
1111 | return -EIO; | |
1112 | } | |
1113 | ||
1114 | reg_write(ohci, OHCI1394_HCControlSet, | |
1115 | OHCI1394_HCControl_linkEnable | | |
1116 | OHCI1394_HCControl_BIBimageValid); | |
1117 | flush_writes(ohci); | |
1118 | ||
1119 | /* We are ready to go, initiate bus reset to finish the | |
1120 | * initialization. */ | |
1121 | ||
1122 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | static int | |
1128 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1129 | { | |
1130 | struct fw_ohci *ohci; | |
1131 | unsigned long flags; | |
1132 | int retval = 0; | |
1133 | __be32 *next_config_rom; | |
1134 | dma_addr_t next_config_rom_bus; | |
1135 | ||
1136 | ohci = fw_ohci(card); | |
1137 | ||
1138 | /* When the OHCI controller is enabled, the config rom update | |
1139 | * mechanism is a bit tricky, but easy enough to use. See | |
1140 | * section 5.5.6 in the OHCI specification. | |
1141 | * | |
1142 | * The OHCI controller caches the new config rom address in a | |
1143 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1144 | * for the changes to take place. When the bus reset is | |
1145 | * detected, the controller loads the new values for the | |
1146 | * ConfigRomHeader and BusOptions registers from the specified | |
1147 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1148 | * shadow register. All automatically and atomically. | |
1149 | * | |
1150 | * Now, there's a twist to this story. The automatic load of | |
1151 | * ConfigRomHeader and BusOptions doesn't honor the | |
1152 | * noByteSwapData bit, so with a be32 config rom, the | |
1153 | * controller will load be32 values in to these registers | |
1154 | * during the atomic update, even on litte endian | |
1155 | * architectures. The workaround we use is to put a 0 in the | |
1156 | * header quadlet; 0 is endian agnostic and means that the | |
1157 | * config rom isn't ready yet. In the bus reset tasklet we | |
1158 | * then set up the real values for the two registers. | |
1159 | * | |
1160 | * We use ohci->lock to avoid racing with the code that sets | |
1161 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1162 | */ | |
1163 | ||
1164 | next_config_rom = | |
1165 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1166 | &next_config_rom_bus, GFP_KERNEL); | |
1167 | if (next_config_rom == NULL) | |
1168 | return -ENOMEM; | |
1169 | ||
1170 | spin_lock_irqsave(&ohci->lock, flags); | |
1171 | ||
1172 | if (ohci->next_config_rom == NULL) { | |
1173 | ohci->next_config_rom = next_config_rom; | |
1174 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1175 | ||
1176 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1177 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1178 | length * 4); | |
1179 | ||
1180 | ohci->next_header = config_rom[0]; | |
1181 | ohci->next_config_rom[0] = 0; | |
1182 | ||
1183 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1184 | ohci->next_config_rom_bus); | |
1185 | } else { | |
1186 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1187 | next_config_rom, next_config_rom_bus); | |
1188 | retval = -EBUSY; | |
1189 | } | |
1190 | ||
1191 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1192 | ||
1193 | /* Now initiate a bus reset to have the changes take | |
1194 | * effect. We clean up the old config rom memory and DMA | |
1195 | * mappings in the bus reset tasklet, since the OHCI | |
1196 | * controller could need to access it before the bus reset | |
1197 | * takes effect. */ | |
1198 | if (retval == 0) | |
1199 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1200 | ||
1201 | return retval; | |
1202 | } | |
1203 | ||
1204 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1205 | { | |
1206 | struct fw_ohci *ohci = fw_ohci(card); | |
1207 | ||
1208 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1209 | } | |
1210 | ||
1211 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1212 | { | |
1213 | struct fw_ohci *ohci = fw_ohci(card); | |
1214 | ||
1215 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1216 | } | |
1217 | ||
730c32f5 KH |
1218 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1219 | { | |
1220 | struct fw_ohci *ohci = fw_ohci(card); | |
1221 | LIST_HEAD(list); | |
1222 | unsigned long flags; | |
1223 | ||
1224 | spin_lock_irqsave(&ohci->lock, flags); | |
1225 | ||
1226 | if (packet->ack == 0) { | |
1227 | fw_notify("cancelling packet %p (header[0]=%08x)\n", | |
1228 | packet, packet->header[0]); | |
1229 | ||
1230 | complete_transmission(packet, RCODE_CANCELLED, &list); | |
1231 | } | |
1232 | ||
1233 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1234 | ||
1235 | do_packet_callbacks(ohci, &list); | |
1236 | ||
1237 | /* Return success if we actually cancelled something. */ | |
1238 | return list_empty(&list) ? -ENOENT : 0; | |
1239 | } | |
1240 | ||
ed568912 KH |
1241 | static int |
1242 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1243 | { | |
1244 | struct fw_ohci *ohci = fw_ohci(card); | |
1245 | unsigned long flags; | |
907293d7 | 1246 | int n, retval = 0; |
ed568912 | 1247 | |
907293d7 SR |
1248 | /* FIXME: Make sure this bitmask is cleared when we clear the busReset |
1249 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ | |
ed568912 KH |
1250 | |
1251 | spin_lock_irqsave(&ohci->lock, flags); | |
1252 | ||
1253 | if (ohci->generation != generation) { | |
1254 | retval = -ESTALE; | |
1255 | goto out; | |
1256 | } | |
1257 | ||
907293d7 SR |
1258 | /* NOTE, if the node ID contains a non-local bus ID, physical DMA is |
1259 | * enabled for _all_ nodes on remote buses. */ | |
1260 | ||
1261 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1262 | if (n < 32) | |
1263 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1264 | else | |
1265 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1266 | ||
ed568912 | 1267 | flush_writes(ohci); |
ed568912 | 1268 | out: |
6cad95fe | 1269 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1270 | return retval; |
1271 | } | |
d2746dc1 KH |
1272 | |
1273 | static int handle_ir_bufferfill_packet(struct context *context, | |
1274 | struct descriptor *d, | |
1275 | struct descriptor *last) | |
1276 | { | |
1277 | struct iso_context *ctx = | |
1278 | container_of(context, struct iso_context, context); | |
ed568912 | 1279 | |
d2746dc1 KH |
1280 | if (d->res_count > 0) |
1281 | return 0; | |
1282 | ||
1283 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
1284 | ctx->base.callback(&ctx->base, | |
1285 | le16_to_cpu(last->res_count), | |
1286 | 0, NULL, ctx->base.callback_data); | |
1287 | ||
1288 | return 1; | |
1289 | } | |
1290 | ||
1291 | static int handle_ir_dualbuffer_packet(struct context *context, | |
1292 | struct descriptor *d, | |
1293 | struct descriptor *last) | |
ed568912 | 1294 | { |
295e3feb KH |
1295 | struct iso_context *ctx = |
1296 | container_of(context, struct iso_context, context); | |
1297 | struct db_descriptor *db = (struct db_descriptor *) d; | |
9b32d5f3 | 1298 | size_t header_length; |
d2746dc1 | 1299 | |
295e3feb KH |
1300 | if (db->first_res_count > 0 && db->second_res_count > 0) |
1301 | /* This descriptor isn't done yet, stop iteration. */ | |
1302 | return 0; | |
1303 | ||
9b32d5f3 KH |
1304 | header_length = db->first_req_count - db->first_res_count; |
1305 | if (ctx->header_length + header_length <= PAGE_SIZE) | |
1306 | memcpy(ctx->header + ctx->header_length, db + 1, header_length); | |
1307 | ctx->header_length += header_length; | |
1308 | ||
1309 | if (le16_to_cpu(db->control) & descriptor_irq_always) { | |
1310 | ctx->base.callback(&ctx->base, 0, | |
1311 | ctx->header_length, ctx->header, | |
295e3feb | 1312 | ctx->base.callback_data); |
9b32d5f3 KH |
1313 | ctx->header_length = 0; |
1314 | } | |
ed568912 | 1315 | |
295e3feb | 1316 | return 1; |
ed568912 KH |
1317 | } |
1318 | ||
1319 | #define ISO_BUFFER_SIZE (64 * 1024) | |
1320 | ||
30200739 KH |
1321 | static int handle_it_packet(struct context *context, |
1322 | struct descriptor *d, | |
1323 | struct descriptor *last) | |
ed568912 | 1324 | { |
30200739 KH |
1325 | struct iso_context *ctx = |
1326 | container_of(context, struct iso_context, context); | |
1327 | ||
1328 | if (last->transfer_status == 0) | |
1329 | /* This descriptor isn't done yet, stop iteration. */ | |
1330 | return 0; | |
1331 | ||
1332 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
9b32d5f3 KH |
1333 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1334 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1335 | |
1336 | return 1; | |
ed568912 KH |
1337 | } |
1338 | ||
30200739 | 1339 | static struct fw_iso_context * |
d2746dc1 | 1340 | ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed568912 KH |
1341 | { |
1342 | struct fw_ohci *ohci = fw_ohci(card); | |
1343 | struct iso_context *ctx, *list; | |
30200739 | 1344 | descriptor_callback_t callback; |
295e3feb | 1345 | u32 *mask, regs; |
ed568912 | 1346 | unsigned long flags; |
9b32d5f3 | 1347 | int index, retval = -ENOMEM; |
ed568912 KH |
1348 | |
1349 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1350 | mask = &ohci->it_context_mask; | |
1351 | list = ohci->it_context_list; | |
30200739 | 1352 | callback = handle_it_packet; |
ed568912 | 1353 | } else { |
295e3feb KH |
1354 | mask = &ohci->ir_context_mask; |
1355 | list = ohci->ir_context_list; | |
d2746dc1 KH |
1356 | if (header_size > 0) |
1357 | callback = handle_ir_dualbuffer_packet; | |
1358 | else | |
1359 | callback = handle_ir_bufferfill_packet; | |
ed568912 KH |
1360 | } |
1361 | ||
e364cf4e KH |
1362 | if (callback == handle_ir_dualbuffer_packet && |
1363 | ohci->version < OHCI_VERSION_1_1) | |
1364 | return ERR_PTR(-EINVAL); | |
1365 | ||
ed568912 KH |
1366 | spin_lock_irqsave(&ohci->lock, flags); |
1367 | index = ffs(*mask) - 1; | |
1368 | if (index >= 0) | |
1369 | *mask &= ~(1 << index); | |
1370 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1371 | ||
1372 | if (index < 0) | |
1373 | return ERR_PTR(-EBUSY); | |
1374 | ||
295e3feb KH |
1375 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1376 | regs = OHCI1394_IsoXmitContextBase(index); | |
1377 | else | |
1378 | regs = OHCI1394_IsoRcvContextBase(index); | |
1379 | ||
ed568912 KH |
1380 | ctx = &list[index]; |
1381 | memset(ctx, 0, sizeof *ctx); | |
9b32d5f3 KH |
1382 | ctx->header_length = 0; |
1383 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1384 | if (ctx->header == NULL) | |
1385 | goto out; | |
1386 | ||
30200739 | 1387 | retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE, |
295e3feb | 1388 | regs, callback); |
9b32d5f3 KH |
1389 | if (retval < 0) |
1390 | goto out_with_header; | |
ed568912 KH |
1391 | |
1392 | return &ctx->base; | |
9b32d5f3 KH |
1393 | |
1394 | out_with_header: | |
1395 | free_page((unsigned long)ctx->header); | |
1396 | out: | |
1397 | spin_lock_irqsave(&ohci->lock, flags); | |
1398 | *mask |= 1 << index; | |
1399 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1400 | ||
1401 | return ERR_PTR(retval); | |
ed568912 KH |
1402 | } |
1403 | ||
69cdb726 | 1404 | static int ohci_start_iso(struct fw_iso_context *base, s32 cycle) |
ed568912 | 1405 | { |
30200739 KH |
1406 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1407 | struct fw_ohci *ohci = ctx->context.ohci; | |
d2746dc1 | 1408 | u32 cycle_match = 0, mode; |
ed568912 KH |
1409 | int index; |
1410 | ||
295e3feb KH |
1411 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1412 | index = ctx - ohci->it_context_list; | |
1413 | if (cycle > 0) | |
1414 | cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
1415 | (cycle & 0x7fff) << 16; | |
1416 | ||
1417 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); | |
1418 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
1419 | context_run(&ctx->context, cycle_match); | |
1420 | } else { | |
1421 | index = ctx - ohci->ir_context_list; | |
ed568912 | 1422 | |
d2746dc1 KH |
1423 | if (ctx->base.header_size > 0) |
1424 | mode = IR_CONTEXT_DUAL_BUFFER_MODE; | |
1425 | else | |
1426 | mode = IR_CONTEXT_BUFFER_FILL; | |
295e3feb KH |
1427 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1428 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
1429 | reg_write(ohci, context_match(ctx->context.regs), | |
1430 | 0xf0000000 | ctx->base.channel); | |
d2746dc1 | 1431 | context_run(&ctx->context, mode); |
295e3feb | 1432 | } |
ed568912 KH |
1433 | |
1434 | return 0; | |
1435 | } | |
1436 | ||
b8295668 KH |
1437 | static int ohci_stop_iso(struct fw_iso_context *base) |
1438 | { | |
1439 | struct fw_ohci *ohci = fw_ohci(base->card); | |
1440 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1441 | int index; | |
1442 | ||
1443 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1444 | index = ctx - ohci->it_context_list; | |
1445 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1446 | } else { | |
1447 | index = ctx - ohci->ir_context_list; | |
1448 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1449 | } | |
1450 | flush_writes(ohci); | |
1451 | context_stop(&ctx->context); | |
1452 | ||
1453 | return 0; | |
1454 | } | |
1455 | ||
ed568912 KH |
1456 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1457 | { | |
1458 | struct fw_ohci *ohci = fw_ohci(base->card); | |
30200739 | 1459 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1460 | unsigned long flags; |
1461 | int index; | |
1462 | ||
b8295668 KH |
1463 | ohci_stop_iso(base); |
1464 | context_release(&ctx->context); | |
9b32d5f3 | 1465 | free_page((unsigned long)ctx->header); |
b8295668 | 1466 | |
ed568912 KH |
1467 | spin_lock_irqsave(&ohci->lock, flags); |
1468 | ||
1469 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1470 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
1471 | ohci->it_context_mask |= 1 << index; |
1472 | } else { | |
1473 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
1474 | ohci->ir_context_mask |= 1 << index; |
1475 | } | |
ed568912 KH |
1476 | |
1477 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1478 | } | |
1479 | ||
1480 | static int | |
295e3feb KH |
1481 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1482 | struct fw_iso_packet *packet, | |
1483 | struct fw_iso_buffer *buffer, | |
1484 | unsigned long payload) | |
ed568912 | 1485 | { |
30200739 KH |
1486 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1487 | struct descriptor *d, *last, *pd; | |
ed568912 KH |
1488 | struct fw_iso_packet *p; |
1489 | __le32 *header; | |
9aad8125 | 1490 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1491 | u32 z, header_z, payload_z, irq; |
1492 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1493 | int page, end_page, i, length, offset; |
ed568912 KH |
1494 | |
1495 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1496 | * packet, retransmit or terminate.. */ | |
1497 | ||
1498 | p = packet; | |
9aad8125 | 1499 | payload_index = payload; |
ed568912 KH |
1500 | |
1501 | if (p->skip) | |
1502 | z = 1; | |
1503 | else | |
1504 | z = 2; | |
1505 | if (p->header_length > 0) | |
1506 | z++; | |
1507 | ||
1508 | /* Determine the first page the payload isn't contained in. */ | |
1509 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1510 | if (p->payload_length > 0) | |
1511 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1512 | else | |
1513 | payload_z = 0; | |
1514 | ||
1515 | z += payload_z; | |
1516 | ||
1517 | /* Get header size in number of descriptors. */ | |
1518 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1519 | ||
30200739 KH |
1520 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
1521 | if (d == NULL) | |
1522 | return -ENOMEM; | |
ed568912 KH |
1523 | |
1524 | if (!p->skip) { | |
1525 | d[0].control = cpu_to_le16(descriptor_key_immediate); | |
1526 | d[0].req_count = cpu_to_le16(8); | |
1527 | ||
1528 | header = (__le32 *) &d[1]; | |
1529 | header[0] = cpu_to_le32(it_header_sy(p->sy) | | |
1530 | it_header_tag(p->tag) | | |
1531 | it_header_tcode(TCODE_STREAM_DATA) | | |
1532 | it_header_channel(ctx->base.channel) | | |
1533 | it_header_speed(ctx->base.speed)); | |
1534 | header[1] = | |
1535 | cpu_to_le32(it_header_data_length(p->header_length + | |
1536 | p->payload_length)); | |
1537 | } | |
1538 | ||
1539 | if (p->header_length > 0) { | |
1540 | d[2].req_count = cpu_to_le16(p->header_length); | |
1541 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d); | |
1542 | memcpy(&d[z], p->header, p->header_length); | |
1543 | } | |
1544 | ||
1545 | pd = d + z - payload_z; | |
1546 | payload_end_index = payload_index + p->payload_length; | |
1547 | for (i = 0; i < payload_z; i++) { | |
1548 | page = payload_index >> PAGE_SHIFT; | |
1549 | offset = payload_index & ~PAGE_MASK; | |
1550 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1551 | length = | |
1552 | min(next_page_index, payload_end_index) - payload_index; | |
1553 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
1554 | |
1555 | page_bus = page_private(buffer->pages[page]); | |
1556 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
1557 | |
1558 | payload_index += length; | |
1559 | } | |
1560 | ||
ed568912 KH |
1561 | if (p->interrupt) |
1562 | irq = descriptor_irq_always; | |
1563 | else | |
1564 | irq = descriptor_no_irq; | |
1565 | ||
30200739 | 1566 | last = z == 2 ? d : d + z - 1; |
cbb59da7 KH |
1567 | last->control |= cpu_to_le16(descriptor_output_last | |
1568 | descriptor_status | | |
1569 | descriptor_branch_always | | |
1570 | irq); | |
ed568912 | 1571 | |
30200739 | 1572 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
1573 | |
1574 | return 0; | |
1575 | } | |
1576 | ||
295e3feb | 1577 | static int |
d2746dc1 KH |
1578 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
1579 | struct fw_iso_packet *packet, | |
1580 | struct fw_iso_buffer *buffer, | |
1581 | unsigned long payload) | |
295e3feb KH |
1582 | { |
1583 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1584 | struct db_descriptor *db = NULL; | |
1585 | struct descriptor *d; | |
1586 | struct fw_iso_packet *p; | |
1587 | dma_addr_t d_bus, page_bus; | |
1588 | u32 z, header_z, length, rest; | |
1589 | int page, offset; | |
1590 | ||
1591 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1592 | * packet, retransmit or terminate.. */ | |
1593 | ||
1594 | p = packet; | |
1595 | z = 2; | |
1596 | ||
1597 | /* Get header size in number of descriptors. */ | |
1598 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1599 | page = payload >> PAGE_SHIFT; | |
1600 | offset = payload & ~PAGE_MASK; | |
1601 | rest = p->payload_length; | |
1602 | ||
1603 | /* FIXME: OHCI 1.0 doesn't support dual buffer receive */ | |
1604 | /* FIXME: handle descriptor_wait */ | |
1605 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ | |
1606 | while (rest > 0) { | |
1607 | d = context_get_descriptors(&ctx->context, | |
1608 | z + header_z, &d_bus); | |
1609 | if (d == NULL) | |
1610 | return -ENOMEM; | |
1611 | ||
1612 | db = (struct db_descriptor *) d; | |
1613 | db->control = cpu_to_le16(descriptor_status | | |
1614 | descriptor_branch_always); | |
1615 | db->first_size = cpu_to_le16(ctx->base.header_size); | |
1616 | db->first_req_count = cpu_to_le16(p->header_length); | |
1e1d196b | 1617 | db->first_res_count = db->first_req_count; |
295e3feb KH |
1618 | db->first_buffer = cpu_to_le32(d_bus + sizeof *db); |
1619 | ||
1620 | if (offset + rest < PAGE_SIZE) | |
1621 | length = rest; | |
1622 | else | |
1623 | length = PAGE_SIZE - offset; | |
1624 | ||
1e1d196b KH |
1625 | db->second_req_count = cpu_to_le16(length); |
1626 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
1627 | page_bus = page_private(buffer->pages[page]); |
1628 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
1629 | ||
cb2d2cdb KH |
1630 | if (p->interrupt && length == rest) |
1631 | db->control |= cpu_to_le16(descriptor_irq_always); | |
1632 | ||
295e3feb KH |
1633 | context_append(&ctx->context, d, z, header_z); |
1634 | offset = (offset + length) & ~PAGE_MASK; | |
1635 | rest -= length; | |
1636 | page++; | |
1637 | } | |
1638 | ||
d2746dc1 KH |
1639 | return 0; |
1640 | } | |
295e3feb | 1641 | |
d2746dc1 KH |
1642 | static int |
1643 | ohci_queue_iso_receive_bufferfill(struct fw_iso_context *base, | |
1644 | struct fw_iso_packet *packet, | |
1645 | struct fw_iso_buffer *buffer, | |
1646 | unsigned long payload) | |
1647 | { | |
1648 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1649 | struct descriptor *d = NULL; | |
1650 | dma_addr_t d_bus, page_bus; | |
1651 | u32 length, rest; | |
1652 | int page, offset; | |
295e3feb | 1653 | |
d2746dc1 KH |
1654 | page = payload >> PAGE_SHIFT; |
1655 | offset = payload & ~PAGE_MASK; | |
1656 | rest = packet->payload_length; | |
1657 | ||
1658 | while (rest > 0) { | |
1659 | d = context_get_descriptors(&ctx->context, 1, &d_bus); | |
1660 | if (d == NULL) | |
1661 | return -ENOMEM; | |
1662 | ||
1663 | d->control = cpu_to_le16(descriptor_input_more | | |
1664 | descriptor_status | | |
1665 | descriptor_branch_always); | |
1666 | ||
1667 | if (offset + rest < PAGE_SIZE) | |
1668 | length = rest; | |
1669 | else | |
1670 | length = PAGE_SIZE - offset; | |
1671 | ||
1672 | page_bus = page_private(buffer->pages[page]); | |
1673 | d->data_address = cpu_to_le32(page_bus + offset); | |
1674 | d->req_count = cpu_to_le16(length); | |
1675 | d->res_count = cpu_to_le16(length); | |
1676 | ||
cb2d2cdb KH |
1677 | if (packet->interrupt && length == rest) |
1678 | d->control |= cpu_to_le16(descriptor_irq_always); | |
1679 | ||
d2746dc1 KH |
1680 | context_append(&ctx->context, d, 1, 0); |
1681 | ||
1682 | offset = (offset + length) & ~PAGE_MASK; | |
1683 | rest -= length; | |
1684 | page++; | |
1685 | } | |
1686 | ||
d2746dc1 KH |
1687 | return 0; |
1688 | } | |
1689 | ||
295e3feb KH |
1690 | static int |
1691 | ohci_queue_iso(struct fw_iso_context *base, | |
1692 | struct fw_iso_packet *packet, | |
1693 | struct fw_iso_buffer *buffer, | |
1694 | unsigned long payload) | |
1695 | { | |
e364cf4e KH |
1696 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1697 | ||
295e3feb KH |
1698 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
1699 | return ohci_queue_iso_transmit(base, packet, buffer, payload); | |
d2746dc1 KH |
1700 | else if (base->header_size == 0) |
1701 | return ohci_queue_iso_receive_bufferfill(base, packet, | |
1702 | buffer, payload); | |
e364cf4e | 1703 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
d2746dc1 KH |
1704 | return ohci_queue_iso_receive_dualbuffer(base, packet, |
1705 | buffer, payload); | |
e364cf4e KH |
1706 | else |
1707 | /* FIXME: Implement fallback for OHCI 1.0 controllers. */ | |
1708 | return -EINVAL; | |
295e3feb KH |
1709 | } |
1710 | ||
21ebcd12 | 1711 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1712 | .name = ohci_driver_name, |
1713 | .enable = ohci_enable, | |
1714 | .update_phy_reg = ohci_update_phy_reg, | |
1715 | .set_config_rom = ohci_set_config_rom, | |
1716 | .send_request = ohci_send_request, | |
1717 | .send_response = ohci_send_response, | |
730c32f5 | 1718 | .cancel_packet = ohci_cancel_packet, |
ed568912 KH |
1719 | .enable_phys_dma = ohci_enable_phys_dma, |
1720 | ||
1721 | .allocate_iso_context = ohci_allocate_iso_context, | |
1722 | .free_iso_context = ohci_free_iso_context, | |
1723 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 1724 | .start_iso = ohci_start_iso, |
b8295668 | 1725 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
1726 | }; |
1727 | ||
1728 | static int software_reset(struct fw_ohci *ohci) | |
1729 | { | |
1730 | int i; | |
1731 | ||
1732 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1733 | ||
1734 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1735 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1736 | OHCI1394_HCControl_softReset) == 0) | |
1737 | return 0; | |
1738 | msleep(1); | |
1739 | } | |
1740 | ||
1741 | return -EBUSY; | |
1742 | } | |
1743 | ||
1744 | /* ---------- pci subsystem interface ---------- */ | |
1745 | ||
1746 | enum { | |
1747 | CLEANUP_SELF_ID, | |
1748 | CLEANUP_REGISTERS, | |
1749 | CLEANUP_IOMEM, | |
1750 | CLEANUP_DISABLE, | |
1751 | CLEANUP_PUT_CARD, | |
1752 | }; | |
1753 | ||
1754 | static int cleanup(struct fw_ohci *ohci, int stage, int code) | |
1755 | { | |
1756 | struct pci_dev *dev = to_pci_dev(ohci->card.device); | |
1757 | ||
1758 | switch (stage) { | |
1759 | case CLEANUP_SELF_ID: | |
1760 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1761 | ohci->self_id_cpu, ohci->self_id_bus); | |
1762 | case CLEANUP_REGISTERS: | |
1763 | kfree(ohci->it_context_list); | |
1764 | kfree(ohci->ir_context_list); | |
1765 | pci_iounmap(dev, ohci->registers); | |
1766 | case CLEANUP_IOMEM: | |
1767 | pci_release_region(dev, 0); | |
1768 | case CLEANUP_DISABLE: | |
1769 | pci_disable_device(dev); | |
1770 | case CLEANUP_PUT_CARD: | |
1771 | fw_card_put(&ohci->card); | |
1772 | } | |
1773 | ||
1774 | return code; | |
1775 | } | |
1776 | ||
1777 | static int __devinit | |
1778 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1779 | { | |
1780 | struct fw_ohci *ohci; | |
e364cf4e | 1781 | u32 bus_options, max_receive, link_speed; |
ed568912 KH |
1782 | u64 guid; |
1783 | int error_code; | |
1784 | size_t size; | |
1785 | ||
1786 | ohci = kzalloc(sizeof *ohci, GFP_KERNEL); | |
1787 | if (ohci == NULL) { | |
1788 | fw_error("Could not malloc fw_ohci data.\n"); | |
1789 | return -ENOMEM; | |
1790 | } | |
1791 | ||
1792 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1793 | ||
1794 | if (pci_enable_device(dev)) { | |
1795 | fw_error("Failed to enable OHCI hardware.\n"); | |
1796 | return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV); | |
1797 | } | |
1798 | ||
1799 | pci_set_master(dev); | |
1800 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1801 | pci_set_drvdata(dev, ohci); | |
1802 | ||
1803 | spin_lock_init(&ohci->lock); | |
1804 | ||
1805 | tasklet_init(&ohci->bus_reset_tasklet, | |
1806 | bus_reset_tasklet, (unsigned long)ohci); | |
1807 | ||
1808 | if (pci_request_region(dev, 0, ohci_driver_name)) { | |
1809 | fw_error("MMIO resource unavailable\n"); | |
1810 | return cleanup(ohci, CLEANUP_DISABLE, -EBUSY); | |
1811 | } | |
1812 | ||
1813 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1814 | if (ohci->registers == NULL) { | |
1815 | fw_error("Failed to remap registers\n"); | |
1816 | return cleanup(ohci, CLEANUP_IOMEM, -ENXIO); | |
1817 | } | |
1818 | ||
1819 | if (software_reset(ohci)) { | |
1820 | fw_error("Failed to reset ohci card.\n"); | |
1821 | return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); | |
1822 | } | |
1823 | ||
1824 | /* Now enable LPS, which we need in order to start accessing | |
1825 | * most of the registers. In fact, on some cards (ALI M5251), | |
1826 | * accessing registers in the SClk domain without LPS enabled | |
1827 | * will lock up the machine. Wait 50msec to make sure we have | |
1828 | * full link enabled. */ | |
1829 | reg_write(ohci, OHCI1394_HCControlSet, | |
1830 | OHCI1394_HCControl_LPS | | |
1831 | OHCI1394_HCControl_postedWriteEnable); | |
1832 | flush_writes(ohci); | |
1833 | msleep(50); | |
1834 | ||
1835 | reg_write(ohci, OHCI1394_HCControlClear, | |
1836 | OHCI1394_HCControl_noByteSwapData); | |
1837 | ||
1838 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1839 | OHCI1394_LinkControl_rcvSelfID | | |
1840 | OHCI1394_LinkControl_cycleTimerEnable | | |
1841 | OHCI1394_LinkControl_cycleMaster); | |
1842 | ||
1843 | ar_context_init(&ohci->ar_request_ctx, ohci, | |
1844 | OHCI1394_AsReqRcvContextControlSet); | |
1845 | ||
1846 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1847 | OHCI1394_AsRspRcvContextControlSet); | |
1848 | ||
1849 | at_context_init(&ohci->at_request_ctx, ohci, | |
1850 | OHCI1394_AsReqTrContextControlSet); | |
1851 | ||
1852 | at_context_init(&ohci->at_response_ctx, ohci, | |
1853 | OHCI1394_AsRspTrContextControlSet); | |
1854 | ||
1855 | reg_write(ohci, OHCI1394_ATRetries, | |
1856 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1857 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1858 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1859 | ||
1860 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); | |
1861 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1862 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1863 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1864 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1865 | ||
1866 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1867 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1868 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1869 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1870 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1871 | ||
1872 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1873 | fw_error("Out of memory for it/ir contexts.\n"); | |
1874 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1875 | } | |
1876 | ||
1877 | /* self-id dma buffer allocation */ | |
1878 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1879 | SELF_ID_BUF_SIZE, | |
1880 | &ohci->self_id_bus, | |
1881 | GFP_KERNEL); | |
1882 | if (ohci->self_id_cpu == NULL) { | |
1883 | fw_error("Out of memory for self ID buffer.\n"); | |
1884 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1885 | } | |
1886 | ||
1887 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1888 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1889 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1890 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1891 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1892 | OHCI1394_selfIDComplete | | |
1893 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1894 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1895 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1896 | OHCI1394_masterIntEnable); | |
1897 | ||
1898 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
1899 | max_receive = (bus_options >> 12) & 0xf; | |
1900 | link_speed = bus_options & 0x7; | |
1901 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1902 | reg_read(ohci, OHCI1394_GUIDLo); | |
1903 | ||
1904 | error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid); | |
1905 | if (error_code < 0) | |
1906 | return cleanup(ohci, CLEANUP_SELF_ID, error_code); | |
1907 | ||
e364cf4e | 1908 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 1909 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 1910 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 KH |
1911 | |
1912 | return 0; | |
1913 | } | |
1914 | ||
1915 | static void pci_remove(struct pci_dev *dev) | |
1916 | { | |
1917 | struct fw_ohci *ohci; | |
1918 | ||
1919 | ohci = pci_get_drvdata(dev); | |
1920 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable); | |
1921 | fw_core_remove_card(&ohci->card); | |
1922 | ||
1923 | /* FIXME: Fail all pending packets here, now that the upper | |
1924 | * layers can't queue any more. */ | |
1925 | ||
1926 | software_reset(ohci); | |
1927 | free_irq(dev->irq, ohci); | |
1928 | cleanup(ohci, CLEANUP_SELF_ID, 0); | |
1929 | ||
1930 | fw_notify("Removed fw-ohci device.\n"); | |
1931 | } | |
1932 | ||
1933 | static struct pci_device_id pci_table[] = { | |
1934 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1935 | { } | |
1936 | }; | |
1937 | ||
1938 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1939 | ||
1940 | static struct pci_driver fw_ohci_pci_driver = { | |
1941 | .name = ohci_driver_name, | |
1942 | .id_table = pci_table, | |
1943 | .probe = pci_probe, | |
1944 | .remove = pci_remove, | |
1945 | }; | |
1946 | ||
1947 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1948 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1949 | MODULE_LICENSE("GPL"); | |
1950 | ||
1951 | static int __init fw_ohci_init(void) | |
1952 | { | |
1953 | return pci_register_driver(&fw_ohci_pci_driver); | |
1954 | } | |
1955 | ||
1956 | static void __exit fw_ohci_cleanup(void) | |
1957 | { | |
1958 | pci_unregister_driver(&fw_ohci_pci_driver); | |
1959 | } | |
1960 | ||
1961 | module_init(fw_ohci_init); | |
1962 | module_exit(fw_ohci_cleanup); |