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f212ec4b BK |
1 | /* |
2 | * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers | |
3 | * | |
4 | * Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de> | |
5 | * | |
6 | * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c | |
7 | * this file has functions to: | |
8 | * - scan the PCI very early on boot for all OHCI 1394-compliant controllers | |
9 | * - reset and initialize them and make them join the IEEE1394 bus and | |
10 | * - enable physical DMA on them to allow remote debugging | |
11 | * | |
12 | * All code and data is marked as __init and __initdata, respective as | |
13 | * during boot, all OHCI1394 controllers may be claimed by the firewire | |
14 | * stack and at this point, this code should not touch them anymore. | |
15 | * | |
16 | * To use physical DMA after the initialization of the firewire stack, | |
17 | * be sure that the stack enables it and (re-)attach after the bus reset | |
18 | * which may be caused by the firewire stack initialization. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software Foundation, | |
32 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
33 | */ | |
34 | ||
f212ec4b | 35 | #include <linux/delay.h> |
1ef5b816 SR |
36 | #include <linux/io.h> |
37 | #include <linux/kernel.h> | |
f212ec4b | 38 | #include <linux/pci.h> /* for PCI defines */ |
1ef5b816 SR |
39 | #include <linux/string.h> |
40 | ||
f212ec4b BK |
41 | #include <asm/pci-direct.h> /* for direct PCI config space access */ |
42 | #include <asm/fixmap.h> | |
43 | ||
1ef5b816 SR |
44 | #include <linux/init_ohci1394_dma.h> |
45 | #include "ohci.h" | |
f212ec4b BK |
46 | |
47 | int __initdata init_ohci1394_dma_early; | |
48 | ||
1ef5b816 SR |
49 | struct ohci { |
50 | void __iomem *registers; | |
51 | }; | |
52 | ||
53 | static inline void reg_write(const struct ohci *ohci, int offset, u32 data) | |
54 | { | |
55 | writel(data, ohci->registers + offset); | |
56 | } | |
57 | ||
58 | static inline u32 reg_read(const struct ohci *ohci, int offset) | |
59 | { | |
60 | return readl(ohci->registers + offset); | |
61 | } | |
62 | ||
63 | #define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */ | |
64 | ||
f212ec4b | 65 | /* Reads a PHY register of an OHCI-1394 controller */ |
1ef5b816 | 66 | static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr) |
f212ec4b BK |
67 | { |
68 | int i; | |
1ef5b816 | 69 | u32 r; |
f212ec4b BK |
70 | |
71 | reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); | |
72 | ||
73 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
74 | if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000) | |
75 | break; | |
76 | mdelay(1); | |
77 | } | |
78 | r = reg_read(ohci, OHCI1394_PhyControl); | |
79 | ||
80 | return (r & 0x00ff0000) >> 16; | |
81 | } | |
82 | ||
83 | /* Writes to a PHY register of an OHCI-1394 controller */ | |
1ef5b816 | 84 | static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data) |
f212ec4b BK |
85 | { |
86 | int i; | |
87 | ||
88 | reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); | |
89 | ||
90 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1ef5b816 | 91 | if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000)) |
f212ec4b BK |
92 | break; |
93 | mdelay(1); | |
94 | } | |
95 | } | |
96 | ||
97 | /* Resets an OHCI-1394 controller (for sane state before initialization) */ | |
1ef5b816 SR |
98 | static inline void __init init_ohci1394_soft_reset(struct ohci *ohci) |
99 | { | |
f212ec4b BK |
100 | int i; |
101 | ||
102 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
103 | ||
104 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
105 | if (!(reg_read(ohci, OHCI1394_HCControlSet) | |
106 | & OHCI1394_HCControl_softReset)) | |
107 | break; | |
108 | mdelay(1); | |
109 | } | |
110 | } | |
111 | ||
1ef5b816 SR |
112 | #define OHCI1394_MAX_AT_REQ_RETRIES 0xf |
113 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
114 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
115 | ||
f212ec4b | 116 | /* Basic OHCI-1394 register and port inititalization */ |
1ef5b816 | 117 | static inline void __init init_ohci1394_initialize(struct ohci *ohci) |
f212ec4b | 118 | { |
1ef5b816 | 119 | u32 bus_options; |
f212ec4b BK |
120 | int num_ports, i; |
121 | ||
122 | /* Put some defaults to these undefined bus options */ | |
123 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
124 | bus_options |= 0x60000000; /* Enable CMC and ISC */ | |
125 | bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */ | |
126 | bus_options &= ~0x18000000; /* Disable PMC and BMC */ | |
127 | reg_write(ohci, OHCI1394_BusOptions, bus_options); | |
128 | ||
129 | /* Set the bus number */ | |
130 | reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); | |
131 | ||
132 | /* Enable posted writes */ | |
133 | reg_write(ohci, OHCI1394_HCControlSet, | |
134 | OHCI1394_HCControl_postedWriteEnable); | |
135 | ||
136 | /* Clear link control register */ | |
137 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); | |
138 | ||
139 | /* enable phys */ | |
140 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1ef5b816 | 141 | OHCI1394_LinkControl_rcvPhyPkt); |
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142 | |
143 | /* Don't accept phy packets into AR request context */ | |
144 | reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); | |
145 | ||
146 | /* Clear the Isochonouys interrupt masks */ | |
147 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); | |
148 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); | |
149 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); | |
150 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); | |
151 | ||
b3834be5 | 152 | /* Accept asynchronous transfer requests from all nodes for now */ |
1ef5b816 | 153 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); |
f212ec4b | 154 | |
b3834be5 | 155 | /* Specify asynchronous transfer retries */ |
f212ec4b BK |
156 | reg_write(ohci, OHCI1394_ATRetries, |
157 | OHCI1394_MAX_AT_REQ_RETRIES | | |
158 | (OHCI1394_MAX_AT_RESP_RETRIES<<4) | | |
159 | (OHCI1394_MAX_PHYS_RESP_RETRIES<<8)); | |
160 | ||
161 | /* We don't want hardware swapping */ | |
1ef5b816 SR |
162 | reg_write(ohci, OHCI1394_HCControlClear, |
163 | OHCI1394_HCControl_noByteSwapData); | |
f212ec4b BK |
164 | |
165 | /* Enable link */ | |
166 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable); | |
167 | ||
168 | /* If anything is connected to a port, make sure it is enabled */ | |
169 | num_ports = get_phy_reg(ohci, 2) & 0xf; | |
170 | for (i = 0; i < num_ports; i++) { | |
171 | unsigned int status; | |
172 | ||
173 | set_phy_reg(ohci, 7, i); | |
174 | status = get_phy_reg(ohci, 8); | |
175 | ||
176 | if (status & 0x20) | |
177 | set_phy_reg(ohci, 8, status & ~1); | |
178 | } | |
179 | } | |
180 | ||
181 | /** | |
182 | * init_ohci1394_wait_for_busresets - wait until bus resets are completed | |
183 | * | |
184 | * OHCI1394 initialization itself and any device going on- or offline | |
185 | * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec | |
186 | * specifies that physical DMA is disabled on each bus reset and it | |
187 | * has to be enabled after each bus reset when needed. We resort | |
188 | * to polling here because on early boot, we have no interrupts. | |
189 | */ | |
1ef5b816 | 190 | static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci) |
f212ec4b BK |
191 | { |
192 | int i, events; | |
193 | ||
1ef5b816 | 194 | for (i = 0; i < 9; i++) { |
f212ec4b BK |
195 | mdelay(200); |
196 | events = reg_read(ohci, OHCI1394_IntEventSet); | |
197 | if (events & OHCI1394_busReset) | |
198 | reg_write(ohci, OHCI1394_IntEventClear, | |
199 | OHCI1394_busReset); | |
200 | } | |
201 | } | |
202 | ||
203 | /** | |
204 | * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging | |
205 | * This enables remote DMA access over IEEE1394 from every host for the low | |
206 | * 4GB of address space. DMA accesses above 4GB are not available currently. | |
207 | */ | |
1ef5b816 | 208 | static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci) |
f212ec4b | 209 | { |
1ef5b816 SR |
210 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 0xffffffff); |
211 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 0xffffffff); | |
212 | reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000); | |
f212ec4b BK |
213 | } |
214 | ||
215 | /** | |
216 | * init_ohci1394_reset_and_init_dma - init controller and enable DMA | |
217 | * This initializes the given controller and enables physical DMA engine in it. | |
218 | */ | |
1ef5b816 | 219 | static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci) |
f212ec4b BK |
220 | { |
221 | /* Start off with a soft reset, clears everything to a sane state. */ | |
222 | init_ohci1394_soft_reset(ohci); | |
223 | ||
224 | /* Accessing some registers without LPS enabled may cause lock up */ | |
225 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); | |
226 | ||
227 | /* Disable and clear interrupts */ | |
228 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | |
229 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | |
230 | ||
231 | mdelay(50); /* Wait 50msec to make sure we have full link enabled */ | |
232 | ||
233 | init_ohci1394_initialize(ohci); | |
234 | /* | |
235 | * The initialization causes at least one IEEE1394 bus reset. Enabling | |
236 | * physical DMA only works *after* *all* bus resets have calmed down: | |
237 | */ | |
238 | init_ohci1394_wait_for_busresets(ohci); | |
239 | ||
240 | /* We had to wait and do this now if we want to debug early problems */ | |
241 | init_ohci1394_enable_physical_dma(ohci); | |
242 | } | |
243 | ||
244 | /** | |
245 | * init_ohci1394_controller - Map the registers of the controller and init DMA | |
246 | * This maps the registers of the specified controller and initializes it | |
247 | */ | |
248 | static inline void __init init_ohci1394_controller(int num, int slot, int func) | |
249 | { | |
250 | unsigned long ohci_base; | |
1ef5b816 | 251 | struct ohci ohci; |
f212ec4b BK |
252 | |
253 | printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394" | |
254 | " at %02x:%02x.%x\n", num, slot, func); | |
255 | ||
256 | ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2)) | |
257 | & PCI_BASE_ADDRESS_MEM_MASK; | |
258 | ||
259 | set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base); | |
260 | ||
1ef5b816 | 261 | ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE); |
f212ec4b BK |
262 | |
263 | init_ohci1394_reset_and_init_dma(&ohci); | |
264 | } | |
265 | ||
266 | /** | |
267 | * debug_init_ohci1394_dma - scan for OHCI1394 controllers and init DMA on them | |
268 | * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them | |
269 | */ | |
270 | void __init init_ohci1394_dma_on_all_controllers(void) | |
271 | { | |
272 | int num, slot, func; | |
1ef5b816 | 273 | u32 class; |
f212ec4b BK |
274 | |
275 | if (!early_pci_allowed()) | |
276 | return; | |
277 | ||
278 | /* Poor man's PCI discovery, the only thing we can do at early boot */ | |
279 | for (num = 0; num < 32; num++) { | |
280 | for (slot = 0; slot < 32; slot++) { | |
281 | for (func = 0; func < 8; func++) { | |
1ef5b816 | 282 | class = read_pci_config(num, slot, func, |
f212ec4b | 283 | PCI_CLASS_REVISION); |
1ef5b816 | 284 | if (class == 0xffffffff) |
f212ec4b BK |
285 | continue; /* No device at this func */ |
286 | ||
287 | if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI) | |
288 | continue; /* Not an OHCI-1394 device */ | |
289 | ||
290 | init_ohci1394_controller(num, slot, func); | |
291 | break; /* Assume one controller per device */ | |
292 | } | |
293 | } | |
294 | } | |
295 | printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n"); | |
296 | } | |
297 | ||
298 | /** | |
299 | * setup_init_ohci1394_early - enables early OHCI1394 DMA initialization | |
300 | */ | |
301 | static int __init setup_ohci1394_dma(char *opt) | |
302 | { | |
303 | if (!strcmp(opt, "early")) | |
304 | init_ohci1394_dma_early = 1; | |
305 | return 0; | |
306 | } | |
307 | ||
308 | /* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */ | |
309 | early_param("ohci1394_dma", setup_ohci1394_dma); |