projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
firewire: ohci: fix PHY reg access after card ejection
[deliverable/linux.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
cf3e72fd 45
e8ca9702 46#include <asm/byteorder.h>
c26f0234 47#include <asm/page.h>
ee71c2f9 48#include <asm/system.h>
ed568912 49
ea8d006b
SR		 50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
77c9a5da
SR		 54#include "core.h"
55#include "ohci.h"
ed568912 56
a77754a7
KH		 57#define DESCRIPTOR_OUTPUT_MORE 0
58#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59#define DESCRIPTOR_INPUT_MORE (2 << 12)
60#define DESCRIPTOR_INPUT_LAST (3 << 12)
61#define DESCRIPTOR_STATUS (1 << 11)
62#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63#define DESCRIPTOR_PING (1 << 7)
64#define DESCRIPTOR_YY (1 << 6)
65#define DESCRIPTOR_NO_IRQ (0 << 4)
66#define DESCRIPTOR_IRQ_ERROR (1 << 4)
67#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 70
71struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78} __attribute__((aligned(16)));
79
a77754a7
KH		 80#define CONTROL_SET(regs) (regs)
81#define CONTROL_CLEAR(regs) ((regs) + 4)
82#define COMMAND_PTR(regs) ((regs) + 12)
83#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 84
7a39d8b8
CL		 85#define AR_BUFFER_SIZE (32*1024)
86#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87/* we need at least two pages for proper list management */
88#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90#define MAX_ASYNC_PAYLOAD 4096
91#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 93
32b46093
KH		 94struct ar_context {
95 struct fw_ohci *ohci;
7a39d8b8
CL		 96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
32b46093 100 void *pointer;
7a39d8b8 101 unsigned int last_buffer_index;
72e318e0 102 u32 regs;
ed568912
KH		 103 struct tasklet_struct tasklet;
104};
105
30200739
KH		 106struct context;
107
108typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
fe5ca634
DM		 111
112/*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122};
123
30200739 124struct context {
373b2edd 125 struct fw_ohci *ohci;
30200739 126 u32 regs;
fe5ca634 127 int total_allocation;
386a4153 128 bool running;
82b662dc 129 bool flushing;
373b2edd 130
fe5ca634
DM		 131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
30200739
KH		 155
156 descriptor_callback_t callback;
157
373b2edd 158 struct tasklet_struct tasklet;
30200739 159};
30200739 160
a77754a7
KH		 161#define IT_HEADER_SY(v) ((v) << 0)
162#define IT_HEADER_TCODE(v) ((v) << 4)
163#define IT_HEADER_CHANNEL(v) ((v) << 8)
164#define IT_HEADER_TAG(v) ((v) << 14)
165#define IT_HEADER_SPEED(v) ((v) << 16)
166#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 167
168struct iso_context {
169 struct fw_iso_context base;
30200739 170 struct context context;
0642b657 171 int excess_bytes;
9b32d5f3
KH		 172 void *header;
173 size_t header_length;
dd23736e
ML		 174
175 u8 sync;
176 u8 tags;
ed568912
KH		 177};
178
179#define CONFIG_ROM_SIZE 1024
180
181struct fw_ohci {
182 struct fw_card card;
183
184 __iomem char *registers;
e636fe25 185 int node_id;
ed568912 186 int generation;
e09770db 187 int request_generation; /* for timestamping incoming requests */
4a635593 188 unsigned quirks;
a1a1132b 189 unsigned int pri_req_max;
a48777e0 190 u32 bus_time;
4ffb7a6a 191 bool is_root;
c8a94ded 192 bool csr_state_setclear_abdicate;
dd23736e
ML		 193 int n_ir;
194 int n_it;
c781c06d
KH		 195 /*
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
198 */
ed568912 199 spinlock_t lock;
ed568912 200
02d37bed
SR		 201 struct mutex phy_reg_mutex;
202
ec766a79
CL		 203 void *misc_buffer;
204 dma_addr_t misc_buffer_bus;
205
ed568912
KH		 206 struct ar_context ar_request_ctx;
207 struct ar_context ar_response_ctx;
f319b6a0
KH		 208 struct context at_request_ctx;
209 struct context at_response_ctx;
ed568912 210
f117a3e3 211 u32 it_context_support;
872e330e 212 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 213 struct iso_context *it_context_list;
872e330e 214 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 215 u32 ir_context_support;
872e330e 216 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 217 struct iso_context *ir_context_list;
872e330e
SR		 218 u64 mc_channels; /* channels in use by the multichannel IR context */
219 bool mc_allocated;
ecb1cf9c
SR		 220
221 __be32 *config_rom;
222 dma_addr_t config_rom_bus;
223 __be32 *next_config_rom;
224 dma_addr_t next_config_rom_bus;
225 __be32 next_header;
226
227 __le32 *self_id_cpu;
228 dma_addr_t self_id_bus;
229 struct tasklet_struct bus_reset_tasklet;
230
231 u32 self_id_buffer[512];
ed568912
KH		 232};
233
95688e97 234static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 235{
236 return container_of(card, struct fw_ohci, card);
237}
238
295e3feb
KH		 239#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
240#define IR_CONTEXT_BUFFER_FILL 0x80000000
241#define IR_CONTEXT_ISOCH_HEADER 0x40000000
242#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
243#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
244#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 245
246#define CONTEXT_RUN 0x8000
247#define CONTEXT_WAKE 0x1000
248#define CONTEXT_DEAD 0x0800
249#define CONTEXT_ACTIVE 0x0400
250
8b7b6afa 251#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 252#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
253#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
254
ed568912
KH		 255#define OHCI1394_REGISTER_SIZE 0x800
256#define OHCI_LOOP_COUNT 500
257#define OHCI1394_PCI_HCI_Control 0x40
258#define SELF_ID_BUF_SIZE 0x800
32b46093 259#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 260#define OHCI_VERSION_1_1 0x010010
0edeefd9 261
ed568912
KH		 262static char ohci_driver_name[] = KBUILD_MODNAME;
263
9993e0fe 264#define PCI_DEVICE_ID_AGERE_FW643 0x5901
262444ee 265#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b
CL		 266#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
267
4a635593
SR		 268#define QUIRK_CYCLE_TIMER 1
269#define QUIRK_RESET_PACKET 2
270#define QUIRK_BE_HEADERS 4
925e7a65 271#define QUIRK_NO_1394A 8
262444ee 272#define QUIRK_NO_MSI 16
4a635593
SR		 273
274/* In case of multiple matches in ohci_quirks[], only the first one is used. */
275static const struct {
9993e0fe 276 unsigned short vendor, device, revision, flags;
4a635593 277} ohci_quirks[] = {
9993e0fe
SR		 278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
279 QUIRK_CYCLE_TIMER},
280
281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
282 QUIRK_BE_HEADERS},
283
284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
285 QUIRK_NO_MSI},
286
287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
288 QUIRK_NO_MSI},
289
290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
291 QUIRK_CYCLE_TIMER},
292
293 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
294 QUIRK_CYCLE_TIMER},
295
296 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
297 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
298
299 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_RESET_PACKET},
301
302 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
303 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 304};
305
3e9cc2f3
SR		 306/* This overrides anything that was found in ohci_quirks[]. */
307static int param_quirks;
308module_param_named(quirks, param_quirks, int, 0644);
309MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
310 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
311 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
312 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 313 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 314 ", disable MSI = " __stringify(QUIRK_NO_MSI)
3e9cc2f3
SR		 315 ")");
316
a007bb85 317#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 318#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 319#define OHCI_PARAM_DEBUG_IRQS 4
320#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8 321
5da3dac8
SR		 322#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
323
ad3c0fe8
SR		 324static int param_debug;
325module_param_named(debug, param_debug, int, 0644);
326MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 327 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 328 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
329 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
330 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 331 ", or a combination, or all = -1)");
332
333static void log_irqs(u32 evt)
334{
a007bb85
SR		 335 if (likely(!(param_debug &
336 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
337 return;
338
339 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
340 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 341 return;
342
f117a3e3 343 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 344 evt & OHCI1394_selfIDComplete ? " selfID" : "",
345 evt & OHCI1394_RQPkt ? " AR_req" : "",
346 evt & OHCI1394_RSPkt ? " AR_resp" : "",
347 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
348 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
349 evt & OHCI1394_isochRx ? " IR" : "",
350 evt & OHCI1394_isochTx ? " IT" : "",
351 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
352 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 353 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 354 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 355 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 356 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 357 evt & OHCI1394_busReset ? " busReset" : "",
358 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
359 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
360 OHCI1394_respTxComplete | OHCI1394_isochRx |
361 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 362 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
363 OHCI1394_cycleInconsistent |
161b96e7 364 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 365 ? " ?" : "");
366}
367
368static const char *speed[] = {
369 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
370};
371static const char *power[] = {
372 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
373 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
374};
375static const char port[] = { '.', '-', 'p', 'c', };
376
377static char _p(u32 *s, int shift)
378{
379 return port[*s >> shift & 3];
380}
381
08ddb2f4 382static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
ad3c0fe8
SR		 383{
384 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
385 return;
386
161b96e7
SR		 387 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
388 self_id_count, generation, node_id);
ad3c0fe8
SR		 389
390 for (; self_id_count--; ++s)
391 if ((*s & 1 << 23) == 0)
161b96e7
SR		 392 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
393 "%s gc=%d %s %s%s%s\n",
394 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
395 speed[*s >> 14 & 3], *s >> 16 & 63,
396 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
397 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 398 else
161b96e7
SR		 399 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
400 *s, *s >> 24 & 63,
401 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
402 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 403}
404
405static const char *evts[] = {
406 [0x00] = "evt_no_status", [0x01] = "-reserved-",
407 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
408 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
409 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
410 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
411 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
412 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
413 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
414 [0x10] = "-reserved-", [0x11] = "ack_complete",
415 [0x12] = "ack_pending ", [0x13] = "-reserved-",
416 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
417 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
418 [0x18] = "-reserved-", [0x19] = "-reserved-",
419 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
420 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
421 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
422 [0x20] = "pending/cancelled",
423};
424static const char *tcodes[] = {
425 [0x0] = "QW req", [0x1] = "BW req",
426 [0x2] = "W resp", [0x3] = "-reserved-",
427 [0x4] = "QR req", [0x5] = "BR req",
428 [0x6] = "QR resp", [0x7] = "BR resp",
429 [0x8] = "cycle start", [0x9] = "Lk req",
430 [0xa] = "async stream packet", [0xb] = "Lk resp",
431 [0xc] = "-reserved-", [0xd] = "-reserved-",
432 [0xe] = "link internal", [0xf] = "-reserved-",
433};
ad3c0fe8
SR		 434
435static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
436{
437 int tcode = header[0] >> 4 & 0xf;
438 char specific[12];
439
440 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
441 return;
442
443 if (unlikely(evt >= ARRAY_SIZE(evts)))
444 evt = 0x1f;
445
08ddb2f4 446 if (evt == OHCI1394_evt_bus_reset) {
161b96e7
SR		 447 fw_notify("A%c evt_bus_reset, generation %d\n",
448 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 449 return;
450 }
451
ad3c0fe8
SR		 452 switch (tcode) {
453 case 0x0: case 0x6: case 0x8:
454 snprintf(specific, sizeof(specific), " = %08x",
455 be32_to_cpu((__force __be32)header[3]));
456 break;
457 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
458 snprintf(specific, sizeof(specific), " %x,%x",
459 header[3] >> 16, header[3] & 0xffff);
460 break;
461 default:
462 specific[0] = '\0';
463 }
464
465 switch (tcode) {
5b06db16 466 case 0xa:
161b96e7 467 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
ad3c0fe8 468 break;
5b06db16
CL		 469 case 0xe:
470 fw_notify("A%c %s, PHY %08x %08x\n",
471 dir, evts[evt], header[1], header[2]);
472 break;
ad3c0fe8 473 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
161b96e7
SR		 474 fw_notify("A%c spd %x tl %02x, "
475 "%04x -> %04x, %s, "
476 "%s, %04x%08x%s\n",
477 dir, speed, header[0] >> 10 & 0x3f,
478 header[1] >> 16, header[0] >> 16, evts[evt],
479 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 480 break;
481 default:
161b96e7
SR		 482 fw_notify("A%c spd %x tl %02x, "
483 "%04x -> %04x, %s, "
484 "%s%s\n",
485 dir, speed, header[0] >> 10 & 0x3f,
486 header[1] >> 16, header[0] >> 16, evts[evt],
487 tcodes[tcode], specific);
ad3c0fe8
SR		 488 }
489}
490
491#else
492
5da3dac8
SR		 493#define param_debug 0
494static inline void log_irqs(u32 evt) {}
495static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
496static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
ad3c0fe8
SR		 497
498#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
499
95688e97 500static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 501{
502 writel(data, ohci->registers + offset);
503}
504
95688e97 505static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 506{
507 return readl(ohci->registers + offset);
508}
509
95688e97 510static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 511{
512 /* Do a dummy read to flush writes. */
513 reg_read(ohci, OHCI1394_Version);
514}
515
b14c369d
SR		 516/*
517 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
518 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
519 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
520 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
521 */
35d999b1 522static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 523{
4a96b4fc 524 u32 val;
35d999b1 525 int i;
ed568912
KH		 526
527 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 528 for (i = 0; i < 3 + 100; i++) {
35d999b1 529 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 530 if (!~val)
531 return -ENODEV; /* Card was ejected. */
532
35d999b1
SR		 533 if (val & OHCI1394_PhyControl_ReadDone)
534 return OHCI1394_PhyControl_ReadData(val);
535
153e3979
CL		 536 /*
537 * Try a few times without waiting. Sleeping is necessary
538 * only when the link/PHY interface is busy.
539 */
540 if (i >= 3)
541 msleep(1);
ed568912 542 }
35d999b1 543 fw_error("failed to read phy reg\n");
ed568912 544
35d999b1
SR		 545 return -EBUSY;
546}
4a96b4fc 547
35d999b1
SR		 548static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
549{
550 int i;
ed568912 551
ed568912 552 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 553 OHCI1394_PhyControl_Write(addr, val));
153e3979 554 for (i = 0; i < 3 + 100; i++) {
35d999b1 555 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 556 if (!~val)
557 return -ENODEV; /* Card was ejected. */
558
35d999b1
SR		 559 if (!(val & OHCI1394_PhyControl_WritePending))
560 return 0;
ed568912 561
153e3979
CL		 562 if (i >= 3)
563 msleep(1);
35d999b1
SR		 564 }
565 fw_error("failed to write phy reg\n");
566
567 return -EBUSY;
4a96b4fc
CL		 568}
569
02d37bed
SR		 570static int update_phy_reg(struct fw_ohci *ohci, int addr,
571 int clear_bits, int set_bits)
4a96b4fc 572{
02d37bed 573 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 574 if (ret < 0)
575 return ret;
4a96b4fc 576
e7014dad
CL		 577 /*
578 * The interrupt status bits are cleared by writing a one bit.
579 * Avoid clearing them unless explicitly requested in set_bits.
580 */
581 if (addr == 5)
582 clear_bits |= PHY_INT_STATUS_BITS;
583
35d999b1 584 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 585}
586
35d999b1 587static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 588{
35d999b1 589 int ret;
925e7a65 590
02d37bed 591 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 592 if (ret < 0)
593 return ret;
925e7a65 594
35d999b1 595 return read_phy_reg(ohci, addr);
ed568912
KH		 596}
597
02d37bed
SR		 598static int ohci_read_phy_reg(struct fw_card *card, int addr)
599{
600 struct fw_ohci *ohci = fw_ohci(card);
601 int ret;
602
603 mutex_lock(&ohci->phy_reg_mutex);
604 ret = read_phy_reg(ohci, addr);
605 mutex_unlock(&ohci->phy_reg_mutex);
606
607 return ret;
608}
609
610static int ohci_update_phy_reg(struct fw_card *card, int addr,
611 int clear_bits, int set_bits)
612{
613 struct fw_ohci *ohci = fw_ohci(card);
614 int ret;
615
616 mutex_lock(&ohci->phy_reg_mutex);
617 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
618 mutex_unlock(&ohci->phy_reg_mutex);
619
620 return ret;
ed568912
KH		 621}
622
7a39d8b8
CL		 623static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
624{
625 return page_private(ctx->pages[i]);
626}
627
628static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 629{
7a39d8b8 630 struct descriptor *d;
32b46093 631
7a39d8b8
CL		 632 d = &ctx->descriptors[index];
633 d->branch_address &= cpu_to_le32(~0xf);
634 d->res_count = cpu_to_le16(PAGE_SIZE);
635 d->transfer_status = 0;
32b46093 636
071595eb 637 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 638 d = &ctx->descriptors[ctx->last_buffer_index];
639 d->branch_address |= cpu_to_le32(1);
640
641 ctx->last_buffer_index = index;
32b46093 642
a77754a7 643 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
837596a6
CL		 644}
645
7a39d8b8 646static void ar_context_release(struct ar_context *ctx)
837596a6 647{
7a39d8b8 648 unsigned int i;
837596a6 649
7a39d8b8
CL		 650 if (ctx->buffer)
651 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 652
7a39d8b8
CL		 653 for (i = 0; i < AR_BUFFERS; i++)
654 if (ctx->pages[i]) {
655 dma_unmap_page(ctx->ohci->card.device,
656 ar_buffer_bus(ctx, i),
657 PAGE_SIZE, DMA_FROM_DEVICE);
658 __free_page(ctx->pages[i]);
659 }
ed568912
KH		 660}
661
7a39d8b8 662static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 663{
7a39d8b8
CL		 664 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
665 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
666 flush_writes(ctx->ohci);
a55709ba 667
7a39d8b8 668 fw_error("AR error: %s; DMA stopped\n", error_msg);
a55709ba 669 }
7a39d8b8
CL		 670 /* FIXME: restart? */
671}
672
673static inline unsigned int ar_next_buffer_index(unsigned int index)
674{
675 return (index + 1) % AR_BUFFERS;
676}
677
678static inline unsigned int ar_prev_buffer_index(unsigned int index)
679{
680 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
681}
682
683static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
684{
685 return ar_next_buffer_index(ctx->last_buffer_index);
686}
687
688/*
689 * We search for the buffer that contains the last AR packet DMA data written
690 * by the controller.
691 */
692static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
693 unsigned int *buffer_offset)
694{
695 unsigned int i, next_i, last = ctx->last_buffer_index;
696 __le16 res_count, next_res_count;
697
698 i = ar_first_buffer_index(ctx);
699 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
700
701 /* A buffer that is not yet completely filled must be the last one. */
702 while (i != last && res_count == 0) {
703
704 /* Peek at the next descriptor. */
705 next_i = ar_next_buffer_index(i);
706 rmb(); /* read descriptors in order */
707 next_res_count = ACCESS_ONCE(
708 ctx->descriptors[next_i].res_count);
709 /*
710 * If the next descriptor is still empty, we must stop at this
711 * descriptor.
712 */
713 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
714 /*
715 * The exception is when the DMA data for one packet is
716 * split over three buffers; in this case, the middle
717 * buffer's descriptor might be never updated by the
718 * controller and look still empty, and we have to peek
719 * at the third one.
720 */
721 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
722 next_i = ar_next_buffer_index(next_i);
723 rmb();
724 next_res_count = ACCESS_ONCE(
725 ctx->descriptors[next_i].res_count);
726 if (next_res_count != cpu_to_le16(PAGE_SIZE))
727 goto next_buffer_is_active;
728 }
729
730 break;
731 }
732
733next_buffer_is_active:
734 i = next_i;
735 res_count = next_res_count;
736 }
737
738 rmb(); /* read res_count before the DMA data */
739
740 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
741 if (*buffer_offset > PAGE_SIZE) {
742 *buffer_offset = 0;
743 ar_context_abort(ctx, "corrupted descriptor");
744 }
745
746 return i;
747}
748
749static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
750 unsigned int end_buffer_index,
751 unsigned int end_buffer_offset)
752{
753 unsigned int i;
754
755 i = ar_first_buffer_index(ctx);
756 while (i != end_buffer_index) {
757 dma_sync_single_for_cpu(ctx->ohci->card.device,
758 ar_buffer_bus(ctx, i),
759 PAGE_SIZE, DMA_FROM_DEVICE);
760 i = ar_next_buffer_index(i);
761 }
762 if (end_buffer_offset > 0)
763 dma_sync_single_for_cpu(ctx->ohci->card.device,
764 ar_buffer_bus(ctx, i),
765 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 766}
767
11bf20ad
SR		 768#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
769#define cond_le32_to_cpu(v) \
4a635593 770 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 771#else
772#define cond_le32_to_cpu(v) le32_to_cpu(v)
773#endif
774
32b46093 775static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 776{
ed568912 777 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 778 struct fw_packet p;
779 u32 status, length, tcode;
43286568 780 int evt;
2639a6fb 781
11bf20ad
SR		 782 p.header[0] = cond_le32_to_cpu(buffer[0]);
783 p.header[1] = cond_le32_to_cpu(buffer[1]);
784 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 785
786 tcode = (p.header[0] >> 4) & 0x0f;
787 switch (tcode) {
788 case TCODE_WRITE_QUADLET_REQUEST:
789 case TCODE_READ_QUADLET_RESPONSE:
32b46093 790 p.header[3] = (__force __u32) buffer[3];
2639a6fb 791 p.header_length = 16;
32b46093 792 p.payload_length = 0;
2639a6fb
KH		 793 break;
794
2639a6fb 795 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 796 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 797 p.header_length = 16;
798 p.payload_length = 0;
799 break;
800
801 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 802 case TCODE_READ_BLOCK_RESPONSE:
803 case TCODE_LOCK_REQUEST:
804 case TCODE_LOCK_RESPONSE:
11bf20ad 805 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 806 p.header_length = 16;
32b46093 807 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 808 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
809 ar_context_abort(ctx, "invalid packet length");
810 return NULL;
811 }
2639a6fb
KH		 812 break;
813
814 case TCODE_WRITE_RESPONSE:
815 case TCODE_READ_QUADLET_REQUEST:
32b46093 816 case OHCI_TCODE_PHY_PACKET:
2639a6fb 817 p.header_length = 12;
32b46093 818 p.payload_length = 0;
2639a6fb 819 break;
ccff9629
SR		 820
821 default:
7a39d8b8
CL		 822 ar_context_abort(ctx, "invalid tcode");
823 return NULL;
2639a6fb 824 }
ed568912 825
32b46093
KH		 826 p.payload = (void *) buffer + p.header_length;
827
828 /* FIXME: What to do about evt_* errors? */
829 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 830 status = cond_le32_to_cpu(buffer[length]);
43286568 831 evt = (status >> 16) & 0x1f;
32b46093 832
43286568 833 p.ack = evt - 16;
32b46093
KH		 834 p.speed = (status >> 21) & 0x7;
835 p.timestamp = status & 0xffff;
836 p.generation = ohci->request_generation;
ed568912 837
43286568 838 log_ar_at_event('R', p.speed, p.header, evt);
ad3c0fe8 839
c781c06d 840 /*
a4dc090b
SR		 841 * Several controllers, notably from NEC and VIA, forget to
842 * write ack_complete status at PHY packet reception.
843 */
844 if (evt == OHCI1394_evt_no_status &&
845 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
846 p.ack = ACK_COMPLETE;
847
848 /*
849 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 850 * the new generation number when a bus reset happens (see
851 * section 8.4.2.3). This helps us determine when a request
852 * was received and make sure we send the response in the same
853 * generation. We only need this for requests; for responses
854 * we use the unique tlabel for finding the matching
c781c06d 855 * request.
d34316a4
SR		 856 *
857 * Alas some chips sometimes emit bus reset packets with a
858 * wrong generation. We set the correct generation for these
859 * at a slightly incorrect time (in bus_reset_tasklet).
c781c06d 860 */
d34316a4 861 if (evt == OHCI1394_evt_bus_reset) {
4a635593 862 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 863 ohci->request_generation = (p.header[2] >> 16) & 0xff;
864 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 865 fw_core_handle_request(&ohci->card, &p);
d34316a4 866 } else {
2639a6fb 867 fw_core_handle_response(&ohci->card, &p);
d34316a4 868 }
ed568912 869
32b46093
KH		 870 return buffer + length + 1;
871}
ed568912 872
7a39d8b8
CL		 873static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
874{
875 void *next;
876
877 while (p < end) {
878 next = handle_ar_packet(ctx, p);
879 if (!next)
880 return p;
881 p = next;
882 }
883
884 return p;
885}
886
887static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
888{
889 unsigned int i;
890
891 i = ar_first_buffer_index(ctx);
892 while (i != end_buffer) {
893 dma_sync_single_for_device(ctx->ohci->card.device,
894 ar_buffer_bus(ctx, i),
895 PAGE_SIZE, DMA_FROM_DEVICE);
896 ar_context_link_page(ctx, i);
897 i = ar_next_buffer_index(i);
898 }
899}
900
32b46093
KH		 901static void ar_context_tasklet(unsigned long data)
902{
903 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 904 unsigned int end_buffer_index, end_buffer_offset;
905 void *p, *end;
32b46093 906
7a39d8b8
CL		 907 p = ctx->pointer;
908 if (!p)
909 return;
32b46093 910
7a39d8b8
CL		 911 end_buffer_index = ar_search_last_active_buffer(ctx,
912 &end_buffer_offset);
913 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
914 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 915
7a39d8b8 916 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 917 /*
7a39d8b8
CL		 918 * The filled part of the overall buffer wraps around; handle
919 * all packets up to the buffer end here. If the last packet
920 * wraps around, its tail will be visible after the buffer end
921 * because the buffer start pages are mapped there again.
c781c06d 922 */
7a39d8b8
CL		 923 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
924 p = handle_ar_packets(ctx, p, buffer_end);
925 if (p < buffer_end)
926 goto error;
927 /* adjust p to point back into the actual buffer */
928 p -= AR_BUFFERS * PAGE_SIZE;
929 }
32b46093 930
7a39d8b8
CL		 931 p = handle_ar_packets(ctx, p, end);
932 if (p != end) {
933 if (p > end)
934 ar_context_abort(ctx, "inconsistent descriptor");
935 goto error;
936 }
32b46093 937
7a39d8b8
CL		 938 ctx->pointer = p;
939 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 940
7a39d8b8 941 return;
a1f805e5 942
7a39d8b8
CL		 943error:
944 ctx->pointer = NULL;
ed568912
KH		 945}
946
ec766a79
CL		 947static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
948 unsigned int descriptors_offset, u32 regs)
ed568912 949{
7a39d8b8
CL		 950 unsigned int i;
951 dma_addr_t dma_addr;
952 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
953 struct descriptor *d;
ed568912 954
72e318e0
KH		 955 ctx->regs = regs;
956 ctx->ohci = ohci;
ed568912
KH		 957 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
958
7a39d8b8
CL		 959 for (i = 0; i < AR_BUFFERS; i++) {
960 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
961 if (!ctx->pages[i])
962 goto out_of_memory;
963 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
964 0, PAGE_SIZE, DMA_FROM_DEVICE);
965 if (dma_mapping_error(ohci->card.device, dma_addr)) {
966 __free_page(ctx->pages[i]);
967 ctx->pages[i] = NULL;
968 goto out_of_memory;
969 }
970 set_page_private(ctx->pages[i], dma_addr);
971 }
972
973 for (i = 0; i < AR_BUFFERS; i++)
974 pages[i] = ctx->pages[i];
975 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
976 pages[AR_BUFFERS + i] = ctx->pages[i];
977 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
14271304 978 -1, PAGE_KERNEL);
7a39d8b8
CL		 979 if (!ctx->buffer)
980 goto out_of_memory;
981
ec766a79
CL		 982 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
983 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 984
985 for (i = 0; i < AR_BUFFERS; i++) {
986 d = &ctx->descriptors[i];
987 d->req_count = cpu_to_le16(PAGE_SIZE);
988 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
989 DESCRIPTOR_STATUS |
990 DESCRIPTOR_BRANCH_ALWAYS);
991 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
992 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
993 ar_next_buffer_index(i) * sizeof(struct descriptor));
994 }
32b46093 995
2aef469a 996 return 0;
7a39d8b8
CL		 997
998out_of_memory:
999 ar_context_release(ctx);
1000
1001 return -ENOMEM;
2aef469a
KH		 1002}
1003
1004static void ar_context_run(struct ar_context *ctx)
1005{
7a39d8b8
CL		 1006 unsigned int i;
1007
1008 for (i = 0; i < AR_BUFFERS; i++)
1009 ar_context_link_page(ctx, i);
2aef469a 1010
7a39d8b8 1011 ctx->pointer = ctx->buffer;
2aef469a 1012
7a39d8b8 1013 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1014 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
ed568912 1015}
373b2edd 1016
53dca511 1017static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1018{
0ff8fbc6 1019 __le16 branch;
a186b4a6 1020
0ff8fbc6 1021 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1022
1023 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1024 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1025 return d;
1026 else
1027 return d + z - 1;
1028}
1029
30200739
KH		 1030static void context_tasklet(unsigned long data)
1031{
1032 struct context *ctx = (struct context *) data;
30200739
KH		 1033 struct descriptor *d, *last;
1034 u32 address;
1035 int z;
fe5ca634 1036 struct descriptor_buffer *desc;
30200739 1037
fe5ca634
DM		 1038 desc = list_entry(ctx->buffer_list.next,
1039 struct descriptor_buffer, list);
1040 last = ctx->last;
30200739 1041 while (last->branch_address != 0) {
fe5ca634 1042 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1043 address = le32_to_cpu(last->branch_address);
1044 z = address & 0xf;
fe5ca634
DM		 1045 address &= ~0xf;
1046
1047 /* If the branch address points to a buffer outside of the
1048 * current buffer, advance to the next buffer. */
1049 if (address < desc->buffer_bus ||
1050 address >= desc->buffer_bus + desc->used)
1051 desc = list_entry(desc->list.next,
1052 struct descriptor_buffer, list);
1053 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1054 last = find_branch_descriptor(d, z);
30200739
KH		 1055
1056 if (!ctx->callback(ctx, d, last))
1057 break;
1058
fe5ca634
DM		 1059 if (old_desc != desc) {
1060 /* If we've advanced to the next buffer, move the
1061 * previous buffer to the free list. */
1062 unsigned long flags;
1063 old_desc->used = 0;
1064 spin_lock_irqsave(&ctx->ohci->lock, flags);
1065 list_move_tail(&old_desc->list, &ctx->buffer_list);
1066 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1067 }
1068 ctx->last = last;
30200739
KH		 1069 }
1070}
1071
fe5ca634
DM		 1072/*
1073 * Allocate a new buffer and add it to the list of free buffers for this
1074 * context. Must be called with ohci->lock held.
1075 */
53dca511 1076static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1077{
1078 struct descriptor_buffer *desc;
f5101d58 1079 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1080 int offset;
1081
1082 /*
1083 * 16MB of descriptors should be far more than enough for any DMA
1084 * program. This will catch run-away userspace or DoS attacks.
1085 */
1086 if (ctx->total_allocation >= 16*1024*1024)
1087 return -ENOMEM;
1088
1089 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1090 &bus_addr, GFP_ATOMIC);
1091 if (!desc)
1092 return -ENOMEM;
1093
1094 offset = (void *)&desc->buffer - (void *)desc;
1095 desc->buffer_size = PAGE_SIZE - offset;
1096 desc->buffer_bus = bus_addr + offset;
1097 desc->used = 0;
1098
1099 list_add_tail(&desc->list, &ctx->buffer_list);
1100 ctx->total_allocation += PAGE_SIZE;
1101
1102 return 0;
1103}
1104
53dca511
SR		 1105static int context_init(struct context *ctx, struct fw_ohci *ohci,
1106 u32 regs, descriptor_callback_t callback)
30200739
KH		 1107{
1108 ctx->ohci = ohci;
1109 ctx->regs = regs;
fe5ca634
DM		 1110 ctx->total_allocation = 0;
1111
1112 INIT_LIST_HEAD(&ctx->buffer_list);
1113 if (context_add_buffer(ctx) < 0)
30200739
KH		 1114 return -ENOMEM;
1115
fe5ca634
DM		 1116 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1117 struct descriptor_buffer, list);
1118
30200739
KH		 1119 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1120 ctx->callback = callback;
1121
c781c06d
KH		 1122 /*
1123 * We put a dummy descriptor in the buffer that has a NULL
30200739 1124 * branch address and looks like it's been sent. That way we
fe5ca634 1125 * have a descriptor to append DMA programs to.
c781c06d 1126 */
fe5ca634
DM		 1127 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1128 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1129 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1130 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1131 ctx->last = ctx->buffer_tail->buffer;
1132 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1133
1134 return 0;
1135}
1136
53dca511 1137static void context_release(struct context *ctx)
30200739
KH		 1138{
1139 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1140 struct descriptor_buffer *desc, *tmp;
30200739 1141
fe5ca634
DM		 1142 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1143 dma_free_coherent(card->device, PAGE_SIZE, desc,
1144 desc->buffer_bus -
1145 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1146}
1147
fe5ca634 1148/* Must be called with ohci->lock held */
53dca511
SR		 1149static struct descriptor *context_get_descriptors(struct context *ctx,
1150 int z, dma_addr_t *d_bus)
30200739 1151{
fe5ca634
DM		 1152 struct descriptor *d = NULL;
1153 struct descriptor_buffer *desc = ctx->buffer_tail;
1154
1155 if (z * sizeof(*d) > desc->buffer_size)
1156 return NULL;
1157
1158 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1159 /* No room for the descriptor in this buffer, so advance to the
1160 * next one. */
30200739 1161
fe5ca634
DM		 1162 if (desc->list.next == &ctx->buffer_list) {
1163 /* If there is no free buffer next in the list,
1164 * allocate one. */
1165 if (context_add_buffer(ctx) < 0)
1166 return NULL;
1167 }
1168 desc = list_entry(desc->list.next,
1169 struct descriptor_buffer, list);
1170 ctx->buffer_tail = desc;
1171 }
30200739 1172
fe5ca634 1173 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1174 memset(d, 0, z * sizeof(*d));
fe5ca634 1175 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1176
1177 return d;
1178}
1179
295e3feb 1180static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1181{
1182 struct fw_ohci *ohci = ctx->ohci;
1183
a77754a7 1184 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1185 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1186 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1187 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1188 ctx->running = true;
30200739
KH		 1189 flush_writes(ohci);
1190}
1191
1192static void context_append(struct context *ctx,
1193 struct descriptor *d, int z, int extra)
1194{
1195 dma_addr_t d_bus;
fe5ca634 1196 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1197
fe5ca634 1198 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1199
fe5ca634 1200 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1201
1202 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1203 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1204 ctx->prev = find_branch_descriptor(d, z);
30200739
KH		 1205}
1206
1207static void context_stop(struct context *ctx)
1208{
1209 u32 reg;
b8295668 1210 int i;
30200739 1211
a77754a7 1212 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1213 ctx->running = false;
30200739 1214
9ef28ccd 1215 for (i = 0; i < 1000; i++) {
a77754a7 1216 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
b8295668 1217 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1218 return;
b8295668 1219
9ef28ccd
SR		 1220 if (i)
1221 udelay(10);
b8295668 1222 }
b0068549 1223 fw_error("Error: DMA context still active (0x%08x)\n", reg);
30200739 1224}
ed568912 1225
f319b6a0 1226struct driver_data {
da28947e 1227 u8 inline_data[8];
f319b6a0
KH		 1228 struct fw_packet *packet;
1229};
ed568912 1230
c781c06d
KH		 1231/*
1232 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1233 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1234 * generation handling and locking around packet queue manipulation.
1235 */
53dca511
SR		 1236static int at_context_queue_packet(struct context *ctx,
1237 struct fw_packet *packet)
ed568912 1238{
ed568912 1239 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1240 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1241 struct driver_data *driver_data;
1242 struct descriptor *d, *last;
1243 __le32 *header;
ed568912
KH		 1244 int z, tcode;
1245
f319b6a0
KH		 1246 d = context_get_descriptors(ctx, 4, &d_bus);
1247 if (d == NULL) {
1248 packet->ack = RCODE_SEND_ERROR;
1249 return -1;
ed568912
KH		 1250 }
1251
a77754a7 1252 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1253 d[0].res_count = cpu_to_le16(packet->timestamp);
1254
c781c06d
KH		 1255 /*
1256 * The DMA format for asyncronous link packets is different
ed568912 1257 * from the IEEE1394 layout, so shift the fields around
5b06db16 1258 * accordingly.
c781c06d 1259 */
f319b6a0 1260
5b06db16 1261 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1262 header = (__le32 *) &d[1];
5b06db16
CL		 1263 switch (tcode) {
1264 case TCODE_WRITE_QUADLET_REQUEST:
1265 case TCODE_WRITE_BLOCK_REQUEST:
1266 case TCODE_WRITE_RESPONSE:
1267 case TCODE_READ_QUADLET_REQUEST:
1268 case TCODE_READ_BLOCK_REQUEST:
1269 case TCODE_READ_QUADLET_RESPONSE:
1270 case TCODE_READ_BLOCK_RESPONSE:
1271 case TCODE_LOCK_REQUEST:
1272 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1273 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1274 (packet->speed << 16));
1275 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1276 (packet->header[0] & 0xffff0000));
1277 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1278
ed568912 1279 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1280 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1281 else
f319b6a0
KH		 1282 header[3] = (__force __le32) packet->header[3];
1283
1284 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1285 break;
1286
5b06db16 1287 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1288 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1289 (packet->speed << 16));
5b06db16
CL		 1290 header[1] = cpu_to_le32(packet->header[1]);
1291 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1292 d[0].req_count = cpu_to_le16(12);
cc550216 1293
5b06db16 1294 if (is_ping_packet(&packet->header[1]))
cc550216 1295 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1296 break;
1297
5b06db16 1298 case TCODE_STREAM_DATA:
f8c2287c
JF		 1299 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1300 (packet->speed << 16));
1301 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1302 d[0].req_count = cpu_to_le16(8);
1303 break;
1304
1305 default:
1306 /* BUG(); */
1307 packet->ack = RCODE_SEND_ERROR;
1308 return -1;
ed568912
KH		 1309 }
1310
da28947e 1311 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1312 driver_data = (struct driver_data *) &d[3];
1313 driver_data->packet = packet;
20d11673 1314 packet->driver_data = driver_data;
a186b4a6 1315
f319b6a0 1316 if (packet->payload_length > 0) {
da28947e
CL		 1317 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1318 payload_bus = dma_map_single(ohci->card.device,
1319 packet->payload,
1320 packet->payload_length,
1321 DMA_TO_DEVICE);
1322 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1323 packet->ack = RCODE_SEND_ERROR;
1324 return -1;
1325 }
1326 packet->payload_bus = payload_bus;
1327 packet->payload_mapped = true;
1328 } else {
1329 memcpy(driver_data->inline_data, packet->payload,
1330 packet->payload_length);
1331 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1332 }
1333
1334 d[2].req_count = cpu_to_le16(packet->payload_length);
1335 d[2].data_address = cpu_to_le32(payload_bus);
1336 last = &d[2];
1337 z = 3;
ed568912 1338 } else {
f319b6a0
KH		 1339 last = &d[0];
1340 z = 2;
ed568912 1341 }
ed568912 1342
a77754a7
KH		 1343 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1344 DESCRIPTOR_IRQ_ALWAYS |
1345 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1346
b6258fc1
SR		 1347 /* FIXME: Document how the locking works. */
1348 if (ohci->generation != packet->generation) {
19593ffd 1349 if (packet->payload_mapped)
ab88ca48
SR		 1350 dma_unmap_single(ohci->card.device, payload_bus,
1351 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1352 packet->ack = RCODE_GENERATION;
1353 return -1;
1354 }
1355
1356 context_append(ctx, d, z, 4 - z);
ed568912 1357
dd6254e5 1358 if (ctx->running)
13882a82 1359 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
dd6254e5 1360 else
f319b6a0
KH		 1361 context_run(ctx, 0);
1362
1363 return 0;
ed568912
KH		 1364}
1365
82b662dc
CL		 1366static void at_context_flush(struct context *ctx)
1367{
1368 tasklet_disable(&ctx->tasklet);
1369
1370 ctx->flushing = true;
1371 context_tasklet((unsigned long)ctx);
1372 ctx->flushing = false;
1373
1374 tasklet_enable(&ctx->tasklet);
1375}
1376
f319b6a0
KH		 1377static int handle_at_packet(struct context *context,
1378 struct descriptor *d,
1379 struct descriptor *last)
ed568912 1380{
f319b6a0 1381 struct driver_data *driver_data;
ed568912 1382 struct fw_packet *packet;
f319b6a0 1383 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1384 int evt;
1385
82b662dc 1386 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1387 /* This descriptor isn't done yet, stop iteration. */
1388 return 0;
ed568912 1389
f319b6a0
KH		 1390 driver_data = (struct driver_data *) &d[3];
1391 packet = driver_data->packet;
1392 if (packet == NULL)
1393 /* This packet was cancelled, just continue. */
1394 return 1;
730c32f5 1395
19593ffd 1396 if (packet->payload_mapped)
1d1dc5e8 1397 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1398 packet->payload_length, DMA_TO_DEVICE);
ed568912 1399
f319b6a0
KH		 1400 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1401 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1402
ad3c0fe8
SR		 1403 log_ar_at_event('T', packet->speed, packet->header, evt);
1404
f319b6a0
KH		 1405 switch (evt) {
1406 case OHCI1394_evt_timeout:
1407 /* Async response transmit timed out. */
1408 packet->ack = RCODE_CANCELLED;
1409 break;
ed568912 1410
f319b6a0 1411 case OHCI1394_evt_flushed:
c781c06d
KH		 1412 /*
1413 * The packet was flushed should give same error as
1414 * when we try to use a stale generation count.
1415 */
f319b6a0
KH		 1416 packet->ack = RCODE_GENERATION;
1417 break;
ed568912 1418
f319b6a0 1419 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1420 if (context->flushing)
1421 packet->ack = RCODE_GENERATION;
1422 else {
1423 /*
1424 * Using a valid (current) generation count, but the
1425 * node is not on the bus or not sending acks.
1426 */
1427 packet->ack = RCODE_NO_ACK;
1428 }
f319b6a0 1429 break;
ed568912 1430
f319b6a0
KH		 1431 case ACK_COMPLETE + 0x10:
1432 case ACK_PENDING + 0x10:
1433 case ACK_BUSY_X + 0x10:
1434 case ACK_BUSY_A + 0x10:
1435 case ACK_BUSY_B + 0x10:
1436 case ACK_DATA_ERROR + 0x10:
1437 case ACK_TYPE_ERROR + 0x10:
1438 packet->ack = evt - 0x10;
1439 break;
ed568912 1440
82b662dc
CL		 1441 case OHCI1394_evt_no_status:
1442 if (context->flushing) {
1443 packet->ack = RCODE_GENERATION;
1444 break;
1445 }
1446 /* fall through */
1447
f319b6a0
KH		 1448 default:
1449 packet->ack = RCODE_SEND_ERROR;
1450 break;
1451 }
ed568912 1452
f319b6a0 1453 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1454
f319b6a0 1455 return 1;
ed568912
KH		 1456}
1457
a77754a7
KH		 1458#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1459#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1460#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1461#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1462#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1463
53dca511
SR		 1464static void handle_local_rom(struct fw_ohci *ohci,
1465 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1466{
1467 struct fw_packet response;
1468 int tcode, length, i;
1469
a77754a7 1470 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1471 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1472 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1473 else
1474 length = 4;
1475
1476 i = csr - CSR_CONFIG_ROM;
1477 if (i + length > CONFIG_ROM_SIZE) {
1478 fw_fill_response(&response, packet->header,
1479 RCODE_ADDRESS_ERROR, NULL, 0);
1480 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1481 fw_fill_response(&response, packet->header,
1482 RCODE_TYPE_ERROR, NULL, 0);
1483 } else {
1484 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1485 (void *) ohci->config_rom + i, length);
1486 }
1487
1488 fw_core_handle_response(&ohci->card, &response);
1489}
1490
53dca511
SR		 1491static void handle_local_lock(struct fw_ohci *ohci,
1492 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1493{
1494 struct fw_packet response;
e1393667 1495 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1496 __be32 *payload, lock_old;
1497 u32 lock_arg, lock_data;
1498
a77754a7
KH		 1499 tcode = HEADER_GET_TCODE(packet->header[0]);
1500 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1501 payload = packet->payload;
a77754a7 1502 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1503
1504 if (tcode == TCODE_LOCK_REQUEST &&
1505 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1506 lock_arg = be32_to_cpu(payload[0]);
1507 lock_data = be32_to_cpu(payload[1]);
1508 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1509 lock_arg = 0;
1510 lock_data = 0;
1511 } else {
1512 fw_fill_response(&response, packet->header,
1513 RCODE_TYPE_ERROR, NULL, 0);
1514 goto out;
1515 }
1516
1517 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1518 reg_write(ohci, OHCI1394_CSRData, lock_data);
1519 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1520 reg_write(ohci, OHCI1394_CSRControl, sel);
1521
e1393667
CL		 1522 for (try = 0; try < 20; try++)
1523 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1524 lock_old = cpu_to_be32(reg_read(ohci,
1525 OHCI1394_CSRData));
1526 fw_fill_response(&response, packet->header,
1527 RCODE_COMPLETE,
1528 &lock_old, sizeof(lock_old));
1529 goto out;
1530 }
1531
1532 fw_error("swap not done (CSR lock timeout)\n");
1533 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1534
93c4cceb
KH		 1535 out:
1536 fw_core_handle_response(&ohci->card, &response);
1537}
1538
53dca511 1539static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1540{
2608203d 1541 u64 offset, csr;
93c4cceb 1542
473d28c7
KH		 1543 if (ctx == &ctx->ohci->at_request_ctx) {
1544 packet->ack = ACK_PENDING;
1545 packet->callback(packet, &ctx->ohci->card, packet->ack);
1546 }
93c4cceb
KH		 1547
1548 offset =
1549 ((unsigned long long)
a77754a7 1550 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1551 packet->header[2];
1552 csr = offset - CSR_REGISTER_BASE;
1553
1554 /* Handle config rom reads. */
1555 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1556 handle_local_rom(ctx->ohci, packet, csr);
1557 else switch (csr) {
1558 case CSR_BUS_MANAGER_ID:
1559 case CSR_BANDWIDTH_AVAILABLE:
1560 case CSR_CHANNELS_AVAILABLE_HI:
1561 case CSR_CHANNELS_AVAILABLE_LO:
1562 handle_local_lock(ctx->ohci, packet, csr);
1563 break;
1564 default:
1565 if (ctx == &ctx->ohci->at_request_ctx)
1566 fw_core_handle_request(&ctx->ohci->card, packet);
1567 else
1568 fw_core_handle_response(&ctx->ohci->card, packet);
1569 break;
1570 }
473d28c7
KH		 1571
1572 if (ctx == &ctx->ohci->at_response_ctx) {
1573 packet->ack = ACK_COMPLETE;
1574 packet->callback(packet, &ctx->ohci->card, packet->ack);
1575 }
93c4cceb 1576}
e636fe25 1577
53dca511 1578static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1579{
ed568912 1580 unsigned long flags;
2dbd7d7e 1581 int ret;
ed568912
KH		 1582
1583 spin_lock_irqsave(&ctx->ohci->lock, flags);
1584
a77754a7 1585 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1586 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1587 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1588 handle_local_request(ctx, packet);
1589 return;
e636fe25 1590 }
ed568912 1591
2dbd7d7e 1592 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1593 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1594
2dbd7d7e 1595 if (ret < 0)
f319b6a0 1596 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1597
ed568912
KH		 1598}
1599
f117a3e3
CL		 1600static void detect_dead_context(struct fw_ohci *ohci,
1601 const char *name, unsigned int regs)
1602{
1603 u32 ctl;
1604
1605 ctl = reg_read(ohci, CONTROL_SET(regs));
1606 if (ctl & CONTEXT_DEAD) {
1607#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1608 fw_error("DMA context %s has stopped, error code: %s\n",
1609 name, evts[ctl & 0x1f]);
1610#else
1611 fw_error("DMA context %s has stopped, error code: %#x\n",
1612 name, ctl & 0x1f);
1613#endif
1614 }
1615}
1616
1617static void handle_dead_contexts(struct fw_ohci *ohci)
1618{
1619 unsigned int i;
1620 char name[8];
1621
1622 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1623 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1624 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1625 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1626 for (i = 0; i < 32; ++i) {
1627 if (!(ohci->it_context_support & (1 << i)))
1628 continue;
1629 sprintf(name, "IT%u", i);
1630 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1631 }
1632 for (i = 0; i < 32; ++i) {
1633 if (!(ohci->ir_context_support & (1 << i)))
1634 continue;
1635 sprintf(name, "IR%u", i);
1636 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1637 }
1638 /* TODO: maybe try to flush and restart the dead contexts */
1639}
1640
a48777e0
CL		 1641static u32 cycle_timer_ticks(u32 cycle_timer)
1642{
1643 u32 ticks;
1644
1645 ticks = cycle_timer & 0xfff;
1646 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1647 ticks += (3072 * 8000) * (cycle_timer >> 25);
1648
1649 return ticks;
1650}
1651
1652/*
1653 * Some controllers exhibit one or more of the following bugs when updating the
1654 * iso cycle timer register:
1655 * - When the lowest six bits are wrapping around to zero, a read that happens
1656 * at the same time will return garbage in the lowest ten bits.
1657 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1658 * not incremented for about 60 ns.
1659 * - Occasionally, the entire register reads zero.
1660 *
1661 * To catch these, we read the register three times and ensure that the
1662 * difference between each two consecutive reads is approximately the same, i.e.
1663 * less than twice the other. Furthermore, any negative difference indicates an
1664 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1665 * execute, so we have enough precision to compute the ratio of the differences.)
1666 */
1667static u32 get_cycle_time(struct fw_ohci *ohci)
1668{
1669 u32 c0, c1, c2;
1670 u32 t0, t1, t2;
1671 s32 diff01, diff12;
1672 int i;
1673
1674 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1675
1676 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1677 i = 0;
1678 c1 = c2;
1679 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1680 do {
1681 c0 = c1;
1682 c1 = c2;
1683 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1684 t0 = cycle_timer_ticks(c0);
1685 t1 = cycle_timer_ticks(c1);
1686 t2 = cycle_timer_ticks(c2);
1687 diff01 = t1 - t0;
1688 diff12 = t2 - t1;
1689 } while ((diff01 <= 0 || diff12 <= 0 ||
1690 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1691 && i++ < 20);
1692 }
1693
1694 return c2;
1695}
1696
1697/*
1698 * This function has to be called at least every 64 seconds. The bus_time
1699 * field stores not only the upper 25 bits of the BUS_TIME register but also
1700 * the most significant bit of the cycle timer in bit 6 so that we can detect
1701 * changes in this bit.
1702 */
1703static u32 update_bus_time(struct fw_ohci *ohci)
1704{
1705 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1706
1707 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1708 ohci->bus_time += 0x40;
1709
1710 return ohci->bus_time | cycle_time_seconds;
1711}
1712
ed568912
KH		 1713static void bus_reset_tasklet(unsigned long data)
1714{
1715 struct fw_ohci *ohci = (struct fw_ohci *)data;
e636fe25 1716 int self_id_count, i, j, reg;
ed568912
KH		 1717 int generation, new_generation;
1718 unsigned long flags;
4eaff7d6
SR		 1719 void *free_rom = NULL;
1720 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1721 bool is_new_root;
ed568912
KH		 1722
1723 reg = reg_read(ohci, OHCI1394_NodeID);
1724 if (!(reg & OHCI1394_NodeID_idValid)) {
02ff8f8e 1725 fw_notify("node ID not valid, new bus reset in progress\n");
ed568912
KH		 1726 return;
1727 }
02ff8f8e
SR		 1728 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1729 fw_notify("malconfigured bus\n");
1730 return;
1731 }
1732 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1733 OHCI1394_NodeID_nodeNumber);
ed568912 1734
4ffb7a6a
CL		 1735 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1736 if (!(ohci->is_root && is_new_root))
1737 reg_write(ohci, OHCI1394_LinkControlSet,
1738 OHCI1394_LinkControl_cycleMaster);
1739 ohci->is_root = is_new_root;
1740
c8a9a498
SR		 1741 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1742 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1743 fw_notify("inconsistent self IDs\n");
1744 return;
1745 }
c781c06d
KH		 1746 /*
1747 * The count in the SelfIDCount register is the number of
ed568912
KH		 1748 * bytes in the self ID receive buffer. Since we also receive
1749 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1750 * bit extra to get the actual number of self IDs.
1751 */
928ec5f1
SR		 1752 self_id_count = (reg >> 3) & 0xff;
1753 if (self_id_count == 0 || self_id_count > 252) {
016bf3df
SR		 1754 fw_notify("inconsistent self IDs\n");
1755 return;
1756 }
11bf20ad 1757 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1758 rmb();
ed568912
KH		 1759
1760 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498
SR		 1761 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1762 fw_notify("inconsistent self IDs\n");
1763 return;
1764 }
11bf20ad
SR		 1765 ohci->self_id_buffer[j] =
1766 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1767 }
ee71c2f9 1768 rmb();
ed568912 1769
c781c06d
KH		 1770 /*
1771 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1772 * problem we face is that a new bus reset can start while we
1773 * read out the self IDs from the DMA buffer. If this happens,
1774 * the DMA buffer will be overwritten with new self IDs and we
1775 * will read out inconsistent data. The OHCI specification
1776 * (section 11.2) recommends a technique similar to
1777 * linux/seqlock.h, where we remember the generation of the
1778 * self IDs in the buffer before reading them out and compare
1779 * it to the current generation after reading them out. If
1780 * the two generations match we know we have a consistent set
c781c06d
KH		 1781 * of self IDs.
1782 */
ed568912
KH		 1783
1784 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1785 if (new_generation != generation) {
1786 fw_notify("recursive bus reset detected, "
1787 "discarding self ids\n");
1788 return;
1789 }
1790
1791 /* FIXME: Document how the locking works. */
1792 spin_lock_irqsave(&ohci->lock, flags);
1793
82b662dc 1794 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 1795 context_stop(&ohci->at_request_ctx);
1796 context_stop(&ohci->at_response_ctx);
82b662dc
CL		 1797
1798 spin_unlock_irqrestore(&ohci->lock, flags);
1799
78dec56d
SR		 1800 /*
1801 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1802 * packets in the AT queues and software needs to drain them.
1803 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1804 */
82b662dc
CL		 1805 at_context_flush(&ohci->at_request_ctx);
1806 at_context_flush(&ohci->at_response_ctx);
1807
1808 spin_lock_irqsave(&ohci->lock, flags);
1809
1810 ohci->generation = generation;
ed568912
KH		 1811 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1812
4a635593 1813 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1814 ohci->request_generation = generation;
1815
c781c06d
KH		 1816 /*
1817 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1818 * have to do it under the spinlock also. If a new config rom
1819 * was set up before this reset, the old one is now no longer
1820 * in use and we can free it. Update the config rom pointers
1821 * to point to the current config rom and clear the
88393161 1822 * next_config_rom pointer so a new update can take place.
c781c06d 1823 */
ed568912
KH		 1824
1825 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 1826 if (ohci->next_config_rom != ohci->config_rom) {
1827 free_rom = ohci->config_rom;
1828 free_rom_bus = ohci->config_rom_bus;
1829 }
ed568912
KH		 1830 ohci->config_rom = ohci->next_config_rom;
1831 ohci->config_rom_bus = ohci->next_config_rom_bus;
1832 ohci->next_config_rom = NULL;
1833
c781c06d
KH		 1834 /*
1835 * Restore config_rom image and manually update
ed568912
KH		 1836 * config_rom registers. Writing the header quadlet
1837 * will indicate that the config rom is ready, so we
c781c06d
KH		 1838 * do that last.
1839 */
ed568912
KH		 1840 reg_write(ohci, OHCI1394_BusOptions,
1841 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 1842 ohci->config_rom[0] = ohci->next_header;
1843 reg_write(ohci, OHCI1394_ConfigROMhdr,
1844 be32_to_cpu(ohci->next_header));
ed568912
KH		 1845 }
1846
080de8c2
SR		 1847#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1848 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1849 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1850#endif
1851
ed568912
KH		 1852 spin_unlock_irqrestore(&ohci->lock, flags);
1853
4eaff7d6
SR		 1854 if (free_rom)
1855 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1856 free_rom, free_rom_bus);
1857
08ddb2f4
SR		 1858 log_selfids(ohci->node_id, generation,
1859 self_id_count, ohci->self_id_buffer);
ad3c0fe8 1860
e636fe25 1861 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 1862 self_id_count, ohci->self_id_buffer,
1863 ohci->csr_state_setclear_abdicate);
1864 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 1865}
1866
1867static irqreturn_t irq_handler(int irq, void *data)
1868{
1869 struct fw_ohci *ohci = data;
168cf9af 1870 u32 event, iso_event;
ed568912
KH		 1871 int i;
1872
1873 event = reg_read(ohci, OHCI1394_IntEventClear);
1874
a515958d 1875 if (!event || !~event)
ed568912
KH		 1876 return IRQ_NONE;
1877
8327b37b
CL		 1878 /*
1879 * busReset and postedWriteErr must not be cleared yet
1880 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1881 */
1882 reg_write(ohci, OHCI1394_IntEventClear,
1883 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
ad3c0fe8 1884 log_irqs(event);
ed568912
KH		 1885
1886 if (event & OHCI1394_selfIDComplete)
1887 tasklet_schedule(&ohci->bus_reset_tasklet);
1888
1889 if (event & OHCI1394_RQPkt)
1890 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1891
1892 if (event & OHCI1394_RSPkt)
1893 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1894
1895 if (event & OHCI1394_reqTxComplete)
1896 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1897
1898 if (event & OHCI1394_respTxComplete)
1899 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1900
2dd5bed5
CL		 1901 if (event & OHCI1394_isochRx) {
1902 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1903 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1904
1905 while (iso_event) {
1906 i = ffs(iso_event) - 1;
1907 tasklet_schedule(
1908 &ohci->ir_context_list[i].context.tasklet);
1909 iso_event &= ~(1 << i);
1910 }
ed568912
KH		 1911 }
1912
2dd5bed5
CL		 1913 if (event & OHCI1394_isochTx) {
1914 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1915 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 1916
2dd5bed5
CL		 1917 while (iso_event) {
1918 i = ffs(iso_event) - 1;
1919 tasklet_schedule(
1920 &ohci->it_context_list[i].context.tasklet);
1921 iso_event &= ~(1 << i);
1922 }
ed568912
KH		 1923 }
1924
75f7832e
JW		 1925 if (unlikely(event & OHCI1394_regAccessFail))
1926 fw_error("Register access failure - "
1927 "please notify linux1394-devel@lists.sf.net\n");
1928
8327b37b
CL		 1929 if (unlikely(event & OHCI1394_postedWriteErr)) {
1930 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1931 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1932 reg_write(ohci, OHCI1394_IntEventClear,
1933 OHCI1394_postedWriteErr);
e524f616 1934 fw_error("PCI posted write error\n");
8327b37b 1935 }
e524f616 1936
bb9f2206
SR		 1937 if (unlikely(event & OHCI1394_cycleTooLong)) {
1938 if (printk_ratelimit())
1939 fw_notify("isochronous cycle too long\n");
1940 reg_write(ohci, OHCI1394_LinkControlSet,
1941 OHCI1394_LinkControl_cycleMaster);
1942 }
1943
5ed1f321
JF		 1944 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1945 /*
1946 * We need to clear this event bit in order to make
1947 * cycleMatch isochronous I/O work. In theory we should
1948 * stop active cycleMatch iso contexts now and restart
1949 * them at least two cycles later. (FIXME?)
1950 */
1951 if (printk_ratelimit())
1952 fw_notify("isochronous cycle inconsistent\n");
1953 }
1954
f117a3e3
CL		 1955 if (unlikely(event & OHCI1394_unrecoverableError))
1956 handle_dead_contexts(ohci);
1957
a48777e0
CL		 1958 if (event & OHCI1394_cycle64Seconds) {
1959 spin_lock(&ohci->lock);
1960 update_bus_time(ohci);
1961 spin_unlock(&ohci->lock);
e597e989
CL		 1962 } else
1963 flush_writes(ohci);
a48777e0 1964
ed568912
KH		 1965 return IRQ_HANDLED;
1966}
1967
2aef469a
KH		 1968static int software_reset(struct fw_ohci *ohci)
1969{
1970 int i;
1971
1972 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1973
1974 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1975 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1976 OHCI1394_HCControl_softReset) == 0)
1977 return 0;
1978 msleep(1);
1979 }
1980
1981 return -EBUSY;
1982}
1983
8e85973e
SR		 1984static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1985{
1986 size_t size = length * 4;
1987
1988 memcpy(dest, src, size);
1989 if (size < CONFIG_ROM_SIZE)
1990 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1991}
1992
925e7a65
CL		 1993static int configure_1394a_enhancements(struct fw_ohci *ohci)
1994{
1995 bool enable_1394a;
35d999b1 1996 int ret, clear, set, offset;
925e7a65
CL		 1997
1998 /* Check if the driver should configure link and PHY. */
1999 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2000 OHCI1394_HCControl_programPhyEnable))
2001 return 0;
2002
2003 /* Paranoia: check whether the PHY supports 1394a, too. */
2004 enable_1394a = false;
35d999b1
SR		 2005 ret = read_phy_reg(ohci, 2);
2006 if (ret < 0)
2007 return ret;
2008 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2009 ret = read_paged_phy_reg(ohci, 1, 8);
2010 if (ret < 0)
2011 return ret;
2012 if (ret >= 1)
925e7a65
CL		 2013 enable_1394a = true;
2014 }
2015
2016 if (ohci->quirks & QUIRK_NO_1394A)
2017 enable_1394a = false;
2018
2019 /* Configure PHY and link consistently. */
2020 if (enable_1394a) {
2021 clear = 0;
2022 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2023 } else {
2024 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2025 set = 0;
2026 }
02d37bed 2027 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2028 if (ret < 0)
2029 return ret;
925e7a65
CL		 2030
2031 if (enable_1394a)
2032 offset = OHCI1394_HCControlSet;
2033 else
2034 offset = OHCI1394_HCControlClear;
2035 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2036
2037 /* Clean up: configuration has been taken care of. */
2038 reg_write(ohci, OHCI1394_HCControlClear,
2039 OHCI1394_HCControl_programPhyEnable);
2040
2041 return 0;
2042}
2043
8e85973e
SR		 2044static int ohci_enable(struct fw_card *card,
2045 const __be32 *config_rom, size_t length)
ed568912
KH		 2046{
2047 struct fw_ohci *ohci = fw_ohci(card);
2048 struct pci_dev *dev = to_pci_dev(card->device);
e91b2787 2049 u32 lps, seconds, version, irqs;
35d999b1 2050 int i, ret;
ed568912 2051
2aef469a
KH		 2052 if (software_reset(ohci)) {
2053 fw_error("Failed to reset ohci card.\n");
2054 return -EBUSY;
2055 }
2056
2057 /*
2058 * Now enable LPS, which we need in order to start accessing
2059 * most of the registers. In fact, on some cards (ALI M5251),
2060 * accessing registers in the SClk domain without LPS enabled
2061 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2062 * full link enabled. However, with some cards (well, at least
2063 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 2064 */
2065 reg_write(ohci, OHCI1394_HCControlSet,
2066 OHCI1394_HCControl_LPS |
2067 OHCI1394_HCControl_postedWriteEnable);
2068 flush_writes(ohci);
02214724
JW		 2069
2070 for (lps = 0, i = 0; !lps && i < 3; i++) {
2071 msleep(50);
2072 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2073 OHCI1394_HCControl_LPS;
2074 }
2075
2076 if (!lps) {
2077 fw_error("Failed to set Link Power Status\n");
2078 return -EIO;
2079 }
2aef469a
KH		 2080
2081 reg_write(ohci, OHCI1394_HCControlClear,
2082 OHCI1394_HCControl_noByteSwapData);
2083
affc9c24 2084 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2085 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2086 OHCI1394_LinkControl_cycleTimerEnable |
2087 OHCI1394_LinkControl_cycleMaster);
2088
2089 reg_write(ohci, OHCI1394_ATRetries,
2090 OHCI1394_MAX_AT_REQ_RETRIES |
2091 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2092 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2093 (200 << 16));
2aef469a 2094
a48777e0
CL		 2095 seconds = lower_32_bits(get_seconds());
2096 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2097 ohci->bus_time = seconds & ~0x3f;
2098
e91b2787
CL		 2099 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2100 if (version >= OHCI_VERSION_1_1) {
2101 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2102 0xfffffffe);
db3c9cc1 2103 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2104 }
2105
a1a1132b
CL		 2106 /* Get implemented bits of the priority arbitration request counter. */
2107 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2108 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2109 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2110 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2111
2aef469a
KH		 2112 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2113 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2114 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2115
35d999b1
SR		 2116 ret = configure_1394a_enhancements(ohci);
2117 if (ret < 0)
2118 return ret;
925e7a65 2119
2aef469a 2120 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2121 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2122 if (ret < 0)
2123 return ret;
2aef469a 2124
c781c06d
KH		 2125 /*
2126 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2127 * update mechanism described below in ohci_set_config_rom()
2128 * is not active. We have to update ConfigRomHeader and
2129 * BusOptions manually, and the write to ConfigROMmap takes
2130 * effect immediately. We tie this to the enabling of the
2131 * link, so we have a valid config rom before enabling - the
2132 * OHCI requires that ConfigROMhdr and BusOptions have valid
2133 * values before enabling.
2134 *
2135 * However, when the ConfigROMmap is written, some controllers
2136 * always read back quadlets 0 and 2 from the config rom to
2137 * the ConfigRomHeader and BusOptions registers on bus reset.
2138 * They shouldn't do that in this initial case where the link
2139 * isn't enabled. This means we have to use the same
2140 * workaround here, setting the bus header to 0 and then write
2141 * the right values in the bus reset tasklet.
2142 */
2143
0bd243c4
KH		 2144 if (config_rom) {
2145 ohci->next_config_rom =
2146 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2147 &ohci->next_config_rom_bus,
2148 GFP_KERNEL);
2149 if (ohci->next_config_rom == NULL)
2150 return -ENOMEM;
ed568912 2151
8e85973e 2152 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2153 } else {
2154 /*
2155 * In the suspend case, config_rom is NULL, which
2156 * means that we just reuse the old config rom.
2157 */
2158 ohci->next_config_rom = ohci->config_rom;
2159 ohci->next_config_rom_bus = ohci->config_rom_bus;
2160 }
ed568912 2161
8e85973e 2162 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2163 ohci->next_config_rom[0] = 0;
2164 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2165 reg_write(ohci, OHCI1394_BusOptions,
2166 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2167 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2168
2169 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2170
262444ee
CL		 2171 if (!(ohci->quirks & QUIRK_NO_MSI))
2172 pci_enable_msi(dev);
ed568912 2173 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2174 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2175 ohci_driver_name, ohci)) {
2176 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2177 pci_disable_msi(dev);
ed568912
KH		 2178 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2179 ohci->config_rom, ohci->config_rom_bus);
2180 return -EIO;
2181 }
2182
148c7866
SR		 2183 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2184 OHCI1394_RQPkt | OHCI1394_RSPkt |
2185 OHCI1394_isochTx | OHCI1394_isochRx |
2186 OHCI1394_postedWriteErr |
2187 OHCI1394_selfIDComplete |
2188 OHCI1394_regAccessFail |
a48777e0 2189 OHCI1394_cycle64Seconds |
f117a3e3
CL		 2190 OHCI1394_cycleInconsistent |
2191 OHCI1394_unrecoverableError |
2192 OHCI1394_cycleTooLong |
148c7866
SR		 2193 OHCI1394_masterIntEnable;
2194 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2195 irqs |= OHCI1394_busReset;
2196 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2197
ed568912
KH		 2198 reg_write(ohci, OHCI1394_HCControlSet,
2199 OHCI1394_HCControl_linkEnable |
2200 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2201
2202 reg_write(ohci, OHCI1394_LinkControlSet,
2203 OHCI1394_LinkControl_rcvSelfID |
2204 OHCI1394_LinkControl_rcvPhyPkt);
2205
2206 ar_context_run(&ohci->ar_request_ctx);
dd6254e5
CL		 2207 ar_context_run(&ohci->ar_response_ctx);
2208
2209 flush_writes(ohci);
ed568912 2210
02d37bed
SR		 2211 /* We are ready to go, reset bus to finish initialization. */
2212 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2213
2214 return 0;
2215}
2216
53dca511 2217static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2218 const __be32 *config_rom, size_t length)
ed568912
KH		 2219{
2220 struct fw_ohci *ohci;
2221 unsigned long flags;
ed568912 2222 __be32 *next_config_rom;
f5101d58 2223 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2224
2225 ohci = fw_ohci(card);
2226
c781c06d
KH		 2227 /*
2228 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2229 * mechanism is a bit tricky, but easy enough to use. See
2230 * section 5.5.6 in the OHCI specification.
2231 *
2232 * The OHCI controller caches the new config rom address in a
2233 * shadow register (ConfigROMmapNext) and needs a bus reset
2234 * for the changes to take place. When the bus reset is
2235 * detected, the controller loads the new values for the
2236 * ConfigRomHeader and BusOptions registers from the specified
2237 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2238 * shadow register. All automatically and atomically.
2239 *
2240 * Now, there's a twist to this story. The automatic load of
2241 * ConfigRomHeader and BusOptions doesn't honor the
2242 * noByteSwapData bit, so with a be32 config rom, the
2243 * controller will load be32 values in to these registers
2244 * during the atomic update, even on litte endian
2245 * architectures. The workaround we use is to put a 0 in the
2246 * header quadlet; 0 is endian agnostic and means that the
2247 * config rom isn't ready yet. In the bus reset tasklet we
2248 * then set up the real values for the two registers.
2249 *
2250 * We use ohci->lock to avoid racing with the code that sets
2251 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2252 */
2253
2254 next_config_rom =
2255 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2256 &next_config_rom_bus, GFP_KERNEL);
2257 if (next_config_rom == NULL)
2258 return -ENOMEM;
2259
2260 spin_lock_irqsave(&ohci->lock, flags);
2261
2e053a27
B		 2262 /*
2263 * If there is not an already pending config_rom update,
2264 * push our new allocation into the ohci->next_config_rom
2265 * and then mark the local variable as null so that we
2266 * won't deallocate the new buffer.
2267 *
2268 * OTOH, if there is a pending config_rom update, just
2269 * use that buffer with the new config_rom data, and
2270 * let this routine free the unused DMA allocation.
2271 */
2272
ed568912
KH		 2273 if (ohci->next_config_rom == NULL) {
2274 ohci->next_config_rom = next_config_rom;
2275 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2276 next_config_rom = NULL;
2277 }
ed568912 2278
2e053a27 2279 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2280
2e053a27
B		 2281 ohci->next_header = config_rom[0];
2282 ohci->next_config_rom[0] = 0;
ed568912 2283
2e053a27 2284 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912
KH		 2285
2286 spin_unlock_irqrestore(&ohci->lock, flags);
2287
2e053a27
B		 2288 /* If we didn't use the DMA allocation, delete it. */
2289 if (next_config_rom != NULL)
2290 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2291 next_config_rom, next_config_rom_bus);
2292
c781c06d
KH		 2293 /*
2294 * Now initiate a bus reset to have the changes take
ed568912
KH		 2295 * effect. We clean up the old config rom memory and DMA
2296 * mappings in the bus reset tasklet, since the OHCI
2297 * controller could need to access it before the bus reset
c781c06d
KH		 2298 * takes effect.
2299 */
ed568912 2300
2e053a27
B		 2301 fw_schedule_bus_reset(&ohci->card, true, true);
2302
2303 return 0;
ed568912
KH		 2304}
2305
2306static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2307{
2308 struct fw_ohci *ohci = fw_ohci(card);
2309
2310 at_context_transmit(&ohci->at_request_ctx, packet);
2311}
2312
2313static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2314{
2315 struct fw_ohci *ohci = fw_ohci(card);
2316
2317 at_context_transmit(&ohci->at_response_ctx, packet);
2318}
2319
730c32f5
KH		 2320static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2321{
2322 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2323 struct context *ctx = &ohci->at_request_ctx;
2324 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2325 int ret = -ENOENT;
730c32f5 2326
f319b6a0 2327 tasklet_disable(&ctx->tasklet);
730c32f5 2328
f319b6a0
KH		 2329 if (packet->ack != 0)
2330 goto out;
730c32f5 2331
19593ffd 2332 if (packet->payload_mapped)
1d1dc5e8
SR		 2333 dma_unmap_single(ohci->card.device, packet->payload_bus,
2334 packet->payload_length, DMA_TO_DEVICE);
2335
ad3c0fe8 2336 log_ar_at_event('T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2337 driver_data->packet = NULL;
2338 packet->ack = RCODE_CANCELLED;
2339 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2340 ret = 0;
f319b6a0
KH		 2341 out:
2342 tasklet_enable(&ctx->tasklet);
730c32f5 2343
2dbd7d7e 2344 return ret;
730c32f5
KH		 2345}
2346
53dca511
SR		 2347static int ohci_enable_phys_dma(struct fw_card *card,
2348 int node_id, int generation)
ed568912 2349{
080de8c2
SR		 2350#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2351 return 0;
2352#else
ed568912
KH		 2353 struct fw_ohci *ohci = fw_ohci(card);
2354 unsigned long flags;
2dbd7d7e 2355 int n, ret = 0;
ed568912 2356
c781c06d
KH		 2357 /*
2358 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2359 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2360 */
ed568912
KH		 2361
2362 spin_lock_irqsave(&ohci->lock, flags);
2363
2364 if (ohci->generation != generation) {
2dbd7d7e 2365 ret = -ESTALE;
ed568912
KH		 2366 goto out;
2367 }
2368
c781c06d
KH		 2369 /*
2370 * Note, if the node ID contains a non-local bus ID, physical DMA is
2371 * enabled for _all_ nodes on remote buses.
2372 */
907293d7
SR		 2373
2374 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2375 if (n < 32)
2376 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2377 else
2378 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2379
ed568912 2380 flush_writes(ohci);
ed568912 2381 out:
6cad95fe 2382 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2383
2384 return ret;
080de8c2 2385#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2386}
373b2edd 2387
0fcff4e3 2388static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2389{
60d32970 2390 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2391 unsigned long flags;
2392 u32 value;
60d32970
CL		 2393
2394 switch (csr_offset) {
4ffb7a6a
CL		 2395 case CSR_STATE_CLEAR:
2396 case CSR_STATE_SET:
4ffb7a6a
CL		 2397 if (ohci->is_root &&
2398 (reg_read(ohci, OHCI1394_LinkControlSet) &
2399 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2400 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2401 else
c8a94ded
SR		 2402 value = 0;
2403 if (ohci->csr_state_setclear_abdicate)
2404 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2405
c8a94ded 2406 return value;
4a9bde9b 2407
506f1a31
CL		 2408 case CSR_NODE_IDS:
2409 return reg_read(ohci, OHCI1394_NodeID) << 16;
2410
60d32970
CL		 2411 case CSR_CYCLE_TIME:
2412 return get_cycle_time(ohci);
2413
a48777e0
CL		 2414 case CSR_BUS_TIME:
2415 /*
2416 * We might be called just after the cycle timer has wrapped
2417 * around but just before the cycle64Seconds handler, so we
2418 * better check here, too, if the bus time needs to be updated.
2419 */
2420 spin_lock_irqsave(&ohci->lock, flags);
2421 value = update_bus_time(ohci);
2422 spin_unlock_irqrestore(&ohci->lock, flags);
2423 return value;
2424
27a2329f
CL		 2425 case CSR_BUSY_TIMEOUT:
2426 value = reg_read(ohci, OHCI1394_ATRetries);
2427 return (value >> 4) & 0x0ffff00f;
2428
a1a1132b
CL		 2429 case CSR_PRIORITY_BUDGET:
2430 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2431 (ohci->pri_req_max << 8);
2432
60d32970
CL		 2433 default:
2434 WARN_ON(1);
2435 return 0;
2436 }
b677532b
CL		 2437}
2438
0fcff4e3 2439static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2440{
2441 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2442 unsigned long flags;
d60d7f1d 2443
506f1a31 2444 switch (csr_offset) {
4ffb7a6a 2445 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2446 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2447 reg_write(ohci, OHCI1394_LinkControlClear,
2448 OHCI1394_LinkControl_cycleMaster);
2449 flush_writes(ohci);
2450 }
c8a94ded
SR		 2451 if (value & CSR_STATE_BIT_ABDICATE)
2452 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2453 break;
4a9bde9b 2454
4ffb7a6a
CL		 2455 case CSR_STATE_SET:
2456 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2457 reg_write(ohci, OHCI1394_LinkControlSet,
2458 OHCI1394_LinkControl_cycleMaster);
2459 flush_writes(ohci);
2460 }
c8a94ded
SR		 2461 if (value & CSR_STATE_BIT_ABDICATE)
2462 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2463 break;
d60d7f1d 2464
506f1a31
CL		 2465 case CSR_NODE_IDS:
2466 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2467 flush_writes(ohci);
2468 break;
2469
9ab5071c
CL		 2470 case CSR_CYCLE_TIME:
2471 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2472 reg_write(ohci, OHCI1394_IntEventSet,
2473 OHCI1394_cycleInconsistent);
2474 flush_writes(ohci);
2475 break;
2476
a48777e0
CL		 2477 case CSR_BUS_TIME:
2478 spin_lock_irqsave(&ohci->lock, flags);
2479 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2480 spin_unlock_irqrestore(&ohci->lock, flags);
2481 break;
2482
27a2329f
CL		 2483 case CSR_BUSY_TIMEOUT:
2484 value = (value & 0xf) | ((value & 0xf) << 4) |
2485 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2486 reg_write(ohci, OHCI1394_ATRetries, value);
2487 flush_writes(ohci);
2488 break;
2489
a1a1132b
CL		 2490 case CSR_PRIORITY_BUDGET:
2491 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2492 flush_writes(ohci);
2493 break;
2494
506f1a31
CL		 2495 default:
2496 WARN_ON(1);
2497 break;
2498 }
d60d7f1d
KH		 2499}
2500
1aa292bb
DM		 2501static void copy_iso_headers(struct iso_context *ctx, void *p)
2502{
2503 int i = ctx->header_length;
2504
2505 if (i + ctx->base.header_size > PAGE_SIZE)
2506 return;
2507
2508 /*
2509 * The iso header is byteswapped to little endian by
2510 * the controller, but the remaining header quadlets
2511 * are big endian. We want to present all the headers
2512 * as big endian, so we have to swap the first quadlet.
2513 */
2514 if (ctx->base.header_size > 0)
2515 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2516 if (ctx->base.header_size > 4)
2517 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2518 if (ctx->base.header_size > 8)
2519 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2520 ctx->header_length += ctx->base.header_size;
2521}
2522
a186b4a6
JW		 2523static int handle_ir_packet_per_buffer(struct context *context,
2524 struct descriptor *d,
2525 struct descriptor *last)
2526{
2527 struct iso_context *ctx =
2528 container_of(context, struct iso_context, context);
bcee893c 2529 struct descriptor *pd;
a186b4a6 2530 __le32 *ir_header;
bcee893c 2531 void *p;
a186b4a6 2532
872e330e 2533 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2534 if (pd->transfer_status)
2535 break;
bcee893c 2536 if (pd > last)
a186b4a6
JW		 2537 /* Descriptor(s) not done yet, stop iteration */
2538 return 0;
2539
1aa292bb
DM		 2540 p = last + 1;
2541 copy_iso_headers(ctx, p);
a186b4a6 2542
bcee893c
DM		 2543 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2544 ir_header = (__le32 *) p;
872e330e
SR		 2545 ctx->base.callback.sc(&ctx->base,
2546 le32_to_cpu(ir_header[0]) & 0xffff,
2547 ctx->header_length, ctx->header,
2548 ctx->base.callback_data);
a186b4a6
JW		 2549 ctx->header_length = 0;
2550 }
2551
a186b4a6
JW		 2552 return 1;
2553}
2554
872e330e
SR		 2555/* d == last because each descriptor block is only a single descriptor. */
2556static int handle_ir_buffer_fill(struct context *context,
2557 struct descriptor *d,
2558 struct descriptor *last)
2559{
2560 struct iso_context *ctx =
2561 container_of(context, struct iso_context, context);
2562
2563 if (!last->transfer_status)
2564 /* Descriptor(s) not done yet, stop iteration */
2565 return 0;
2566
2567 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2568 ctx->base.callback.mc(&ctx->base,
2569 le32_to_cpu(last->data_address) +
2570 le16_to_cpu(last->req_count) -
2571 le16_to_cpu(last->res_count),
2572 ctx->base.callback_data);
2573
2574 return 1;
2575}
2576
30200739
KH		 2577static int handle_it_packet(struct context *context,
2578 struct descriptor *d,
2579 struct descriptor *last)
ed568912 2580{
30200739
KH		 2581 struct iso_context *ctx =
2582 container_of(context, struct iso_context, context);
31769cef
JF		 2583 int i;
2584 struct descriptor *pd;
373b2edd 2585
31769cef
JF		 2586 for (pd = d; pd <= last; pd++)
2587 if (pd->transfer_status)
2588 break;
2589 if (pd > last)
2590 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2591 return 0;
2592
31769cef
JF		 2593 i = ctx->header_length;
2594 if (i + 4 < PAGE_SIZE) {
2595 /* Present this value as big-endian to match the receive code */
2596 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2597 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2598 le16_to_cpu(pd->res_count));
2599 ctx->header_length += 4;
2600 }
2601 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
872e330e
SR		 2602 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2603 ctx->header_length, ctx->header,
2604 ctx->base.callback_data);
31769cef
JF		 2605 ctx->header_length = 0;
2606 }
30200739 2607 return 1;
ed568912
KH		 2608}
2609
872e330e
SR		 2610static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2611{
2612 u32 hi = channels >> 32, lo = channels;
2613
2614 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2615 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2616 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2617 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2618 mmiowb();
2619 ohci->mc_channels = channels;
2620}
2621
53dca511 2622static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2623 int type, int channel, size_t header_size)
ed568912
KH		 2624{
2625 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2626 struct iso_context *uninitialized_var(ctx);
2627 descriptor_callback_t uninitialized_var(callback);
2628 u64 *uninitialized_var(channels);
2629 u32 *uninitialized_var(mask), uninitialized_var(regs);
ed568912 2630 unsigned long flags;
872e330e 2631 int index, ret = -EBUSY;
ed568912 2632
872e330e 2633 spin_lock_irqsave(&ohci->lock, flags);
ed568912 2634
872e330e
SR		 2635 switch (type) {
2636 case FW_ISO_CONTEXT_TRANSMIT:
2637 mask = &ohci->it_context_mask;
30200739 2638 callback = handle_it_packet;
872e330e
SR		 2639 index = ffs(*mask) - 1;
2640 if (index >= 0) {
2641 *mask &= ~(1 << index);
2642 regs = OHCI1394_IsoXmitContextBase(index);
2643 ctx = &ohci->it_context_list[index];
2644 }
2645 break;
2646
2647 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2648 channels = &ohci->ir_context_channels;
872e330e 2649 mask = &ohci->ir_context_mask;
6498ba04 2650 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2651 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2652 if (index >= 0) {
2653 *channels &= ~(1ULL << channel);
2654 *mask &= ~(1 << index);
2655 regs = OHCI1394_IsoRcvContextBase(index);
2656 ctx = &ohci->ir_context_list[index];
2657 }
2658 break;
ed568912 2659
872e330e
SR		 2660 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2661 mask = &ohci->ir_context_mask;
2662 callback = handle_ir_buffer_fill;
2663 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2664 if (index >= 0) {
2665 ohci->mc_allocated = true;
2666 *mask &= ~(1 << index);
2667 regs = OHCI1394_IsoRcvContextBase(index);
2668 ctx = &ohci->ir_context_list[index];
2669 }
2670 break;
2671
2672 default:
2673 index = -1;
2674 ret = -ENOSYS;
4817ed24 2675 }
872e330e 2676
ed568912
KH		 2677 spin_unlock_irqrestore(&ohci->lock, flags);
2678
2679 if (index < 0)
872e330e 2680 return ERR_PTR(ret);
373b2edd 2681
2d826cc5 2682 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2683 ctx->header_length = 0;
2684 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2685 if (ctx->header == NULL) {
2686 ret = -ENOMEM;
9b32d5f3 2687 goto out;
872e330e 2688 }
2dbd7d7e
SR		 2689 ret = context_init(&ctx->context, ohci, regs, callback);
2690 if (ret < 0)
9b32d5f3 2691 goto out_with_header;
ed568912 2692
872e330e
SR		 2693 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2694 set_multichannel_mask(ohci, 0);
2695
ed568912 2696 return &ctx->base;
9b32d5f3
KH		 2697
2698 out_with_header:
2699 free_page((unsigned long)ctx->header);
2700 out:
2701 spin_lock_irqsave(&ohci->lock, flags);
872e330e
SR		 2702
2703 switch (type) {
2704 case FW_ISO_CONTEXT_RECEIVE:
2705 *channels |= 1ULL << channel;
2706 break;
2707
2708 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2709 ohci->mc_allocated = false;
2710 break;
2711 }
9b32d5f3 2712 *mask |= 1 << index;
872e330e 2713
9b32d5f3
KH		 2714 spin_unlock_irqrestore(&ohci->lock, flags);
2715
2dbd7d7e 2716 return ERR_PTR(ret);
ed568912
KH		 2717}
2718
eb0306ea
KH		 2719static int ohci_start_iso(struct fw_iso_context *base,
2720 s32 cycle, u32 sync, u32 tags)
ed568912 2721{
373b2edd 2722 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 2723 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 2724 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 2725 int index;
2726
44b74d90
CL		 2727 /* the controller cannot start without any queued packets */
2728 if (ctx->context.last->branch_address == 0)
2729 return -ENODATA;
2730
872e330e
SR		 2731 switch (ctx->base.type) {
2732 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 2733 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 2734 match = 0;
2735 if (cycle >= 0)
2736 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 2737 (cycle & 0x7fff) << 16;
21efb3cf 2738
295e3feb
KH		 2739 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2740 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 2741 context_run(&ctx->context, match);
872e330e
SR		 2742 break;
2743
2744 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2745 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2746 /* fall through */
2747 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 2748 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 2749 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2750 if (cycle >= 0) {
2751 match |= (cycle & 0x07fff) << 12;
2752 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2753 }
ed568912 2754
295e3feb
KH		 2755 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2756 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 2757 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 2758 context_run(&ctx->context, control);
dd23736e
ML		 2759
2760 ctx->sync = sync;
2761 ctx->tags = tags;
2762
872e330e 2763 break;
295e3feb 2764 }
ed568912
KH		 2765
2766 return 0;
2767}
2768
b8295668
KH		 2769static int ohci_stop_iso(struct fw_iso_context *base)
2770{
2771 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2772 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 2773 int index;
2774
872e330e
SR		 2775 switch (ctx->base.type) {
2776 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 2777 index = ctx - ohci->it_context_list;
2778 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 2779 break;
2780
2781 case FW_ISO_CONTEXT_RECEIVE:
2782 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 2783 index = ctx - ohci->ir_context_list;
2784 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 2785 break;
b8295668
KH		 2786 }
2787 flush_writes(ohci);
2788 context_stop(&ctx->context);
e81cbebd 2789 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 2790
2791 return 0;
2792}
2793
ed568912
KH		 2794static void ohci_free_iso_context(struct fw_iso_context *base)
2795{
2796 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2797 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 2798 unsigned long flags;
2799 int index;
2800
b8295668
KH		 2801 ohci_stop_iso(base);
2802 context_release(&ctx->context);
9b32d5f3 2803 free_page((unsigned long)ctx->header);
b8295668 2804
ed568912
KH		 2805 spin_lock_irqsave(&ohci->lock, flags);
2806
872e330e
SR		 2807 switch (base->type) {
2808 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 2809 index = ctx - ohci->it_context_list;
ed568912 2810 ohci->it_context_mask |= 1 << index;
872e330e
SR		 2811 break;
2812
2813 case FW_ISO_CONTEXT_RECEIVE:
ed568912 2814 index = ctx - ohci->ir_context_list;
ed568912 2815 ohci->ir_context_mask |= 1 << index;
4817ed24 2816 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 2817 break;
2818
2819 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2820 index = ctx - ohci->ir_context_list;
2821 ohci->ir_context_mask |= 1 << index;
2822 ohci->ir_context_channels |= ohci->mc_channels;
2823 ohci->mc_channels = 0;
2824 ohci->mc_allocated = false;
2825 break;
ed568912 2826 }
ed568912
KH		 2827
2828 spin_unlock_irqrestore(&ohci->lock, flags);
2829}
2830
872e330e
SR		 2831static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2832{
2833 struct fw_ohci *ohci = fw_ohci(base->card);
2834 unsigned long flags;
2835 int ret;
2836
2837 switch (base->type) {
2838 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2839
2840 spin_lock_irqsave(&ohci->lock, flags);
2841
2842 /* Don't allow multichannel to grab other contexts' channels. */
2843 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2844 *channels = ohci->ir_context_channels;
2845 ret = -EBUSY;
2846 } else {
2847 set_multichannel_mask(ohci, *channels);
2848 ret = 0;
2849 }
2850
2851 spin_unlock_irqrestore(&ohci->lock, flags);
2852
2853 break;
2854 default:
2855 ret = -EINVAL;
2856 }
2857
2858 return ret;
2859}
2860
dd23736e
ML		 2861#ifdef CONFIG_PM
2862static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2863{
2864 int i;
2865 struct iso_context *ctx;
2866
2867 for (i = 0 ; i < ohci->n_ir ; i++) {
2868 ctx = &ohci->ir_context_list[i];
693a50b5 2869 if (ctx->context.running)
dd23736e
ML		 2870 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2871 }
2872
2873 for (i = 0 ; i < ohci->n_it ; i++) {
2874 ctx = &ohci->it_context_list[i];
693a50b5 2875 if (ctx->context.running)
dd23736e
ML		 2876 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2877 }
2878}
2879#endif
2880
872e330e
SR		 2881static int queue_iso_transmit(struct iso_context *ctx,
2882 struct fw_iso_packet *packet,
2883 struct fw_iso_buffer *buffer,
2884 unsigned long payload)
ed568912 2885{
30200739 2886 struct descriptor *d, *last, *pd;
ed568912
KH		 2887 struct fw_iso_packet *p;
2888 __le32 *header;
9aad8125 2889 dma_addr_t d_bus, page_bus;
ed568912
KH		 2890 u32 z, header_z, payload_z, irq;
2891 u32 payload_index, payload_end_index, next_page_index;
30200739 2892 int page, end_page, i, length, offset;
ed568912 2893
ed568912 2894 p = packet;
9aad8125 2895 payload_index = payload;
ed568912
KH		 2896
2897 if (p->skip)
2898 z = 1;
2899 else
2900 z = 2;
2901 if (p->header_length > 0)
2902 z++;
2903
2904 /* Determine the first page the payload isn't contained in. */
2905 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2906 if (p->payload_length > 0)
2907 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2908 else
2909 payload_z = 0;
2910
2911 z += payload_z;
2912
2913 /* Get header size in number of descriptors. */
2d826cc5 2914 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 2915
30200739
KH		 2916 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2917 if (d == NULL)
2918 return -ENOMEM;
ed568912
KH		 2919
2920 if (!p->skip) {
a77754a7 2921 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 2922 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 2923 /*
2924 * Link the skip address to this descriptor itself. This causes
2925 * a context to skip a cycle whenever lost cycles or FIFO
2926 * overruns occur, without dropping the data. The application
2927 * should then decide whether this is an error condition or not.
2928 * FIXME: Make the context's cycle-lost behaviour configurable?
2929 */
2930 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 2931
2932 header = (__le32 *) &d[1];
a77754a7
KH		 2933 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2934 IT_HEADER_TAG(p->tag) |
2935 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2936 IT_HEADER_CHANNEL(ctx->base.channel) |
2937 IT_HEADER_SPEED(ctx->base.speed));
ed568912 2938 header[1] =
a77754a7 2939 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 2940 p->payload_length));
2941 }
2942
2943 if (p->header_length > 0) {
2944 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 2945 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 2946 memcpy(&d[z], p->header, p->header_length);
2947 }
2948
2949 pd = d + z - payload_z;
2950 payload_end_index = payload_index + p->payload_length;
2951 for (i = 0; i < payload_z; i++) {
2952 page = payload_index >> PAGE_SHIFT;
2953 offset = payload_index & ~PAGE_MASK;
2954 next_page_index = (page + 1) << PAGE_SHIFT;
2955 length =
2956 min(next_page_index, payload_end_index) - payload_index;
2957 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 2958
2959 page_bus = page_private(buffer->pages[page]);
2960 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912
KH		 2961
2962 payload_index += length;
2963 }
2964
ed568912 2965 if (p->interrupt)
a77754a7 2966 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 2967 else
a77754a7 2968 irq = DESCRIPTOR_NO_IRQ;
ed568912 2969
30200739 2970 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 2971 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2972 DESCRIPTOR_STATUS |
2973 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 2974 irq);
ed568912 2975
30200739 2976 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 2977
2978 return 0;
2979}
373b2edd 2980
872e330e
SR		 2981static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2982 struct fw_iso_packet *packet,
2983 struct fw_iso_buffer *buffer,
2984 unsigned long payload)
a186b4a6 2985{
8c0c0cc2 2986 struct descriptor *d, *pd;
a186b4a6
JW		 2987 dma_addr_t d_bus, page_bus;
2988 u32 z, header_z, rest;
bcee893c
DM		 2989 int i, j, length;
2990 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 2991
2992 /*
1aa292bb
DM		 2993 * The OHCI controller puts the isochronous header and trailer in the
2994 * buffer, so we need at least 8 bytes.
a186b4a6 2995 */
872e330e 2996 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 2997 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 2998
2999 /* Get header size in number of descriptors. */
3000 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3001 page = payload >> PAGE_SHIFT;
3002 offset = payload & ~PAGE_MASK;
872e330e 3003 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 3004
3005 for (i = 0; i < packet_count; i++) {
3006 /* d points to the header descriptor */
bcee893c 3007 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 3008 d = context_get_descriptors(&ctx->context,
bcee893c 3009 z + header_z, &d_bus);
a186b4a6
JW		 3010 if (d == NULL)
3011 return -ENOMEM;
3012
bcee893c
DM		 3013 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3014 DESCRIPTOR_INPUT_MORE);
872e330e 3015 if (packet->skip && i == 0)
bcee893c 3016 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3017 d->req_count = cpu_to_le16(header_size);
3018 d->res_count = d->req_count;
bcee893c 3019 d->transfer_status = 0;
a186b4a6
JW		 3020 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3021
bcee893c 3022 rest = payload_per_buffer;
8c0c0cc2 3023 pd = d;
bcee893c 3024 for (j = 1; j < z; j++) {
8c0c0cc2 3025 pd++;
bcee893c
DM		 3026 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3027 DESCRIPTOR_INPUT_MORE);
3028
3029 if (offset + rest < PAGE_SIZE)
3030 length = rest;
3031 else
3032 length = PAGE_SIZE - offset;
3033 pd->req_count = cpu_to_le16(length);
3034 pd->res_count = pd->req_count;
3035 pd->transfer_status = 0;
3036
3037 page_bus = page_private(buffer->pages[page]);
3038 pd->data_address = cpu_to_le32(page_bus + offset);
3039
3040 offset = (offset + length) & ~PAGE_MASK;
3041 rest -= length;
3042 if (offset == 0)
3043 page++;
3044 }
a186b4a6
JW		 3045 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3046 DESCRIPTOR_INPUT_LAST |
3047 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3048 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3049 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3050
a186b4a6
JW		 3051 context_append(&ctx->context, d, z, header_z);
3052 }
3053
3054 return 0;
3055}
3056
872e330e
SR		 3057static int queue_iso_buffer_fill(struct iso_context *ctx,
3058 struct fw_iso_packet *packet,
3059 struct fw_iso_buffer *buffer,
3060 unsigned long payload)
3061{
3062 struct descriptor *d;
3063 dma_addr_t d_bus, page_bus;
3064 int page, offset, rest, z, i, length;
3065
3066 page = payload >> PAGE_SHIFT;
3067 offset = payload & ~PAGE_MASK;
3068 rest = packet->payload_length;
3069
3070 /* We need one descriptor for each page in the buffer. */
3071 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3072
3073 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3074 return -EFAULT;
3075
3076 for (i = 0; i < z; i++) {
3077 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3078 if (d == NULL)
3079 return -ENOMEM;
3080
3081 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3082 DESCRIPTOR_BRANCH_ALWAYS);
3083 if (packet->skip && i == 0)
3084 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3085 if (packet->interrupt && i == z - 1)
3086 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3087
3088 if (offset + rest < PAGE_SIZE)
3089 length = rest;
3090 else
3091 length = PAGE_SIZE - offset;
3092 d->req_count = cpu_to_le16(length);
3093 d->res_count = d->req_count;
3094 d->transfer_status = 0;
3095
3096 page_bus = page_private(buffer->pages[page]);
3097 d->data_address = cpu_to_le32(page_bus + offset);
3098
3099 rest -= length;
3100 offset = 0;
3101 page++;
3102
3103 context_append(&ctx->context, d, 1, 0);
3104 }
3105
3106 return 0;
3107}
3108
53dca511
SR		 3109static int ohci_queue_iso(struct fw_iso_context *base,
3110 struct fw_iso_packet *packet,
3111 struct fw_iso_buffer *buffer,
3112 unsigned long payload)
295e3feb 3113{
e364cf4e 3114 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3115 unsigned long flags;
872e330e 3116 int ret = -ENOSYS;
e364cf4e 3117
fe5ca634 3118 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3119 switch (base->type) {
3120 case FW_ISO_CONTEXT_TRANSMIT:
3121 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3122 break;
3123 case FW_ISO_CONTEXT_RECEIVE:
3124 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3125 break;
3126 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3127 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3128 break;
3129 }
fe5ca634
DM		 3130 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3131
2dbd7d7e 3132 return ret;
295e3feb
KH		 3133}
3134
13882a82
CL		 3135static void ohci_flush_queue_iso(struct fw_iso_context *base)
3136{
3137 struct context *ctx =
3138 &container_of(base, struct iso_context, base)->context;
3139
3140 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
13882a82
CL		 3141}
3142
21ebcd12 3143static const struct fw_card_driver ohci_driver = {
ed568912 3144 .enable = ohci_enable,
02d37bed 3145 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3146 .update_phy_reg = ohci_update_phy_reg,
3147 .set_config_rom = ohci_set_config_rom,
3148 .send_request = ohci_send_request,
3149 .send_response = ohci_send_response,
730c32f5 3150 .cancel_packet = ohci_cancel_packet,
ed568912 3151 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3152 .read_csr = ohci_read_csr,
3153 .write_csr = ohci_write_csr,
ed568912
KH		 3154
3155 .allocate_iso_context = ohci_allocate_iso_context,
3156 .free_iso_context = ohci_free_iso_context,
872e330e 3157 .set_iso_channels = ohci_set_iso_channels,
ed568912 3158 .queue_iso = ohci_queue_iso,
13882a82 3159 .flush_queue_iso = ohci_flush_queue_iso,
69cdb726 3160 .start_iso = ohci_start_iso,
b8295668 3161 .stop_iso = ohci_stop_iso,
ed568912
KH		 3162};
3163
ea8d006b 3164#ifdef CONFIG_PPC_PMAC
5da3dac8 3165static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3166{
ea8d006b
SR		 3167 if (machine_is(powermac)) {
3168 struct device_node *ofn = pci_device_to_OF_node(dev);
3169
3170 if (ofn) {
3171 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3172 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3173 }
3174 }
2ed0f181
SR		 3175}
3176
5da3dac8 3177static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3178{
3179 if (machine_is(powermac)) {
3180 struct device_node *ofn = pci_device_to_OF_node(dev);
3181
3182 if (ofn) {
3183 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3184 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3185 }
3186 }
3187}
3188#else
5da3dac8
SR		 3189static inline void pmac_ohci_on(struct pci_dev *dev) {}
3190static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3191#endif /* CONFIG_PPC_PMAC */
3192
53dca511
SR		 3193static int __devinit pci_probe(struct pci_dev *dev,
3194 const struct pci_device_id *ent)
2ed0f181
SR		 3195{
3196 struct fw_ohci *ohci;
aa0170ff 3197 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3198 u64 guid;
dd23736e 3199 int i, err;
2ed0f181
SR		 3200 size_t size;
3201
2d826cc5 3202 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3203 if (ohci == NULL) {
7007a076
SR		 3204 err = -ENOMEM;
3205 goto fail;
ed568912
KH		 3206 }
3207
3208 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3209
5da3dac8 3210 pmac_ohci_on(dev);
130d5496 3211
d79406dd
KH		 3212 err = pci_enable_device(dev);
3213 if (err) {
7007a076 3214 fw_error("Failed to enable OHCI hardware\n");
bd7dee63 3215 goto fail_free;
ed568912
KH		 3216 }
3217
3218 pci_set_master(dev);
3219 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3220 pci_set_drvdata(dev, ohci);
3221
3222 spin_lock_init(&ohci->lock);
02d37bed 3223 mutex_init(&ohci->phy_reg_mutex);
ed568912
KH		 3224
3225 tasklet_init(&ohci->bus_reset_tasklet,
3226 bus_reset_tasklet, (unsigned long)ohci);
3227
d79406dd
KH		 3228 err = pci_request_region(dev, 0, ohci_driver_name);
3229 if (err) {
ed568912 3230 fw_error("MMIO resource unavailable\n");
d79406dd 3231 goto fail_disable;
ed568912
KH		 3232 }
3233
3234 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3235 if (ohci->registers == NULL) {
3236 fw_error("Failed to remap registers\n");
d79406dd
KH		 3237 err = -ENXIO;
3238 goto fail_iomem;
ed568912
KH		 3239 }
3240
4a635593 3241 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3242 if ((ohci_quirks[i].vendor == dev->vendor) &&
3243 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3244 ohci_quirks[i].device == dev->device) &&
3245 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3246 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3247 ohci->quirks = ohci_quirks[i].flags;
3248 break;
3249 }
3e9cc2f3
SR		 3250 if (param_quirks)
3251 ohci->quirks = param_quirks;
b677532b 3252
ec766a79
CL		 3253 /*
3254 * Because dma_alloc_coherent() allocates at least one page,
3255 * we save space by using a common buffer for the AR request/
3256 * response descriptors and the self IDs buffer.
3257 */
3258 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3259 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3260 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3261 PAGE_SIZE,
3262 &ohci->misc_buffer_bus,
3263 GFP_KERNEL);
3264 if (!ohci->misc_buffer) {
3265 err = -ENOMEM;
3266 goto fail_iounmap;
3267 }
3268
3269 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3270 OHCI1394_AsReqRcvContextControlSet);
3271 if (err < 0)
ec766a79 3272 goto fail_misc_buf;
ed568912 3273
ec766a79 3274 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3275 OHCI1394_AsRspRcvContextControlSet);
3276 if (err < 0)
3277 goto fail_arreq_ctx;
ed568912 3278
c088ab30
CL		 3279 err = context_init(&ohci->at_request_ctx, ohci,
3280 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3281 if (err < 0)
3282 goto fail_arrsp_ctx;
ed568912 3283
c088ab30
CL		 3284 err = context_init(&ohci->at_response_ctx, ohci,
3285 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3286 if (err < 0)
3287 goto fail_atreq_ctx;
ed568912 3288
ed568912 3289 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3290 ohci->ir_context_channels = ~0ULL;
f117a3e3 3291 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3292 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3293 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3294 ohci->n_ir = hweight32(ohci->ir_context_mask);
3295 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3296 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3297
3298 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3299 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3300 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3301 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3302 ohci->n_it = hweight32(ohci->it_context_mask);
3303 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3304 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3305
3306 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3307 err = -ENOMEM;
7007a076 3308 goto fail_contexts;
ed568912
KH		 3309 }
3310
ec766a79
CL		 3311 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3312 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3313
ed568912
KH		 3314 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3315 max_receive = (bus_options >> 12) & 0xf;
3316 link_speed = bus_options & 0x7;
3317 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3318 reg_read(ohci, OHCI1394_GUIDLo);
3319
d79406dd 3320 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3321 if (err)
ec766a79 3322 goto fail_contexts;
ed568912 3323
6fdb2ee2
SR		 3324 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3325 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3326 "%d IR + %d IT contexts, quirks 0x%x\n",
3327 dev_name(&dev->dev), version >> 16, version & 0xff,
dd23736e 3328 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3329
ed568912 3330 return 0;
d79406dd 3331
7007a076 3332 fail_contexts:
d79406dd 3333 kfree(ohci->ir_context_list);
7007a076
SR		 3334 kfree(ohci->it_context_list);
3335 context_release(&ohci->at_response_ctx);
c088ab30 3336 fail_atreq_ctx:
7007a076 3337 context_release(&ohci->at_request_ctx);
c088ab30 3338 fail_arrsp_ctx:
7007a076 3339 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3340 fail_arreq_ctx:
7007a076 3341 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3342 fail_misc_buf:
3343 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3344 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3345 fail_iounmap:
d79406dd
KH		 3346 pci_iounmap(dev, ohci->registers);
3347 fail_iomem:
3348 pci_release_region(dev, 0);
3349 fail_disable:
3350 pci_disable_device(dev);
bd7dee63 3351 fail_free:
d838d2c0 3352 kfree(ohci);
5da3dac8 3353 pmac_ohci_off(dev);
7007a076
SR		 3354 fail:
3355 if (err == -ENOMEM)
3356 fw_error("Out of memory\n");
d79406dd
KH		 3357
3358 return err;
ed568912
KH		 3359}
3360
3361static void pci_remove(struct pci_dev *dev)
3362{
3363 struct fw_ohci *ohci;
3364
3365 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3366 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3367 flush_writes(ohci);
ed568912
KH		 3368 fw_core_remove_card(&ohci->card);
3369
c781c06d
KH		 3370 /*
3371 * FIXME: Fail all pending packets here, now that the upper
3372 * layers can't queue any more.
3373 */
ed568912
KH		 3374
3375 software_reset(ohci);
3376 free_irq(dev->irq, ohci);
a55709ba
JF		 3377
3378 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3379 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3380 ohci->next_config_rom, ohci->next_config_rom_bus);
3381 if (ohci->config_rom)
3382 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3383 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3384 ar_context_release(&ohci->ar_request_ctx);
3385 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3386 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3387 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3388 context_release(&ohci->at_request_ctx);
3389 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3390 kfree(ohci->it_context_list);
3391 kfree(ohci->ir_context_list);
262444ee 3392 pci_disable_msi(dev);
d79406dd
KH		 3393 pci_iounmap(dev, ohci->registers);
3394 pci_release_region(dev, 0);
3395 pci_disable_device(dev);
d838d2c0 3396 kfree(ohci);
5da3dac8 3397 pmac_ohci_off(dev);
ea8d006b 3398
ed568912
KH		 3399 fw_notify("Removed fw-ohci device.\n");
3400}
3401
2aef469a 3402#ifdef CONFIG_PM
2ed0f181 3403static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3404{
2ed0f181 3405 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3406 int err;
3407
3408 software_reset(ohci);
2ed0f181 3409 free_irq(dev->irq, ohci);
262444ee 3410 pci_disable_msi(dev);
2ed0f181 3411 err = pci_save_state(dev);
2aef469a 3412 if (err) {
8a8cea27 3413 fw_error("pci_save_state failed\n");
2aef469a
KH		 3414 return err;
3415 }
2ed0f181 3416 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428
SR		 3417 if (err)
3418 fw_error("pci_set_power_state failed with %d\n", err);
5da3dac8 3419 pmac_ohci_off(dev);
ea8d006b 3420
2aef469a
KH		 3421 return 0;
3422}
3423
2ed0f181 3424static int pci_resume(struct pci_dev *dev)
2aef469a 3425{
2ed0f181 3426 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3427 int err;
3428
5da3dac8 3429 pmac_ohci_on(dev);
2ed0f181
SR		 3430 pci_set_power_state(dev, PCI_D0);
3431 pci_restore_state(dev);
3432 err = pci_enable_device(dev);
2aef469a 3433 if (err) {
8a8cea27 3434 fw_error("pci_enable_device failed\n");
2aef469a
KH		 3435 return err;
3436 }
3437
8662b6b0
ML		 3438 /* Some systems don't setup GUID register on resume from ram */
3439 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3440 !reg_read(ohci, OHCI1394_GUIDHi)) {
3441 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3442 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3443 }
3444
dd23736e 3445 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3446 if (err)
3447 return err;
3448
3449 ohci_resume_iso_dma(ohci);
693a50b5 3450
dd23736e 3451 return 0;
2aef469a
KH		 3452}
3453#endif
3454
a67483d2 3455static const struct pci_device_id pci_table[] = {
ed568912
KH		 3456 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3457 { }
3458};
3459
3460MODULE_DEVICE_TABLE(pci, pci_table);
3461
3462static struct pci_driver fw_ohci_pci_driver = {
3463 .name = ohci_driver_name,
3464 .id_table = pci_table,
3465 .probe = pci_probe,
3466 .remove = pci_remove,
2aef469a
KH		 3467#ifdef CONFIG_PM
3468 .resume = pci_resume,
3469 .suspend = pci_suspend,
3470#endif
ed568912
KH		 3471};
3472
3473MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3474MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3475MODULE_LICENSE("GPL");
3476
1e4c7b0d
OH		 3477/* Provide a module alias so root-on-sbp2 initrds don't break. */
3478#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3479MODULE_ALIAS("ohci1394");
3480#endif
3481
ed568912
KH		 3482static int __init fw_ohci_init(void)
3483{
3484 return pci_register_driver(&fw_ohci_pci_driver);
3485}
3486
3487static void __exit fw_ohci_cleanup(void)
3488{
3489 pci_unregister_driver(&fw_ohci_pci_driver);
3490}
3491
3492module_init(fw_ohci_init);
3493module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
This page took 0.745772 seconds and 5 git commands to generate.