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firewire: ohci: work around selfID junk due to wrong gap count
[deliverable/linux.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
2d7a36e2 45#include <linux/workqueue.h>
cf3e72fd 46
e8ca9702 47#include <asm/byteorder.h>
c26f0234 48#include <asm/page.h>
ee71c2f9 49#include <asm/system.h>
ed568912 50
ea8d006b
SR		 51#ifdef CONFIG_PPC_PMAC
52#include <asm/pmac_feature.h>
53#endif
54
77c9a5da
SR		 55#include "core.h"
56#include "ohci.h"
ed568912 57
a77754a7
KH		 58#define DESCRIPTOR_OUTPUT_MORE 0
59#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
60#define DESCRIPTOR_INPUT_MORE (2 << 12)
61#define DESCRIPTOR_INPUT_LAST (3 << 12)
62#define DESCRIPTOR_STATUS (1 << 11)
63#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
64#define DESCRIPTOR_PING (1 << 7)
65#define DESCRIPTOR_YY (1 << 6)
66#define DESCRIPTOR_NO_IRQ (0 << 4)
67#define DESCRIPTOR_IRQ_ERROR (1 << 4)
68#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
69#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
70#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 71
72struct descriptor {
73 __le16 req_count;
74 __le16 control;
75 __le32 data_address;
76 __le32 branch_address;
77 __le16 res_count;
78 __le16 transfer_status;
79} __attribute__((aligned(16)));
80
a77754a7
KH		 81#define CONTROL_SET(regs) (regs)
82#define CONTROL_CLEAR(regs) ((regs) + 4)
83#define COMMAND_PTR(regs) ((regs) + 12)
84#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 85
7a39d8b8
CL		 86#define AR_BUFFER_SIZE (32*1024)
87#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
88/* we need at least two pages for proper list management */
89#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
90
91#define MAX_ASYNC_PAYLOAD 4096
92#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
93#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 94
32b46093
KH		 95struct ar_context {
96 struct fw_ohci *ohci;
7a39d8b8
CL		 97 struct page *pages[AR_BUFFERS];
98 void *buffer;
99 struct descriptor *descriptors;
100 dma_addr_t descriptors_bus;
32b46093 101 void *pointer;
7a39d8b8 102 unsigned int last_buffer_index;
72e318e0 103 u32 regs;
ed568912
KH		 104 struct tasklet_struct tasklet;
105};
106
30200739
KH		 107struct context;
108
109typedef int (*descriptor_callback_t)(struct context *ctx,
110 struct descriptor *d,
111 struct descriptor *last);
fe5ca634
DM		 112
113/*
114 * A buffer that contains a block of DMA-able coherent memory used for
115 * storing a portion of a DMA descriptor program.
116 */
117struct descriptor_buffer {
118 struct list_head list;
119 dma_addr_t buffer_bus;
120 size_t buffer_size;
121 size_t used;
122 struct descriptor buffer[0];
123};
124
30200739 125struct context {
373b2edd 126 struct fw_ohci *ohci;
30200739 127 u32 regs;
fe5ca634 128 int total_allocation;
386a4153 129 bool running;
82b662dc 130 bool flushing;
373b2edd 131
fe5ca634
DM		 132 /*
133 * List of page-sized buffers for storing DMA descriptors.
134 * Head of list contains buffers in use and tail of list contains
135 * free buffers.
136 */
137 struct list_head buffer_list;
138
139 /*
140 * Pointer to a buffer inside buffer_list that contains the tail
141 * end of the current DMA program.
142 */
143 struct descriptor_buffer *buffer_tail;
144
145 /*
146 * The descriptor containing the branch address of the first
147 * descriptor that has not yet been filled by the device.
148 */
149 struct descriptor *last;
150
151 /*
152 * The last descriptor in the DMA program. It contains the branch
153 * address that must be updated upon appending a new descriptor.
154 */
155 struct descriptor *prev;
30200739
KH		 156
157 descriptor_callback_t callback;
158
373b2edd 159 struct tasklet_struct tasklet;
30200739 160};
30200739 161
a77754a7
KH		 162#define IT_HEADER_SY(v) ((v) << 0)
163#define IT_HEADER_TCODE(v) ((v) << 4)
164#define IT_HEADER_CHANNEL(v) ((v) << 8)
165#define IT_HEADER_TAG(v) ((v) << 14)
166#define IT_HEADER_SPEED(v) ((v) << 16)
167#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 168
169struct iso_context {
170 struct fw_iso_context base;
30200739 171 struct context context;
0642b657 172 int excess_bytes;
9b32d5f3
KH		 173 void *header;
174 size_t header_length;
dd23736e
ML		 175
176 u8 sync;
177 u8 tags;
ed568912
KH		 178};
179
180#define CONFIG_ROM_SIZE 1024
181
182struct fw_ohci {
183 struct fw_card card;
184
185 __iomem char *registers;
e636fe25 186 int node_id;
ed568912 187 int generation;
e09770db 188 int request_generation; /* for timestamping incoming requests */
4a635593 189 unsigned quirks;
a1a1132b 190 unsigned int pri_req_max;
a48777e0 191 u32 bus_time;
4ffb7a6a 192 bool is_root;
c8a94ded 193 bool csr_state_setclear_abdicate;
dd23736e
ML		 194 int n_ir;
195 int n_it;
c781c06d
KH		 196 /*
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
199 */
ed568912 200 spinlock_t lock;
ed568912 201
02d37bed
SR		 202 struct mutex phy_reg_mutex;
203
ec766a79
CL		 204 void *misc_buffer;
205 dma_addr_t misc_buffer_bus;
206
ed568912
KH		 207 struct ar_context ar_request_ctx;
208 struct ar_context ar_response_ctx;
f319b6a0
KH		 209 struct context at_request_ctx;
210 struct context at_response_ctx;
ed568912 211
f117a3e3 212 u32 it_context_support;
872e330e 213 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 214 struct iso_context *it_context_list;
872e330e 215 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 216 u32 ir_context_support;
872e330e 217 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 218 struct iso_context *ir_context_list;
872e330e
SR		 219 u64 mc_channels; /* channels in use by the multichannel IR context */
220 bool mc_allocated;
ecb1cf9c
SR		 221
222 __be32 *config_rom;
223 dma_addr_t config_rom_bus;
224 __be32 *next_config_rom;
225 dma_addr_t next_config_rom_bus;
226 __be32 next_header;
227
228 __le32 *self_id_cpu;
229 dma_addr_t self_id_bus;
2d7a36e2 230 struct work_struct bus_reset_work;
ecb1cf9c
SR		 231
232 u32 self_id_buffer[512];
ed568912
KH		 233};
234
95688e97 235static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 236{
237 return container_of(card, struct fw_ohci, card);
238}
239
295e3feb
KH		 240#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
241#define IR_CONTEXT_BUFFER_FILL 0x80000000
242#define IR_CONTEXT_ISOCH_HEADER 0x40000000
243#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
244#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
245#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 246
247#define CONTEXT_RUN 0x8000
248#define CONTEXT_WAKE 0x1000
249#define CONTEXT_DEAD 0x0800
250#define CONTEXT_ACTIVE 0x0400
251
8b7b6afa 252#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 253#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
254#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
255
ed568912 256#define OHCI1394_REGISTER_SIZE 0x800
ed568912
KH		 257#define OHCI1394_PCI_HCI_Control 0x40
258#define SELF_ID_BUF_SIZE 0x800
32b46093 259#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 260#define OHCI_VERSION_1_1 0x010010
0edeefd9 261
ed568912
KH		 262static char ohci_driver_name[] = KBUILD_MODNAME;
263
9993e0fe 264#define PCI_DEVICE_ID_AGERE_FW643 0x5901
262444ee 265#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b 266#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
25935ebe
SG		 267#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
268#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
7f7e3711 269#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
8301b91b 270
4a635593
SR		 271#define QUIRK_CYCLE_TIMER 1
272#define QUIRK_RESET_PACKET 2
273#define QUIRK_BE_HEADERS 4
925e7a65 274#define QUIRK_NO_1394A 8
262444ee 275#define QUIRK_NO_MSI 16
25935ebe 276#define QUIRK_TI_SLLZ059 32
4a635593
SR		 277
278/* In case of multiple matches in ohci_quirks[], only the first one is used. */
279static const struct {
9993e0fe 280 unsigned short vendor, device, revision, flags;
4a635593 281} ohci_quirks[] = {
9993e0fe
SR		 282 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
283 QUIRK_CYCLE_TIMER},
284
285 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
286 QUIRK_BE_HEADERS},
287
288 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
289 QUIRK_NO_MSI},
290
291 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
292 QUIRK_NO_MSI},
293
294 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
295 QUIRK_CYCLE_TIMER},
296
f39aa30d
ML		 297 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
298 QUIRK_NO_MSI},
299
9993e0fe
SR		 300 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
301 QUIRK_CYCLE_TIMER},
302
303 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
304 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
305
25935ebe
SG		 306 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
307 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
308
309 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
310 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
311
9993e0fe
SR		 312 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
313 QUIRK_RESET_PACKET},
314
315 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
316 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 317};
318
3e9cc2f3
SR		 319/* This overrides anything that was found in ohci_quirks[]. */
320static int param_quirks;
321module_param_named(quirks, param_quirks, int, 0644);
322MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
323 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
324 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
325 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 326 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 327 ", disable MSI = " __stringify(QUIRK_NO_MSI)
28897fb7 328 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
3e9cc2f3
SR		 329 ")");
330
a007bb85 331#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 332#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 333#define OHCI_PARAM_DEBUG_IRQS 4
334#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8 335
5da3dac8
SR		 336#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
337
ad3c0fe8
SR		 338static int param_debug;
339module_param_named(debug, param_debug, int, 0644);
340MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 341 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 342 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
343 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
344 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 345 ", or a combination, or all = -1)");
346
347static void log_irqs(u32 evt)
348{
a007bb85
SR		 349 if (likely(!(param_debug &
350 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
351 return;
352
353 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
354 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 355 return;
356
f117a3e3 357 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 358 evt & OHCI1394_selfIDComplete ? " selfID" : "",
359 evt & OHCI1394_RQPkt ? " AR_req" : "",
360 evt & OHCI1394_RSPkt ? " AR_resp" : "",
361 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
362 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
363 evt & OHCI1394_isochRx ? " IR" : "",
364 evt & OHCI1394_isochTx ? " IT" : "",
365 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
366 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 367 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 368 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 369 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 370 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 371 evt & OHCI1394_busReset ? " busReset" : "",
372 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
373 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
374 OHCI1394_respTxComplete | OHCI1394_isochRx |
375 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 376 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
377 OHCI1394_cycleInconsistent |
161b96e7 378 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 379 ? " ?" : "");
380}
381
382static const char *speed[] = {
383 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
384};
385static const char *power[] = {
386 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
387 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
388};
389static const char port[] = { '.', '-', 'p', 'c', };
390
391static char _p(u32 *s, int shift)
392{
393 return port[*s >> shift & 3];
394}
395
08ddb2f4 396static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
ad3c0fe8
SR		 397{
398 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
399 return;
400
161b96e7
SR		 401 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
402 self_id_count, generation, node_id);
ad3c0fe8
SR		 403
404 for (; self_id_count--; ++s)
405 if ((*s & 1 << 23) == 0)
161b96e7
SR		 406 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
407 "%s gc=%d %s %s%s%s\n",
408 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
409 speed[*s >> 14 & 3], *s >> 16 & 63,
410 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
411 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 412 else
161b96e7
SR		 413 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
414 *s, *s >> 24 & 63,
415 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
416 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 417}
418
419static const char *evts[] = {
420 [0x00] = "evt_no_status", [0x01] = "-reserved-",
421 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
422 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
423 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
424 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
425 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
426 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
427 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
428 [0x10] = "-reserved-", [0x11] = "ack_complete",
429 [0x12] = "ack_pending ", [0x13] = "-reserved-",
430 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
431 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
432 [0x18] = "-reserved-", [0x19] = "-reserved-",
433 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
434 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
435 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
436 [0x20] = "pending/cancelled",
437};
438static const char *tcodes[] = {
439 [0x0] = "QW req", [0x1] = "BW req",
440 [0x2] = "W resp", [0x3] = "-reserved-",
441 [0x4] = "QR req", [0x5] = "BR req",
442 [0x6] = "QR resp", [0x7] = "BR resp",
443 [0x8] = "cycle start", [0x9] = "Lk req",
444 [0xa] = "async stream packet", [0xb] = "Lk resp",
445 [0xc] = "-reserved-", [0xd] = "-reserved-",
446 [0xe] = "link internal", [0xf] = "-reserved-",
447};
ad3c0fe8
SR		 448
449static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
450{
451 int tcode = header[0] >> 4 & 0xf;
452 char specific[12];
453
454 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
455 return;
456
457 if (unlikely(evt >= ARRAY_SIZE(evts)))
458 evt = 0x1f;
459
08ddb2f4 460 if (evt == OHCI1394_evt_bus_reset) {
161b96e7
SR		 461 fw_notify("A%c evt_bus_reset, generation %d\n",
462 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 463 return;
464 }
465
ad3c0fe8
SR		 466 switch (tcode) {
467 case 0x0: case 0x6: case 0x8:
468 snprintf(specific, sizeof(specific), " = %08x",
469 be32_to_cpu((__force __be32)header[3]));
470 break;
471 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
472 snprintf(specific, sizeof(specific), " %x,%x",
473 header[3] >> 16, header[3] & 0xffff);
474 break;
475 default:
476 specific[0] = '\0';
477 }
478
479 switch (tcode) {
5b06db16 480 case 0xa:
161b96e7 481 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
ad3c0fe8 482 break;
5b06db16
CL		 483 case 0xe:
484 fw_notify("A%c %s, PHY %08x %08x\n",
485 dir, evts[evt], header[1], header[2]);
486 break;
ad3c0fe8 487 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
161b96e7
SR		 488 fw_notify("A%c spd %x tl %02x, "
489 "%04x -> %04x, %s, "
490 "%s, %04x%08x%s\n",
491 dir, speed, header[0] >> 10 & 0x3f,
492 header[1] >> 16, header[0] >> 16, evts[evt],
493 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 494 break;
495 default:
161b96e7
SR		 496 fw_notify("A%c spd %x tl %02x, "
497 "%04x -> %04x, %s, "
498 "%s%s\n",
499 dir, speed, header[0] >> 10 & 0x3f,
500 header[1] >> 16, header[0] >> 16, evts[evt],
501 tcodes[tcode], specific);
ad3c0fe8
SR		 502 }
503}
504
505#else
506
5da3dac8
SR		 507#define param_debug 0
508static inline void log_irqs(u32 evt) {}
509static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
510static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
ad3c0fe8
SR		 511
512#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
513
95688e97 514static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 515{
516 writel(data, ohci->registers + offset);
517}
518
95688e97 519static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 520{
521 return readl(ohci->registers + offset);
522}
523
95688e97 524static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 525{
526 /* Do a dummy read to flush writes. */
527 reg_read(ohci, OHCI1394_Version);
528}
529
b14c369d
SR		 530/*
531 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
532 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
533 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
534 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
535 */
35d999b1 536static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 537{
4a96b4fc 538 u32 val;
35d999b1 539 int i;
ed568912
KH		 540
541 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 542 for (i = 0; i < 3 + 100; i++) {
35d999b1 543 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 544 if (!~val)
545 return -ENODEV; /* Card was ejected. */
546
35d999b1
SR		 547 if (val & OHCI1394_PhyControl_ReadDone)
548 return OHCI1394_PhyControl_ReadData(val);
549
153e3979
CL		 550 /*
551 * Try a few times without waiting. Sleeping is necessary
552 * only when the link/PHY interface is busy.
553 */
554 if (i >= 3)
555 msleep(1);
ed568912 556 }
35d999b1 557 fw_error("failed to read phy reg\n");
ed568912 558
35d999b1
SR		 559 return -EBUSY;
560}
4a96b4fc 561
35d999b1
SR		 562static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
563{
564 int i;
ed568912 565
ed568912 566 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 567 OHCI1394_PhyControl_Write(addr, val));
153e3979 568 for (i = 0; i < 3 + 100; i++) {
35d999b1 569 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 570 if (!~val)
571 return -ENODEV; /* Card was ejected. */
572
35d999b1
SR		 573 if (!(val & OHCI1394_PhyControl_WritePending))
574 return 0;
ed568912 575
153e3979
CL		 576 if (i >= 3)
577 msleep(1);
35d999b1
SR		 578 }
579 fw_error("failed to write phy reg\n");
580
581 return -EBUSY;
4a96b4fc
CL		 582}
583
02d37bed
SR		 584static int update_phy_reg(struct fw_ohci *ohci, int addr,
585 int clear_bits, int set_bits)
4a96b4fc 586{
02d37bed 587 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 588 if (ret < 0)
589 return ret;
4a96b4fc 590
e7014dad
CL		 591 /*
592 * The interrupt status bits are cleared by writing a one bit.
593 * Avoid clearing them unless explicitly requested in set_bits.
594 */
595 if (addr == 5)
596 clear_bits |= PHY_INT_STATUS_BITS;
597
35d999b1 598 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 599}
600
35d999b1 601static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 602{
35d999b1 603 int ret;
925e7a65 604
02d37bed 605 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 606 if (ret < 0)
607 return ret;
925e7a65 608
35d999b1 609 return read_phy_reg(ohci, addr);
ed568912
KH		 610}
611
02d37bed
SR		 612static int ohci_read_phy_reg(struct fw_card *card, int addr)
613{
614 struct fw_ohci *ohci = fw_ohci(card);
615 int ret;
616
617 mutex_lock(&ohci->phy_reg_mutex);
618 ret = read_phy_reg(ohci, addr);
619 mutex_unlock(&ohci->phy_reg_mutex);
620
621 return ret;
622}
623
624static int ohci_update_phy_reg(struct fw_card *card, int addr,
625 int clear_bits, int set_bits)
626{
627 struct fw_ohci *ohci = fw_ohci(card);
628 int ret;
629
630 mutex_lock(&ohci->phy_reg_mutex);
631 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
632 mutex_unlock(&ohci->phy_reg_mutex);
633
634 return ret;
ed568912
KH		 635}
636
7a39d8b8
CL		 637static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
638{
639 return page_private(ctx->pages[i]);
640}
641
642static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 643{
7a39d8b8 644 struct descriptor *d;
32b46093 645
7a39d8b8
CL		 646 d = &ctx->descriptors[index];
647 d->branch_address &= cpu_to_le32(~0xf);
648 d->res_count = cpu_to_le16(PAGE_SIZE);
649 d->transfer_status = 0;
32b46093 650
071595eb 651 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 652 d = &ctx->descriptors[ctx->last_buffer_index];
653 d->branch_address |= cpu_to_le32(1);
654
655 ctx->last_buffer_index = index;
32b46093 656
a77754a7 657 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
837596a6
CL		 658}
659
7a39d8b8 660static void ar_context_release(struct ar_context *ctx)
837596a6 661{
7a39d8b8 662 unsigned int i;
837596a6 663
7a39d8b8
CL		 664 if (ctx->buffer)
665 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 666
7a39d8b8
CL		 667 for (i = 0; i < AR_BUFFERS; i++)
668 if (ctx->pages[i]) {
669 dma_unmap_page(ctx->ohci->card.device,
670 ar_buffer_bus(ctx, i),
671 PAGE_SIZE, DMA_FROM_DEVICE);
672 __free_page(ctx->pages[i]);
673 }
ed568912
KH		 674}
675
7a39d8b8 676static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 677{
7a39d8b8
CL		 678 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
679 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
680 flush_writes(ctx->ohci);
a55709ba 681
7a39d8b8 682 fw_error("AR error: %s; DMA stopped\n", error_msg);
a55709ba 683 }
7a39d8b8
CL		 684 /* FIXME: restart? */
685}
686
687static inline unsigned int ar_next_buffer_index(unsigned int index)
688{
689 return (index + 1) % AR_BUFFERS;
690}
691
692static inline unsigned int ar_prev_buffer_index(unsigned int index)
693{
694 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
695}
696
697static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
698{
699 return ar_next_buffer_index(ctx->last_buffer_index);
700}
701
702/*
703 * We search for the buffer that contains the last AR packet DMA data written
704 * by the controller.
705 */
706static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
707 unsigned int *buffer_offset)
708{
709 unsigned int i, next_i, last = ctx->last_buffer_index;
710 __le16 res_count, next_res_count;
711
712 i = ar_first_buffer_index(ctx);
713 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
714
715 /* A buffer that is not yet completely filled must be the last one. */
716 while (i != last && res_count == 0) {
717
718 /* Peek at the next descriptor. */
719 next_i = ar_next_buffer_index(i);
720 rmb(); /* read descriptors in order */
721 next_res_count = ACCESS_ONCE(
722 ctx->descriptors[next_i].res_count);
723 /*
724 * If the next descriptor is still empty, we must stop at this
725 * descriptor.
726 */
727 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
728 /*
729 * The exception is when the DMA data for one packet is
730 * split over three buffers; in this case, the middle
731 * buffer's descriptor might be never updated by the
732 * controller and look still empty, and we have to peek
733 * at the third one.
734 */
735 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
736 next_i = ar_next_buffer_index(next_i);
737 rmb();
738 next_res_count = ACCESS_ONCE(
739 ctx->descriptors[next_i].res_count);
740 if (next_res_count != cpu_to_le16(PAGE_SIZE))
741 goto next_buffer_is_active;
742 }
743
744 break;
745 }
746
747next_buffer_is_active:
748 i = next_i;
749 res_count = next_res_count;
750 }
751
752 rmb(); /* read res_count before the DMA data */
753
754 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
755 if (*buffer_offset > PAGE_SIZE) {
756 *buffer_offset = 0;
757 ar_context_abort(ctx, "corrupted descriptor");
758 }
759
760 return i;
761}
762
763static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
764 unsigned int end_buffer_index,
765 unsigned int end_buffer_offset)
766{
767 unsigned int i;
768
769 i = ar_first_buffer_index(ctx);
770 while (i != end_buffer_index) {
771 dma_sync_single_for_cpu(ctx->ohci->card.device,
772 ar_buffer_bus(ctx, i),
773 PAGE_SIZE, DMA_FROM_DEVICE);
774 i = ar_next_buffer_index(i);
775 }
776 if (end_buffer_offset > 0)
777 dma_sync_single_for_cpu(ctx->ohci->card.device,
778 ar_buffer_bus(ctx, i),
779 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 780}
781
11bf20ad
SR		 782#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
783#define cond_le32_to_cpu(v) \
4a635593 784 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 785#else
786#define cond_le32_to_cpu(v) le32_to_cpu(v)
787#endif
788
32b46093 789static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 790{
ed568912 791 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 792 struct fw_packet p;
793 u32 status, length, tcode;
43286568 794 int evt;
2639a6fb 795
11bf20ad
SR		 796 p.header[0] = cond_le32_to_cpu(buffer[0]);
797 p.header[1] = cond_le32_to_cpu(buffer[1]);
798 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 799
800 tcode = (p.header[0] >> 4) & 0x0f;
801 switch (tcode) {
802 case TCODE_WRITE_QUADLET_REQUEST:
803 case TCODE_READ_QUADLET_RESPONSE:
32b46093 804 p.header[3] = (__force __u32) buffer[3];
2639a6fb 805 p.header_length = 16;
32b46093 806 p.payload_length = 0;
2639a6fb
KH		 807 break;
808
2639a6fb 809 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 810 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 811 p.header_length = 16;
812 p.payload_length = 0;
813 break;
814
815 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 816 case TCODE_READ_BLOCK_RESPONSE:
817 case TCODE_LOCK_REQUEST:
818 case TCODE_LOCK_RESPONSE:
11bf20ad 819 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 820 p.header_length = 16;
32b46093 821 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 822 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
823 ar_context_abort(ctx, "invalid packet length");
824 return NULL;
825 }
2639a6fb
KH		 826 break;
827
828 case TCODE_WRITE_RESPONSE:
829 case TCODE_READ_QUADLET_REQUEST:
32b46093 830 case OHCI_TCODE_PHY_PACKET:
2639a6fb 831 p.header_length = 12;
32b46093 832 p.payload_length = 0;
2639a6fb 833 break;
ccff9629
SR		 834
835 default:
7a39d8b8
CL		 836 ar_context_abort(ctx, "invalid tcode");
837 return NULL;
2639a6fb 838 }
ed568912 839
32b46093
KH		 840 p.payload = (void *) buffer + p.header_length;
841
842 /* FIXME: What to do about evt_* errors? */
843 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 844 status = cond_le32_to_cpu(buffer[length]);
43286568 845 evt = (status >> 16) & 0x1f;
32b46093 846
43286568 847 p.ack = evt - 16;
32b46093
KH		 848 p.speed = (status >> 21) & 0x7;
849 p.timestamp = status & 0xffff;
850 p.generation = ohci->request_generation;
ed568912 851
43286568 852 log_ar_at_event('R', p.speed, p.header, evt);
ad3c0fe8 853
c781c06d 854 /*
a4dc090b
SR		 855 * Several controllers, notably from NEC and VIA, forget to
856 * write ack_complete status at PHY packet reception.
857 */
858 if (evt == OHCI1394_evt_no_status &&
859 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
860 p.ack = ACK_COMPLETE;
861
862 /*
863 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 864 * the new generation number when a bus reset happens (see
865 * section 8.4.2.3). This helps us determine when a request
866 * was received and make sure we send the response in the same
867 * generation. We only need this for requests; for responses
868 * we use the unique tlabel for finding the matching
c781c06d 869 * request.
d34316a4
SR		 870 *
871 * Alas some chips sometimes emit bus reset packets with a
872 * wrong generation. We set the correct generation for these
2d7a36e2 873 * at a slightly incorrect time (in bus_reset_work).
c781c06d 874 */
d34316a4 875 if (evt == OHCI1394_evt_bus_reset) {
4a635593 876 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 877 ohci->request_generation = (p.header[2] >> 16) & 0xff;
878 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 879 fw_core_handle_request(&ohci->card, &p);
d34316a4 880 } else {
2639a6fb 881 fw_core_handle_response(&ohci->card, &p);
d34316a4 882 }
ed568912 883
32b46093
KH		 884 return buffer + length + 1;
885}
ed568912 886
7a39d8b8
CL		 887static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
888{
889 void *next;
890
891 while (p < end) {
892 next = handle_ar_packet(ctx, p);
893 if (!next)
894 return p;
895 p = next;
896 }
897
898 return p;
899}
900
901static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
902{
903 unsigned int i;
904
905 i = ar_first_buffer_index(ctx);
906 while (i != end_buffer) {
907 dma_sync_single_for_device(ctx->ohci->card.device,
908 ar_buffer_bus(ctx, i),
909 PAGE_SIZE, DMA_FROM_DEVICE);
910 ar_context_link_page(ctx, i);
911 i = ar_next_buffer_index(i);
912 }
913}
914
32b46093
KH		 915static void ar_context_tasklet(unsigned long data)
916{
917 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 918 unsigned int end_buffer_index, end_buffer_offset;
919 void *p, *end;
32b46093 920
7a39d8b8
CL		 921 p = ctx->pointer;
922 if (!p)
923 return;
32b46093 924
7a39d8b8
CL		 925 end_buffer_index = ar_search_last_active_buffer(ctx,
926 &end_buffer_offset);
927 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
928 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 929
7a39d8b8 930 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 931 /*
7a39d8b8
CL		 932 * The filled part of the overall buffer wraps around; handle
933 * all packets up to the buffer end here. If the last packet
934 * wraps around, its tail will be visible after the buffer end
935 * because the buffer start pages are mapped there again.
c781c06d 936 */
7a39d8b8
CL		 937 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
938 p = handle_ar_packets(ctx, p, buffer_end);
939 if (p < buffer_end)
940 goto error;
941 /* adjust p to point back into the actual buffer */
942 p -= AR_BUFFERS * PAGE_SIZE;
943 }
32b46093 944
7a39d8b8
CL		 945 p = handle_ar_packets(ctx, p, end);
946 if (p != end) {
947 if (p > end)
948 ar_context_abort(ctx, "inconsistent descriptor");
949 goto error;
950 }
32b46093 951
7a39d8b8
CL		 952 ctx->pointer = p;
953 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 954
7a39d8b8 955 return;
a1f805e5 956
7a39d8b8
CL		 957error:
958 ctx->pointer = NULL;
ed568912
KH		 959}
960
ec766a79
CL		 961static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
962 unsigned int descriptors_offset, u32 regs)
ed568912 963{
7a39d8b8
CL		 964 unsigned int i;
965 dma_addr_t dma_addr;
966 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
967 struct descriptor *d;
ed568912 968
72e318e0
KH		 969 ctx->regs = regs;
970 ctx->ohci = ohci;
ed568912
KH		 971 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
972
7a39d8b8
CL		 973 for (i = 0; i < AR_BUFFERS; i++) {
974 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
975 if (!ctx->pages[i])
976 goto out_of_memory;
977 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
978 0, PAGE_SIZE, DMA_FROM_DEVICE);
979 if (dma_mapping_error(ohci->card.device, dma_addr)) {
980 __free_page(ctx->pages[i]);
981 ctx->pages[i] = NULL;
982 goto out_of_memory;
983 }
984 set_page_private(ctx->pages[i], dma_addr);
985 }
986
987 for (i = 0; i < AR_BUFFERS; i++)
988 pages[i] = ctx->pages[i];
989 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
990 pages[AR_BUFFERS + i] = ctx->pages[i];
991 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
14271304 992 -1, PAGE_KERNEL);
7a39d8b8
CL		 993 if (!ctx->buffer)
994 goto out_of_memory;
995
ec766a79
CL		 996 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
997 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 998
999 for (i = 0; i < AR_BUFFERS; i++) {
1000 d = &ctx->descriptors[i];
1001 d->req_count = cpu_to_le16(PAGE_SIZE);
1002 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1003 DESCRIPTOR_STATUS |
1004 DESCRIPTOR_BRANCH_ALWAYS);
1005 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1006 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1007 ar_next_buffer_index(i) * sizeof(struct descriptor));
1008 }
32b46093 1009
2aef469a 1010 return 0;
7a39d8b8
CL		 1011
1012out_of_memory:
1013 ar_context_release(ctx);
1014
1015 return -ENOMEM;
2aef469a
KH		 1016}
1017
1018static void ar_context_run(struct ar_context *ctx)
1019{
7a39d8b8
CL		 1020 unsigned int i;
1021
1022 for (i = 0; i < AR_BUFFERS; i++)
1023 ar_context_link_page(ctx, i);
2aef469a 1024
7a39d8b8 1025 ctx->pointer = ctx->buffer;
2aef469a 1026
7a39d8b8 1027 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1028 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
ed568912 1029}
373b2edd 1030
53dca511 1031static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1032{
0ff8fbc6 1033 __le16 branch;
a186b4a6 1034
0ff8fbc6 1035 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1036
1037 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1038 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1039 return d;
1040 else
1041 return d + z - 1;
1042}
1043
30200739
KH		 1044static void context_tasklet(unsigned long data)
1045{
1046 struct context *ctx = (struct context *) data;
30200739
KH		 1047 struct descriptor *d, *last;
1048 u32 address;
1049 int z;
fe5ca634 1050 struct descriptor_buffer *desc;
30200739 1051
fe5ca634
DM		 1052 desc = list_entry(ctx->buffer_list.next,
1053 struct descriptor_buffer, list);
1054 last = ctx->last;
30200739 1055 while (last->branch_address != 0) {
fe5ca634 1056 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1057 address = le32_to_cpu(last->branch_address);
1058 z = address & 0xf;
fe5ca634
DM		 1059 address &= ~0xf;
1060
1061 /* If the branch address points to a buffer outside of the
1062 * current buffer, advance to the next buffer. */
1063 if (address < desc->buffer_bus ||
1064 address >= desc->buffer_bus + desc->used)
1065 desc = list_entry(desc->list.next,
1066 struct descriptor_buffer, list);
1067 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1068 last = find_branch_descriptor(d, z);
30200739
KH		 1069
1070 if (!ctx->callback(ctx, d, last))
1071 break;
1072
fe5ca634
DM		 1073 if (old_desc != desc) {
1074 /* If we've advanced to the next buffer, move the
1075 * previous buffer to the free list. */
1076 unsigned long flags;
1077 old_desc->used = 0;
1078 spin_lock_irqsave(&ctx->ohci->lock, flags);
1079 list_move_tail(&old_desc->list, &ctx->buffer_list);
1080 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1081 }
1082 ctx->last = last;
30200739
KH		 1083 }
1084}
1085
fe5ca634
DM		 1086/*
1087 * Allocate a new buffer and add it to the list of free buffers for this
1088 * context. Must be called with ohci->lock held.
1089 */
53dca511 1090static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1091{
1092 struct descriptor_buffer *desc;
f5101d58 1093 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1094 int offset;
1095
1096 /*
1097 * 16MB of descriptors should be far more than enough for any DMA
1098 * program. This will catch run-away userspace or DoS attacks.
1099 */
1100 if (ctx->total_allocation >= 16*1024*1024)
1101 return -ENOMEM;
1102
1103 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1104 &bus_addr, GFP_ATOMIC);
1105 if (!desc)
1106 return -ENOMEM;
1107
1108 offset = (void *)&desc->buffer - (void *)desc;
1109 desc->buffer_size = PAGE_SIZE - offset;
1110 desc->buffer_bus = bus_addr + offset;
1111 desc->used = 0;
1112
1113 list_add_tail(&desc->list, &ctx->buffer_list);
1114 ctx->total_allocation += PAGE_SIZE;
1115
1116 return 0;
1117}
1118
53dca511
SR		 1119static int context_init(struct context *ctx, struct fw_ohci *ohci,
1120 u32 regs, descriptor_callback_t callback)
30200739
KH		 1121{
1122 ctx->ohci = ohci;
1123 ctx->regs = regs;
fe5ca634
DM		 1124 ctx->total_allocation = 0;
1125
1126 INIT_LIST_HEAD(&ctx->buffer_list);
1127 if (context_add_buffer(ctx) < 0)
30200739
KH		 1128 return -ENOMEM;
1129
fe5ca634
DM		 1130 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1131 struct descriptor_buffer, list);
1132
30200739
KH		 1133 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1134 ctx->callback = callback;
1135
c781c06d
KH		 1136 /*
1137 * We put a dummy descriptor in the buffer that has a NULL
30200739 1138 * branch address and looks like it's been sent. That way we
fe5ca634 1139 * have a descriptor to append DMA programs to.
c781c06d 1140 */
fe5ca634
DM		 1141 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1142 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1143 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1144 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1145 ctx->last = ctx->buffer_tail->buffer;
1146 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1147
1148 return 0;
1149}
1150
53dca511 1151static void context_release(struct context *ctx)
30200739
KH		 1152{
1153 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1154 struct descriptor_buffer *desc, *tmp;
30200739 1155
fe5ca634
DM		 1156 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1157 dma_free_coherent(card->device, PAGE_SIZE, desc,
1158 desc->buffer_bus -
1159 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1160}
1161
fe5ca634 1162/* Must be called with ohci->lock held */
53dca511
SR		 1163static struct descriptor *context_get_descriptors(struct context *ctx,
1164 int z, dma_addr_t *d_bus)
30200739 1165{
fe5ca634
DM		 1166 struct descriptor *d = NULL;
1167 struct descriptor_buffer *desc = ctx->buffer_tail;
1168
1169 if (z * sizeof(*d) > desc->buffer_size)
1170 return NULL;
1171
1172 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1173 /* No room for the descriptor in this buffer, so advance to the
1174 * next one. */
30200739 1175
fe5ca634
DM		 1176 if (desc->list.next == &ctx->buffer_list) {
1177 /* If there is no free buffer next in the list,
1178 * allocate one. */
1179 if (context_add_buffer(ctx) < 0)
1180 return NULL;
1181 }
1182 desc = list_entry(desc->list.next,
1183 struct descriptor_buffer, list);
1184 ctx->buffer_tail = desc;
1185 }
30200739 1186
fe5ca634 1187 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1188 memset(d, 0, z * sizeof(*d));
fe5ca634 1189 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1190
1191 return d;
1192}
1193
295e3feb 1194static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1195{
1196 struct fw_ohci *ohci = ctx->ohci;
1197
a77754a7 1198 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1199 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1200 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1201 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1202 ctx->running = true;
30200739
KH		 1203 flush_writes(ohci);
1204}
1205
1206static void context_append(struct context *ctx,
1207 struct descriptor *d, int z, int extra)
1208{
1209 dma_addr_t d_bus;
fe5ca634 1210 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1211
fe5ca634 1212 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1213
fe5ca634 1214 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1215
1216 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1217 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1218 ctx->prev = find_branch_descriptor(d, z);
30200739
KH		 1219}
1220
1221static void context_stop(struct context *ctx)
1222{
1223 u32 reg;
b8295668 1224 int i;
30200739 1225
a77754a7 1226 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1227 ctx->running = false;
30200739 1228
9ef28ccd 1229 for (i = 0; i < 1000; i++) {
a77754a7 1230 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
b8295668 1231 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1232 return;
b8295668 1233
9ef28ccd
SR		 1234 if (i)
1235 udelay(10);
b8295668 1236 }
b0068549 1237 fw_error("Error: DMA context still active (0x%08x)\n", reg);
30200739 1238}
ed568912 1239
f319b6a0 1240struct driver_data {
da28947e 1241 u8 inline_data[8];
f319b6a0
KH		 1242 struct fw_packet *packet;
1243};
ed568912 1244
c781c06d
KH		 1245/*
1246 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1247 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1248 * generation handling and locking around packet queue manipulation.
1249 */
53dca511
SR		 1250static int at_context_queue_packet(struct context *ctx,
1251 struct fw_packet *packet)
ed568912 1252{
ed568912 1253 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1254 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1255 struct driver_data *driver_data;
1256 struct descriptor *d, *last;
1257 __le32 *header;
ed568912
KH		 1258 int z, tcode;
1259
f319b6a0
KH		 1260 d = context_get_descriptors(ctx, 4, &d_bus);
1261 if (d == NULL) {
1262 packet->ack = RCODE_SEND_ERROR;
1263 return -1;
ed568912
KH		 1264 }
1265
a77754a7 1266 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1267 d[0].res_count = cpu_to_le16(packet->timestamp);
1268
c781c06d
KH		 1269 /*
1270 * The DMA format for asyncronous link packets is different
ed568912 1271 * from the IEEE1394 layout, so shift the fields around
5b06db16 1272 * accordingly.
c781c06d 1273 */
f319b6a0 1274
5b06db16 1275 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1276 header = (__le32 *) &d[1];
5b06db16
CL		 1277 switch (tcode) {
1278 case TCODE_WRITE_QUADLET_REQUEST:
1279 case TCODE_WRITE_BLOCK_REQUEST:
1280 case TCODE_WRITE_RESPONSE:
1281 case TCODE_READ_QUADLET_REQUEST:
1282 case TCODE_READ_BLOCK_REQUEST:
1283 case TCODE_READ_QUADLET_RESPONSE:
1284 case TCODE_READ_BLOCK_RESPONSE:
1285 case TCODE_LOCK_REQUEST:
1286 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1287 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1288 (packet->speed << 16));
1289 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1290 (packet->header[0] & 0xffff0000));
1291 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1292
ed568912 1293 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1294 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1295 else
f319b6a0
KH		 1296 header[3] = (__force __le32) packet->header[3];
1297
1298 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1299 break;
1300
5b06db16 1301 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1302 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1303 (packet->speed << 16));
5b06db16
CL		 1304 header[1] = cpu_to_le32(packet->header[1]);
1305 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1306 d[0].req_count = cpu_to_le16(12);
cc550216 1307
5b06db16 1308 if (is_ping_packet(&packet->header[1]))
cc550216 1309 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1310 break;
1311
5b06db16 1312 case TCODE_STREAM_DATA:
f8c2287c
JF		 1313 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1314 (packet->speed << 16));
1315 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1316 d[0].req_count = cpu_to_le16(8);
1317 break;
1318
1319 default:
1320 /* BUG(); */
1321 packet->ack = RCODE_SEND_ERROR;
1322 return -1;
ed568912
KH		 1323 }
1324
da28947e 1325 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1326 driver_data = (struct driver_data *) &d[3];
1327 driver_data->packet = packet;
20d11673 1328 packet->driver_data = driver_data;
a186b4a6 1329
f319b6a0 1330 if (packet->payload_length > 0) {
da28947e
CL		 1331 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1332 payload_bus = dma_map_single(ohci->card.device,
1333 packet->payload,
1334 packet->payload_length,
1335 DMA_TO_DEVICE);
1336 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1337 packet->ack = RCODE_SEND_ERROR;
1338 return -1;
1339 }
1340 packet->payload_bus = payload_bus;
1341 packet->payload_mapped = true;
1342 } else {
1343 memcpy(driver_data->inline_data, packet->payload,
1344 packet->payload_length);
1345 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1346 }
1347
1348 d[2].req_count = cpu_to_le16(packet->payload_length);
1349 d[2].data_address = cpu_to_le32(payload_bus);
1350 last = &d[2];
1351 z = 3;
ed568912 1352 } else {
f319b6a0
KH		 1353 last = &d[0];
1354 z = 2;
ed568912 1355 }
ed568912 1356
a77754a7
KH		 1357 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1358 DESCRIPTOR_IRQ_ALWAYS |
1359 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1360
b6258fc1
SR		 1361 /* FIXME: Document how the locking works. */
1362 if (ohci->generation != packet->generation) {
19593ffd 1363 if (packet->payload_mapped)
ab88ca48
SR		 1364 dma_unmap_single(ohci->card.device, payload_bus,
1365 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1366 packet->ack = RCODE_GENERATION;
1367 return -1;
1368 }
1369
1370 context_append(ctx, d, z, 4 - z);
ed568912 1371
dd6254e5 1372 if (ctx->running)
13882a82 1373 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
dd6254e5 1374 else
f319b6a0
KH		 1375 context_run(ctx, 0);
1376
1377 return 0;
ed568912
KH		 1378}
1379
82b662dc
CL		 1380static void at_context_flush(struct context *ctx)
1381{
1382 tasklet_disable(&ctx->tasklet);
1383
1384 ctx->flushing = true;
1385 context_tasklet((unsigned long)ctx);
1386 ctx->flushing = false;
1387
1388 tasklet_enable(&ctx->tasklet);
1389}
1390
f319b6a0
KH		 1391static int handle_at_packet(struct context *context,
1392 struct descriptor *d,
1393 struct descriptor *last)
ed568912 1394{
f319b6a0 1395 struct driver_data *driver_data;
ed568912 1396 struct fw_packet *packet;
f319b6a0 1397 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1398 int evt;
1399
82b662dc 1400 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1401 /* This descriptor isn't done yet, stop iteration. */
1402 return 0;
ed568912 1403
f319b6a0
KH		 1404 driver_data = (struct driver_data *) &d[3];
1405 packet = driver_data->packet;
1406 if (packet == NULL)
1407 /* This packet was cancelled, just continue. */
1408 return 1;
730c32f5 1409
19593ffd 1410 if (packet->payload_mapped)
1d1dc5e8 1411 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1412 packet->payload_length, DMA_TO_DEVICE);
ed568912 1413
f319b6a0
KH		 1414 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1415 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1416
ad3c0fe8
SR		 1417 log_ar_at_event('T', packet->speed, packet->header, evt);
1418
f319b6a0
KH		 1419 switch (evt) {
1420 case OHCI1394_evt_timeout:
1421 /* Async response transmit timed out. */
1422 packet->ack = RCODE_CANCELLED;
1423 break;
ed568912 1424
f319b6a0 1425 case OHCI1394_evt_flushed:
c781c06d
KH		 1426 /*
1427 * The packet was flushed should give same error as
1428 * when we try to use a stale generation count.
1429 */
f319b6a0
KH		 1430 packet->ack = RCODE_GENERATION;
1431 break;
ed568912 1432
f319b6a0 1433 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1434 if (context->flushing)
1435 packet->ack = RCODE_GENERATION;
1436 else {
1437 /*
1438 * Using a valid (current) generation count, but the
1439 * node is not on the bus or not sending acks.
1440 */
1441 packet->ack = RCODE_NO_ACK;
1442 }
f319b6a0 1443 break;
ed568912 1444
f319b6a0
KH		 1445 case ACK_COMPLETE + 0x10:
1446 case ACK_PENDING + 0x10:
1447 case ACK_BUSY_X + 0x10:
1448 case ACK_BUSY_A + 0x10:
1449 case ACK_BUSY_B + 0x10:
1450 case ACK_DATA_ERROR + 0x10:
1451 case ACK_TYPE_ERROR + 0x10:
1452 packet->ack = evt - 0x10;
1453 break;
ed568912 1454
82b662dc
CL		 1455 case OHCI1394_evt_no_status:
1456 if (context->flushing) {
1457 packet->ack = RCODE_GENERATION;
1458 break;
1459 }
1460 /* fall through */
1461
f319b6a0
KH		 1462 default:
1463 packet->ack = RCODE_SEND_ERROR;
1464 break;
1465 }
ed568912 1466
f319b6a0 1467 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1468
f319b6a0 1469 return 1;
ed568912
KH		 1470}
1471
a77754a7
KH		 1472#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1473#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1474#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1475#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1476#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1477
53dca511
SR		 1478static void handle_local_rom(struct fw_ohci *ohci,
1479 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1480{
1481 struct fw_packet response;
1482 int tcode, length, i;
1483
a77754a7 1484 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1485 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1486 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1487 else
1488 length = 4;
1489
1490 i = csr - CSR_CONFIG_ROM;
1491 if (i + length > CONFIG_ROM_SIZE) {
1492 fw_fill_response(&response, packet->header,
1493 RCODE_ADDRESS_ERROR, NULL, 0);
1494 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1495 fw_fill_response(&response, packet->header,
1496 RCODE_TYPE_ERROR, NULL, 0);
1497 } else {
1498 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1499 (void *) ohci->config_rom + i, length);
1500 }
1501
1502 fw_core_handle_response(&ohci->card, &response);
1503}
1504
53dca511
SR		 1505static void handle_local_lock(struct fw_ohci *ohci,
1506 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1507{
1508 struct fw_packet response;
e1393667 1509 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1510 __be32 *payload, lock_old;
1511 u32 lock_arg, lock_data;
1512
a77754a7
KH		 1513 tcode = HEADER_GET_TCODE(packet->header[0]);
1514 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1515 payload = packet->payload;
a77754a7 1516 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1517
1518 if (tcode == TCODE_LOCK_REQUEST &&
1519 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1520 lock_arg = be32_to_cpu(payload[0]);
1521 lock_data = be32_to_cpu(payload[1]);
1522 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1523 lock_arg = 0;
1524 lock_data = 0;
1525 } else {
1526 fw_fill_response(&response, packet->header,
1527 RCODE_TYPE_ERROR, NULL, 0);
1528 goto out;
1529 }
1530
1531 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1532 reg_write(ohci, OHCI1394_CSRData, lock_data);
1533 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1534 reg_write(ohci, OHCI1394_CSRControl, sel);
1535
e1393667
CL		 1536 for (try = 0; try < 20; try++)
1537 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1538 lock_old = cpu_to_be32(reg_read(ohci,
1539 OHCI1394_CSRData));
1540 fw_fill_response(&response, packet->header,
1541 RCODE_COMPLETE,
1542 &lock_old, sizeof(lock_old));
1543 goto out;
1544 }
1545
1546 fw_error("swap not done (CSR lock timeout)\n");
1547 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1548
93c4cceb
KH		 1549 out:
1550 fw_core_handle_response(&ohci->card, &response);
1551}
1552
53dca511 1553static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1554{
2608203d 1555 u64 offset, csr;
93c4cceb 1556
473d28c7
KH		 1557 if (ctx == &ctx->ohci->at_request_ctx) {
1558 packet->ack = ACK_PENDING;
1559 packet->callback(packet, &ctx->ohci->card, packet->ack);
1560 }
93c4cceb
KH		 1561
1562 offset =
1563 ((unsigned long long)
a77754a7 1564 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1565 packet->header[2];
1566 csr = offset - CSR_REGISTER_BASE;
1567
1568 /* Handle config rom reads. */
1569 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1570 handle_local_rom(ctx->ohci, packet, csr);
1571 else switch (csr) {
1572 case CSR_BUS_MANAGER_ID:
1573 case CSR_BANDWIDTH_AVAILABLE:
1574 case CSR_CHANNELS_AVAILABLE_HI:
1575 case CSR_CHANNELS_AVAILABLE_LO:
1576 handle_local_lock(ctx->ohci, packet, csr);
1577 break;
1578 default:
1579 if (ctx == &ctx->ohci->at_request_ctx)
1580 fw_core_handle_request(&ctx->ohci->card, packet);
1581 else
1582 fw_core_handle_response(&ctx->ohci->card, packet);
1583 break;
1584 }
473d28c7
KH		 1585
1586 if (ctx == &ctx->ohci->at_response_ctx) {
1587 packet->ack = ACK_COMPLETE;
1588 packet->callback(packet, &ctx->ohci->card, packet->ack);
1589 }
93c4cceb 1590}
e636fe25 1591
53dca511 1592static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1593{
ed568912 1594 unsigned long flags;
2dbd7d7e 1595 int ret;
ed568912
KH		 1596
1597 spin_lock_irqsave(&ctx->ohci->lock, flags);
1598
a77754a7 1599 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1600 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1601 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1602 handle_local_request(ctx, packet);
1603 return;
e636fe25 1604 }
ed568912 1605
2dbd7d7e 1606 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1607 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1608
2dbd7d7e 1609 if (ret < 0)
f319b6a0 1610 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1611
ed568912
KH		 1612}
1613
f117a3e3
CL		 1614static void detect_dead_context(struct fw_ohci *ohci,
1615 const char *name, unsigned int regs)
1616{
1617 u32 ctl;
1618
1619 ctl = reg_read(ohci, CONTROL_SET(regs));
1620 if (ctl & CONTEXT_DEAD) {
1621#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1622 fw_error("DMA context %s has stopped, error code: %s\n",
1623 name, evts[ctl & 0x1f]);
1624#else
1625 fw_error("DMA context %s has stopped, error code: %#x\n",
1626 name, ctl & 0x1f);
1627#endif
1628 }
1629}
1630
1631static void handle_dead_contexts(struct fw_ohci *ohci)
1632{
1633 unsigned int i;
1634 char name[8];
1635
1636 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1637 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1638 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1639 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1640 for (i = 0; i < 32; ++i) {
1641 if (!(ohci->it_context_support & (1 << i)))
1642 continue;
1643 sprintf(name, "IT%u", i);
1644 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1645 }
1646 for (i = 0; i < 32; ++i) {
1647 if (!(ohci->ir_context_support & (1 << i)))
1648 continue;
1649 sprintf(name, "IR%u", i);
1650 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1651 }
1652 /* TODO: maybe try to flush and restart the dead contexts */
1653}
1654
a48777e0
CL		 1655static u32 cycle_timer_ticks(u32 cycle_timer)
1656{
1657 u32 ticks;
1658
1659 ticks = cycle_timer & 0xfff;
1660 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1661 ticks += (3072 * 8000) * (cycle_timer >> 25);
1662
1663 return ticks;
1664}
1665
1666/*
1667 * Some controllers exhibit one or more of the following bugs when updating the
1668 * iso cycle timer register:
1669 * - When the lowest six bits are wrapping around to zero, a read that happens
1670 * at the same time will return garbage in the lowest ten bits.
1671 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1672 * not incremented for about 60 ns.
1673 * - Occasionally, the entire register reads zero.
1674 *
1675 * To catch these, we read the register three times and ensure that the
1676 * difference between each two consecutive reads is approximately the same, i.e.
1677 * less than twice the other. Furthermore, any negative difference indicates an
1678 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1679 * execute, so we have enough precision to compute the ratio of the differences.)
1680 */
1681static u32 get_cycle_time(struct fw_ohci *ohci)
1682{
1683 u32 c0, c1, c2;
1684 u32 t0, t1, t2;
1685 s32 diff01, diff12;
1686 int i;
1687
1688 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1689
1690 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1691 i = 0;
1692 c1 = c2;
1693 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1694 do {
1695 c0 = c1;
1696 c1 = c2;
1697 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1698 t0 = cycle_timer_ticks(c0);
1699 t1 = cycle_timer_ticks(c1);
1700 t2 = cycle_timer_ticks(c2);
1701 diff01 = t1 - t0;
1702 diff12 = t2 - t1;
1703 } while ((diff01 <= 0 || diff12 <= 0 ||
1704 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1705 && i++ < 20);
1706 }
1707
1708 return c2;
1709}
1710
1711/*
1712 * This function has to be called at least every 64 seconds. The bus_time
1713 * field stores not only the upper 25 bits of the BUS_TIME register but also
1714 * the most significant bit of the cycle timer in bit 6 so that we can detect
1715 * changes in this bit.
1716 */
1717static u32 update_bus_time(struct fw_ohci *ohci)
1718{
1719 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1720
1721 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1722 ohci->bus_time += 0x40;
1723
1724 return ohci->bus_time | cycle_time_seconds;
1725}
1726
25935ebe
SG		 1727static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1728{
1729 int reg;
1730
1731 mutex_lock(&ohci->phy_reg_mutex);
1732 reg = write_phy_reg(ohci, 7, port_index);
28897fb7
SR		 1733 if (reg >= 0)
1734 reg = read_phy_reg(ohci, 8);
25935ebe
SG		 1735 mutex_unlock(&ohci->phy_reg_mutex);
1736 if (reg < 0)
1737 return reg;
1738
1739 switch (reg & 0x0f) {
1740 case 0x06:
1741 return 2; /* is child node (connected to parent node) */
1742 case 0x0e:
1743 return 3; /* is parent node (connected to child node) */
1744 }
1745 return 1; /* not connected */
1746}
1747
1748static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1749 int self_id_count)
1750{
1751 int i;
1752 u32 entry;
28897fb7 1753
25935ebe
SG		 1754 for (i = 0; i < self_id_count; i++) {
1755 entry = ohci->self_id_buffer[i];
1756 if ((self_id & 0xff000000) == (entry & 0xff000000))
1757 return -1;
1758 if ((self_id & 0xff000000) < (entry & 0xff000000))
1759 return i;
1760 }
1761 return i;
1762}
1763
1764/*
28897fb7
SR		 1765 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1766 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1767 * Construct the selfID from phy register contents.
1768 * FIXME: How to determine the selfID.i flag?
25935ebe 1769 */
25935ebe
SG		 1770static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1771{
28897fb7
SR		 1772 int reg, i, pos, status;
1773 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1774 u32 self_id = 0x8040c800;
25935ebe
SG		 1775
1776 reg = reg_read(ohci, OHCI1394_NodeID);
1777 if (!(reg & OHCI1394_NodeID_idValid)) {
1778 fw_notify("node ID not valid, new bus reset in progress\n");
1779 return -EBUSY;
1780 }
1781 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1782
28897fb7 1783 reg = ohci_read_phy_reg(&ohci->card, 4);
25935ebe
SG		 1784 if (reg < 0)
1785 return reg;
1786 self_id |= ((reg & 0x07) << 8); /* power class */
1787
28897fb7 1788 reg = ohci_read_phy_reg(&ohci->card, 1);
25935ebe
SG		 1789 if (reg < 0)
1790 return reg;
1791 self_id |= ((reg & 0x3f) << 16); /* gap count */
1792
1793 for (i = 0; i < 3; i++) {
1794 status = get_status_for_port(ohci, i);
1795 if (status < 0)
1796 return status;
1797 self_id |= ((status & 0x3) << (6 - (i * 2)));
1798 }
1799
1800 pos = get_self_id_pos(ohci, self_id, self_id_count);
1801 if (pos >= 0) {
1802 memmove(&(ohci->self_id_buffer[pos+1]),
1803 &(ohci->self_id_buffer[pos]),
1804 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1805 ohci->self_id_buffer[pos] = self_id;
1806 self_id_count++;
1807 }
1808 return self_id_count;
1809}
1810
2d7a36e2 1811static void bus_reset_work(struct work_struct *work)
ed568912 1812{
2d7a36e2
SG		 1813 struct fw_ohci *ohci =
1814 container_of(work, struct fw_ohci, bus_reset_work);
e636fe25 1815 int self_id_count, i, j, reg;
ed568912
KH		 1816 int generation, new_generation;
1817 unsigned long flags;
4eaff7d6
SR		 1818 void *free_rom = NULL;
1819 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1820 bool is_new_root;
ed568912
KH		 1821
1822 reg = reg_read(ohci, OHCI1394_NodeID);
1823 if (!(reg & OHCI1394_NodeID_idValid)) {
02ff8f8e 1824 fw_notify("node ID not valid, new bus reset in progress\n");
ed568912
KH		 1825 return;
1826 }
02ff8f8e
SR		 1827 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1828 fw_notify("malconfigured bus\n");
1829 return;
1830 }
1831 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1832 OHCI1394_NodeID_nodeNumber);
ed568912 1833
4ffb7a6a
CL		 1834 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1835 if (!(ohci->is_root && is_new_root))
1836 reg_write(ohci, OHCI1394_LinkControlSet,
1837 OHCI1394_LinkControl_cycleMaster);
1838 ohci->is_root = is_new_root;
1839
c8a9a498
SR		 1840 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1841 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1842 fw_notify("inconsistent self IDs\n");
1843 return;
1844 }
c781c06d
KH		 1845 /*
1846 * The count in the SelfIDCount register is the number of
ed568912
KH		 1847 * bytes in the self ID receive buffer. Since we also receive
1848 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1849 * bit extra to get the actual number of self IDs.
1850 */
928ec5f1 1851 self_id_count = (reg >> 3) & 0xff;
25935ebe
SG		 1852
1853 if (self_id_count > 252) {
016bf3df
SR		 1854 fw_notify("inconsistent self IDs\n");
1855 return;
1856 }
25935ebe 1857
11bf20ad 1858 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1859 rmb();
ed568912
KH		 1860
1861 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498 1862 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
32eaeae1
CL		 1863 /*
1864 * If the invalid data looks like a cycle start packet,
1865 * it's likely to be the result of the cycle master
1866 * having a wrong gap count. In this case, the self IDs
1867 * so far are valid and should be processed so that the
1868 * bus manager can then correct the gap count.
1869 */
1870 if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1871 == 0xffff008f) {
1872 fw_notify("ignoring spurious self IDs\n");
1873 self_id_count = j;
1874 break;
1875 } else {
1876 fw_notify("inconsistent self IDs\n");
1877 return;
1878 }
c8a9a498 1879 }
11bf20ad
SR		 1880 ohci->self_id_buffer[j] =
1881 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1882 }
25935ebe
SG		 1883
1884 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1885 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1886 if (self_id_count < 0) {
28897fb7 1887 fw_notify("could not construct local self ID\n");
25935ebe
SG		 1888 return;
1889 }
1890 }
1891
1892 if (self_id_count == 0) {
1893 fw_notify("inconsistent self IDs\n");
1894 return;
1895 }
ee71c2f9 1896 rmb();
ed568912 1897
c781c06d
KH		 1898 /*
1899 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1900 * problem we face is that a new bus reset can start while we
1901 * read out the self IDs from the DMA buffer. If this happens,
1902 * the DMA buffer will be overwritten with new self IDs and we
1903 * will read out inconsistent data. The OHCI specification
1904 * (section 11.2) recommends a technique similar to
1905 * linux/seqlock.h, where we remember the generation of the
1906 * self IDs in the buffer before reading them out and compare
1907 * it to the current generation after reading them out. If
1908 * the two generations match we know we have a consistent set
c781c06d
KH		 1909 * of self IDs.
1910 */
ed568912
KH		 1911
1912 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1913 if (new_generation != generation) {
1914 fw_notify("recursive bus reset detected, "
1915 "discarding self ids\n");
1916 return;
1917 }
1918
1919 /* FIXME: Document how the locking works. */
1920 spin_lock_irqsave(&ohci->lock, flags);
1921
82b662dc 1922 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 1923 context_stop(&ohci->at_request_ctx);
1924 context_stop(&ohci->at_response_ctx);
82b662dc
CL		 1925
1926 spin_unlock_irqrestore(&ohci->lock, flags);
1927
78dec56d
SR		 1928 /*
1929 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1930 * packets in the AT queues and software needs to drain them.
1931 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1932 */
82b662dc
CL		 1933 at_context_flush(&ohci->at_request_ctx);
1934 at_context_flush(&ohci->at_response_ctx);
1935
1936 spin_lock_irqsave(&ohci->lock, flags);
1937
1938 ohci->generation = generation;
ed568912
KH		 1939 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1940
4a635593 1941 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1942 ohci->request_generation = generation;
1943
c781c06d
KH		 1944 /*
1945 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1946 * have to do it under the spinlock also. If a new config rom
1947 * was set up before this reset, the old one is now no longer
1948 * in use and we can free it. Update the config rom pointers
1949 * to point to the current config rom and clear the
88393161 1950 * next_config_rom pointer so a new update can take place.
c781c06d 1951 */
ed568912
KH		 1952
1953 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 1954 if (ohci->next_config_rom != ohci->config_rom) {
1955 free_rom = ohci->config_rom;
1956 free_rom_bus = ohci->config_rom_bus;
1957 }
ed568912
KH		 1958 ohci->config_rom = ohci->next_config_rom;
1959 ohci->config_rom_bus = ohci->next_config_rom_bus;
1960 ohci->next_config_rom = NULL;
1961
c781c06d
KH		 1962 /*
1963 * Restore config_rom image and manually update
ed568912
KH		 1964 * config_rom registers. Writing the header quadlet
1965 * will indicate that the config rom is ready, so we
c781c06d
KH		 1966 * do that last.
1967 */
ed568912
KH		 1968 reg_write(ohci, OHCI1394_BusOptions,
1969 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 1970 ohci->config_rom[0] = ohci->next_header;
1971 reg_write(ohci, OHCI1394_ConfigROMhdr,
1972 be32_to_cpu(ohci->next_header));
ed568912
KH		 1973 }
1974
080de8c2
SR		 1975#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1976 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1977 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1978#endif
1979
ed568912
KH		 1980 spin_unlock_irqrestore(&ohci->lock, flags);
1981
4eaff7d6
SR		 1982 if (free_rom)
1983 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1984 free_rom, free_rom_bus);
1985
08ddb2f4
SR		 1986 log_selfids(ohci->node_id, generation,
1987 self_id_count, ohci->self_id_buffer);
ad3c0fe8 1988
e636fe25 1989 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 1990 self_id_count, ohci->self_id_buffer,
1991 ohci->csr_state_setclear_abdicate);
1992 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 1993}
1994
1995static irqreturn_t irq_handler(int irq, void *data)
1996{
1997 struct fw_ohci *ohci = data;
168cf9af 1998 u32 event, iso_event;
ed568912
KH		 1999 int i;
2000
2001 event = reg_read(ohci, OHCI1394_IntEventClear);
2002
a515958d 2003 if (!event || !~event)
ed568912
KH		 2004 return IRQ_NONE;
2005
8327b37b
CL		 2006 /*
2007 * busReset and postedWriteErr must not be cleared yet
2008 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2009 */
2010 reg_write(ohci, OHCI1394_IntEventClear,
2011 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
ad3c0fe8 2012 log_irqs(event);
ed568912
KH		 2013
2014 if (event & OHCI1394_selfIDComplete)
2d7a36e2 2015 queue_work(fw_workqueue, &ohci->bus_reset_work);
ed568912
KH		 2016
2017 if (event & OHCI1394_RQPkt)
2018 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2019
2020 if (event & OHCI1394_RSPkt)
2021 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2022
2023 if (event & OHCI1394_reqTxComplete)
2024 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2025
2026 if (event & OHCI1394_respTxComplete)
2027 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2028
2dd5bed5
CL		 2029 if (event & OHCI1394_isochRx) {
2030 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2031 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2032
2033 while (iso_event) {
2034 i = ffs(iso_event) - 1;
2035 tasklet_schedule(
2036 &ohci->ir_context_list[i].context.tasklet);
2037 iso_event &= ~(1 << i);
2038 }
ed568912
KH		 2039 }
2040
2dd5bed5
CL		 2041 if (event & OHCI1394_isochTx) {
2042 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2043 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 2044
2dd5bed5
CL		 2045 while (iso_event) {
2046 i = ffs(iso_event) - 1;
2047 tasklet_schedule(
2048 &ohci->it_context_list[i].context.tasklet);
2049 iso_event &= ~(1 << i);
2050 }
ed568912
KH		 2051 }
2052
75f7832e
JW		 2053 if (unlikely(event & OHCI1394_regAccessFail))
2054 fw_error("Register access failure - "
2055 "please notify linux1394-devel@lists.sf.net\n");
2056
8327b37b
CL		 2057 if (unlikely(event & OHCI1394_postedWriteErr)) {
2058 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2059 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2060 reg_write(ohci, OHCI1394_IntEventClear,
2061 OHCI1394_postedWriteErr);
a74477db
SG		 2062 if (printk_ratelimit())
2063 fw_error("PCI posted write error\n");
8327b37b 2064 }
e524f616 2065
bb9f2206
SR		 2066 if (unlikely(event & OHCI1394_cycleTooLong)) {
2067 if (printk_ratelimit())
2068 fw_notify("isochronous cycle too long\n");
2069 reg_write(ohci, OHCI1394_LinkControlSet,
2070 OHCI1394_LinkControl_cycleMaster);
2071 }
2072
5ed1f321
JF		 2073 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2074 /*
2075 * We need to clear this event bit in order to make
2076 * cycleMatch isochronous I/O work. In theory we should
2077 * stop active cycleMatch iso contexts now and restart
2078 * them at least two cycles later. (FIXME?)
2079 */
2080 if (printk_ratelimit())
2081 fw_notify("isochronous cycle inconsistent\n");
2082 }
2083
f117a3e3
CL		 2084 if (unlikely(event & OHCI1394_unrecoverableError))
2085 handle_dead_contexts(ohci);
2086
a48777e0
CL		 2087 if (event & OHCI1394_cycle64Seconds) {
2088 spin_lock(&ohci->lock);
2089 update_bus_time(ohci);
2090 spin_unlock(&ohci->lock);
e597e989
CL		 2091 } else
2092 flush_writes(ohci);
a48777e0 2093
ed568912
KH		 2094 return IRQ_HANDLED;
2095}
2096
2aef469a
KH		 2097static int software_reset(struct fw_ohci *ohci)
2098{
9f426173 2099 u32 val;
2aef469a
KH		 2100 int i;
2101
2102 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
9f426173
SR		 2103 for (i = 0; i < 500; i++) {
2104 val = reg_read(ohci, OHCI1394_HCControlSet);
2105 if (!~val)
2106 return -ENODEV; /* Card was ejected. */
2aef469a 2107
9f426173 2108 if (!(val & OHCI1394_HCControl_softReset))
2aef469a 2109 return 0;
9f426173 2110
2aef469a
KH		 2111 msleep(1);
2112 }
2113
2114 return -EBUSY;
2115}
2116
8e85973e
SR		 2117static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2118{
2119 size_t size = length * 4;
2120
2121 memcpy(dest, src, size);
2122 if (size < CONFIG_ROM_SIZE)
2123 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2124}
2125
925e7a65
CL		 2126static int configure_1394a_enhancements(struct fw_ohci *ohci)
2127{
2128 bool enable_1394a;
35d999b1 2129 int ret, clear, set, offset;
925e7a65
CL		 2130
2131 /* Check if the driver should configure link and PHY. */
2132 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2133 OHCI1394_HCControl_programPhyEnable))
2134 return 0;
2135
2136 /* Paranoia: check whether the PHY supports 1394a, too. */
2137 enable_1394a = false;
35d999b1
SR		 2138 ret = read_phy_reg(ohci, 2);
2139 if (ret < 0)
2140 return ret;
2141 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2142 ret = read_paged_phy_reg(ohci, 1, 8);
2143 if (ret < 0)
2144 return ret;
2145 if (ret >= 1)
925e7a65
CL		 2146 enable_1394a = true;
2147 }
2148
2149 if (ohci->quirks & QUIRK_NO_1394A)
2150 enable_1394a = false;
2151
2152 /* Configure PHY and link consistently. */
2153 if (enable_1394a) {
2154 clear = 0;
2155 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2156 } else {
2157 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2158 set = 0;
2159 }
02d37bed 2160 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2161 if (ret < 0)
2162 return ret;
925e7a65
CL		 2163
2164 if (enable_1394a)
2165 offset = OHCI1394_HCControlSet;
2166 else
2167 offset = OHCI1394_HCControlClear;
2168 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2169
2170 /* Clean up: configuration has been taken care of. */
2171 reg_write(ohci, OHCI1394_HCControlClear,
2172 OHCI1394_HCControl_programPhyEnable);
2173
2174 return 0;
2175}
2176
25935ebe
SG		 2177static int probe_tsb41ba3d(struct fw_ohci *ohci)
2178{
b810e4ae
SR		 2179 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2180 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2181 int reg, i;
25935ebe
SG		 2182
2183 reg = read_phy_reg(ohci, 2);
2184 if (reg < 0)
2185 return reg;
b810e4ae
SR		 2186 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2187 return 0;
25935ebe 2188
b810e4ae
SR		 2189 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2190 reg = read_paged_phy_reg(ohci, 1, i + 10);
2191 if (reg < 0)
2192 return reg;
2193 if (reg != id[i])
2194 return 0;
25935ebe 2195 }
b810e4ae 2196 return 1;
25935ebe
SG		 2197}
2198
8e85973e
SR		 2199static int ohci_enable(struct fw_card *card,
2200 const __be32 *config_rom, size_t length)
ed568912
KH		 2201{
2202 struct fw_ohci *ohci = fw_ohci(card);
2203 struct pci_dev *dev = to_pci_dev(card->device);
e91b2787 2204 u32 lps, seconds, version, irqs;
28897fb7 2205 int i, ret;
ed568912 2206
2aef469a
KH		 2207 if (software_reset(ohci)) {
2208 fw_error("Failed to reset ohci card.\n");
2209 return -EBUSY;
2210 }
2211
2212 /*
2213 * Now enable LPS, which we need in order to start accessing
2214 * most of the registers. In fact, on some cards (ALI M5251),
2215 * accessing registers in the SClk domain without LPS enabled
2216 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2217 * full link enabled. However, with some cards (well, at least
2218 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 2219 */
2220 reg_write(ohci, OHCI1394_HCControlSet,
2221 OHCI1394_HCControl_LPS |
2222 OHCI1394_HCControl_postedWriteEnable);
2223 flush_writes(ohci);
02214724
JW		 2224
2225 for (lps = 0, i = 0; !lps && i < 3; i++) {
2226 msleep(50);
2227 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2228 OHCI1394_HCControl_LPS;
2229 }
2230
2231 if (!lps) {
2232 fw_error("Failed to set Link Power Status\n");
2233 return -EIO;
2234 }
2aef469a 2235
25935ebe 2236 if (ohci->quirks & QUIRK_TI_SLLZ059) {
28897fb7
SR		 2237 ret = probe_tsb41ba3d(ohci);
2238 if (ret < 0)
2239 return ret;
2240 if (ret)
2241 fw_notify("local TSB41BA3D phy\n");
2242 else
25935ebe 2243 ohci->quirks &= ~QUIRK_TI_SLLZ059;
25935ebe
SG		 2244 }
2245
2aef469a
KH		 2246 reg_write(ohci, OHCI1394_HCControlClear,
2247 OHCI1394_HCControl_noByteSwapData);
2248
affc9c24 2249 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2250 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2251 OHCI1394_LinkControl_cycleTimerEnable |
2252 OHCI1394_LinkControl_cycleMaster);
2253
2254 reg_write(ohci, OHCI1394_ATRetries,
2255 OHCI1394_MAX_AT_REQ_RETRIES |
2256 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2257 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2258 (200 << 16));
2aef469a 2259
a48777e0
CL		 2260 seconds = lower_32_bits(get_seconds());
2261 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2262 ohci->bus_time = seconds & ~0x3f;
2263
e91b2787
CL		 2264 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2265 if (version >= OHCI_VERSION_1_1) {
2266 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2267 0xfffffffe);
db3c9cc1 2268 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2269 }
2270
a1a1132b
CL		 2271 /* Get implemented bits of the priority arbitration request counter. */
2272 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2273 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2274 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2275 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2276
2aef469a
KH		 2277 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2278 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2279 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2280
35d999b1
SR		 2281 ret = configure_1394a_enhancements(ohci);
2282 if (ret < 0)
2283 return ret;
925e7a65 2284
2aef469a 2285 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2286 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2287 if (ret < 0)
2288 return ret;
2aef469a 2289
c781c06d
KH		 2290 /*
2291 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2292 * update mechanism described below in ohci_set_config_rom()
2293 * is not active. We have to update ConfigRomHeader and
2294 * BusOptions manually, and the write to ConfigROMmap takes
2295 * effect immediately. We tie this to the enabling of the
2296 * link, so we have a valid config rom before enabling - the
2297 * OHCI requires that ConfigROMhdr and BusOptions have valid
2298 * values before enabling.
2299 *
2300 * However, when the ConfigROMmap is written, some controllers
2301 * always read back quadlets 0 and 2 from the config rom to
2302 * the ConfigRomHeader and BusOptions registers on bus reset.
2303 * They shouldn't do that in this initial case where the link
2304 * isn't enabled. This means we have to use the same
2305 * workaround here, setting the bus header to 0 and then write
2306 * the right values in the bus reset tasklet.
2307 */
2308
0bd243c4
KH		 2309 if (config_rom) {
2310 ohci->next_config_rom =
2311 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2312 &ohci->next_config_rom_bus,
2313 GFP_KERNEL);
2314 if (ohci->next_config_rom == NULL)
2315 return -ENOMEM;
ed568912 2316
8e85973e 2317 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2318 } else {
2319 /*
2320 * In the suspend case, config_rom is NULL, which
2321 * means that we just reuse the old config rom.
2322 */
2323 ohci->next_config_rom = ohci->config_rom;
2324 ohci->next_config_rom_bus = ohci->config_rom_bus;
2325 }
ed568912 2326
8e85973e 2327 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2328 ohci->next_config_rom[0] = 0;
2329 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2330 reg_write(ohci, OHCI1394_BusOptions,
2331 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2332 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2333
2334 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2335
262444ee
CL		 2336 if (!(ohci->quirks & QUIRK_NO_MSI))
2337 pci_enable_msi(dev);
ed568912 2338 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2339 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2340 ohci_driver_name, ohci)) {
2341 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2342 pci_disable_msi(dev);
a01e8360
SR		 2343
2344 if (config_rom) {
2345 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2346 ohci->next_config_rom,
2347 ohci->next_config_rom_bus);
2348 ohci->next_config_rom = NULL;
2349 }
ed568912
KH		 2350 return -EIO;
2351 }
2352
148c7866
SR		 2353 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2354 OHCI1394_RQPkt | OHCI1394_RSPkt |
2355 OHCI1394_isochTx | OHCI1394_isochRx |
2356 OHCI1394_postedWriteErr |
2357 OHCI1394_selfIDComplete |
2358 OHCI1394_regAccessFail |
a48777e0 2359 OHCI1394_cycle64Seconds |
f117a3e3
CL		 2360 OHCI1394_cycleInconsistent |
2361 OHCI1394_unrecoverableError |
2362 OHCI1394_cycleTooLong |
148c7866
SR		 2363 OHCI1394_masterIntEnable;
2364 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2365 irqs |= OHCI1394_busReset;
2366 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2367
ed568912
KH		 2368 reg_write(ohci, OHCI1394_HCControlSet,
2369 OHCI1394_HCControl_linkEnable |
2370 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2371
2372 reg_write(ohci, OHCI1394_LinkControlSet,
2373 OHCI1394_LinkControl_rcvSelfID |
2374 OHCI1394_LinkControl_rcvPhyPkt);
2375
2376 ar_context_run(&ohci->ar_request_ctx);
dd6254e5
CL		 2377 ar_context_run(&ohci->ar_response_ctx);
2378
2379 flush_writes(ohci);
ed568912 2380
02d37bed
SR		 2381 /* We are ready to go, reset bus to finish initialization. */
2382 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2383
2384 return 0;
2385}
2386
53dca511 2387static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2388 const __be32 *config_rom, size_t length)
ed568912
KH		 2389{
2390 struct fw_ohci *ohci;
2391 unsigned long flags;
ed568912 2392 __be32 *next_config_rom;
f5101d58 2393 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2394
2395 ohci = fw_ohci(card);
2396
c781c06d
KH		 2397 /*
2398 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2399 * mechanism is a bit tricky, but easy enough to use. See
2400 * section 5.5.6 in the OHCI specification.
2401 *
2402 * The OHCI controller caches the new config rom address in a
2403 * shadow register (ConfigROMmapNext) and needs a bus reset
2404 * for the changes to take place. When the bus reset is
2405 * detected, the controller loads the new values for the
2406 * ConfigRomHeader and BusOptions registers from the specified
2407 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2408 * shadow register. All automatically and atomically.
2409 *
2410 * Now, there's a twist to this story. The automatic load of
2411 * ConfigRomHeader and BusOptions doesn't honor the
2412 * noByteSwapData bit, so with a be32 config rom, the
2413 * controller will load be32 values in to these registers
2414 * during the atomic update, even on litte endian
2415 * architectures. The workaround we use is to put a 0 in the
2416 * header quadlet; 0 is endian agnostic and means that the
2417 * config rom isn't ready yet. In the bus reset tasklet we
2418 * then set up the real values for the two registers.
2419 *
2420 * We use ohci->lock to avoid racing with the code that sets
2d7a36e2 2421 * ohci->next_config_rom to NULL (see bus_reset_work).
ed568912
KH		 2422 */
2423
2424 next_config_rom =
2425 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2426 &next_config_rom_bus, GFP_KERNEL);
2427 if (next_config_rom == NULL)
2428 return -ENOMEM;
2429
2430 spin_lock_irqsave(&ohci->lock, flags);
2431
2e053a27
B		 2432 /*
2433 * If there is not an already pending config_rom update,
2434 * push our new allocation into the ohci->next_config_rom
2435 * and then mark the local variable as null so that we
2436 * won't deallocate the new buffer.
2437 *
2438 * OTOH, if there is a pending config_rom update, just
2439 * use that buffer with the new config_rom data, and
2440 * let this routine free the unused DMA allocation.
2441 */
2442
ed568912
KH		 2443 if (ohci->next_config_rom == NULL) {
2444 ohci->next_config_rom = next_config_rom;
2445 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2446 next_config_rom = NULL;
2447 }
ed568912 2448
2e053a27 2449 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2450
2e053a27
B		 2451 ohci->next_header = config_rom[0];
2452 ohci->next_config_rom[0] = 0;
ed568912 2453
2e053a27 2454 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912
KH		 2455
2456 spin_unlock_irqrestore(&ohci->lock, flags);
2457
2e053a27
B		 2458 /* If we didn't use the DMA allocation, delete it. */
2459 if (next_config_rom != NULL)
2460 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2461 next_config_rom, next_config_rom_bus);
2462
c781c06d
KH		 2463 /*
2464 * Now initiate a bus reset to have the changes take
ed568912
KH		 2465 * effect. We clean up the old config rom memory and DMA
2466 * mappings in the bus reset tasklet, since the OHCI
2467 * controller could need to access it before the bus reset
c781c06d
KH		 2468 * takes effect.
2469 */
ed568912 2470
2e053a27
B		 2471 fw_schedule_bus_reset(&ohci->card, true, true);
2472
2473 return 0;
ed568912
KH		 2474}
2475
2476static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2477{
2478 struct fw_ohci *ohci = fw_ohci(card);
2479
2480 at_context_transmit(&ohci->at_request_ctx, packet);
2481}
2482
2483static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2484{
2485 struct fw_ohci *ohci = fw_ohci(card);
2486
2487 at_context_transmit(&ohci->at_response_ctx, packet);
2488}
2489
730c32f5
KH		 2490static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2491{
2492 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2493 struct context *ctx = &ohci->at_request_ctx;
2494 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2495 int ret = -ENOENT;
730c32f5 2496
f319b6a0 2497 tasklet_disable(&ctx->tasklet);
730c32f5 2498
f319b6a0
KH		 2499 if (packet->ack != 0)
2500 goto out;
730c32f5 2501
19593ffd 2502 if (packet->payload_mapped)
1d1dc5e8
SR		 2503 dma_unmap_single(ohci->card.device, packet->payload_bus,
2504 packet->payload_length, DMA_TO_DEVICE);
2505
ad3c0fe8 2506 log_ar_at_event('T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2507 driver_data->packet = NULL;
2508 packet->ack = RCODE_CANCELLED;
2509 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2510 ret = 0;
f319b6a0
KH		 2511 out:
2512 tasklet_enable(&ctx->tasklet);
730c32f5 2513
2dbd7d7e 2514 return ret;
730c32f5
KH		 2515}
2516
53dca511
SR		 2517static int ohci_enable_phys_dma(struct fw_card *card,
2518 int node_id, int generation)
ed568912 2519{
080de8c2
SR		 2520#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2521 return 0;
2522#else
ed568912
KH		 2523 struct fw_ohci *ohci = fw_ohci(card);
2524 unsigned long flags;
2dbd7d7e 2525 int n, ret = 0;
ed568912 2526
c781c06d
KH		 2527 /*
2528 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2529 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2530 */
ed568912
KH		 2531
2532 spin_lock_irqsave(&ohci->lock, flags);
2533
2534 if (ohci->generation != generation) {
2dbd7d7e 2535 ret = -ESTALE;
ed568912
KH		 2536 goto out;
2537 }
2538
c781c06d
KH		 2539 /*
2540 * Note, if the node ID contains a non-local bus ID, physical DMA is
2541 * enabled for _all_ nodes on remote buses.
2542 */
907293d7
SR		 2543
2544 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2545 if (n < 32)
2546 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2547 else
2548 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2549
ed568912 2550 flush_writes(ohci);
ed568912 2551 out:
6cad95fe 2552 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2553
2554 return ret;
080de8c2 2555#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2556}
373b2edd 2557
0fcff4e3 2558static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2559{
60d32970 2560 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2561 unsigned long flags;
2562 u32 value;
60d32970
CL		 2563
2564 switch (csr_offset) {
4ffb7a6a
CL		 2565 case CSR_STATE_CLEAR:
2566 case CSR_STATE_SET:
4ffb7a6a
CL		 2567 if (ohci->is_root &&
2568 (reg_read(ohci, OHCI1394_LinkControlSet) &
2569 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2570 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2571 else
c8a94ded
SR		 2572 value = 0;
2573 if (ohci->csr_state_setclear_abdicate)
2574 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2575
c8a94ded 2576 return value;
4a9bde9b 2577
506f1a31
CL		 2578 case CSR_NODE_IDS:
2579 return reg_read(ohci, OHCI1394_NodeID) << 16;
2580
60d32970
CL		 2581 case CSR_CYCLE_TIME:
2582 return get_cycle_time(ohci);
2583
a48777e0
CL		 2584 case CSR_BUS_TIME:
2585 /*
2586 * We might be called just after the cycle timer has wrapped
2587 * around but just before the cycle64Seconds handler, so we
2588 * better check here, too, if the bus time needs to be updated.
2589 */
2590 spin_lock_irqsave(&ohci->lock, flags);
2591 value = update_bus_time(ohci);
2592 spin_unlock_irqrestore(&ohci->lock, flags);
2593 return value;
2594
27a2329f
CL		 2595 case CSR_BUSY_TIMEOUT:
2596 value = reg_read(ohci, OHCI1394_ATRetries);
2597 return (value >> 4) & 0x0ffff00f;
2598
a1a1132b
CL		 2599 case CSR_PRIORITY_BUDGET:
2600 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2601 (ohci->pri_req_max << 8);
2602
60d32970
CL		 2603 default:
2604 WARN_ON(1);
2605 return 0;
2606 }
b677532b
CL		 2607}
2608
0fcff4e3 2609static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2610{
2611 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2612 unsigned long flags;
d60d7f1d 2613
506f1a31 2614 switch (csr_offset) {
4ffb7a6a 2615 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2616 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2617 reg_write(ohci, OHCI1394_LinkControlClear,
2618 OHCI1394_LinkControl_cycleMaster);
2619 flush_writes(ohci);
2620 }
c8a94ded
SR		 2621 if (value & CSR_STATE_BIT_ABDICATE)
2622 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2623 break;
4a9bde9b 2624
4ffb7a6a
CL		 2625 case CSR_STATE_SET:
2626 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2627 reg_write(ohci, OHCI1394_LinkControlSet,
2628 OHCI1394_LinkControl_cycleMaster);
2629 flush_writes(ohci);
2630 }
c8a94ded
SR		 2631 if (value & CSR_STATE_BIT_ABDICATE)
2632 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2633 break;
d60d7f1d 2634
506f1a31
CL		 2635 case CSR_NODE_IDS:
2636 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2637 flush_writes(ohci);
2638 break;
2639
9ab5071c
CL		 2640 case CSR_CYCLE_TIME:
2641 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2642 reg_write(ohci, OHCI1394_IntEventSet,
2643 OHCI1394_cycleInconsistent);
2644 flush_writes(ohci);
2645 break;
2646
a48777e0
CL		 2647 case CSR_BUS_TIME:
2648 spin_lock_irqsave(&ohci->lock, flags);
2649 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2650 spin_unlock_irqrestore(&ohci->lock, flags);
2651 break;
2652
27a2329f
CL		 2653 case CSR_BUSY_TIMEOUT:
2654 value = (value & 0xf) | ((value & 0xf) << 4) |
2655 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2656 reg_write(ohci, OHCI1394_ATRetries, value);
2657 flush_writes(ohci);
2658 break;
2659
a1a1132b
CL		 2660 case CSR_PRIORITY_BUDGET:
2661 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2662 flush_writes(ohci);
2663 break;
2664
506f1a31
CL		 2665 default:
2666 WARN_ON(1);
2667 break;
2668 }
d60d7f1d
KH		 2669}
2670
1aa292bb
DM		 2671static void copy_iso_headers(struct iso_context *ctx, void *p)
2672{
2673 int i = ctx->header_length;
2674
2675 if (i + ctx->base.header_size > PAGE_SIZE)
2676 return;
2677
2678 /*
2679 * The iso header is byteswapped to little endian by
2680 * the controller, but the remaining header quadlets
2681 * are big endian. We want to present all the headers
2682 * as big endian, so we have to swap the first quadlet.
2683 */
2684 if (ctx->base.header_size > 0)
2685 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2686 if (ctx->base.header_size > 4)
2687 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2688 if (ctx->base.header_size > 8)
2689 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2690 ctx->header_length += ctx->base.header_size;
2691}
2692
a186b4a6
JW		 2693static int handle_ir_packet_per_buffer(struct context *context,
2694 struct descriptor *d,
2695 struct descriptor *last)
2696{
2697 struct iso_context *ctx =
2698 container_of(context, struct iso_context, context);
bcee893c 2699 struct descriptor *pd;
a186b4a6 2700 __le32 *ir_header;
bcee893c 2701 void *p;
a186b4a6 2702
872e330e 2703 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2704 if (pd->transfer_status)
2705 break;
bcee893c 2706 if (pd > last)
a186b4a6
JW		 2707 /* Descriptor(s) not done yet, stop iteration */
2708 return 0;
2709
1aa292bb
DM		 2710 p = last + 1;
2711 copy_iso_headers(ctx, p);
a186b4a6 2712
bcee893c
DM		 2713 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2714 ir_header = (__le32 *) p;
872e330e
SR		 2715 ctx->base.callback.sc(&ctx->base,
2716 le32_to_cpu(ir_header[0]) & 0xffff,
2717 ctx->header_length, ctx->header,
2718 ctx->base.callback_data);
a186b4a6
JW		 2719 ctx->header_length = 0;
2720 }
2721
a186b4a6
JW		 2722 return 1;
2723}
2724
872e330e
SR		 2725/* d == last because each descriptor block is only a single descriptor. */
2726static int handle_ir_buffer_fill(struct context *context,
2727 struct descriptor *d,
2728 struct descriptor *last)
2729{
2730 struct iso_context *ctx =
2731 container_of(context, struct iso_context, context);
2732
2733 if (!last->transfer_status)
2734 /* Descriptor(s) not done yet, stop iteration */
2735 return 0;
2736
2737 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2738 ctx->base.callback.mc(&ctx->base,
2739 le32_to_cpu(last->data_address) +
2740 le16_to_cpu(last->req_count) -
2741 le16_to_cpu(last->res_count),
2742 ctx->base.callback_data);
2743
2744 return 1;
2745}
2746
30200739
KH		 2747static int handle_it_packet(struct context *context,
2748 struct descriptor *d,
2749 struct descriptor *last)
ed568912 2750{
30200739
KH		 2751 struct iso_context *ctx =
2752 container_of(context, struct iso_context, context);
31769cef
JF		 2753 int i;
2754 struct descriptor *pd;
373b2edd 2755
31769cef
JF		 2756 for (pd = d; pd <= last; pd++)
2757 if (pd->transfer_status)
2758 break;
2759 if (pd > last)
2760 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2761 return 0;
2762
31769cef
JF		 2763 i = ctx->header_length;
2764 if (i + 4 < PAGE_SIZE) {
2765 /* Present this value as big-endian to match the receive code */
2766 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2767 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2768 le16_to_cpu(pd->res_count));
2769 ctx->header_length += 4;
2770 }
2771 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
872e330e
SR		 2772 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2773 ctx->header_length, ctx->header,
2774 ctx->base.callback_data);
31769cef
JF		 2775 ctx->header_length = 0;
2776 }
30200739 2777 return 1;
ed568912
KH		 2778}
2779
872e330e
SR		 2780static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2781{
2782 u32 hi = channels >> 32, lo = channels;
2783
2784 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2785 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2786 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2787 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2788 mmiowb();
2789 ohci->mc_channels = channels;
2790}
2791
53dca511 2792static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2793 int type, int channel, size_t header_size)
ed568912
KH		 2794{
2795 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2796 struct iso_context *uninitialized_var(ctx);
2797 descriptor_callback_t uninitialized_var(callback);
2798 u64 *uninitialized_var(channels);
2799 u32 *uninitialized_var(mask), uninitialized_var(regs);
ed568912 2800 unsigned long flags;
872e330e 2801 int index, ret = -EBUSY;
ed568912 2802
872e330e 2803 spin_lock_irqsave(&ohci->lock, flags);
ed568912 2804
872e330e
SR		 2805 switch (type) {
2806 case FW_ISO_CONTEXT_TRANSMIT:
2807 mask = &ohci->it_context_mask;
30200739 2808 callback = handle_it_packet;
872e330e
SR		 2809 index = ffs(*mask) - 1;
2810 if (index >= 0) {
2811 *mask &= ~(1 << index);
2812 regs = OHCI1394_IsoXmitContextBase(index);
2813 ctx = &ohci->it_context_list[index];
2814 }
2815 break;
2816
2817 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2818 channels = &ohci->ir_context_channels;
872e330e 2819 mask = &ohci->ir_context_mask;
6498ba04 2820 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2821 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2822 if (index >= 0) {
2823 *channels &= ~(1ULL << channel);
2824 *mask &= ~(1 << index);
2825 regs = OHCI1394_IsoRcvContextBase(index);
2826 ctx = &ohci->ir_context_list[index];
2827 }
2828 break;
ed568912 2829
872e330e
SR		 2830 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2831 mask = &ohci->ir_context_mask;
2832 callback = handle_ir_buffer_fill;
2833 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2834 if (index >= 0) {
2835 ohci->mc_allocated = true;
2836 *mask &= ~(1 << index);
2837 regs = OHCI1394_IsoRcvContextBase(index);
2838 ctx = &ohci->ir_context_list[index];
2839 }
2840 break;
2841
2842 default:
2843 index = -1;
2844 ret = -ENOSYS;
4817ed24 2845 }
872e330e 2846
ed568912
KH		 2847 spin_unlock_irqrestore(&ohci->lock, flags);
2848
2849 if (index < 0)
872e330e 2850 return ERR_PTR(ret);
373b2edd 2851
2d826cc5 2852 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2853 ctx->header_length = 0;
2854 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2855 if (ctx->header == NULL) {
2856 ret = -ENOMEM;
9b32d5f3 2857 goto out;
872e330e 2858 }
2dbd7d7e
SR		 2859 ret = context_init(&ctx->context, ohci, regs, callback);
2860 if (ret < 0)
9b32d5f3 2861 goto out_with_header;
ed568912 2862
872e330e
SR		 2863 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2864 set_multichannel_mask(ohci, 0);
2865
ed568912 2866 return &ctx->base;
9b32d5f3
KH		 2867
2868 out_with_header:
2869 free_page((unsigned long)ctx->header);
2870 out:
2871 spin_lock_irqsave(&ohci->lock, flags);
872e330e
SR		 2872
2873 switch (type) {
2874 case FW_ISO_CONTEXT_RECEIVE:
2875 *channels |= 1ULL << channel;
2876 break;
2877
2878 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2879 ohci->mc_allocated = false;
2880 break;
2881 }
9b32d5f3 2882 *mask |= 1 << index;
872e330e 2883
9b32d5f3
KH		 2884 spin_unlock_irqrestore(&ohci->lock, flags);
2885
2dbd7d7e 2886 return ERR_PTR(ret);
ed568912
KH		 2887}
2888
eb0306ea
KH		 2889static int ohci_start_iso(struct fw_iso_context *base,
2890 s32 cycle, u32 sync, u32 tags)
ed568912 2891{
373b2edd 2892 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 2893 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 2894 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 2895 int index;
2896
44b74d90
CL		 2897 /* the controller cannot start without any queued packets */
2898 if (ctx->context.last->branch_address == 0)
2899 return -ENODATA;
2900
872e330e
SR		 2901 switch (ctx->base.type) {
2902 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 2903 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 2904 match = 0;
2905 if (cycle >= 0)
2906 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 2907 (cycle & 0x7fff) << 16;
21efb3cf 2908
295e3feb
KH		 2909 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2910 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 2911 context_run(&ctx->context, match);
872e330e
SR		 2912 break;
2913
2914 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2915 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2916 /* fall through */
2917 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 2918 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 2919 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2920 if (cycle >= 0) {
2921 match |= (cycle & 0x07fff) << 12;
2922 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2923 }
ed568912 2924
295e3feb
KH		 2925 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2926 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 2927 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 2928 context_run(&ctx->context, control);
dd23736e
ML		 2929
2930 ctx->sync = sync;
2931 ctx->tags = tags;
2932
872e330e 2933 break;
295e3feb 2934 }
ed568912
KH		 2935
2936 return 0;
2937}
2938
b8295668
KH		 2939static int ohci_stop_iso(struct fw_iso_context *base)
2940{
2941 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2942 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 2943 int index;
2944
872e330e
SR		 2945 switch (ctx->base.type) {
2946 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 2947 index = ctx - ohci->it_context_list;
2948 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 2949 break;
2950
2951 case FW_ISO_CONTEXT_RECEIVE:
2952 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 2953 index = ctx - ohci->ir_context_list;
2954 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 2955 break;
b8295668
KH		 2956 }
2957 flush_writes(ohci);
2958 context_stop(&ctx->context);
e81cbebd 2959 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 2960
2961 return 0;
2962}
2963
ed568912
KH		 2964static void ohci_free_iso_context(struct fw_iso_context *base)
2965{
2966 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2967 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 2968 unsigned long flags;
2969 int index;
2970
b8295668
KH		 2971 ohci_stop_iso(base);
2972 context_release(&ctx->context);
9b32d5f3 2973 free_page((unsigned long)ctx->header);
b8295668 2974
ed568912
KH		 2975 spin_lock_irqsave(&ohci->lock, flags);
2976
872e330e
SR		 2977 switch (base->type) {
2978 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 2979 index = ctx - ohci->it_context_list;
ed568912 2980 ohci->it_context_mask |= 1 << index;
872e330e
SR		 2981 break;
2982
2983 case FW_ISO_CONTEXT_RECEIVE:
ed568912 2984 index = ctx - ohci->ir_context_list;
ed568912 2985 ohci->ir_context_mask |= 1 << index;
4817ed24 2986 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 2987 break;
2988
2989 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2990 index = ctx - ohci->ir_context_list;
2991 ohci->ir_context_mask |= 1 << index;
2992 ohci->ir_context_channels |= ohci->mc_channels;
2993 ohci->mc_channels = 0;
2994 ohci->mc_allocated = false;
2995 break;
ed568912 2996 }
ed568912
KH		 2997
2998 spin_unlock_irqrestore(&ohci->lock, flags);
2999}
3000
872e330e
SR		 3001static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3002{
3003 struct fw_ohci *ohci = fw_ohci(base->card);
3004 unsigned long flags;
3005 int ret;
3006
3007 switch (base->type) {
3008 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3009
3010 spin_lock_irqsave(&ohci->lock, flags);
3011
3012 /* Don't allow multichannel to grab other contexts' channels. */
3013 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3014 *channels = ohci->ir_context_channels;
3015 ret = -EBUSY;
3016 } else {
3017 set_multichannel_mask(ohci, *channels);
3018 ret = 0;
3019 }
3020
3021 spin_unlock_irqrestore(&ohci->lock, flags);
3022
3023 break;
3024 default:
3025 ret = -EINVAL;
3026 }
3027
3028 return ret;
3029}
3030
dd23736e
ML		 3031#ifdef CONFIG_PM
3032static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3033{
3034 int i;
3035 struct iso_context *ctx;
3036
3037 for (i = 0 ; i < ohci->n_ir ; i++) {
3038 ctx = &ohci->ir_context_list[i];
693a50b5 3039 if (ctx->context.running)
dd23736e
ML		 3040 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3041 }
3042
3043 for (i = 0 ; i < ohci->n_it ; i++) {
3044 ctx = &ohci->it_context_list[i];
693a50b5 3045 if (ctx->context.running)
dd23736e
ML		 3046 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3047 }
3048}
3049#endif
3050
872e330e
SR		 3051static int queue_iso_transmit(struct iso_context *ctx,
3052 struct fw_iso_packet *packet,
3053 struct fw_iso_buffer *buffer,
3054 unsigned long payload)
ed568912 3055{
30200739 3056 struct descriptor *d, *last, *pd;
ed568912
KH		 3057 struct fw_iso_packet *p;
3058 __le32 *header;
9aad8125 3059 dma_addr_t d_bus, page_bus;
ed568912
KH		 3060 u32 z, header_z, payload_z, irq;
3061 u32 payload_index, payload_end_index, next_page_index;
30200739 3062 int page, end_page, i, length, offset;
ed568912 3063
ed568912 3064 p = packet;
9aad8125 3065 payload_index = payload;
ed568912
KH		 3066
3067 if (p->skip)
3068 z = 1;
3069 else
3070 z = 2;
3071 if (p->header_length > 0)
3072 z++;
3073
3074 /* Determine the first page the payload isn't contained in. */
3075 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3076 if (p->payload_length > 0)
3077 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3078 else
3079 payload_z = 0;
3080
3081 z += payload_z;
3082
3083 /* Get header size in number of descriptors. */
2d826cc5 3084 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 3085
30200739
KH		 3086 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3087 if (d == NULL)
3088 return -ENOMEM;
ed568912
KH		 3089
3090 if (!p->skip) {
a77754a7 3091 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 3092 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 3093 /*
3094 * Link the skip address to this descriptor itself. This causes
3095 * a context to skip a cycle whenever lost cycles or FIFO
3096 * overruns occur, without dropping the data. The application
3097 * should then decide whether this is an error condition or not.
3098 * FIXME: Make the context's cycle-lost behaviour configurable?
3099 */
3100 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 3101
3102 header = (__le32 *) &d[1];
a77754a7
KH		 3103 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3104 IT_HEADER_TAG(p->tag) |
3105 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3106 IT_HEADER_CHANNEL(ctx->base.channel) |
3107 IT_HEADER_SPEED(ctx->base.speed));
ed568912 3108 header[1] =
a77754a7 3109 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 3110 p->payload_length));
3111 }
3112
3113 if (p->header_length > 0) {
3114 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 3115 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 3116 memcpy(&d[z], p->header, p->header_length);
3117 }
3118
3119 pd = d + z - payload_z;
3120 payload_end_index = payload_index + p->payload_length;
3121 for (i = 0; i < payload_z; i++) {
3122 page = payload_index >> PAGE_SHIFT;
3123 offset = payload_index & ~PAGE_MASK;
3124 next_page_index = (page + 1) << PAGE_SHIFT;
3125 length =
3126 min(next_page_index, payload_end_index) - payload_index;
3127 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 3128
3129 page_bus = page_private(buffer->pages[page]);
3130 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912
KH		 3131
3132 payload_index += length;
3133 }
3134
ed568912 3135 if (p->interrupt)
a77754a7 3136 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 3137 else
a77754a7 3138 irq = DESCRIPTOR_NO_IRQ;
ed568912 3139
30200739 3140 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 3141 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3142 DESCRIPTOR_STATUS |
3143 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 3144 irq);
ed568912 3145
30200739 3146 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 3147
3148 return 0;
3149}
373b2edd 3150
872e330e
SR		 3151static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3152 struct fw_iso_packet *packet,
3153 struct fw_iso_buffer *buffer,
3154 unsigned long payload)
a186b4a6 3155{
8c0c0cc2 3156 struct descriptor *d, *pd;
a186b4a6
JW		 3157 dma_addr_t d_bus, page_bus;
3158 u32 z, header_z, rest;
bcee893c
DM		 3159 int i, j, length;
3160 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 3161
3162 /*
1aa292bb
DM		 3163 * The OHCI controller puts the isochronous header and trailer in the
3164 * buffer, so we need at least 8 bytes.
a186b4a6 3165 */
872e330e 3166 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 3167 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 3168
3169 /* Get header size in number of descriptors. */
3170 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3171 page = payload >> PAGE_SHIFT;
3172 offset = payload & ~PAGE_MASK;
872e330e 3173 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 3174
3175 for (i = 0; i < packet_count; i++) {
3176 /* d points to the header descriptor */
bcee893c 3177 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 3178 d = context_get_descriptors(&ctx->context,
bcee893c 3179 z + header_z, &d_bus);
a186b4a6
JW		 3180 if (d == NULL)
3181 return -ENOMEM;
3182
bcee893c
DM		 3183 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3184 DESCRIPTOR_INPUT_MORE);
872e330e 3185 if (packet->skip && i == 0)
bcee893c 3186 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3187 d->req_count = cpu_to_le16(header_size);
3188 d->res_count = d->req_count;
bcee893c 3189 d->transfer_status = 0;
a186b4a6
JW		 3190 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3191
bcee893c 3192 rest = payload_per_buffer;
8c0c0cc2 3193 pd = d;
bcee893c 3194 for (j = 1; j < z; j++) {
8c0c0cc2 3195 pd++;
bcee893c
DM		 3196 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3197 DESCRIPTOR_INPUT_MORE);
3198
3199 if (offset + rest < PAGE_SIZE)
3200 length = rest;
3201 else
3202 length = PAGE_SIZE - offset;
3203 pd->req_count = cpu_to_le16(length);
3204 pd->res_count = pd->req_count;
3205 pd->transfer_status = 0;
3206
3207 page_bus = page_private(buffer->pages[page]);
3208 pd->data_address = cpu_to_le32(page_bus + offset);
3209
3210 offset = (offset + length) & ~PAGE_MASK;
3211 rest -= length;
3212 if (offset == 0)
3213 page++;
3214 }
a186b4a6
JW		 3215 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3216 DESCRIPTOR_INPUT_LAST |
3217 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3218 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3219 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3220
a186b4a6
JW		 3221 context_append(&ctx->context, d, z, header_z);
3222 }
3223
3224 return 0;
3225}
3226
872e330e
SR		 3227static int queue_iso_buffer_fill(struct iso_context *ctx,
3228 struct fw_iso_packet *packet,
3229 struct fw_iso_buffer *buffer,
3230 unsigned long payload)
3231{
3232 struct descriptor *d;
3233 dma_addr_t d_bus, page_bus;
3234 int page, offset, rest, z, i, length;
3235
3236 page = payload >> PAGE_SHIFT;
3237 offset = payload & ~PAGE_MASK;
3238 rest = packet->payload_length;
3239
3240 /* We need one descriptor for each page in the buffer. */
3241 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3242
3243 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3244 return -EFAULT;
3245
3246 for (i = 0; i < z; i++) {
3247 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3248 if (d == NULL)
3249 return -ENOMEM;
3250
3251 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3252 DESCRIPTOR_BRANCH_ALWAYS);
3253 if (packet->skip && i == 0)
3254 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3255 if (packet->interrupt && i == z - 1)
3256 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3257
3258 if (offset + rest < PAGE_SIZE)
3259 length = rest;
3260 else
3261 length = PAGE_SIZE - offset;
3262 d->req_count = cpu_to_le16(length);
3263 d->res_count = d->req_count;
3264 d->transfer_status = 0;
3265
3266 page_bus = page_private(buffer->pages[page]);
3267 d->data_address = cpu_to_le32(page_bus + offset);
3268
3269 rest -= length;
3270 offset = 0;
3271 page++;
3272
3273 context_append(&ctx->context, d, 1, 0);
3274 }
3275
3276 return 0;
3277}
3278
53dca511
SR		 3279static int ohci_queue_iso(struct fw_iso_context *base,
3280 struct fw_iso_packet *packet,
3281 struct fw_iso_buffer *buffer,
3282 unsigned long payload)
295e3feb 3283{
e364cf4e 3284 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3285 unsigned long flags;
872e330e 3286 int ret = -ENOSYS;
e364cf4e 3287
fe5ca634 3288 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3289 switch (base->type) {
3290 case FW_ISO_CONTEXT_TRANSMIT:
3291 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3292 break;
3293 case FW_ISO_CONTEXT_RECEIVE:
3294 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3295 break;
3296 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3297 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3298 break;
3299 }
fe5ca634
DM		 3300 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3301
2dbd7d7e 3302 return ret;
295e3feb
KH		 3303}
3304
13882a82
CL		 3305static void ohci_flush_queue_iso(struct fw_iso_context *base)
3306{
3307 struct context *ctx =
3308 &container_of(base, struct iso_context, base)->context;
3309
3310 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
13882a82
CL		 3311}
3312
21ebcd12 3313static const struct fw_card_driver ohci_driver = {
ed568912 3314 .enable = ohci_enable,
02d37bed 3315 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3316 .update_phy_reg = ohci_update_phy_reg,
3317 .set_config_rom = ohci_set_config_rom,
3318 .send_request = ohci_send_request,
3319 .send_response = ohci_send_response,
730c32f5 3320 .cancel_packet = ohci_cancel_packet,
ed568912 3321 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3322 .read_csr = ohci_read_csr,
3323 .write_csr = ohci_write_csr,
ed568912
KH		 3324
3325 .allocate_iso_context = ohci_allocate_iso_context,
3326 .free_iso_context = ohci_free_iso_context,
872e330e 3327 .set_iso_channels = ohci_set_iso_channels,
ed568912 3328 .queue_iso = ohci_queue_iso,
13882a82 3329 .flush_queue_iso = ohci_flush_queue_iso,
69cdb726 3330 .start_iso = ohci_start_iso,
b8295668 3331 .stop_iso = ohci_stop_iso,
ed568912
KH		 3332};
3333
ea8d006b 3334#ifdef CONFIG_PPC_PMAC
5da3dac8 3335static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3336{
ea8d006b
SR		 3337 if (machine_is(powermac)) {
3338 struct device_node *ofn = pci_device_to_OF_node(dev);
3339
3340 if (ofn) {
3341 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3342 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3343 }
3344 }
2ed0f181
SR		 3345}
3346
5da3dac8 3347static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3348{
3349 if (machine_is(powermac)) {
3350 struct device_node *ofn = pci_device_to_OF_node(dev);
3351
3352 if (ofn) {
3353 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3354 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3355 }
3356 }
3357}
3358#else
5da3dac8
SR		 3359static inline void pmac_ohci_on(struct pci_dev *dev) {}
3360static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3361#endif /* CONFIG_PPC_PMAC */
3362
53dca511
SR		 3363static int __devinit pci_probe(struct pci_dev *dev,
3364 const struct pci_device_id *ent)
2ed0f181
SR		 3365{
3366 struct fw_ohci *ohci;
aa0170ff 3367 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3368 u64 guid;
dd23736e 3369 int i, err;
2ed0f181
SR		 3370 size_t size;
3371
7f7e3711
SR		 3372 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3373 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3374 return -ENOSYS;
3375 }
3376
2d826cc5 3377 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3378 if (ohci == NULL) {
7007a076
SR		 3379 err = -ENOMEM;
3380 goto fail;
ed568912
KH		 3381 }
3382
3383 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3384
5da3dac8 3385 pmac_ohci_on(dev);
130d5496 3386
d79406dd
KH		 3387 err = pci_enable_device(dev);
3388 if (err) {
7007a076 3389 fw_error("Failed to enable OHCI hardware\n");
bd7dee63 3390 goto fail_free;
ed568912
KH		 3391 }
3392
3393 pci_set_master(dev);
3394 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3395 pci_set_drvdata(dev, ohci);
3396
3397 spin_lock_init(&ohci->lock);
02d37bed 3398 mutex_init(&ohci->phy_reg_mutex);
ed568912 3399
2d7a36e2 3400 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
ed568912 3401
d79406dd
KH		 3402 err = pci_request_region(dev, 0, ohci_driver_name);
3403 if (err) {
ed568912 3404 fw_error("MMIO resource unavailable\n");
d79406dd 3405 goto fail_disable;
ed568912
KH		 3406 }
3407
3408 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3409 if (ohci->registers == NULL) {
3410 fw_error("Failed to remap registers\n");
d79406dd
KH		 3411 err = -ENXIO;
3412 goto fail_iomem;
ed568912
KH		 3413 }
3414
4a635593 3415 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3416 if ((ohci_quirks[i].vendor == dev->vendor) &&
3417 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3418 ohci_quirks[i].device == dev->device) &&
3419 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3420 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3421 ohci->quirks = ohci_quirks[i].flags;
3422 break;
3423 }
3e9cc2f3
SR		 3424 if (param_quirks)
3425 ohci->quirks = param_quirks;
b677532b 3426
ec766a79
CL		 3427 /*
3428 * Because dma_alloc_coherent() allocates at least one page,
3429 * we save space by using a common buffer for the AR request/
3430 * response descriptors and the self IDs buffer.
3431 */
3432 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3433 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3434 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3435 PAGE_SIZE,
3436 &ohci->misc_buffer_bus,
3437 GFP_KERNEL);
3438 if (!ohci->misc_buffer) {
3439 err = -ENOMEM;
3440 goto fail_iounmap;
3441 }
3442
3443 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3444 OHCI1394_AsReqRcvContextControlSet);
3445 if (err < 0)
ec766a79 3446 goto fail_misc_buf;
ed568912 3447
ec766a79 3448 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3449 OHCI1394_AsRspRcvContextControlSet);
3450 if (err < 0)
3451 goto fail_arreq_ctx;
ed568912 3452
c088ab30
CL		 3453 err = context_init(&ohci->at_request_ctx, ohci,
3454 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3455 if (err < 0)
3456 goto fail_arrsp_ctx;
ed568912 3457
c088ab30
CL		 3458 err = context_init(&ohci->at_response_ctx, ohci,
3459 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3460 if (err < 0)
3461 goto fail_atreq_ctx;
ed568912 3462
ed568912 3463 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3464 ohci->ir_context_channels = ~0ULL;
f117a3e3 3465 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3466 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3467 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3468 ohci->n_ir = hweight32(ohci->ir_context_mask);
3469 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3470 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3471
3472 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3473 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3474 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3475 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3476 ohci->n_it = hweight32(ohci->it_context_mask);
3477 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3478 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3479
3480 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3481 err = -ENOMEM;
7007a076 3482 goto fail_contexts;
ed568912
KH		 3483 }
3484
ec766a79
CL		 3485 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3486 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3487
ed568912
KH		 3488 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3489 max_receive = (bus_options >> 12) & 0xf;
3490 link_speed = bus_options & 0x7;
3491 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3492 reg_read(ohci, OHCI1394_GUIDLo);
3493
d79406dd 3494 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3495 if (err)
ec766a79 3496 goto fail_contexts;
ed568912 3497
6fdb2ee2
SR		 3498 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3499 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3500 "%d IR + %d IT contexts, quirks 0x%x\n",
3501 dev_name(&dev->dev), version >> 16, version & 0xff,
dd23736e 3502 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3503
ed568912 3504 return 0;
d79406dd 3505
7007a076 3506 fail_contexts:
d79406dd 3507 kfree(ohci->ir_context_list);
7007a076
SR		 3508 kfree(ohci->it_context_list);
3509 context_release(&ohci->at_response_ctx);
c088ab30 3510 fail_atreq_ctx:
7007a076 3511 context_release(&ohci->at_request_ctx);
c088ab30 3512 fail_arrsp_ctx:
7007a076 3513 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3514 fail_arreq_ctx:
7007a076 3515 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3516 fail_misc_buf:
3517 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3518 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3519 fail_iounmap:
d79406dd
KH		 3520 pci_iounmap(dev, ohci->registers);
3521 fail_iomem:
3522 pci_release_region(dev, 0);
3523 fail_disable:
3524 pci_disable_device(dev);
bd7dee63 3525 fail_free:
d838d2c0 3526 kfree(ohci);
5da3dac8 3527 pmac_ohci_off(dev);
7007a076
SR		 3528 fail:
3529 if (err == -ENOMEM)
3530 fw_error("Out of memory\n");
d79406dd
KH		 3531
3532 return err;
ed568912
KH		 3533}
3534
3535static void pci_remove(struct pci_dev *dev)
3536{
3537 struct fw_ohci *ohci;
3538
3539 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3540 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3541 flush_writes(ohci);
2d7a36e2 3542 cancel_work_sync(&ohci->bus_reset_work);
ed568912
KH		 3543 fw_core_remove_card(&ohci->card);
3544
c781c06d
KH		 3545 /*
3546 * FIXME: Fail all pending packets here, now that the upper
3547 * layers can't queue any more.
3548 */
ed568912
KH		 3549
3550 software_reset(ohci);
3551 free_irq(dev->irq, ohci);
a55709ba
JF		 3552
3553 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3554 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3555 ohci->next_config_rom, ohci->next_config_rom_bus);
3556 if (ohci->config_rom)
3557 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3558 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3559 ar_context_release(&ohci->ar_request_ctx);
3560 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3561 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3562 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3563 context_release(&ohci->at_request_ctx);
3564 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3565 kfree(ohci->it_context_list);
3566 kfree(ohci->ir_context_list);
262444ee 3567 pci_disable_msi(dev);
d79406dd
KH		 3568 pci_iounmap(dev, ohci->registers);
3569 pci_release_region(dev, 0);
3570 pci_disable_device(dev);
d838d2c0 3571 kfree(ohci);
5da3dac8 3572 pmac_ohci_off(dev);
ea8d006b 3573
ed568912
KH		 3574 fw_notify("Removed fw-ohci device.\n");
3575}
3576
2aef469a 3577#ifdef CONFIG_PM
2ed0f181 3578static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3579{
2ed0f181 3580 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3581 int err;
3582
3583 software_reset(ohci);
2ed0f181 3584 free_irq(dev->irq, ohci);
262444ee 3585 pci_disable_msi(dev);
2ed0f181 3586 err = pci_save_state(dev);
2aef469a 3587 if (err) {
8a8cea27 3588 fw_error("pci_save_state failed\n");
2aef469a
KH		 3589 return err;
3590 }
2ed0f181 3591 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428
SR		 3592 if (err)
3593 fw_error("pci_set_power_state failed with %d\n", err);
5da3dac8 3594 pmac_ohci_off(dev);
ea8d006b 3595
2aef469a
KH		 3596 return 0;
3597}
3598
2ed0f181 3599static int pci_resume(struct pci_dev *dev)
2aef469a 3600{
2ed0f181 3601 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3602 int err;
3603
5da3dac8 3604 pmac_ohci_on(dev);
2ed0f181
SR		 3605 pci_set_power_state(dev, PCI_D0);
3606 pci_restore_state(dev);
3607 err = pci_enable_device(dev);
2aef469a 3608 if (err) {
8a8cea27 3609 fw_error("pci_enable_device failed\n");
2aef469a
KH		 3610 return err;
3611 }
3612
8662b6b0
ML		 3613 /* Some systems don't setup GUID register on resume from ram */
3614 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3615 !reg_read(ohci, OHCI1394_GUIDHi)) {
3616 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3617 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3618 }
3619
dd23736e 3620 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3621 if (err)
3622 return err;
3623
3624 ohci_resume_iso_dma(ohci);
693a50b5 3625
dd23736e 3626 return 0;
2aef469a
KH		 3627}
3628#endif
3629
a67483d2 3630static const struct pci_device_id pci_table[] = {
ed568912
KH		 3631 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3632 { }
3633};
3634
3635MODULE_DEVICE_TABLE(pci, pci_table);
3636
3637static struct pci_driver fw_ohci_pci_driver = {
3638 .name = ohci_driver_name,
3639 .id_table = pci_table,
3640 .probe = pci_probe,
3641 .remove = pci_remove,
2aef469a
KH		 3642#ifdef CONFIG_PM
3643 .resume = pci_resume,
3644 .suspend = pci_suspend,
3645#endif
ed568912
KH		 3646};
3647
3648MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3649MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3650MODULE_LICENSE("GPL");
3651
1e4c7b0d
OH		 3652/* Provide a module alias so root-on-sbp2 initrds don't break. */
3653#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3654MODULE_ALIAS("ohci1394");
3655#endif
3656
ed568912
KH		 3657static int __init fw_ohci_init(void)
3658{
3659 return pci_register_driver(&fw_ohci_pci_driver);
3660}
3661
3662static void __exit fw_ohci_cleanup(void)
3663{
3664 pci_unregister_driver(&fw_ohci_pci_driver);
3665}
3666
3667module_init(fw_ohci_init);
3668module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
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