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firewire: make PHY packet header format consistent
[deliverable/linux.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
65b2742a 21#include <linux/bug.h>
e524f616 22#include <linux/compiler.h>
ed568912 23#include <linux/delay.h>
e8ca9702 24#include <linux/device.h>
cf3e72fd 25#include <linux/dma-mapping.h>
77c9a5da 26#include <linux/firewire.h>
e8ca9702 27#include <linux/firewire-constants.h>
a7fb60db
SR		 28#include <linux/init.h>
29#include <linux/interrupt.h>
e8ca9702 30#include <linux/io.h>
a7fb60db 31#include <linux/kernel.h>
e8ca9702 32#include <linux/list.h>
faa2fb4e 33#include <linux/mm.h>
a7fb60db 34#include <linux/module.h>
ad3c0fe8 35#include <linux/moduleparam.h>
02d37bed 36#include <linux/mutex.h>
a7fb60db 37#include <linux/pci.h>
fc383796 38#include <linux/pci_ids.h>
5a0e3ad6 39#include <linux/slab.h>
c26f0234 40#include <linux/spinlock.h>
e8ca9702 41#include <linux/string.h>
e78483c5 42#include <linux/time.h>
7a39d8b8 43#include <linux/vmalloc.h>
cf3e72fd 44
e8ca9702 45#include <asm/byteorder.h>
c26f0234 46#include <asm/page.h>
ee71c2f9 47#include <asm/system.h>
ed568912 48
ea8d006b
SR		 49#ifdef CONFIG_PPC_PMAC
50#include <asm/pmac_feature.h>
51#endif
52
77c9a5da
SR		 53#include "core.h"
54#include "ohci.h"
ed568912 55
a77754a7
KH		 56#define DESCRIPTOR_OUTPUT_MORE 0
57#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
58#define DESCRIPTOR_INPUT_MORE (2 << 12)
59#define DESCRIPTOR_INPUT_LAST (3 << 12)
60#define DESCRIPTOR_STATUS (1 << 11)
61#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
62#define DESCRIPTOR_PING (1 << 7)
63#define DESCRIPTOR_YY (1 << 6)
64#define DESCRIPTOR_NO_IRQ (0 << 4)
65#define DESCRIPTOR_IRQ_ERROR (1 << 4)
66#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
67#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
68#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 69
70struct descriptor {
71 __le16 req_count;
72 __le16 control;
73 __le32 data_address;
74 __le32 branch_address;
75 __le16 res_count;
76 __le16 transfer_status;
77} __attribute__((aligned(16)));
78
a77754a7
KH		 79#define CONTROL_SET(regs) (regs)
80#define CONTROL_CLEAR(regs) ((regs) + 4)
81#define COMMAND_PTR(regs) ((regs) + 12)
82#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 83
7a39d8b8
CL		 84#define AR_BUFFER_SIZE (32*1024)
85#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
86/* we need at least two pages for proper list management */
87#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
88
89#define MAX_ASYNC_PAYLOAD 4096
90#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
91#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 92
32b46093
KH		 93struct ar_context {
94 struct fw_ohci *ohci;
7a39d8b8
CL		 95 struct page *pages[AR_BUFFERS];
96 void *buffer;
97 struct descriptor *descriptors;
98 dma_addr_t descriptors_bus;
32b46093 99 void *pointer;
7a39d8b8 100 unsigned int last_buffer_index;
72e318e0 101 u32 regs;
ed568912
KH		 102 struct tasklet_struct tasklet;
103};
104
30200739
KH		 105struct context;
106
107typedef int (*descriptor_callback_t)(struct context *ctx,
108 struct descriptor *d,
109 struct descriptor *last);
fe5ca634
DM		 110
111/*
112 * A buffer that contains a block of DMA-able coherent memory used for
113 * storing a portion of a DMA descriptor program.
114 */
115struct descriptor_buffer {
116 struct list_head list;
117 dma_addr_t buffer_bus;
118 size_t buffer_size;
119 size_t used;
120 struct descriptor buffer[0];
121};
122
30200739 123struct context {
373b2edd 124 struct fw_ohci *ohci;
30200739 125 u32 regs;
fe5ca634 126 int total_allocation;
373b2edd 127
fe5ca634
DM		 128 /*
129 * List of page-sized buffers for storing DMA descriptors.
130 * Head of list contains buffers in use and tail of list contains
131 * free buffers.
132 */
133 struct list_head buffer_list;
134
135 /*
136 * Pointer to a buffer inside buffer_list that contains the tail
137 * end of the current DMA program.
138 */
139 struct descriptor_buffer *buffer_tail;
140
141 /*
142 * The descriptor containing the branch address of the first
143 * descriptor that has not yet been filled by the device.
144 */
145 struct descriptor *last;
146
147 /*
148 * The last descriptor in the DMA program. It contains the branch
149 * address that must be updated upon appending a new descriptor.
150 */
151 struct descriptor *prev;
30200739
KH		 152
153 descriptor_callback_t callback;
154
373b2edd 155 struct tasklet_struct tasklet;
30200739 156};
30200739 157
a77754a7
KH		 158#define IT_HEADER_SY(v) ((v) << 0)
159#define IT_HEADER_TCODE(v) ((v) << 4)
160#define IT_HEADER_CHANNEL(v) ((v) << 8)
161#define IT_HEADER_TAG(v) ((v) << 14)
162#define IT_HEADER_SPEED(v) ((v) << 16)
163#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 164
165struct iso_context {
166 struct fw_iso_context base;
30200739 167 struct context context;
0642b657 168 int excess_bytes;
9b32d5f3
KH		 169 void *header;
170 size_t header_length;
ed568912
KH		 171};
172
173#define CONFIG_ROM_SIZE 1024
174
175struct fw_ohci {
176 struct fw_card card;
177
178 __iomem char *registers;
e636fe25 179 int node_id;
ed568912 180 int generation;
e09770db 181 int request_generation; /* for timestamping incoming requests */
4a635593 182 unsigned quirks;
a1a1132b 183 unsigned int pri_req_max;
a48777e0 184 u32 bus_time;
4ffb7a6a 185 bool is_root;
c8a94ded 186 bool csr_state_setclear_abdicate;
ed568912 187
c781c06d
KH		 188 /*
189 * Spinlock for accessing fw_ohci data. Never call out of
190 * this driver with this lock held.
191 */
ed568912 192 spinlock_t lock;
ed568912 193
02d37bed
SR		 194 struct mutex phy_reg_mutex;
195
ed568912
KH		 196 struct ar_context ar_request_ctx;
197 struct ar_context ar_response_ctx;
f319b6a0
KH		 198 struct context at_request_ctx;
199 struct context at_response_ctx;
ed568912 200
872e330e 201 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 202 struct iso_context *it_context_list;
872e330e
SR		 203 u64 ir_context_channels; /* unoccupied channels */
204 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 205 struct iso_context *ir_context_list;
872e330e
SR		 206 u64 mc_channels; /* channels in use by the multichannel IR context */
207 bool mc_allocated;
ecb1cf9c
SR		 208
209 __be32 *config_rom;
210 dma_addr_t config_rom_bus;
211 __be32 *next_config_rom;
212 dma_addr_t next_config_rom_bus;
213 __be32 next_header;
214
215 __le32 *self_id_cpu;
216 dma_addr_t self_id_bus;
217 struct tasklet_struct bus_reset_tasklet;
218
219 u32 self_id_buffer[512];
ed568912
KH		 220};
221
95688e97 222static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 223{
224 return container_of(card, struct fw_ohci, card);
225}
226
295e3feb
KH		 227#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228#define IR_CONTEXT_BUFFER_FILL 0x80000000
229#define IR_CONTEXT_ISOCH_HEADER 0x40000000
230#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 233
234#define CONTEXT_RUN 0x8000
235#define CONTEXT_WAKE 0x1000
236#define CONTEXT_DEAD 0x0800
237#define CONTEXT_ACTIVE 0x0400
238
8b7b6afa 239#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 240#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
242
ed568912
KH		 243#define OHCI1394_REGISTER_SIZE 0x800
244#define OHCI_LOOP_COUNT 500
245#define OHCI1394_PCI_HCI_Control 0x40
246#define SELF_ID_BUF_SIZE 0x800
32b46093 247#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 248#define OHCI_VERSION_1_1 0x010010
0edeefd9 249
ed568912
KH		 250static char ohci_driver_name[] = KBUILD_MODNAME;
251
9993e0fe 252#define PCI_DEVICE_ID_AGERE_FW643 0x5901
262444ee 253#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b
CL		 254#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
255
4a635593
SR		 256#define QUIRK_CYCLE_TIMER 1
257#define QUIRK_RESET_PACKET 2
258#define QUIRK_BE_HEADERS 4
925e7a65 259#define QUIRK_NO_1394A 8
262444ee 260#define QUIRK_NO_MSI 16
4a635593
SR		 261
262/* In case of multiple matches in ohci_quirks[], only the first one is used. */
263static const struct {
9993e0fe 264 unsigned short vendor, device, revision, flags;
4a635593 265} ohci_quirks[] = {
9993e0fe
SR		 266 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
267 QUIRK_CYCLE_TIMER},
268
269 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
270 QUIRK_BE_HEADERS},
271
272 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
273 QUIRK_NO_MSI},
274
275 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
276 QUIRK_NO_MSI},
277
278 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
279 QUIRK_CYCLE_TIMER},
280
281 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
282 QUIRK_CYCLE_TIMER},
283
284 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
285 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
286
287 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
288 QUIRK_RESET_PACKET},
289
290 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
291 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 292};
293
3e9cc2f3
SR		 294/* This overrides anything that was found in ohci_quirks[]. */
295static int param_quirks;
296module_param_named(quirks, param_quirks, int, 0644);
297MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
298 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
299 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
300 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 301 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 302 ", disable MSI = " __stringify(QUIRK_NO_MSI)
3e9cc2f3
SR		 303 ")");
304
a007bb85 305#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 306#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 307#define OHCI_PARAM_DEBUG_IRQS 4
308#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8 309
5da3dac8
SR		 310#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
311
ad3c0fe8
SR		 312static int param_debug;
313module_param_named(debug, param_debug, int, 0644);
314MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 315 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 316 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
317 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
318 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 319 ", or a combination, or all = -1)");
320
321static void log_irqs(u32 evt)
322{
a007bb85
SR		 323 if (likely(!(param_debug &
324 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
325 return;
326
327 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
328 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 329 return;
330
a48777e0 331 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 332 evt & OHCI1394_selfIDComplete ? " selfID" : "",
333 evt & OHCI1394_RQPkt ? " AR_req" : "",
334 evt & OHCI1394_RSPkt ? " AR_resp" : "",
335 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
336 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
337 evt & OHCI1394_isochRx ? " IR" : "",
338 evt & OHCI1394_isochTx ? " IT" : "",
339 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
340 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 341 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 342 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7
SR		 343 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
344 evt & OHCI1394_busReset ? " busReset" : "",
345 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
346 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
347 OHCI1394_respTxComplete | OHCI1394_isochRx |
348 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 349 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
350 OHCI1394_cycleInconsistent |
161b96e7 351 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 352 ? " ?" : "");
353}
354
355static const char *speed[] = {
356 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
357};
358static const char *power[] = {
359 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
360 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
361};
362static const char port[] = { '.', '-', 'p', 'c', };
363
364static char _p(u32 *s, int shift)
365{
366 return port[*s >> shift & 3];
367}
368
08ddb2f4 369static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
ad3c0fe8
SR		 370{
371 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
372 return;
373
161b96e7
SR		 374 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
375 self_id_count, generation, node_id);
ad3c0fe8
SR		 376
377 for (; self_id_count--; ++s)
378 if ((*s & 1 << 23) == 0)
161b96e7
SR		 379 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
380 "%s gc=%d %s %s%s%s\n",
381 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
382 speed[*s >> 14 & 3], *s >> 16 & 63,
383 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
384 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 385 else
161b96e7
SR		 386 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
387 *s, *s >> 24 & 63,
388 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
389 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 390}
391
392static const char *evts[] = {
393 [0x00] = "evt_no_status", [0x01] = "-reserved-",
394 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
395 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
396 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
397 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
398 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
399 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
400 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
401 [0x10] = "-reserved-", [0x11] = "ack_complete",
402 [0x12] = "ack_pending ", [0x13] = "-reserved-",
403 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
404 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
405 [0x18] = "-reserved-", [0x19] = "-reserved-",
406 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
407 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
408 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
409 [0x20] = "pending/cancelled",
410};
411static const char *tcodes[] = {
412 [0x0] = "QW req", [0x1] = "BW req",
413 [0x2] = "W resp", [0x3] = "-reserved-",
414 [0x4] = "QR req", [0x5] = "BR req",
415 [0x6] = "QR resp", [0x7] = "BR resp",
416 [0x8] = "cycle start", [0x9] = "Lk req",
417 [0xa] = "async stream packet", [0xb] = "Lk resp",
418 [0xc] = "-reserved-", [0xd] = "-reserved-",
419 [0xe] = "link internal", [0xf] = "-reserved-",
420};
ad3c0fe8
SR		 421
422static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
423{
424 int tcode = header[0] >> 4 & 0xf;
425 char specific[12];
426
427 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
428 return;
429
430 if (unlikely(evt >= ARRAY_SIZE(evts)))
431 evt = 0x1f;
432
08ddb2f4 433 if (evt == OHCI1394_evt_bus_reset) {
161b96e7
SR		 434 fw_notify("A%c evt_bus_reset, generation %d\n",
435 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 436 return;
437 }
438
ad3c0fe8
SR		 439 switch (tcode) {
440 case 0x0: case 0x6: case 0x8:
441 snprintf(specific, sizeof(specific), " = %08x",
442 be32_to_cpu((__force __be32)header[3]));
443 break;
444 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
445 snprintf(specific, sizeof(specific), " %x,%x",
446 header[3] >> 16, header[3] & 0xffff);
447 break;
448 default:
449 specific[0] = '\0';
450 }
451
452 switch (tcode) {
5b06db16 453 case 0xa:
161b96e7 454 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
ad3c0fe8 455 break;
5b06db16
CL		 456 case 0xe:
457 fw_notify("A%c %s, PHY %08x %08x\n",
458 dir, evts[evt], header[1], header[2]);
459 break;
ad3c0fe8 460 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
161b96e7
SR		 461 fw_notify("A%c spd %x tl %02x, "
462 "%04x -> %04x, %s, "
463 "%s, %04x%08x%s\n",
464 dir, speed, header[0] >> 10 & 0x3f,
465 header[1] >> 16, header[0] >> 16, evts[evt],
466 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 467 break;
468 default:
161b96e7
SR		 469 fw_notify("A%c spd %x tl %02x, "
470 "%04x -> %04x, %s, "
471 "%s%s\n",
472 dir, speed, header[0] >> 10 & 0x3f,
473 header[1] >> 16, header[0] >> 16, evts[evt],
474 tcodes[tcode], specific);
ad3c0fe8
SR		 475 }
476}
477
478#else
479
5da3dac8
SR		 480#define param_debug 0
481static inline void log_irqs(u32 evt) {}
482static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
483static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
ad3c0fe8
SR		 484
485#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
486
95688e97 487static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 488{
489 writel(data, ohci->registers + offset);
490}
491
95688e97 492static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 493{
494 return readl(ohci->registers + offset);
495}
496
95688e97 497static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 498{
499 /* Do a dummy read to flush writes. */
500 reg_read(ohci, OHCI1394_Version);
501}
502
35d999b1 503static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 504{
4a96b4fc 505 u32 val;
35d999b1 506 int i;
ed568912
KH		 507
508 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 509 for (i = 0; i < 3 + 100; i++) {
35d999b1
SR		 510 val = reg_read(ohci, OHCI1394_PhyControl);
511 if (val & OHCI1394_PhyControl_ReadDone)
512 return OHCI1394_PhyControl_ReadData(val);
513
153e3979
CL		 514 /*
515 * Try a few times without waiting. Sleeping is necessary
516 * only when the link/PHY interface is busy.
517 */
518 if (i >= 3)
519 msleep(1);
ed568912 520 }
35d999b1 521 fw_error("failed to read phy reg\n");
ed568912 522
35d999b1
SR		 523 return -EBUSY;
524}
4a96b4fc 525
35d999b1
SR		 526static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
527{
528 int i;
ed568912 529
ed568912 530 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 531 OHCI1394_PhyControl_Write(addr, val));
153e3979 532 for (i = 0; i < 3 + 100; i++) {
35d999b1
SR		 533 val = reg_read(ohci, OHCI1394_PhyControl);
534 if (!(val & OHCI1394_PhyControl_WritePending))
535 return 0;
ed568912 536
153e3979
CL		 537 if (i >= 3)
538 msleep(1);
35d999b1
SR		 539 }
540 fw_error("failed to write phy reg\n");
541
542 return -EBUSY;
4a96b4fc
CL		 543}
544
02d37bed
SR		 545static int update_phy_reg(struct fw_ohci *ohci, int addr,
546 int clear_bits, int set_bits)
4a96b4fc 547{
02d37bed 548 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 549 if (ret < 0)
550 return ret;
4a96b4fc 551
e7014dad
CL		 552 /*
553 * The interrupt status bits are cleared by writing a one bit.
554 * Avoid clearing them unless explicitly requested in set_bits.
555 */
556 if (addr == 5)
557 clear_bits |= PHY_INT_STATUS_BITS;
558
35d999b1 559 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 560}
561
35d999b1 562static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 563{
35d999b1 564 int ret;
925e7a65 565
02d37bed 566 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 567 if (ret < 0)
568 return ret;
925e7a65 569
35d999b1 570 return read_phy_reg(ohci, addr);
ed568912
KH		 571}
572
02d37bed
SR		 573static int ohci_read_phy_reg(struct fw_card *card, int addr)
574{
575 struct fw_ohci *ohci = fw_ohci(card);
576 int ret;
577
578 mutex_lock(&ohci->phy_reg_mutex);
579 ret = read_phy_reg(ohci, addr);
580 mutex_unlock(&ohci->phy_reg_mutex);
581
582 return ret;
583}
584
585static int ohci_update_phy_reg(struct fw_card *card, int addr,
586 int clear_bits, int set_bits)
587{
588 struct fw_ohci *ohci = fw_ohci(card);
589 int ret;
590
591 mutex_lock(&ohci->phy_reg_mutex);
592 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
593 mutex_unlock(&ohci->phy_reg_mutex);
594
595 return ret;
ed568912
KH		 596}
597
7a39d8b8
CL		 598static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
599{
600 return page_private(ctx->pages[i]);
601}
602
603static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 604{
7a39d8b8 605 struct descriptor *d;
32b46093 606
7a39d8b8
CL		 607 d = &ctx->descriptors[index];
608 d->branch_address &= cpu_to_le32(~0xf);
609 d->res_count = cpu_to_le16(PAGE_SIZE);
610 d->transfer_status = 0;
32b46093 611
071595eb 612 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 613 d = &ctx->descriptors[ctx->last_buffer_index];
614 d->branch_address |= cpu_to_le32(1);
615
616 ctx->last_buffer_index = index;
32b46093 617
a77754a7 618 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
ed568912 619 flush_writes(ctx->ohci);
837596a6
CL		 620}
621
7a39d8b8 622static void ar_context_release(struct ar_context *ctx)
837596a6 623{
7a39d8b8 624 unsigned int i;
837596a6 625
7a39d8b8
CL		 626 if (ctx->descriptors)
627 dma_free_coherent(ctx->ohci->card.device,
628 AR_BUFFERS * sizeof(struct descriptor),
629 ctx->descriptors, ctx->descriptors_bus);
837596a6 630
7a39d8b8
CL		 631 if (ctx->buffer)
632 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 633
7a39d8b8
CL		 634 for (i = 0; i < AR_BUFFERS; i++)
635 if (ctx->pages[i]) {
636 dma_unmap_page(ctx->ohci->card.device,
637 ar_buffer_bus(ctx, i),
638 PAGE_SIZE, DMA_FROM_DEVICE);
639 __free_page(ctx->pages[i]);
640 }
ed568912
KH		 641}
642
7a39d8b8 643static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 644{
7a39d8b8
CL		 645 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
646 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
647 flush_writes(ctx->ohci);
a55709ba 648
7a39d8b8 649 fw_error("AR error: %s; DMA stopped\n", error_msg);
a55709ba 650 }
7a39d8b8
CL		 651 /* FIXME: restart? */
652}
653
654static inline unsigned int ar_next_buffer_index(unsigned int index)
655{
656 return (index + 1) % AR_BUFFERS;
657}
658
659static inline unsigned int ar_prev_buffer_index(unsigned int index)
660{
661 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
662}
663
664static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
665{
666 return ar_next_buffer_index(ctx->last_buffer_index);
667}
668
669/*
670 * We search for the buffer that contains the last AR packet DMA data written
671 * by the controller.
672 */
673static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
674 unsigned int *buffer_offset)
675{
676 unsigned int i, next_i, last = ctx->last_buffer_index;
677 __le16 res_count, next_res_count;
678
679 i = ar_first_buffer_index(ctx);
680 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
681
682 /* A buffer that is not yet completely filled must be the last one. */
683 while (i != last && res_count == 0) {
684
685 /* Peek at the next descriptor. */
686 next_i = ar_next_buffer_index(i);
687 rmb(); /* read descriptors in order */
688 next_res_count = ACCESS_ONCE(
689 ctx->descriptors[next_i].res_count);
690 /*
691 * If the next descriptor is still empty, we must stop at this
692 * descriptor.
693 */
694 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
695 /*
696 * The exception is when the DMA data for one packet is
697 * split over three buffers; in this case, the middle
698 * buffer's descriptor might be never updated by the
699 * controller and look still empty, and we have to peek
700 * at the third one.
701 */
702 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
703 next_i = ar_next_buffer_index(next_i);
704 rmb();
705 next_res_count = ACCESS_ONCE(
706 ctx->descriptors[next_i].res_count);
707 if (next_res_count != cpu_to_le16(PAGE_SIZE))
708 goto next_buffer_is_active;
709 }
710
711 break;
712 }
713
714next_buffer_is_active:
715 i = next_i;
716 res_count = next_res_count;
717 }
718
719 rmb(); /* read res_count before the DMA data */
720
721 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
722 if (*buffer_offset > PAGE_SIZE) {
723 *buffer_offset = 0;
724 ar_context_abort(ctx, "corrupted descriptor");
725 }
726
727 return i;
728}
729
730static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
731 unsigned int end_buffer_index,
732 unsigned int end_buffer_offset)
733{
734 unsigned int i;
735
736 i = ar_first_buffer_index(ctx);
737 while (i != end_buffer_index) {
738 dma_sync_single_for_cpu(ctx->ohci->card.device,
739 ar_buffer_bus(ctx, i),
740 PAGE_SIZE, DMA_FROM_DEVICE);
741 i = ar_next_buffer_index(i);
742 }
743 if (end_buffer_offset > 0)
744 dma_sync_single_for_cpu(ctx->ohci->card.device,
745 ar_buffer_bus(ctx, i),
746 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 747}
748
11bf20ad
SR		 749#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
750#define cond_le32_to_cpu(v) \
4a635593 751 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 752#else
753#define cond_le32_to_cpu(v) le32_to_cpu(v)
754#endif
755
32b46093 756static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 757{
ed568912 758 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 759 struct fw_packet p;
760 u32 status, length, tcode;
43286568 761 int evt;
2639a6fb 762
11bf20ad
SR		 763 p.header[0] = cond_le32_to_cpu(buffer[0]);
764 p.header[1] = cond_le32_to_cpu(buffer[1]);
765 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 766
767 tcode = (p.header[0] >> 4) & 0x0f;
768 switch (tcode) {
769 case TCODE_WRITE_QUADLET_REQUEST:
770 case TCODE_READ_QUADLET_RESPONSE:
32b46093 771 p.header[3] = (__force __u32) buffer[3];
2639a6fb 772 p.header_length = 16;
32b46093 773 p.payload_length = 0;
2639a6fb
KH		 774 break;
775
2639a6fb 776 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 777 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 778 p.header_length = 16;
779 p.payload_length = 0;
780 break;
781
782 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 783 case TCODE_READ_BLOCK_RESPONSE:
784 case TCODE_LOCK_REQUEST:
785 case TCODE_LOCK_RESPONSE:
11bf20ad 786 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 787 p.header_length = 16;
32b46093 788 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 789 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
790 ar_context_abort(ctx, "invalid packet length");
791 return NULL;
792 }
2639a6fb
KH		 793 break;
794
795 case TCODE_WRITE_RESPONSE:
796 case TCODE_READ_QUADLET_REQUEST:
32b46093 797 case OHCI_TCODE_PHY_PACKET:
2639a6fb 798 p.header_length = 12;
32b46093 799 p.payload_length = 0;
2639a6fb 800 break;
ccff9629
SR		 801
802 default:
7a39d8b8
CL		 803 ar_context_abort(ctx, "invalid tcode");
804 return NULL;
2639a6fb 805 }
ed568912 806
32b46093
KH		 807 p.payload = (void *) buffer + p.header_length;
808
809 /* FIXME: What to do about evt_* errors? */
810 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 811 status = cond_le32_to_cpu(buffer[length]);
43286568 812 evt = (status >> 16) & 0x1f;
32b46093 813
43286568 814 p.ack = evt - 16;
32b46093
KH		 815 p.speed = (status >> 21) & 0x7;
816 p.timestamp = status & 0xffff;
817 p.generation = ohci->request_generation;
ed568912 818
43286568 819 log_ar_at_event('R', p.speed, p.header, evt);
ad3c0fe8 820
c781c06d 821 /*
a4dc090b
SR		 822 * Several controllers, notably from NEC and VIA, forget to
823 * write ack_complete status at PHY packet reception.
824 */
825 if (evt == OHCI1394_evt_no_status &&
826 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
827 p.ack = ACK_COMPLETE;
828
829 /*
830 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 831 * the new generation number when a bus reset happens (see
832 * section 8.4.2.3). This helps us determine when a request
833 * was received and make sure we send the response in the same
834 * generation. We only need this for requests; for responses
835 * we use the unique tlabel for finding the matching
c781c06d 836 * request.
d34316a4
SR		 837 *
838 * Alas some chips sometimes emit bus reset packets with a
839 * wrong generation. We set the correct generation for these
840 * at a slightly incorrect time (in bus_reset_tasklet).
c781c06d 841 */
d34316a4 842 if (evt == OHCI1394_evt_bus_reset) {
4a635593 843 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 844 ohci->request_generation = (p.header[2] >> 16) & 0xff;
845 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 846 fw_core_handle_request(&ohci->card, &p);
d34316a4 847 } else {
2639a6fb 848 fw_core_handle_response(&ohci->card, &p);
d34316a4 849 }
ed568912 850
32b46093
KH		 851 return buffer + length + 1;
852}
ed568912 853
7a39d8b8
CL		 854static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
855{
856 void *next;
857
858 while (p < end) {
859 next = handle_ar_packet(ctx, p);
860 if (!next)
861 return p;
862 p = next;
863 }
864
865 return p;
866}
867
868static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
869{
870 unsigned int i;
871
872 i = ar_first_buffer_index(ctx);
873 while (i != end_buffer) {
874 dma_sync_single_for_device(ctx->ohci->card.device,
875 ar_buffer_bus(ctx, i),
876 PAGE_SIZE, DMA_FROM_DEVICE);
877 ar_context_link_page(ctx, i);
878 i = ar_next_buffer_index(i);
879 }
880}
881
32b46093
KH		 882static void ar_context_tasklet(unsigned long data)
883{
884 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 885 unsigned int end_buffer_index, end_buffer_offset;
886 void *p, *end;
32b46093 887
7a39d8b8
CL		 888 p = ctx->pointer;
889 if (!p)
890 return;
32b46093 891
7a39d8b8
CL		 892 end_buffer_index = ar_search_last_active_buffer(ctx,
893 &end_buffer_offset);
894 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
895 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 896
7a39d8b8 897 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 898 /*
7a39d8b8
CL		 899 * The filled part of the overall buffer wraps around; handle
900 * all packets up to the buffer end here. If the last packet
901 * wraps around, its tail will be visible after the buffer end
902 * because the buffer start pages are mapped there again.
c781c06d 903 */
7a39d8b8
CL		 904 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
905 p = handle_ar_packets(ctx, p, buffer_end);
906 if (p < buffer_end)
907 goto error;
908 /* adjust p to point back into the actual buffer */
909 p -= AR_BUFFERS * PAGE_SIZE;
910 }
32b46093 911
7a39d8b8
CL		 912 p = handle_ar_packets(ctx, p, end);
913 if (p != end) {
914 if (p > end)
915 ar_context_abort(ctx, "inconsistent descriptor");
916 goto error;
917 }
32b46093 918
7a39d8b8
CL		 919 ctx->pointer = p;
920 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 921
7a39d8b8 922 return;
a1f805e5 923
7a39d8b8
CL		 924error:
925 ctx->pointer = NULL;
ed568912
KH		 926}
927
53dca511
SR		 928static int ar_context_init(struct ar_context *ctx,
929 struct fw_ohci *ohci, u32 regs)
ed568912 930{
7a39d8b8
CL		 931 unsigned int i;
932 dma_addr_t dma_addr;
933 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
934 struct descriptor *d;
ed568912 935
72e318e0
KH		 936 ctx->regs = regs;
937 ctx->ohci = ohci;
ed568912
KH		 938 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
939
7a39d8b8
CL		 940 for (i = 0; i < AR_BUFFERS; i++) {
941 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
942 if (!ctx->pages[i])
943 goto out_of_memory;
944 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
945 0, PAGE_SIZE, DMA_FROM_DEVICE);
946 if (dma_mapping_error(ohci->card.device, dma_addr)) {
947 __free_page(ctx->pages[i]);
948 ctx->pages[i] = NULL;
949 goto out_of_memory;
950 }
951 set_page_private(ctx->pages[i], dma_addr);
952 }
953
954 for (i = 0; i < AR_BUFFERS; i++)
955 pages[i] = ctx->pages[i];
956 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
957 pages[AR_BUFFERS + i] = ctx->pages[i];
958 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
959 -1, PAGE_KERNEL_RO);
960 if (!ctx->buffer)
961 goto out_of_memory;
962
963 ctx->descriptors =
964 dma_alloc_coherent(ohci->card.device,
965 AR_BUFFERS * sizeof(struct descriptor),
966 &ctx->descriptors_bus,
967 GFP_KERNEL);
968 if (!ctx->descriptors)
969 goto out_of_memory;
970
971 for (i = 0; i < AR_BUFFERS; i++) {
972 d = &ctx->descriptors[i];
973 d->req_count = cpu_to_le16(PAGE_SIZE);
974 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
975 DESCRIPTOR_STATUS |
976 DESCRIPTOR_BRANCH_ALWAYS);
977 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
978 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
979 ar_next_buffer_index(i) * sizeof(struct descriptor));
980 }
32b46093 981
2aef469a 982 return 0;
7a39d8b8
CL		 983
984out_of_memory:
985 ar_context_release(ctx);
986
987 return -ENOMEM;
2aef469a
KH		 988}
989
990static void ar_context_run(struct ar_context *ctx)
991{
7a39d8b8
CL		 992 unsigned int i;
993
994 for (i = 0; i < AR_BUFFERS; i++)
995 ar_context_link_page(ctx, i);
2aef469a 996
7a39d8b8 997 ctx->pointer = ctx->buffer;
2aef469a 998
7a39d8b8 999 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1000 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
32b46093 1001 flush_writes(ctx->ohci);
ed568912 1002}
373b2edd 1003
53dca511 1004static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6
JW		 1005{
1006 int b, key;
1007
1008 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1009 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1010
1011 /* figure out which descriptor the branch address goes in */
1012 if (z == 2 && (b == 3 || key == 2))
1013 return d;
1014 else
1015 return d + z - 1;
1016}
1017
30200739
KH		 1018static void context_tasklet(unsigned long data)
1019{
1020 struct context *ctx = (struct context *) data;
30200739
KH		 1021 struct descriptor *d, *last;
1022 u32 address;
1023 int z;
fe5ca634 1024 struct descriptor_buffer *desc;
30200739 1025
fe5ca634
DM		 1026 desc = list_entry(ctx->buffer_list.next,
1027 struct descriptor_buffer, list);
1028 last = ctx->last;
30200739 1029 while (last->branch_address != 0) {
fe5ca634 1030 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1031 address = le32_to_cpu(last->branch_address);
1032 z = address & 0xf;
fe5ca634
DM		 1033 address &= ~0xf;
1034
1035 /* If the branch address points to a buffer outside of the
1036 * current buffer, advance to the next buffer. */
1037 if (address < desc->buffer_bus ||
1038 address >= desc->buffer_bus + desc->used)
1039 desc = list_entry(desc->list.next,
1040 struct descriptor_buffer, list);
1041 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1042 last = find_branch_descriptor(d, z);
30200739
KH		 1043
1044 if (!ctx->callback(ctx, d, last))
1045 break;
1046
fe5ca634
DM		 1047 if (old_desc != desc) {
1048 /* If we've advanced to the next buffer, move the
1049 * previous buffer to the free list. */
1050 unsigned long flags;
1051 old_desc->used = 0;
1052 spin_lock_irqsave(&ctx->ohci->lock, flags);
1053 list_move_tail(&old_desc->list, &ctx->buffer_list);
1054 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1055 }
1056 ctx->last = last;
30200739
KH		 1057 }
1058}
1059
fe5ca634
DM		 1060/*
1061 * Allocate a new buffer and add it to the list of free buffers for this
1062 * context. Must be called with ohci->lock held.
1063 */
53dca511 1064static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1065{
1066 struct descriptor_buffer *desc;
f5101d58 1067 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1068 int offset;
1069
1070 /*
1071 * 16MB of descriptors should be far more than enough for any DMA
1072 * program. This will catch run-away userspace or DoS attacks.
1073 */
1074 if (ctx->total_allocation >= 16*1024*1024)
1075 return -ENOMEM;
1076
1077 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1078 &bus_addr, GFP_ATOMIC);
1079 if (!desc)
1080 return -ENOMEM;
1081
1082 offset = (void *)&desc->buffer - (void *)desc;
1083 desc->buffer_size = PAGE_SIZE - offset;
1084 desc->buffer_bus = bus_addr + offset;
1085 desc->used = 0;
1086
1087 list_add_tail(&desc->list, &ctx->buffer_list);
1088 ctx->total_allocation += PAGE_SIZE;
1089
1090 return 0;
1091}
1092
53dca511
SR		 1093static int context_init(struct context *ctx, struct fw_ohci *ohci,
1094 u32 regs, descriptor_callback_t callback)
30200739
KH		 1095{
1096 ctx->ohci = ohci;
1097 ctx->regs = regs;
fe5ca634
DM		 1098 ctx->total_allocation = 0;
1099
1100 INIT_LIST_HEAD(&ctx->buffer_list);
1101 if (context_add_buffer(ctx) < 0)
30200739
KH		 1102 return -ENOMEM;
1103
fe5ca634
DM		 1104 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1105 struct descriptor_buffer, list);
1106
30200739
KH		 1107 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1108 ctx->callback = callback;
1109
c781c06d
KH		 1110 /*
1111 * We put a dummy descriptor in the buffer that has a NULL
30200739 1112 * branch address and looks like it's been sent. That way we
fe5ca634 1113 * have a descriptor to append DMA programs to.
c781c06d 1114 */
fe5ca634
DM		 1115 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1116 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1117 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1118 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1119 ctx->last = ctx->buffer_tail->buffer;
1120 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1121
1122 return 0;
1123}
1124
53dca511 1125static void context_release(struct context *ctx)
30200739
KH		 1126{
1127 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1128 struct descriptor_buffer *desc, *tmp;
30200739 1129
fe5ca634
DM		 1130 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1131 dma_free_coherent(card->device, PAGE_SIZE, desc,
1132 desc->buffer_bus -
1133 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1134}
1135
fe5ca634 1136/* Must be called with ohci->lock held */
53dca511
SR		 1137static struct descriptor *context_get_descriptors(struct context *ctx,
1138 int z, dma_addr_t *d_bus)
30200739 1139{
fe5ca634
DM		 1140 struct descriptor *d = NULL;
1141 struct descriptor_buffer *desc = ctx->buffer_tail;
1142
1143 if (z * sizeof(*d) > desc->buffer_size)
1144 return NULL;
1145
1146 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1147 /* No room for the descriptor in this buffer, so advance to the
1148 * next one. */
30200739 1149
fe5ca634
DM		 1150 if (desc->list.next == &ctx->buffer_list) {
1151 /* If there is no free buffer next in the list,
1152 * allocate one. */
1153 if (context_add_buffer(ctx) < 0)
1154 return NULL;
1155 }
1156 desc = list_entry(desc->list.next,
1157 struct descriptor_buffer, list);
1158 ctx->buffer_tail = desc;
1159 }
30200739 1160
fe5ca634 1161 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1162 memset(d, 0, z * sizeof(*d));
fe5ca634 1163 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1164
1165 return d;
1166}
1167
295e3feb 1168static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1169{
1170 struct fw_ohci *ohci = ctx->ohci;
1171
a77754a7 1172 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1173 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1174 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1175 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
30200739
KH		 1176 flush_writes(ohci);
1177}
1178
1179static void context_append(struct context *ctx,
1180 struct descriptor *d, int z, int extra)
1181{
1182 dma_addr_t d_bus;
fe5ca634 1183 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1184
fe5ca634 1185 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1186
fe5ca634 1187 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1188
1189 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1190 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1191 ctx->prev = find_branch_descriptor(d, z);
30200739 1192
a77754a7 1193 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
30200739
KH		 1194 flush_writes(ctx->ohci);
1195}
1196
1197static void context_stop(struct context *ctx)
1198{
1199 u32 reg;
b8295668 1200 int i;
30200739 1201
a77754a7 1202 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
b8295668 1203 flush_writes(ctx->ohci);
30200739 1204
b8295668 1205 for (i = 0; i < 10; i++) {
a77754a7 1206 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
b8295668 1207 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1208 return;
b8295668 1209
b980f5a2 1210 mdelay(1);
b8295668 1211 }
b0068549 1212 fw_error("Error: DMA context still active (0x%08x)\n", reg);
30200739 1213}
ed568912 1214
f319b6a0
KH		 1215struct driver_data {
1216 struct fw_packet *packet;
1217};
ed568912 1218
c781c06d
KH		 1219/*
1220 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1221 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1222 * generation handling and locking around packet queue manipulation.
1223 */
53dca511
SR		 1224static int at_context_queue_packet(struct context *ctx,
1225 struct fw_packet *packet)
ed568912 1226{
ed568912 1227 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1228 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1229 struct driver_data *driver_data;
1230 struct descriptor *d, *last;
1231 __le32 *header;
ed568912 1232 int z, tcode;
f319b6a0 1233 u32 reg;
ed568912 1234
f319b6a0
KH		 1235 d = context_get_descriptors(ctx, 4, &d_bus);
1236 if (d == NULL) {
1237 packet->ack = RCODE_SEND_ERROR;
1238 return -1;
ed568912
KH		 1239 }
1240
a77754a7 1241 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1242 d[0].res_count = cpu_to_le16(packet->timestamp);
1243
c781c06d
KH		 1244 /*
1245 * The DMA format for asyncronous link packets is different
ed568912 1246 * from the IEEE1394 layout, so shift the fields around
5b06db16 1247 * accordingly.
c781c06d 1248 */
f319b6a0 1249
5b06db16 1250 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1251 header = (__le32 *) &d[1];
5b06db16
CL		 1252 switch (tcode) {
1253 case TCODE_WRITE_QUADLET_REQUEST:
1254 case TCODE_WRITE_BLOCK_REQUEST:
1255 case TCODE_WRITE_RESPONSE:
1256 case TCODE_READ_QUADLET_REQUEST:
1257 case TCODE_READ_BLOCK_REQUEST:
1258 case TCODE_READ_QUADLET_RESPONSE:
1259 case TCODE_READ_BLOCK_RESPONSE:
1260 case TCODE_LOCK_REQUEST:
1261 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1262 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1263 (packet->speed << 16));
1264 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1265 (packet->header[0] & 0xffff0000));
1266 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1267
ed568912 1268 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1269 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1270 else
f319b6a0
KH		 1271 header[3] = (__force __le32) packet->header[3];
1272
1273 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1274 break;
1275
5b06db16 1276 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1277 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1278 (packet->speed << 16));
5b06db16
CL		 1279 header[1] = cpu_to_le32(packet->header[1]);
1280 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1281 d[0].req_count = cpu_to_le16(12);
cc550216 1282
5b06db16 1283 if (is_ping_packet(&packet->header[1]))
cc550216 1284 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1285 break;
1286
5b06db16 1287 case TCODE_STREAM_DATA:
f8c2287c
JF		 1288 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1289 (packet->speed << 16));
1290 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1291 d[0].req_count = cpu_to_le16(8);
1292 break;
1293
1294 default:
1295 /* BUG(); */
1296 packet->ack = RCODE_SEND_ERROR;
1297 return -1;
ed568912
KH		 1298 }
1299
f319b6a0
KH		 1300 driver_data = (struct driver_data *) &d[3];
1301 driver_data->packet = packet;
20d11673 1302 packet->driver_data = driver_data;
a186b4a6 1303
f319b6a0
KH		 1304 if (packet->payload_length > 0) {
1305 payload_bus =
1306 dma_map_single(ohci->card.device, packet->payload,
1307 packet->payload_length, DMA_TO_DEVICE);
8d8bb39b 1308 if (dma_mapping_error(ohci->card.device, payload_bus)) {
f319b6a0
KH		 1309 packet->ack = RCODE_SEND_ERROR;
1310 return -1;
1311 }
19593ffd
SR		 1312 packet->payload_bus = payload_bus;
1313 packet->payload_mapped = true;
f319b6a0
KH		 1314
1315 d[2].req_count = cpu_to_le16(packet->payload_length);
1316 d[2].data_address = cpu_to_le32(payload_bus);
1317 last = &d[2];
1318 z = 3;
ed568912 1319 } else {
f319b6a0
KH		 1320 last = &d[0];
1321 z = 2;
ed568912 1322 }
ed568912 1323
a77754a7
KH		 1324 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1325 DESCRIPTOR_IRQ_ALWAYS |
1326 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1327
76f73ca1
JW		 1328 /*
1329 * If the controller and packet generations don't match, we need to
1330 * bail out and try again. If IntEvent.busReset is set, the AT context
1331 * is halted, so appending to the context and trying to run it is
1332 * futile. Most controllers do the right thing and just flush the AT
1333 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1334 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1335 * up stalling out. So we just bail out in software and try again
1336 * later, and everyone is happy.
1337 * FIXME: Document how the locking works.
1338 */
1339 if (ohci->generation != packet->generation ||
1340 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
19593ffd 1341 if (packet->payload_mapped)
ab88ca48
SR		 1342 dma_unmap_single(ohci->card.device, payload_bus,
1343 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1344 packet->ack = RCODE_GENERATION;
1345 return -1;
1346 }
1347
1348 context_append(ctx, d, z, 4 - z);
ed568912 1349
f319b6a0 1350 /* If the context isn't already running, start it up. */
a77754a7 1351 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
053b3080 1352 if ((reg & CONTEXT_RUN) == 0)
f319b6a0
KH		 1353 context_run(ctx, 0);
1354
1355 return 0;
ed568912
KH		 1356}
1357
f319b6a0
KH		 1358static int handle_at_packet(struct context *context,
1359 struct descriptor *d,
1360 struct descriptor *last)
ed568912 1361{
f319b6a0 1362 struct driver_data *driver_data;
ed568912 1363 struct fw_packet *packet;
f319b6a0 1364 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1365 int evt;
1366
f319b6a0
KH		 1367 if (last->transfer_status == 0)
1368 /* This descriptor isn't done yet, stop iteration. */
1369 return 0;
ed568912 1370
f319b6a0
KH		 1371 driver_data = (struct driver_data *) &d[3];
1372 packet = driver_data->packet;
1373 if (packet == NULL)
1374 /* This packet was cancelled, just continue. */
1375 return 1;
730c32f5 1376
19593ffd 1377 if (packet->payload_mapped)
1d1dc5e8 1378 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1379 packet->payload_length, DMA_TO_DEVICE);
ed568912 1380
f319b6a0
KH		 1381 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1382 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1383
ad3c0fe8
SR		 1384 log_ar_at_event('T', packet->speed, packet->header, evt);
1385
f319b6a0
KH		 1386 switch (evt) {
1387 case OHCI1394_evt_timeout:
1388 /* Async response transmit timed out. */
1389 packet->ack = RCODE_CANCELLED;
1390 break;
ed568912 1391
f319b6a0 1392 case OHCI1394_evt_flushed:
c781c06d
KH		 1393 /*
1394 * The packet was flushed should give same error as
1395 * when we try to use a stale generation count.
1396 */
f319b6a0
KH		 1397 packet->ack = RCODE_GENERATION;
1398 break;
ed568912 1399
f319b6a0 1400 case OHCI1394_evt_missing_ack:
c781c06d
KH		 1401 /*
1402 * Using a valid (current) generation count, but the
1403 * node is not on the bus or not sending acks.
1404 */
f319b6a0
KH		 1405 packet->ack = RCODE_NO_ACK;
1406 break;
ed568912 1407
f319b6a0
KH		 1408 case ACK_COMPLETE + 0x10:
1409 case ACK_PENDING + 0x10:
1410 case ACK_BUSY_X + 0x10:
1411 case ACK_BUSY_A + 0x10:
1412 case ACK_BUSY_B + 0x10:
1413 case ACK_DATA_ERROR + 0x10:
1414 case ACK_TYPE_ERROR + 0x10:
1415 packet->ack = evt - 0x10;
1416 break;
ed568912 1417
f319b6a0
KH		 1418 default:
1419 packet->ack = RCODE_SEND_ERROR;
1420 break;
1421 }
ed568912 1422
f319b6a0 1423 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1424
f319b6a0 1425 return 1;
ed568912
KH		 1426}
1427
a77754a7
KH		 1428#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1429#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1430#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1431#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1432#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1433
53dca511
SR		 1434static void handle_local_rom(struct fw_ohci *ohci,
1435 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1436{
1437 struct fw_packet response;
1438 int tcode, length, i;
1439
a77754a7 1440 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1441 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1442 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1443 else
1444 length = 4;
1445
1446 i = csr - CSR_CONFIG_ROM;
1447 if (i + length > CONFIG_ROM_SIZE) {
1448 fw_fill_response(&response, packet->header,
1449 RCODE_ADDRESS_ERROR, NULL, 0);
1450 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1451 fw_fill_response(&response, packet->header,
1452 RCODE_TYPE_ERROR, NULL, 0);
1453 } else {
1454 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1455 (void *) ohci->config_rom + i, length);
1456 }
1457
1458 fw_core_handle_response(&ohci->card, &response);
1459}
1460
53dca511
SR		 1461static void handle_local_lock(struct fw_ohci *ohci,
1462 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1463{
1464 struct fw_packet response;
e1393667 1465 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1466 __be32 *payload, lock_old;
1467 u32 lock_arg, lock_data;
1468
a77754a7
KH		 1469 tcode = HEADER_GET_TCODE(packet->header[0]);
1470 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1471 payload = packet->payload;
a77754a7 1472 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1473
1474 if (tcode == TCODE_LOCK_REQUEST &&
1475 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1476 lock_arg = be32_to_cpu(payload[0]);
1477 lock_data = be32_to_cpu(payload[1]);
1478 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1479 lock_arg = 0;
1480 lock_data = 0;
1481 } else {
1482 fw_fill_response(&response, packet->header,
1483 RCODE_TYPE_ERROR, NULL, 0);
1484 goto out;
1485 }
1486
1487 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1488 reg_write(ohci, OHCI1394_CSRData, lock_data);
1489 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1490 reg_write(ohci, OHCI1394_CSRControl, sel);
1491
e1393667
CL		 1492 for (try = 0; try < 20; try++)
1493 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1494 lock_old = cpu_to_be32(reg_read(ohci,
1495 OHCI1394_CSRData));
1496 fw_fill_response(&response, packet->header,
1497 RCODE_COMPLETE,
1498 &lock_old, sizeof(lock_old));
1499 goto out;
1500 }
1501
1502 fw_error("swap not done (CSR lock timeout)\n");
1503 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1504
93c4cceb
KH		 1505 out:
1506 fw_core_handle_response(&ohci->card, &response);
1507}
1508
53dca511 1509static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1510{
2608203d 1511 u64 offset, csr;
93c4cceb 1512
473d28c7
KH		 1513 if (ctx == &ctx->ohci->at_request_ctx) {
1514 packet->ack = ACK_PENDING;
1515 packet->callback(packet, &ctx->ohci->card, packet->ack);
1516 }
93c4cceb
KH		 1517
1518 offset =
1519 ((unsigned long long)
a77754a7 1520 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1521 packet->header[2];
1522 csr = offset - CSR_REGISTER_BASE;
1523
1524 /* Handle config rom reads. */
1525 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1526 handle_local_rom(ctx->ohci, packet, csr);
1527 else switch (csr) {
1528 case CSR_BUS_MANAGER_ID:
1529 case CSR_BANDWIDTH_AVAILABLE:
1530 case CSR_CHANNELS_AVAILABLE_HI:
1531 case CSR_CHANNELS_AVAILABLE_LO:
1532 handle_local_lock(ctx->ohci, packet, csr);
1533 break;
1534 default:
1535 if (ctx == &ctx->ohci->at_request_ctx)
1536 fw_core_handle_request(&ctx->ohci->card, packet);
1537 else
1538 fw_core_handle_response(&ctx->ohci->card, packet);
1539 break;
1540 }
473d28c7
KH		 1541
1542 if (ctx == &ctx->ohci->at_response_ctx) {
1543 packet->ack = ACK_COMPLETE;
1544 packet->callback(packet, &ctx->ohci->card, packet->ack);
1545 }
93c4cceb 1546}
e636fe25 1547
53dca511 1548static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1549{
ed568912 1550 unsigned long flags;
2dbd7d7e 1551 int ret;
ed568912
KH		 1552
1553 spin_lock_irqsave(&ctx->ohci->lock, flags);
1554
a77754a7 1555 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1556 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1557 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1558 handle_local_request(ctx, packet);
1559 return;
e636fe25 1560 }
ed568912 1561
2dbd7d7e 1562 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1563 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1564
2dbd7d7e 1565 if (ret < 0)
f319b6a0 1566 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1567
ed568912
KH		 1568}
1569
a48777e0
CL		 1570static u32 cycle_timer_ticks(u32 cycle_timer)
1571{
1572 u32 ticks;
1573
1574 ticks = cycle_timer & 0xfff;
1575 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1576 ticks += (3072 * 8000) * (cycle_timer >> 25);
1577
1578 return ticks;
1579}
1580
1581/*
1582 * Some controllers exhibit one or more of the following bugs when updating the
1583 * iso cycle timer register:
1584 * - When the lowest six bits are wrapping around to zero, a read that happens
1585 * at the same time will return garbage in the lowest ten bits.
1586 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1587 * not incremented for about 60 ns.
1588 * - Occasionally, the entire register reads zero.
1589 *
1590 * To catch these, we read the register three times and ensure that the
1591 * difference between each two consecutive reads is approximately the same, i.e.
1592 * less than twice the other. Furthermore, any negative difference indicates an
1593 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1594 * execute, so we have enough precision to compute the ratio of the differences.)
1595 */
1596static u32 get_cycle_time(struct fw_ohci *ohci)
1597{
1598 u32 c0, c1, c2;
1599 u32 t0, t1, t2;
1600 s32 diff01, diff12;
1601 int i;
1602
1603 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1604
1605 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1606 i = 0;
1607 c1 = c2;
1608 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1609 do {
1610 c0 = c1;
1611 c1 = c2;
1612 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1613 t0 = cycle_timer_ticks(c0);
1614 t1 = cycle_timer_ticks(c1);
1615 t2 = cycle_timer_ticks(c2);
1616 diff01 = t1 - t0;
1617 diff12 = t2 - t1;
1618 } while ((diff01 <= 0 || diff12 <= 0 ||
1619 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1620 && i++ < 20);
1621 }
1622
1623 return c2;
1624}
1625
1626/*
1627 * This function has to be called at least every 64 seconds. The bus_time
1628 * field stores not only the upper 25 bits of the BUS_TIME register but also
1629 * the most significant bit of the cycle timer in bit 6 so that we can detect
1630 * changes in this bit.
1631 */
1632static u32 update_bus_time(struct fw_ohci *ohci)
1633{
1634 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1635
1636 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1637 ohci->bus_time += 0x40;
1638
1639 return ohci->bus_time | cycle_time_seconds;
1640}
1641
ed568912
KH		 1642static void bus_reset_tasklet(unsigned long data)
1643{
1644 struct fw_ohci *ohci = (struct fw_ohci *)data;
e636fe25 1645 int self_id_count, i, j, reg;
ed568912
KH		 1646 int generation, new_generation;
1647 unsigned long flags;
4eaff7d6
SR		 1648 void *free_rom = NULL;
1649 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1650 bool is_new_root;
ed568912
KH		 1651
1652 reg = reg_read(ohci, OHCI1394_NodeID);
1653 if (!(reg & OHCI1394_NodeID_idValid)) {
02ff8f8e 1654 fw_notify("node ID not valid, new bus reset in progress\n");
ed568912
KH		 1655 return;
1656 }
02ff8f8e
SR		 1657 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1658 fw_notify("malconfigured bus\n");
1659 return;
1660 }
1661 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1662 OHCI1394_NodeID_nodeNumber);
ed568912 1663
4ffb7a6a
CL		 1664 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1665 if (!(ohci->is_root && is_new_root))
1666 reg_write(ohci, OHCI1394_LinkControlSet,
1667 OHCI1394_LinkControl_cycleMaster);
1668 ohci->is_root = is_new_root;
1669
c8a9a498
SR		 1670 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1671 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1672 fw_notify("inconsistent self IDs\n");
1673 return;
1674 }
c781c06d
KH		 1675 /*
1676 * The count in the SelfIDCount register is the number of
ed568912
KH		 1677 * bytes in the self ID receive buffer. Since we also receive
1678 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1679 * bit extra to get the actual number of self IDs.
1680 */
928ec5f1
SR		 1681 self_id_count = (reg >> 3) & 0xff;
1682 if (self_id_count == 0 || self_id_count > 252) {
016bf3df
SR		 1683 fw_notify("inconsistent self IDs\n");
1684 return;
1685 }
11bf20ad 1686 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1687 rmb();
ed568912
KH		 1688
1689 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498
SR		 1690 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1691 fw_notify("inconsistent self IDs\n");
1692 return;
1693 }
11bf20ad
SR		 1694 ohci->self_id_buffer[j] =
1695 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1696 }
ee71c2f9 1697 rmb();
ed568912 1698
c781c06d
KH		 1699 /*
1700 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1701 * problem we face is that a new bus reset can start while we
1702 * read out the self IDs from the DMA buffer. If this happens,
1703 * the DMA buffer will be overwritten with new self IDs and we
1704 * will read out inconsistent data. The OHCI specification
1705 * (section 11.2) recommends a technique similar to
1706 * linux/seqlock.h, where we remember the generation of the
1707 * self IDs in the buffer before reading them out and compare
1708 * it to the current generation after reading them out. If
1709 * the two generations match we know we have a consistent set
c781c06d
KH		 1710 * of self IDs.
1711 */
ed568912
KH		 1712
1713 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1714 if (new_generation != generation) {
1715 fw_notify("recursive bus reset detected, "
1716 "discarding self ids\n");
1717 return;
1718 }
1719
1720 /* FIXME: Document how the locking works. */
1721 spin_lock_irqsave(&ohci->lock, flags);
1722
1723 ohci->generation = generation;
f319b6a0
KH		 1724 context_stop(&ohci->at_request_ctx);
1725 context_stop(&ohci->at_response_ctx);
ed568912
KH		 1726 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1727
4a635593 1728 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1729 ohci->request_generation = generation;
1730
c781c06d
KH		 1731 /*
1732 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1733 * have to do it under the spinlock also. If a new config rom
1734 * was set up before this reset, the old one is now no longer
1735 * in use and we can free it. Update the config rom pointers
1736 * to point to the current config rom and clear the
88393161 1737 * next_config_rom pointer so a new update can take place.
c781c06d 1738 */
ed568912
KH		 1739
1740 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 1741 if (ohci->next_config_rom != ohci->config_rom) {
1742 free_rom = ohci->config_rom;
1743 free_rom_bus = ohci->config_rom_bus;
1744 }
ed568912
KH		 1745 ohci->config_rom = ohci->next_config_rom;
1746 ohci->config_rom_bus = ohci->next_config_rom_bus;
1747 ohci->next_config_rom = NULL;
1748
c781c06d
KH		 1749 /*
1750 * Restore config_rom image and manually update
ed568912
KH		 1751 * config_rom registers. Writing the header quadlet
1752 * will indicate that the config rom is ready, so we
c781c06d
KH		 1753 * do that last.
1754 */
ed568912
KH		 1755 reg_write(ohci, OHCI1394_BusOptions,
1756 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 1757 ohci->config_rom[0] = ohci->next_header;
1758 reg_write(ohci, OHCI1394_ConfigROMhdr,
1759 be32_to_cpu(ohci->next_header));
ed568912
KH		 1760 }
1761
080de8c2
SR		 1762#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1763 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1764 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1765#endif
1766
ed568912
KH		 1767 spin_unlock_irqrestore(&ohci->lock, flags);
1768
4eaff7d6
SR		 1769 if (free_rom)
1770 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1771 free_rom, free_rom_bus);
1772
08ddb2f4
SR		 1773 log_selfids(ohci->node_id, generation,
1774 self_id_count, ohci->self_id_buffer);
ad3c0fe8 1775
e636fe25 1776 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 1777 self_id_count, ohci->self_id_buffer,
1778 ohci->csr_state_setclear_abdicate);
1779 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 1780}
1781
1782static irqreturn_t irq_handler(int irq, void *data)
1783{
1784 struct fw_ohci *ohci = data;
168cf9af 1785 u32 event, iso_event;
ed568912
KH		 1786 int i;
1787
1788 event = reg_read(ohci, OHCI1394_IntEventClear);
1789
a515958d 1790 if (!event || !~event)
ed568912
KH		 1791 return IRQ_NONE;
1792
8327b37b
CL		 1793 /*
1794 * busReset and postedWriteErr must not be cleared yet
1795 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1796 */
1797 reg_write(ohci, OHCI1394_IntEventClear,
1798 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
ad3c0fe8 1799 log_irqs(event);
ed568912
KH		 1800
1801 if (event & OHCI1394_selfIDComplete)
1802 tasklet_schedule(&ohci->bus_reset_tasklet);
1803
1804 if (event & OHCI1394_RQPkt)
1805 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1806
1807 if (event & OHCI1394_RSPkt)
1808 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1809
1810 if (event & OHCI1394_reqTxComplete)
1811 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1812
1813 if (event & OHCI1394_respTxComplete)
1814 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1815
c889475f 1816 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
ed568912
KH		 1817 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1818
1819 while (iso_event) {
1820 i = ffs(iso_event) - 1;
30200739 1821 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
ed568912
KH		 1822 iso_event &= ~(1 << i);
1823 }
1824
c889475f 1825 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
ed568912
KH		 1826 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1827
1828 while (iso_event) {
1829 i = ffs(iso_event) - 1;
30200739 1830 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
ed568912
KH		 1831 iso_event &= ~(1 << i);
1832 }
1833
75f7832e
JW		 1834 if (unlikely(event & OHCI1394_regAccessFail))
1835 fw_error("Register access failure - "
1836 "please notify linux1394-devel@lists.sf.net\n");
1837
8327b37b
CL		 1838 if (unlikely(event & OHCI1394_postedWriteErr)) {
1839 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1840 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1841 reg_write(ohci, OHCI1394_IntEventClear,
1842 OHCI1394_postedWriteErr);
e524f616 1843 fw_error("PCI posted write error\n");
8327b37b 1844 }
e524f616 1845
bb9f2206
SR		 1846 if (unlikely(event & OHCI1394_cycleTooLong)) {
1847 if (printk_ratelimit())
1848 fw_notify("isochronous cycle too long\n");
1849 reg_write(ohci, OHCI1394_LinkControlSet,
1850 OHCI1394_LinkControl_cycleMaster);
1851 }
1852
5ed1f321
JF		 1853 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1854 /*
1855 * We need to clear this event bit in order to make
1856 * cycleMatch isochronous I/O work. In theory we should
1857 * stop active cycleMatch iso contexts now and restart
1858 * them at least two cycles later. (FIXME?)
1859 */
1860 if (printk_ratelimit())
1861 fw_notify("isochronous cycle inconsistent\n");
1862 }
1863
a48777e0
CL		 1864 if (event & OHCI1394_cycle64Seconds) {
1865 spin_lock(&ohci->lock);
1866 update_bus_time(ohci);
1867 spin_unlock(&ohci->lock);
e597e989
CL		 1868 } else
1869 flush_writes(ohci);
a48777e0 1870
ed568912
KH		 1871 return IRQ_HANDLED;
1872}
1873
2aef469a
KH		 1874static int software_reset(struct fw_ohci *ohci)
1875{
1876 int i;
1877
1878 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1879
1880 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1881 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1882 OHCI1394_HCControl_softReset) == 0)
1883 return 0;
1884 msleep(1);
1885 }
1886
1887 return -EBUSY;
1888}
1889
8e85973e
SR		 1890static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1891{
1892 size_t size = length * 4;
1893
1894 memcpy(dest, src, size);
1895 if (size < CONFIG_ROM_SIZE)
1896 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1897}
1898
925e7a65
CL		 1899static int configure_1394a_enhancements(struct fw_ohci *ohci)
1900{
1901 bool enable_1394a;
35d999b1 1902 int ret, clear, set, offset;
925e7a65
CL		 1903
1904 /* Check if the driver should configure link and PHY. */
1905 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1906 OHCI1394_HCControl_programPhyEnable))
1907 return 0;
1908
1909 /* Paranoia: check whether the PHY supports 1394a, too. */
1910 enable_1394a = false;
35d999b1
SR		 1911 ret = read_phy_reg(ohci, 2);
1912 if (ret < 0)
1913 return ret;
1914 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1915 ret = read_paged_phy_reg(ohci, 1, 8);
1916 if (ret < 0)
1917 return ret;
1918 if (ret >= 1)
925e7a65
CL		 1919 enable_1394a = true;
1920 }
1921
1922 if (ohci->quirks & QUIRK_NO_1394A)
1923 enable_1394a = false;
1924
1925 /* Configure PHY and link consistently. */
1926 if (enable_1394a) {
1927 clear = 0;
1928 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1929 } else {
1930 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1931 set = 0;
1932 }
02d37bed 1933 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 1934 if (ret < 0)
1935 return ret;
925e7a65
CL		 1936
1937 if (enable_1394a)
1938 offset = OHCI1394_HCControlSet;
1939 else
1940 offset = OHCI1394_HCControlClear;
1941 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1942
1943 /* Clean up: configuration has been taken care of. */
1944 reg_write(ohci, OHCI1394_HCControlClear,
1945 OHCI1394_HCControl_programPhyEnable);
1946
1947 return 0;
1948}
1949
8e85973e
SR		 1950static int ohci_enable(struct fw_card *card,
1951 const __be32 *config_rom, size_t length)
ed568912
KH		 1952{
1953 struct fw_ohci *ohci = fw_ohci(card);
1954 struct pci_dev *dev = to_pci_dev(card->device);
e91b2787 1955 u32 lps, seconds, version, irqs;
35d999b1 1956 int i, ret;
ed568912 1957
2aef469a
KH		 1958 if (software_reset(ohci)) {
1959 fw_error("Failed to reset ohci card.\n");
1960 return -EBUSY;
1961 }
1962
1963 /*
1964 * Now enable LPS, which we need in order to start accessing
1965 * most of the registers. In fact, on some cards (ALI M5251),
1966 * accessing registers in the SClk domain without LPS enabled
1967 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 1968 * full link enabled. However, with some cards (well, at least
1969 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 1970 */
1971 reg_write(ohci, OHCI1394_HCControlSet,
1972 OHCI1394_HCControl_LPS |
1973 OHCI1394_HCControl_postedWriteEnable);
1974 flush_writes(ohci);
02214724
JW		 1975
1976 for (lps = 0, i = 0; !lps && i < 3; i++) {
1977 msleep(50);
1978 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1979 OHCI1394_HCControl_LPS;
1980 }
1981
1982 if (!lps) {
1983 fw_error("Failed to set Link Power Status\n");
1984 return -EIO;
1985 }
2aef469a
KH		 1986
1987 reg_write(ohci, OHCI1394_HCControlClear,
1988 OHCI1394_HCControl_noByteSwapData);
1989
affc9c24 1990 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a
KH		 1991 reg_write(ohci, OHCI1394_LinkControlSet,
1992 OHCI1394_LinkControl_rcvSelfID |
bf54e146 1993 OHCI1394_LinkControl_rcvPhyPkt |
2aef469a
KH		 1994 OHCI1394_LinkControl_cycleTimerEnable |
1995 OHCI1394_LinkControl_cycleMaster);
1996
1997 reg_write(ohci, OHCI1394_ATRetries,
1998 OHCI1394_MAX_AT_REQ_RETRIES |
1999 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2000 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2001 (200 << 16));
2aef469a 2002
a48777e0
CL		 2003 seconds = lower_32_bits(get_seconds());
2004 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2005 ohci->bus_time = seconds & ~0x3f;
2006
e91b2787
CL		 2007 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2008 if (version >= OHCI_VERSION_1_1) {
2009 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2010 0xfffffffe);
db3c9cc1 2011 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2012 }
2013
a1a1132b
CL		 2014 /* Get implemented bits of the priority arbitration request counter. */
2015 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2016 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2017 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2018 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a
KH		 2019
2020 ar_context_run(&ohci->ar_request_ctx);
2021 ar_context_run(&ohci->ar_response_ctx);
2022
2aef469a
KH		 2023 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2024 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2025 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2026
35d999b1
SR		 2027 ret = configure_1394a_enhancements(ohci);
2028 if (ret < 0)
2029 return ret;
925e7a65 2030
2aef469a 2031 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2032 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2033 if (ret < 0)
2034 return ret;
2aef469a 2035
c781c06d
KH		 2036 /*
2037 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2038 * update mechanism described below in ohci_set_config_rom()
2039 * is not active. We have to update ConfigRomHeader and
2040 * BusOptions manually, and the write to ConfigROMmap takes
2041 * effect immediately. We tie this to the enabling of the
2042 * link, so we have a valid config rom before enabling - the
2043 * OHCI requires that ConfigROMhdr and BusOptions have valid
2044 * values before enabling.
2045 *
2046 * However, when the ConfigROMmap is written, some controllers
2047 * always read back quadlets 0 and 2 from the config rom to
2048 * the ConfigRomHeader and BusOptions registers on bus reset.
2049 * They shouldn't do that in this initial case where the link
2050 * isn't enabled. This means we have to use the same
2051 * workaround here, setting the bus header to 0 and then write
2052 * the right values in the bus reset tasklet.
2053 */
2054
0bd243c4
KH		 2055 if (config_rom) {
2056 ohci->next_config_rom =
2057 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2058 &ohci->next_config_rom_bus,
2059 GFP_KERNEL);
2060 if (ohci->next_config_rom == NULL)
2061 return -ENOMEM;
ed568912 2062
8e85973e 2063 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2064 } else {
2065 /*
2066 * In the suspend case, config_rom is NULL, which
2067 * means that we just reuse the old config rom.
2068 */
2069 ohci->next_config_rom = ohci->config_rom;
2070 ohci->next_config_rom_bus = ohci->config_rom_bus;
2071 }
ed568912 2072
8e85973e 2073 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2074 ohci->next_config_rom[0] = 0;
2075 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2076 reg_write(ohci, OHCI1394_BusOptions,
2077 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2078 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2079
2080 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2081
262444ee
CL		 2082 if (!(ohci->quirks & QUIRK_NO_MSI))
2083 pci_enable_msi(dev);
ed568912 2084 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2085 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2086 ohci_driver_name, ohci)) {
2087 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2088 pci_disable_msi(dev);
ed568912
KH		 2089 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2090 ohci->config_rom, ohci->config_rom_bus);
2091 return -EIO;
2092 }
2093
148c7866
SR		 2094 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2095 OHCI1394_RQPkt | OHCI1394_RSPkt |
2096 OHCI1394_isochTx | OHCI1394_isochRx |
2097 OHCI1394_postedWriteErr |
2098 OHCI1394_selfIDComplete |
2099 OHCI1394_regAccessFail |
a48777e0 2100 OHCI1394_cycle64Seconds |
148c7866
SR		 2101 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2102 OHCI1394_masterIntEnable;
2103 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2104 irqs |= OHCI1394_busReset;
2105 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2106
ed568912
KH		 2107 reg_write(ohci, OHCI1394_HCControlSet,
2108 OHCI1394_HCControl_linkEnable |
2109 OHCI1394_HCControl_BIBimageValid);
2110 flush_writes(ohci);
2111
02d37bed
SR		 2112 /* We are ready to go, reset bus to finish initialization. */
2113 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2114
2115 return 0;
2116}
2117
53dca511 2118static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2119 const __be32 *config_rom, size_t length)
ed568912
KH		 2120{
2121 struct fw_ohci *ohci;
2122 unsigned long flags;
2dbd7d7e 2123 int ret = -EBUSY;
ed568912 2124 __be32 *next_config_rom;
f5101d58 2125 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2126
2127 ohci = fw_ohci(card);
2128
c781c06d
KH		 2129 /*
2130 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2131 * mechanism is a bit tricky, but easy enough to use. See
2132 * section 5.5.6 in the OHCI specification.
2133 *
2134 * The OHCI controller caches the new config rom address in a
2135 * shadow register (ConfigROMmapNext) and needs a bus reset
2136 * for the changes to take place. When the bus reset is
2137 * detected, the controller loads the new values for the
2138 * ConfigRomHeader and BusOptions registers from the specified
2139 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2140 * shadow register. All automatically and atomically.
2141 *
2142 * Now, there's a twist to this story. The automatic load of
2143 * ConfigRomHeader and BusOptions doesn't honor the
2144 * noByteSwapData bit, so with a be32 config rom, the
2145 * controller will load be32 values in to these registers
2146 * during the atomic update, even on litte endian
2147 * architectures. The workaround we use is to put a 0 in the
2148 * header quadlet; 0 is endian agnostic and means that the
2149 * config rom isn't ready yet. In the bus reset tasklet we
2150 * then set up the real values for the two registers.
2151 *
2152 * We use ohci->lock to avoid racing with the code that sets
2153 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2154 */
2155
2156 next_config_rom =
2157 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2158 &next_config_rom_bus, GFP_KERNEL);
2159 if (next_config_rom == NULL)
2160 return -ENOMEM;
2161
2162 spin_lock_irqsave(&ohci->lock, flags);
2163
2164 if (ohci->next_config_rom == NULL) {
2165 ohci->next_config_rom = next_config_rom;
2166 ohci->next_config_rom_bus = next_config_rom_bus;
2167
8e85973e 2168 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912
KH		 2169
2170 ohci->next_header = config_rom[0];
2171 ohci->next_config_rom[0] = 0;
2172
2173 reg_write(ohci, OHCI1394_ConfigROMmap,
2174 ohci->next_config_rom_bus);
2dbd7d7e 2175 ret = 0;
ed568912
KH		 2176 }
2177
2178 spin_unlock_irqrestore(&ohci->lock, flags);
2179
c781c06d
KH		 2180 /*
2181 * Now initiate a bus reset to have the changes take
ed568912
KH		 2182 * effect. We clean up the old config rom memory and DMA
2183 * mappings in the bus reset tasklet, since the OHCI
2184 * controller could need to access it before the bus reset
c781c06d
KH		 2185 * takes effect.
2186 */
2dbd7d7e 2187 if (ret == 0)
02d37bed 2188 fw_schedule_bus_reset(&ohci->card, true, true);
4eaff7d6
SR		 2189 else
2190 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2191 next_config_rom, next_config_rom_bus);
ed568912 2192
2dbd7d7e 2193 return ret;
ed568912
KH		 2194}
2195
2196static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2197{
2198 struct fw_ohci *ohci = fw_ohci(card);
2199
2200 at_context_transmit(&ohci->at_request_ctx, packet);
2201}
2202
2203static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2204{
2205 struct fw_ohci *ohci = fw_ohci(card);
2206
2207 at_context_transmit(&ohci->at_response_ctx, packet);
2208}
2209
730c32f5
KH		 2210static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2211{
2212 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2213 struct context *ctx = &ohci->at_request_ctx;
2214 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2215 int ret = -ENOENT;
730c32f5 2216
f319b6a0 2217 tasklet_disable(&ctx->tasklet);
730c32f5 2218
f319b6a0
KH		 2219 if (packet->ack != 0)
2220 goto out;
730c32f5 2221
19593ffd 2222 if (packet->payload_mapped)
1d1dc5e8
SR		 2223 dma_unmap_single(ohci->card.device, packet->payload_bus,
2224 packet->payload_length, DMA_TO_DEVICE);
2225
ad3c0fe8 2226 log_ar_at_event('T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2227 driver_data->packet = NULL;
2228 packet->ack = RCODE_CANCELLED;
2229 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2230 ret = 0;
f319b6a0
KH		 2231 out:
2232 tasklet_enable(&ctx->tasklet);
730c32f5 2233
2dbd7d7e 2234 return ret;
730c32f5
KH		 2235}
2236
53dca511
SR		 2237static int ohci_enable_phys_dma(struct fw_card *card,
2238 int node_id, int generation)
ed568912 2239{
080de8c2
SR		 2240#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2241 return 0;
2242#else
ed568912
KH		 2243 struct fw_ohci *ohci = fw_ohci(card);
2244 unsigned long flags;
2dbd7d7e 2245 int n, ret = 0;
ed568912 2246
c781c06d
KH		 2247 /*
2248 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2249 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2250 */
ed568912
KH		 2251
2252 spin_lock_irqsave(&ohci->lock, flags);
2253
2254 if (ohci->generation != generation) {
2dbd7d7e 2255 ret = -ESTALE;
ed568912
KH		 2256 goto out;
2257 }
2258
c781c06d
KH		 2259 /*
2260 * Note, if the node ID contains a non-local bus ID, physical DMA is
2261 * enabled for _all_ nodes on remote buses.
2262 */
907293d7
SR		 2263
2264 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2265 if (n < 32)
2266 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2267 else
2268 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2269
ed568912 2270 flush_writes(ohci);
ed568912 2271 out:
6cad95fe 2272 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2273
2274 return ret;
080de8c2 2275#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2276}
373b2edd 2277
0fcff4e3 2278static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2279{
60d32970 2280 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2281 unsigned long flags;
2282 u32 value;
60d32970
CL		 2283
2284 switch (csr_offset) {
4ffb7a6a
CL		 2285 case CSR_STATE_CLEAR:
2286 case CSR_STATE_SET:
4ffb7a6a
CL		 2287 if (ohci->is_root &&
2288 (reg_read(ohci, OHCI1394_LinkControlSet) &
2289 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2290 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2291 else
c8a94ded
SR		 2292 value = 0;
2293 if (ohci->csr_state_setclear_abdicate)
2294 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2295
c8a94ded 2296 return value;
4a9bde9b 2297
506f1a31
CL		 2298 case CSR_NODE_IDS:
2299 return reg_read(ohci, OHCI1394_NodeID) << 16;
2300
60d32970
CL		 2301 case CSR_CYCLE_TIME:
2302 return get_cycle_time(ohci);
2303
a48777e0
CL		 2304 case CSR_BUS_TIME:
2305 /*
2306 * We might be called just after the cycle timer has wrapped
2307 * around but just before the cycle64Seconds handler, so we
2308 * better check here, too, if the bus time needs to be updated.
2309 */
2310 spin_lock_irqsave(&ohci->lock, flags);
2311 value = update_bus_time(ohci);
2312 spin_unlock_irqrestore(&ohci->lock, flags);
2313 return value;
2314
27a2329f
CL		 2315 case CSR_BUSY_TIMEOUT:
2316 value = reg_read(ohci, OHCI1394_ATRetries);
2317 return (value >> 4) & 0x0ffff00f;
2318
a1a1132b
CL		 2319 case CSR_PRIORITY_BUDGET:
2320 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2321 (ohci->pri_req_max << 8);
2322
60d32970
CL		 2323 default:
2324 WARN_ON(1);
2325 return 0;
2326 }
b677532b
CL		 2327}
2328
0fcff4e3 2329static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2330{
2331 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2332 unsigned long flags;
d60d7f1d 2333
506f1a31 2334 switch (csr_offset) {
4ffb7a6a 2335 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2336 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2337 reg_write(ohci, OHCI1394_LinkControlClear,
2338 OHCI1394_LinkControl_cycleMaster);
2339 flush_writes(ohci);
2340 }
c8a94ded
SR		 2341 if (value & CSR_STATE_BIT_ABDICATE)
2342 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2343 break;
4a9bde9b 2344
4ffb7a6a
CL		 2345 case CSR_STATE_SET:
2346 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2347 reg_write(ohci, OHCI1394_LinkControlSet,
2348 OHCI1394_LinkControl_cycleMaster);
2349 flush_writes(ohci);
2350 }
c8a94ded
SR		 2351 if (value & CSR_STATE_BIT_ABDICATE)
2352 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2353 break;
d60d7f1d 2354
506f1a31
CL		 2355 case CSR_NODE_IDS:
2356 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2357 flush_writes(ohci);
2358 break;
2359
9ab5071c
CL		 2360 case CSR_CYCLE_TIME:
2361 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2362 reg_write(ohci, OHCI1394_IntEventSet,
2363 OHCI1394_cycleInconsistent);
2364 flush_writes(ohci);
2365 break;
2366
a48777e0
CL		 2367 case CSR_BUS_TIME:
2368 spin_lock_irqsave(&ohci->lock, flags);
2369 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2370 spin_unlock_irqrestore(&ohci->lock, flags);
2371 break;
2372
27a2329f
CL		 2373 case CSR_BUSY_TIMEOUT:
2374 value = (value & 0xf) | ((value & 0xf) << 4) |
2375 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2376 reg_write(ohci, OHCI1394_ATRetries, value);
2377 flush_writes(ohci);
2378 break;
2379
a1a1132b
CL		 2380 case CSR_PRIORITY_BUDGET:
2381 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2382 flush_writes(ohci);
2383 break;
2384
506f1a31
CL		 2385 default:
2386 WARN_ON(1);
2387 break;
2388 }
d60d7f1d
KH		 2389}
2390
1aa292bb
DM		 2391static void copy_iso_headers(struct iso_context *ctx, void *p)
2392{
2393 int i = ctx->header_length;
2394
2395 if (i + ctx->base.header_size > PAGE_SIZE)
2396 return;
2397
2398 /*
2399 * The iso header is byteswapped to little endian by
2400 * the controller, but the remaining header quadlets
2401 * are big endian. We want to present all the headers
2402 * as big endian, so we have to swap the first quadlet.
2403 */
2404 if (ctx->base.header_size > 0)
2405 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2406 if (ctx->base.header_size > 4)
2407 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2408 if (ctx->base.header_size > 8)
2409 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2410 ctx->header_length += ctx->base.header_size;
2411}
2412
a186b4a6
JW		 2413static int handle_ir_packet_per_buffer(struct context *context,
2414 struct descriptor *d,
2415 struct descriptor *last)
2416{
2417 struct iso_context *ctx =
2418 container_of(context, struct iso_context, context);
bcee893c 2419 struct descriptor *pd;
a186b4a6 2420 __le32 *ir_header;
bcee893c 2421 void *p;
a186b4a6 2422
872e330e 2423 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2424 if (pd->transfer_status)
2425 break;
bcee893c 2426 if (pd > last)
a186b4a6
JW		 2427 /* Descriptor(s) not done yet, stop iteration */
2428 return 0;
2429
1aa292bb
DM		 2430 p = last + 1;
2431 copy_iso_headers(ctx, p);
a186b4a6 2432
bcee893c
DM		 2433 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2434 ir_header = (__le32 *) p;
872e330e
SR		 2435 ctx->base.callback.sc(&ctx->base,
2436 le32_to_cpu(ir_header[0]) & 0xffff,
2437 ctx->header_length, ctx->header,
2438 ctx->base.callback_data);
a186b4a6
JW		 2439 ctx->header_length = 0;
2440 }
2441
a186b4a6
JW		 2442 return 1;
2443}
2444
872e330e
SR		 2445/* d == last because each descriptor block is only a single descriptor. */
2446static int handle_ir_buffer_fill(struct context *context,
2447 struct descriptor *d,
2448 struct descriptor *last)
2449{
2450 struct iso_context *ctx =
2451 container_of(context, struct iso_context, context);
2452
2453 if (!last->transfer_status)
2454 /* Descriptor(s) not done yet, stop iteration */
2455 return 0;
2456
2457 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2458 ctx->base.callback.mc(&ctx->base,
2459 le32_to_cpu(last->data_address) +
2460 le16_to_cpu(last->req_count) -
2461 le16_to_cpu(last->res_count),
2462 ctx->base.callback_data);
2463
2464 return 1;
2465}
2466
30200739
KH		 2467static int handle_it_packet(struct context *context,
2468 struct descriptor *d,
2469 struct descriptor *last)
ed568912 2470{
30200739
KH		 2471 struct iso_context *ctx =
2472 container_of(context, struct iso_context, context);
31769cef
JF		 2473 int i;
2474 struct descriptor *pd;
373b2edd 2475
31769cef
JF		 2476 for (pd = d; pd <= last; pd++)
2477 if (pd->transfer_status)
2478 break;
2479 if (pd > last)
2480 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2481 return 0;
2482
31769cef
JF		 2483 i = ctx->header_length;
2484 if (i + 4 < PAGE_SIZE) {
2485 /* Present this value as big-endian to match the receive code */
2486 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2487 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2488 le16_to_cpu(pd->res_count));
2489 ctx->header_length += 4;
2490 }
2491 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
872e330e
SR		 2492 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2493 ctx->header_length, ctx->header,
2494 ctx->base.callback_data);
31769cef
JF		 2495 ctx->header_length = 0;
2496 }
30200739 2497 return 1;
ed568912
KH		 2498}
2499
872e330e
SR		 2500static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2501{
2502 u32 hi = channels >> 32, lo = channels;
2503
2504 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2505 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2506 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2507 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2508 mmiowb();
2509 ohci->mc_channels = channels;
2510}
2511
53dca511 2512static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2513 int type, int channel, size_t header_size)
ed568912
KH		 2514{
2515 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2516 struct iso_context *uninitialized_var(ctx);
2517 descriptor_callback_t uninitialized_var(callback);
2518 u64 *uninitialized_var(channels);
2519 u32 *uninitialized_var(mask), uninitialized_var(regs);
ed568912 2520 unsigned long flags;
872e330e 2521 int index, ret = -EBUSY;
ed568912 2522
872e330e 2523 spin_lock_irqsave(&ohci->lock, flags);
ed568912 2524
872e330e
SR		 2525 switch (type) {
2526 case FW_ISO_CONTEXT_TRANSMIT:
2527 mask = &ohci->it_context_mask;
30200739 2528 callback = handle_it_packet;
872e330e
SR		 2529 index = ffs(*mask) - 1;
2530 if (index >= 0) {
2531 *mask &= ~(1 << index);
2532 regs = OHCI1394_IsoXmitContextBase(index);
2533 ctx = &ohci->it_context_list[index];
2534 }
2535 break;
2536
2537 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2538 channels = &ohci->ir_context_channels;
872e330e 2539 mask = &ohci->ir_context_mask;
6498ba04 2540 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2541 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2542 if (index >= 0) {
2543 *channels &= ~(1ULL << channel);
2544 *mask &= ~(1 << index);
2545 regs = OHCI1394_IsoRcvContextBase(index);
2546 ctx = &ohci->ir_context_list[index];
2547 }
2548 break;
ed568912 2549
872e330e
SR		 2550 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2551 mask = &ohci->ir_context_mask;
2552 callback = handle_ir_buffer_fill;
2553 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2554 if (index >= 0) {
2555 ohci->mc_allocated = true;
2556 *mask &= ~(1 << index);
2557 regs = OHCI1394_IsoRcvContextBase(index);
2558 ctx = &ohci->ir_context_list[index];
2559 }
2560 break;
2561
2562 default:
2563 index = -1;
2564 ret = -ENOSYS;
4817ed24 2565 }
872e330e 2566
ed568912
KH		 2567 spin_unlock_irqrestore(&ohci->lock, flags);
2568
2569 if (index < 0)
872e330e 2570 return ERR_PTR(ret);
373b2edd 2571
2d826cc5 2572 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2573 ctx->header_length = 0;
2574 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2575 if (ctx->header == NULL) {
2576 ret = -ENOMEM;
9b32d5f3 2577 goto out;
872e330e 2578 }
2dbd7d7e
SR		 2579 ret = context_init(&ctx->context, ohci, regs, callback);
2580 if (ret < 0)
9b32d5f3 2581 goto out_with_header;
ed568912 2582
872e330e
SR		 2583 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2584 set_multichannel_mask(ohci, 0);
2585
ed568912 2586 return &ctx->base;
9b32d5f3
KH		 2587
2588 out_with_header:
2589 free_page((unsigned long)ctx->header);
2590 out:
2591 spin_lock_irqsave(&ohci->lock, flags);
872e330e
SR		 2592
2593 switch (type) {
2594 case FW_ISO_CONTEXT_RECEIVE:
2595 *channels |= 1ULL << channel;
2596 break;
2597
2598 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2599 ohci->mc_allocated = false;
2600 break;
2601 }
9b32d5f3 2602 *mask |= 1 << index;
872e330e 2603
9b32d5f3
KH		 2604 spin_unlock_irqrestore(&ohci->lock, flags);
2605
2dbd7d7e 2606 return ERR_PTR(ret);
ed568912
KH		 2607}
2608
eb0306ea
KH		 2609static int ohci_start_iso(struct fw_iso_context *base,
2610 s32 cycle, u32 sync, u32 tags)
ed568912 2611{
373b2edd 2612 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 2613 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 2614 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 2615 int index;
2616
872e330e
SR		 2617 switch (ctx->base.type) {
2618 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 2619 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 2620 match = 0;
2621 if (cycle >= 0)
2622 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 2623 (cycle & 0x7fff) << 16;
21efb3cf 2624
295e3feb
KH		 2625 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2626 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 2627 context_run(&ctx->context, match);
872e330e
SR		 2628 break;
2629
2630 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2631 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2632 /* fall through */
2633 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 2634 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 2635 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2636 if (cycle >= 0) {
2637 match |= (cycle & 0x07fff) << 12;
2638 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2639 }
ed568912 2640
295e3feb
KH		 2641 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2642 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 2643 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 2644 context_run(&ctx->context, control);
872e330e 2645 break;
295e3feb 2646 }
ed568912
KH		 2647
2648 return 0;
2649}
2650
b8295668
KH		 2651static int ohci_stop_iso(struct fw_iso_context *base)
2652{
2653 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2654 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 2655 int index;
2656
872e330e
SR		 2657 switch (ctx->base.type) {
2658 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 2659 index = ctx - ohci->it_context_list;
2660 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 2661 break;
2662
2663 case FW_ISO_CONTEXT_RECEIVE:
2664 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 2665 index = ctx - ohci->ir_context_list;
2666 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 2667 break;
b8295668
KH		 2668 }
2669 flush_writes(ohci);
2670 context_stop(&ctx->context);
2671
2672 return 0;
2673}
2674
ed568912
KH		 2675static void ohci_free_iso_context(struct fw_iso_context *base)
2676{
2677 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2678 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 2679 unsigned long flags;
2680 int index;
2681
b8295668
KH		 2682 ohci_stop_iso(base);
2683 context_release(&ctx->context);
9b32d5f3 2684 free_page((unsigned long)ctx->header);
b8295668 2685
ed568912
KH		 2686 spin_lock_irqsave(&ohci->lock, flags);
2687
872e330e
SR		 2688 switch (base->type) {
2689 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 2690 index = ctx - ohci->it_context_list;
ed568912 2691 ohci->it_context_mask |= 1 << index;
872e330e
SR		 2692 break;
2693
2694 case FW_ISO_CONTEXT_RECEIVE:
ed568912 2695 index = ctx - ohci->ir_context_list;
ed568912 2696 ohci->ir_context_mask |= 1 << index;
4817ed24 2697 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 2698 break;
2699
2700 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2701 index = ctx - ohci->ir_context_list;
2702 ohci->ir_context_mask |= 1 << index;
2703 ohci->ir_context_channels |= ohci->mc_channels;
2704 ohci->mc_channels = 0;
2705 ohci->mc_allocated = false;
2706 break;
ed568912 2707 }
ed568912
KH		 2708
2709 spin_unlock_irqrestore(&ohci->lock, flags);
2710}
2711
872e330e
SR		 2712static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2713{
2714 struct fw_ohci *ohci = fw_ohci(base->card);
2715 unsigned long flags;
2716 int ret;
2717
2718 switch (base->type) {
2719 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2720
2721 spin_lock_irqsave(&ohci->lock, flags);
2722
2723 /* Don't allow multichannel to grab other contexts' channels. */
2724 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2725 *channels = ohci->ir_context_channels;
2726 ret = -EBUSY;
2727 } else {
2728 set_multichannel_mask(ohci, *channels);
2729 ret = 0;
2730 }
2731
2732 spin_unlock_irqrestore(&ohci->lock, flags);
2733
2734 break;
2735 default:
2736 ret = -EINVAL;
2737 }
2738
2739 return ret;
2740}
2741
2742static int queue_iso_transmit(struct iso_context *ctx,
2743 struct fw_iso_packet *packet,
2744 struct fw_iso_buffer *buffer,
2745 unsigned long payload)
ed568912 2746{
30200739 2747 struct descriptor *d, *last, *pd;
ed568912
KH		 2748 struct fw_iso_packet *p;
2749 __le32 *header;
9aad8125 2750 dma_addr_t d_bus, page_bus;
ed568912
KH		 2751 u32 z, header_z, payload_z, irq;
2752 u32 payload_index, payload_end_index, next_page_index;
30200739 2753 int page, end_page, i, length, offset;
ed568912 2754
ed568912 2755 p = packet;
9aad8125 2756 payload_index = payload;
ed568912
KH		 2757
2758 if (p->skip)
2759 z = 1;
2760 else
2761 z = 2;
2762 if (p->header_length > 0)
2763 z++;
2764
2765 /* Determine the first page the payload isn't contained in. */
2766 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2767 if (p->payload_length > 0)
2768 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2769 else
2770 payload_z = 0;
2771
2772 z += payload_z;
2773
2774 /* Get header size in number of descriptors. */
2d826cc5 2775 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 2776
30200739
KH		 2777 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2778 if (d == NULL)
2779 return -ENOMEM;
ed568912
KH		 2780
2781 if (!p->skip) {
a77754a7 2782 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 2783 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 2784 /*
2785 * Link the skip address to this descriptor itself. This causes
2786 * a context to skip a cycle whenever lost cycles or FIFO
2787 * overruns occur, without dropping the data. The application
2788 * should then decide whether this is an error condition or not.
2789 * FIXME: Make the context's cycle-lost behaviour configurable?
2790 */
2791 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 2792
2793 header = (__le32 *) &d[1];
a77754a7
KH		 2794 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2795 IT_HEADER_TAG(p->tag) |
2796 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2797 IT_HEADER_CHANNEL(ctx->base.channel) |
2798 IT_HEADER_SPEED(ctx->base.speed));
ed568912 2799 header[1] =
a77754a7 2800 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 2801 p->payload_length));
2802 }
2803
2804 if (p->header_length > 0) {
2805 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 2806 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 2807 memcpy(&d[z], p->header, p->header_length);
2808 }
2809
2810 pd = d + z - payload_z;
2811 payload_end_index = payload_index + p->payload_length;
2812 for (i = 0; i < payload_z; i++) {
2813 page = payload_index >> PAGE_SHIFT;
2814 offset = payload_index & ~PAGE_MASK;
2815 next_page_index = (page + 1) << PAGE_SHIFT;
2816 length =
2817 min(next_page_index, payload_end_index) - payload_index;
2818 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 2819
2820 page_bus = page_private(buffer->pages[page]);
2821 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912
KH		 2822
2823 payload_index += length;
2824 }
2825
ed568912 2826 if (p->interrupt)
a77754a7 2827 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 2828 else
a77754a7 2829 irq = DESCRIPTOR_NO_IRQ;
ed568912 2830
30200739 2831 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 2832 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2833 DESCRIPTOR_STATUS |
2834 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 2835 irq);
ed568912 2836
30200739 2837 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 2838
2839 return 0;
2840}
373b2edd 2841
872e330e
SR		 2842static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2843 struct fw_iso_packet *packet,
2844 struct fw_iso_buffer *buffer,
2845 unsigned long payload)
a186b4a6 2846{
8c0c0cc2 2847 struct descriptor *d, *pd;
a186b4a6
JW		 2848 dma_addr_t d_bus, page_bus;
2849 u32 z, header_z, rest;
bcee893c
DM		 2850 int i, j, length;
2851 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 2852
2853 /*
1aa292bb
DM		 2854 * The OHCI controller puts the isochronous header and trailer in the
2855 * buffer, so we need at least 8 bytes.
a186b4a6 2856 */
872e330e 2857 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 2858 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 2859
2860 /* Get header size in number of descriptors. */
2861 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2862 page = payload >> PAGE_SHIFT;
2863 offset = payload & ~PAGE_MASK;
872e330e 2864 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 2865
2866 for (i = 0; i < packet_count; i++) {
2867 /* d points to the header descriptor */
bcee893c 2868 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 2869 d = context_get_descriptors(&ctx->context,
bcee893c 2870 z + header_z, &d_bus);
a186b4a6
JW		 2871 if (d == NULL)
2872 return -ENOMEM;
2873
bcee893c
DM		 2874 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2875 DESCRIPTOR_INPUT_MORE);
872e330e 2876 if (packet->skip && i == 0)
bcee893c 2877 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 2878 d->req_count = cpu_to_le16(header_size);
2879 d->res_count = d->req_count;
bcee893c 2880 d->transfer_status = 0;
a186b4a6
JW		 2881 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2882
bcee893c 2883 rest = payload_per_buffer;
8c0c0cc2 2884 pd = d;
bcee893c 2885 for (j = 1; j < z; j++) {
8c0c0cc2 2886 pd++;
bcee893c
DM		 2887 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2888 DESCRIPTOR_INPUT_MORE);
2889
2890 if (offset + rest < PAGE_SIZE)
2891 length = rest;
2892 else
2893 length = PAGE_SIZE - offset;
2894 pd->req_count = cpu_to_le16(length);
2895 pd->res_count = pd->req_count;
2896 pd->transfer_status = 0;
2897
2898 page_bus = page_private(buffer->pages[page]);
2899 pd->data_address = cpu_to_le32(page_bus + offset);
2900
2901 offset = (offset + length) & ~PAGE_MASK;
2902 rest -= length;
2903 if (offset == 0)
2904 page++;
2905 }
a186b4a6
JW		 2906 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2907 DESCRIPTOR_INPUT_LAST |
2908 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 2909 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 2910 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2911
a186b4a6
JW		 2912 context_append(&ctx->context, d, z, header_z);
2913 }
2914
2915 return 0;
2916}
2917
872e330e
SR		 2918static int queue_iso_buffer_fill(struct iso_context *ctx,
2919 struct fw_iso_packet *packet,
2920 struct fw_iso_buffer *buffer,
2921 unsigned long payload)
2922{
2923 struct descriptor *d;
2924 dma_addr_t d_bus, page_bus;
2925 int page, offset, rest, z, i, length;
2926
2927 page = payload >> PAGE_SHIFT;
2928 offset = payload & ~PAGE_MASK;
2929 rest = packet->payload_length;
2930
2931 /* We need one descriptor for each page in the buffer. */
2932 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2933
2934 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2935 return -EFAULT;
2936
2937 for (i = 0; i < z; i++) {
2938 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2939 if (d == NULL)
2940 return -ENOMEM;
2941
2942 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2943 DESCRIPTOR_BRANCH_ALWAYS);
2944 if (packet->skip && i == 0)
2945 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2946 if (packet->interrupt && i == z - 1)
2947 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2948
2949 if (offset + rest < PAGE_SIZE)
2950 length = rest;
2951 else
2952 length = PAGE_SIZE - offset;
2953 d->req_count = cpu_to_le16(length);
2954 d->res_count = d->req_count;
2955 d->transfer_status = 0;
2956
2957 page_bus = page_private(buffer->pages[page]);
2958 d->data_address = cpu_to_le32(page_bus + offset);
2959
2960 rest -= length;
2961 offset = 0;
2962 page++;
2963
2964 context_append(&ctx->context, d, 1, 0);
2965 }
2966
2967 return 0;
2968}
2969
53dca511
SR		 2970static int ohci_queue_iso(struct fw_iso_context *base,
2971 struct fw_iso_packet *packet,
2972 struct fw_iso_buffer *buffer,
2973 unsigned long payload)
295e3feb 2974{
e364cf4e 2975 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 2976 unsigned long flags;
872e330e 2977 int ret = -ENOSYS;
e364cf4e 2978
fe5ca634 2979 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 2980 switch (base->type) {
2981 case FW_ISO_CONTEXT_TRANSMIT:
2982 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2983 break;
2984 case FW_ISO_CONTEXT_RECEIVE:
2985 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2986 break;
2987 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2988 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2989 break;
2990 }
fe5ca634
DM		 2991 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2992
2dbd7d7e 2993 return ret;
295e3feb
KH		 2994}
2995
21ebcd12 2996static const struct fw_card_driver ohci_driver = {
ed568912 2997 .enable = ohci_enable,
02d37bed 2998 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 2999 .update_phy_reg = ohci_update_phy_reg,
3000 .set_config_rom = ohci_set_config_rom,
3001 .send_request = ohci_send_request,
3002 .send_response = ohci_send_response,
730c32f5 3003 .cancel_packet = ohci_cancel_packet,
ed568912 3004 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3005 .read_csr = ohci_read_csr,
3006 .write_csr = ohci_write_csr,
ed568912
KH		 3007
3008 .allocate_iso_context = ohci_allocate_iso_context,
3009 .free_iso_context = ohci_free_iso_context,
872e330e 3010 .set_iso_channels = ohci_set_iso_channels,
ed568912 3011 .queue_iso = ohci_queue_iso,
69cdb726 3012 .start_iso = ohci_start_iso,
b8295668 3013 .stop_iso = ohci_stop_iso,
ed568912
KH		 3014};
3015
ea8d006b 3016#ifdef CONFIG_PPC_PMAC
5da3dac8 3017static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3018{
ea8d006b
SR		 3019 if (machine_is(powermac)) {
3020 struct device_node *ofn = pci_device_to_OF_node(dev);
3021
3022 if (ofn) {
3023 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3024 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3025 }
3026 }
2ed0f181
SR		 3027}
3028
5da3dac8 3029static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3030{
3031 if (machine_is(powermac)) {
3032 struct device_node *ofn = pci_device_to_OF_node(dev);
3033
3034 if (ofn) {
3035 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3036 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3037 }
3038 }
3039}
3040#else
5da3dac8
SR		 3041static inline void pmac_ohci_on(struct pci_dev *dev) {}
3042static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3043#endif /* CONFIG_PPC_PMAC */
3044
53dca511
SR		 3045static int __devinit pci_probe(struct pci_dev *dev,
3046 const struct pci_device_id *ent)
2ed0f181
SR		 3047{
3048 struct fw_ohci *ohci;
aa0170ff 3049 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3050 u64 guid;
6fdb2ee2 3051 int i, err, n_ir, n_it;
2ed0f181
SR		 3052 size_t size;
3053
2d826cc5 3054 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3055 if (ohci == NULL) {
7007a076
SR		 3056 err = -ENOMEM;
3057 goto fail;
ed568912
KH		 3058 }
3059
3060 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3061
5da3dac8 3062 pmac_ohci_on(dev);
130d5496 3063
d79406dd
KH		 3064 err = pci_enable_device(dev);
3065 if (err) {
7007a076 3066 fw_error("Failed to enable OHCI hardware\n");
bd7dee63 3067 goto fail_free;
ed568912
KH		 3068 }
3069
3070 pci_set_master(dev);
3071 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3072 pci_set_drvdata(dev, ohci);
3073
3074 spin_lock_init(&ohci->lock);
02d37bed 3075 mutex_init(&ohci->phy_reg_mutex);
ed568912
KH		 3076
3077 tasklet_init(&ohci->bus_reset_tasklet,
3078 bus_reset_tasklet, (unsigned long)ohci);
3079
d79406dd
KH		 3080 err = pci_request_region(dev, 0, ohci_driver_name);
3081 if (err) {
ed568912 3082 fw_error("MMIO resource unavailable\n");
d79406dd 3083 goto fail_disable;
ed568912
KH		 3084 }
3085
3086 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3087 if (ohci->registers == NULL) {
3088 fw_error("Failed to remap registers\n");
d79406dd
KH		 3089 err = -ENXIO;
3090 goto fail_iomem;
ed568912
KH		 3091 }
3092
4a635593 3093 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3094 if ((ohci_quirks[i].vendor == dev->vendor) &&
3095 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3096 ohci_quirks[i].device == dev->device) &&
3097 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3098 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3099 ohci->quirks = ohci_quirks[i].flags;
3100 break;
3101 }
3e9cc2f3
SR		 3102 if (param_quirks)
3103 ohci->quirks = param_quirks;
b677532b 3104
7a39d8b8
CL		 3105 err = ar_context_init(&ohci->ar_request_ctx, ohci,
3106 OHCI1394_AsReqRcvContextControlSet);
3107 if (err < 0)
3108 goto fail_iounmap;
ed568912 3109
7a39d8b8
CL		 3110 err = ar_context_init(&ohci->ar_response_ctx, ohci,
3111 OHCI1394_AsRspRcvContextControlSet);
3112 if (err < 0)
3113 goto fail_arreq_ctx;
ed568912 3114
c088ab30
CL		 3115 err = context_init(&ohci->at_request_ctx, ohci,
3116 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3117 if (err < 0)
3118 goto fail_arrsp_ctx;
ed568912 3119
c088ab30
CL		 3120 err = context_init(&ohci->at_response_ctx, ohci,
3121 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3122 if (err < 0)
3123 goto fail_atreq_ctx;
ed568912 3124
ed568912 3125 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d
SR		 3126 ohci->ir_context_channels = ~0ULL;
3127 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3128 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
6fdb2ee2
SR		 3129 n_ir = hweight32(ohci->ir_context_mask);
3130 size = sizeof(struct iso_context) * n_ir;
4802f16d 3131 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3132
3133 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
4802f16d 3134 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3135 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
6fdb2ee2
SR		 3136 n_it = hweight32(ohci->it_context_mask);
3137 size = sizeof(struct iso_context) * n_it;
4802f16d 3138 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3139
3140 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3141 err = -ENOMEM;
7007a076 3142 goto fail_contexts;
ed568912
KH		 3143 }
3144
3145 /* self-id dma buffer allocation */
3146 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
3147 SELF_ID_BUF_SIZE,
3148 &ohci->self_id_bus,
3149 GFP_KERNEL);
3150 if (ohci->self_id_cpu == NULL) {
d79406dd 3151 err = -ENOMEM;
7007a076 3152 goto fail_contexts;
ed568912
KH		 3153 }
3154
ed568912
KH		 3155 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3156 max_receive = (bus_options >> 12) & 0xf;
3157 link_speed = bus_options & 0x7;
3158 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3159 reg_read(ohci, OHCI1394_GUIDLo);
3160
d79406dd 3161 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3162 if (err)
d79406dd 3163 goto fail_self_id;
ed568912 3164
6fdb2ee2
SR		 3165 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3166 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3167 "%d IR + %d IT contexts, quirks 0x%x\n",
3168 dev_name(&dev->dev), version >> 16, version & 0xff,
3169 n_ir, n_it, ohci->quirks);
e1eff7a3 3170
ed568912 3171 return 0;
d79406dd
KH		 3172
3173 fail_self_id:
3174 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3175 ohci->self_id_cpu, ohci->self_id_bus);
7007a076 3176 fail_contexts:
d79406dd 3177 kfree(ohci->ir_context_list);
7007a076
SR		 3178 kfree(ohci->it_context_list);
3179 context_release(&ohci->at_response_ctx);
c088ab30 3180 fail_atreq_ctx:
7007a076 3181 context_release(&ohci->at_request_ctx);
c088ab30 3182 fail_arrsp_ctx:
7007a076 3183 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3184 fail_arreq_ctx:
7007a076 3185 ar_context_release(&ohci->ar_request_ctx);
7a39d8b8 3186 fail_iounmap:
d79406dd
KH		 3187 pci_iounmap(dev, ohci->registers);
3188 fail_iomem:
3189 pci_release_region(dev, 0);
3190 fail_disable:
3191 pci_disable_device(dev);
bd7dee63
SR		 3192 fail_free:
3193 kfree(&ohci->card);
5da3dac8 3194 pmac_ohci_off(dev);
7007a076
SR		 3195 fail:
3196 if (err == -ENOMEM)
3197 fw_error("Out of memory\n");
d79406dd
KH		 3198
3199 return err;
ed568912
KH		 3200}
3201
3202static void pci_remove(struct pci_dev *dev)
3203{
3204 struct fw_ohci *ohci;
3205
3206 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3207 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3208 flush_writes(ohci);
ed568912
KH		 3209 fw_core_remove_card(&ohci->card);
3210
c781c06d
KH		 3211 /*
3212 * FIXME: Fail all pending packets here, now that the upper
3213 * layers can't queue any more.
3214 */
ed568912
KH		 3215
3216 software_reset(ohci);
3217 free_irq(dev->irq, ohci);
a55709ba
JF		 3218
3219 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3220 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3221 ohci->next_config_rom, ohci->next_config_rom_bus);
3222 if (ohci->config_rom)
3223 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3224 ohci->config_rom, ohci->config_rom_bus);
d79406dd
KH		 3225 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3226 ohci->self_id_cpu, ohci->self_id_bus);
a55709ba
JF		 3227 ar_context_release(&ohci->ar_request_ctx);
3228 ar_context_release(&ohci->ar_response_ctx);
3229 context_release(&ohci->at_request_ctx);
3230 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3231 kfree(ohci->it_context_list);
3232 kfree(ohci->ir_context_list);
262444ee 3233 pci_disable_msi(dev);
d79406dd
KH		 3234 pci_iounmap(dev, ohci->registers);
3235 pci_release_region(dev, 0);
3236 pci_disable_device(dev);
bd7dee63 3237 kfree(&ohci->card);
5da3dac8 3238 pmac_ohci_off(dev);
ea8d006b 3239
ed568912
KH		 3240 fw_notify("Removed fw-ohci device.\n");
3241}
3242
2aef469a 3243#ifdef CONFIG_PM
2ed0f181 3244static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3245{
2ed0f181 3246 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3247 int err;
3248
3249 software_reset(ohci);
2ed0f181 3250 free_irq(dev->irq, ohci);
262444ee 3251 pci_disable_msi(dev);
2ed0f181 3252 err = pci_save_state(dev);
2aef469a 3253 if (err) {
8a8cea27 3254 fw_error("pci_save_state failed\n");
2aef469a
KH		 3255 return err;
3256 }
2ed0f181 3257 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428
SR		 3258 if (err)
3259 fw_error("pci_set_power_state failed with %d\n", err);
5da3dac8 3260 pmac_ohci_off(dev);
ea8d006b 3261
2aef469a
KH		 3262 return 0;
3263}
3264
2ed0f181 3265static int pci_resume(struct pci_dev *dev)
2aef469a 3266{
2ed0f181 3267 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3268 int err;
3269
5da3dac8 3270 pmac_ohci_on(dev);
2ed0f181
SR		 3271 pci_set_power_state(dev, PCI_D0);
3272 pci_restore_state(dev);
3273 err = pci_enable_device(dev);
2aef469a 3274 if (err) {
8a8cea27 3275 fw_error("pci_enable_device failed\n");
2aef469a
KH		 3276 return err;
3277 }
3278
0bd243c4 3279 return ohci_enable(&ohci->card, NULL, 0);
2aef469a
KH		 3280}
3281#endif
3282
a67483d2 3283static const struct pci_device_id pci_table[] = {
ed568912
KH		 3284 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3285 { }
3286};
3287
3288MODULE_DEVICE_TABLE(pci, pci_table);
3289
3290static struct pci_driver fw_ohci_pci_driver = {
3291 .name = ohci_driver_name,
3292 .id_table = pci_table,
3293 .probe = pci_probe,
3294 .remove = pci_remove,
2aef469a
KH		 3295#ifdef CONFIG_PM
3296 .resume = pci_resume,
3297 .suspend = pci_suspend,
3298#endif
ed568912
KH		 3299};
3300
3301MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3302MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3303MODULE_LICENSE("GPL");
3304
1e4c7b0d
OH		 3305/* Provide a module alias so root-on-sbp2 initrds don't break. */
3306#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3307MODULE_ALIAS("ohci1394");
3308#endif
3309
ed568912
KH		 3310static int __init fw_ohci_init(void)
3311{
3312 return pci_register_driver(&fw_ohci_pci_driver);
3313}
3314
3315static void __exit fw_ohci_cleanup(void)
3316{
3317 pci_unregister_driver(&fw_ohci_pci_driver);
3318}
3319
3320module_init(fw_ohci_init);
3321module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
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