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firewire: ohci: Turn remote DMA support into a module parameter
[deliverable/linux.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
2d7a36e2 45#include <linux/workqueue.h>
cf3e72fd 46
e8ca9702 47#include <asm/byteorder.h>
c26f0234 48#include <asm/page.h>
ed568912 49
ea8d006b
SR		 50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
77c9a5da
SR		 54#include "core.h"
55#include "ohci.h"
ed568912 56
de97cb64
PH		 57#define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58#define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59#define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
a77754a7
KH		 61#define DESCRIPTOR_OUTPUT_MORE 0
62#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63#define DESCRIPTOR_INPUT_MORE (2 << 12)
64#define DESCRIPTOR_INPUT_LAST (3 << 12)
65#define DESCRIPTOR_STATUS (1 << 11)
66#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67#define DESCRIPTOR_PING (1 << 7)
68#define DESCRIPTOR_YY (1 << 6)
69#define DESCRIPTOR_NO_IRQ (0 << 4)
70#define DESCRIPTOR_IRQ_ERROR (1 << 4)
71#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73#define DESCRIPTOR_WAIT (3 << 0)
ed568912 74
be8dcab9
AL		 75#define DESCRIPTOR_CMD (0xf << 12)
76
ed568912
KH		 77struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84} __attribute__((aligned(16)));
85
a77754a7
KH		 86#define CONTROL_SET(regs) (regs)
87#define CONTROL_CLEAR(regs) ((regs) + 4)
88#define COMMAND_PTR(regs) ((regs) + 12)
89#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 90
7a39d8b8
CL		 91#define AR_BUFFER_SIZE (32*1024)
92#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93/* we need at least two pages for proper list management */
94#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96#define MAX_ASYNC_PAYLOAD 4096
97#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 99
32b46093
KH		 100struct ar_context {
101 struct fw_ohci *ohci;
7a39d8b8
CL		 102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
32b46093 106 void *pointer;
7a39d8b8 107 unsigned int last_buffer_index;
72e318e0 108 u32 regs;
ed568912
KH		 109 struct tasklet_struct tasklet;
110};
111
30200739
KH		 112struct context;
113
114typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
fe5ca634
DM		 117
118/*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128};
129
30200739 130struct context {
373b2edd 131 struct fw_ohci *ohci;
30200739 132 u32 regs;
fe5ca634 133 int total_allocation;
a572e688 134 u32 current_bus;
386a4153 135 bool running;
82b662dc 136 bool flushing;
373b2edd 137
fe5ca634
DM		 138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
be8dcab9 158 * The last descriptor block in the DMA program. It contains the branch
fe5ca634
DM		 159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
be8dcab9 162 int prev_z;
30200739
KH		 163
164 descriptor_callback_t callback;
165
373b2edd 166 struct tasklet_struct tasklet;
30200739 167};
30200739 168
a77754a7
KH		 169#define IT_HEADER_SY(v) ((v) << 0)
170#define IT_HEADER_TCODE(v) ((v) << 4)
171#define IT_HEADER_CHANNEL(v) ((v) << 8)
172#define IT_HEADER_TAG(v) ((v) << 14)
173#define IT_HEADER_SPEED(v) ((v) << 16)
174#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 175
176struct iso_context {
177 struct fw_iso_context base;
30200739 178 struct context context;
9b32d5f3
KH		 179 void *header;
180 size_t header_length;
d1bbd209
CL		 181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
910e76c6 184 u16 last_timestamp;
dd23736e
ML		 185 u8 sync;
186 u8 tags;
ed568912
KH		 187};
188
189#define CONFIG_ROM_SIZE 1024
190
191struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
e636fe25 195 int node_id;
ed568912 196 int generation;
e09770db 197 int request_generation; /* for timestamping incoming requests */
4a635593 198 unsigned quirks;
a1a1132b 199 unsigned int pri_req_max;
a48777e0 200 u32 bus_time;
9d60ef2b 201 bool bus_time_running;
4ffb7a6a 202 bool is_root;
c8a94ded 203 bool csr_state_setclear_abdicate;
dd23736e
ML		 204 int n_ir;
205 int n_it;
c781c06d
KH		 206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
ed568912 210 spinlock_t lock;
ed568912 211
02d37bed
SR		 212 struct mutex phy_reg_mutex;
213
ec766a79
CL		 214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
ed568912
KH		 217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
f319b6a0
KH		 219 struct context at_request_ctx;
220 struct context at_response_ctx;
ed568912 221
f117a3e3 222 u32 it_context_support;
872e330e 223 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 224 struct iso_context *it_context_list;
872e330e 225 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 226 u32 ir_context_support;
872e330e 227 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 228 struct iso_context *ir_context_list;
872e330e
SR		 229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
ecb1cf9c
SR		 231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
af53122a 238 __le32 *self_id;
ecb1cf9c 239 dma_addr_t self_id_bus;
2d7a36e2 240 struct work_struct bus_reset_work;
ecb1cf9c
SR		 241
242 u32 self_id_buffer[512];
ed568912
KH		 243};
244
db9ae8fe
SG		 245static struct workqueue_struct *selfid_workqueue;
246
95688e97 247static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 248{
249 return container_of(card, struct fw_ohci, card);
250}
251
295e3feb
KH		 252#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253#define IR_CONTEXT_BUFFER_FILL 0x80000000
254#define IR_CONTEXT_ISOCH_HEADER 0x40000000
255#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 258
259#define CONTEXT_RUN 0x8000
260#define CONTEXT_WAKE 0x1000
261#define CONTEXT_DEAD 0x0800
262#define CONTEXT_ACTIVE 0x0400
263
8b7b6afa 264#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 265#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
ed568912 268#define OHCI1394_REGISTER_SIZE 0x800
ed568912
KH		 269#define OHCI1394_PCI_HCI_Control 0x40
270#define SELF_ID_BUF_SIZE 0x800
32b46093 271#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 272#define OHCI_VERSION_1_1 0x010010
0edeefd9 273
ed568912
KH		 274static char ohci_driver_name[] = KBUILD_MODNAME;
275
0dbe15f8 276#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
9993e0fe 277#define PCI_DEVICE_ID_AGERE_FW643 0x5901
d1bb399a 278#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
262444ee 279#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b 280#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
25935ebe
SG		 281#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
be8dcab9 283#define PCI_DEVICE_ID_VIA_VT630X 0x3044
be8dcab9 284#define PCI_REV_ID_VIA_VT6306 0x46
8301b91b 285
0dbe15f8
SR		 286#define QUIRK_CYCLE_TIMER 0x1
287#define QUIRK_RESET_PACKET 0x2
288#define QUIRK_BE_HEADERS 0x4
289#define QUIRK_NO_1394A 0x8
290#define QUIRK_NO_MSI 0x10
291#define QUIRK_TI_SLLZ059 0x20
292#define QUIRK_IR_WAKE 0x40
293#define QUIRK_PHY_LCTRL_TIMEOUT 0x80
4a635593
SR		 294
295/* In case of multiple matches in ohci_quirks[], only the first one is used. */
296static const struct {
9993e0fe 297 unsigned short vendor, device, revision, flags;
4a635593 298} ohci_quirks[] = {
9993e0fe
SR		 299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER},
301
302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
303 QUIRK_BE_HEADERS},
304
305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
bd972688
PH		 306 QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI},
307
308 {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID,
309 QUIRK_PHY_LCTRL_TIMEOUT},
9993e0fe 310
d1bb399a
CL		 311 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
312 QUIRK_RESET_PACKET},
313
9993e0fe
SR		 314 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
315 QUIRK_NO_MSI},
316
317 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_CYCLE_TIMER},
319
f39aa30d
ML		 320 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
321 QUIRK_NO_MSI},
322
9993e0fe 323 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
320cfa6c 324 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
9993e0fe
SR		 325
326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
327 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
328
25935ebe
SG		 329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
331
332 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
333 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
334
9993e0fe
SR		 335 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
336 QUIRK_RESET_PACKET},
337
be8dcab9
AL		 338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
339 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
340
9993e0fe
SR		 341 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
342 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 343};
344
3e9cc2f3
SR		 345/* This overrides anything that was found in ohci_quirks[]. */
346static int param_quirks;
347module_param_named(quirks, param_quirks, int, 0644);
348MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
349 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
350 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
8a168ca7 351 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
925e7a65 352 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 353 ", disable MSI = " __stringify(QUIRK_NO_MSI)
28897fb7 354 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
be8dcab9 355 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
bd972688 356 ", phy LCtrl timeout = " __stringify(QUIRK_PHY_LCTRL_TIMEOUT)
3e9cc2f3
SR		 357 ")");
358
a007bb85 359#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 360#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 361#define OHCI_PARAM_DEBUG_IRQS 4
362#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8
SR		 363
364static int param_debug;
365module_param_named(debug, param_debug, int, 0644);
366MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 367 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 368 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
369 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
370 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 371 ", or a combination, or all = -1)");
372
8bc588e0
LR		 373static bool param_remote_dma;
374module_param_named(remote_dma, param_remote_dma, bool, 0444);
375MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
376
64d21720 377static void log_irqs(struct fw_ohci *ohci, u32 evt)
ad3c0fe8 378{
a007bb85
SR		 379 if (likely(!(param_debug &
380 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
381 return;
382
383 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
384 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 385 return;
386
de97cb64 387 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 388 evt & OHCI1394_selfIDComplete ? " selfID" : "",
389 evt & OHCI1394_RQPkt ? " AR_req" : "",
390 evt & OHCI1394_RSPkt ? " AR_resp" : "",
391 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
392 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
393 evt & OHCI1394_isochRx ? " IR" : "",
394 evt & OHCI1394_isochTx ? " IT" : "",
395 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
396 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 397 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 398 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 399 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 400 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 401 evt & OHCI1394_busReset ? " busReset" : "",
402 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
403 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
404 OHCI1394_respTxComplete | OHCI1394_isochRx |
405 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 406 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
407 OHCI1394_cycleInconsistent |
161b96e7 408 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 409 ? " ?" : "");
410}
411
412static const char *speed[] = {
413 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
414};
415static const char *power[] = {
416 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
417 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
418};
419static const char port[] = { '.', '-', 'p', 'c', };
420
421static char _p(u32 *s, int shift)
422{
423 return port[*s >> shift & 3];
424}
425
64d21720 426static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
ad3c0fe8 427{
64d21720
SR		 428 u32 *s;
429
ad3c0fe8
SR		 430 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
431 return;
432
de97cb64
PH		 433 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
434 self_id_count, generation, ohci->node_id);
ad3c0fe8 435
64d21720 436 for (s = ohci->self_id_buffer; self_id_count--; ++s)
ad3c0fe8 437 if ((*s & 1 << 23) == 0)
de97cb64
PH		 438 ohci_notice(ohci,
439 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
161b96e7
SR		 440 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
441 speed[*s >> 14 & 3], *s >> 16 & 63,
442 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
443 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 444 else
de97cb64 445 ohci_notice(ohci,
64d21720 446 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
161b96e7
SR		 447 *s, *s >> 24 & 63,
448 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
449 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 450}
451
452static const char *evts[] = {
453 [0x00] = "evt_no_status", [0x01] = "-reserved-",
454 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
455 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
456 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
457 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
458 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
459 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
460 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
461 [0x10] = "-reserved-", [0x11] = "ack_complete",
462 [0x12] = "ack_pending ", [0x13] = "-reserved-",
463 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
464 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
465 [0x18] = "-reserved-", [0x19] = "-reserved-",
466 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
467 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
468 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
469 [0x20] = "pending/cancelled",
470};
471static const char *tcodes[] = {
472 [0x0] = "QW req", [0x1] = "BW req",
473 [0x2] = "W resp", [0x3] = "-reserved-",
474 [0x4] = "QR req", [0x5] = "BR req",
475 [0x6] = "QR resp", [0x7] = "BR resp",
476 [0x8] = "cycle start", [0x9] = "Lk req",
477 [0xa] = "async stream packet", [0xb] = "Lk resp",
478 [0xc] = "-reserved-", [0xd] = "-reserved-",
479 [0xe] = "link internal", [0xf] = "-reserved-",
480};
ad3c0fe8 481
64d21720
SR		 482static void log_ar_at_event(struct fw_ohci *ohci,
483 char dir, int speed, u32 *header, int evt)
ad3c0fe8
SR		 484{
485 int tcode = header[0] >> 4 & 0xf;
486 char specific[12];
487
488 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
489 return;
490
491 if (unlikely(evt >= ARRAY_SIZE(evts)))
492 evt = 0x1f;
493
08ddb2f4 494 if (evt == OHCI1394_evt_bus_reset) {
de97cb64
PH		 495 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
496 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 497 return;
498 }
499
ad3c0fe8
SR		 500 switch (tcode) {
501 case 0x0: case 0x6: case 0x8:
502 snprintf(specific, sizeof(specific), " = %08x",
503 be32_to_cpu((__force __be32)header[3]));
504 break;
505 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
506 snprintf(specific, sizeof(specific), " %x,%x",
507 header[3] >> 16, header[3] & 0xffff);
508 break;
509 default:
510 specific[0] = '\0';
511 }
512
513 switch (tcode) {
5b06db16 514 case 0xa:
de97cb64
PH		 515 ohci_notice(ohci, "A%c %s, %s\n",
516 dir, evts[evt], tcodes[tcode]);
ad3c0fe8 517 break;
5b06db16 518 case 0xe:
de97cb64
PH		 519 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
520 dir, evts[evt], header[1], header[2]);
5b06db16 521 break;
ad3c0fe8 522 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
de97cb64
PH		 523 ohci_notice(ohci,
524 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
525 dir, speed, header[0] >> 10 & 0x3f,
526 header[1] >> 16, header[0] >> 16, evts[evt],
527 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 528 break;
529 default:
de97cb64
PH		 530 ohci_notice(ohci,
531 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
532 dir, speed, header[0] >> 10 & 0x3f,
533 header[1] >> 16, header[0] >> 16, evts[evt],
534 tcodes[tcode], specific);
ad3c0fe8
SR		 535 }
536}
537
95688e97 538static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 539{
540 writel(data, ohci->registers + offset);
541}
542
95688e97 543static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 544{
545 return readl(ohci->registers + offset);
546}
547
95688e97 548static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 549{
550 /* Do a dummy read to flush writes. */
551 reg_read(ohci, OHCI1394_Version);
552}
553
b14c369d
SR		 554/*
555 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
556 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
557 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
558 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
559 */
35d999b1 560static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 561{
4a96b4fc 562 u32 val;
35d999b1 563 int i;
ed568912
KH		 564
565 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 566 for (i = 0; i < 3 + 100; i++) {
35d999b1 567 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 568 if (!~val)
569 return -ENODEV; /* Card was ejected. */
570
35d999b1
SR		 571 if (val & OHCI1394_PhyControl_ReadDone)
572 return OHCI1394_PhyControl_ReadData(val);
573
153e3979
CL		 574 /*
575 * Try a few times without waiting. Sleeping is necessary
576 * only when the link/PHY interface is busy.
577 */
578 if (i >= 3)
579 msleep(1);
ed568912 580 }
6fe9efb9
PH		 581 ohci_err(ohci, "failed to read phy reg %d\n", addr);
582 dump_stack();
ed568912 583
35d999b1
SR		 584 return -EBUSY;
585}
4a96b4fc 586
35d999b1
SR		 587static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
588{
589 int i;
ed568912 590
ed568912 591 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 592 OHCI1394_PhyControl_Write(addr, val));
153e3979 593 for (i = 0; i < 3 + 100; i++) {
35d999b1 594 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 595 if (!~val)
596 return -ENODEV; /* Card was ejected. */
597
35d999b1
SR		 598 if (!(val & OHCI1394_PhyControl_WritePending))
599 return 0;
ed568912 600
153e3979
CL		 601 if (i >= 3)
602 msleep(1);
35d999b1 603 }
6fe9efb9
PH		 604 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
605 dump_stack();
35d999b1
SR		 606
607 return -EBUSY;
4a96b4fc
CL		 608}
609
02d37bed
SR		 610static int update_phy_reg(struct fw_ohci *ohci, int addr,
611 int clear_bits, int set_bits)
4a96b4fc 612{
02d37bed 613 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 614 if (ret < 0)
615 return ret;
4a96b4fc 616
e7014dad
CL		 617 /*
618 * The interrupt status bits are cleared by writing a one bit.
619 * Avoid clearing them unless explicitly requested in set_bits.
620 */
621 if (addr == 5)
622 clear_bits |= PHY_INT_STATUS_BITS;
623
35d999b1 624 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 625}
626
35d999b1 627static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 628{
35d999b1 629 int ret;
925e7a65 630
02d37bed 631 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 632 if (ret < 0)
633 return ret;
925e7a65 634
35d999b1 635 return read_phy_reg(ohci, addr);
ed568912
KH		 636}
637
02d37bed
SR		 638static int ohci_read_phy_reg(struct fw_card *card, int addr)
639{
640 struct fw_ohci *ohci = fw_ohci(card);
641 int ret;
642
643 mutex_lock(&ohci->phy_reg_mutex);
644 ret = read_phy_reg(ohci, addr);
645 mutex_unlock(&ohci->phy_reg_mutex);
646
647 return ret;
648}
649
650static int ohci_update_phy_reg(struct fw_card *card, int addr,
651 int clear_bits, int set_bits)
652{
653 struct fw_ohci *ohci = fw_ohci(card);
654 int ret;
655
656 mutex_lock(&ohci->phy_reg_mutex);
657 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
658 mutex_unlock(&ohci->phy_reg_mutex);
659
660 return ret;
ed568912
KH		 661}
662
7a39d8b8
CL		 663static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
664{
665 return page_private(ctx->pages[i]);
666}
667
668static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 669{
7a39d8b8 670 struct descriptor *d;
32b46093 671
7a39d8b8
CL		 672 d = &ctx->descriptors[index];
673 d->branch_address &= cpu_to_le32(~0xf);
674 d->res_count = cpu_to_le16(PAGE_SIZE);
675 d->transfer_status = 0;
32b46093 676
071595eb 677 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 678 d = &ctx->descriptors[ctx->last_buffer_index];
679 d->branch_address |= cpu_to_le32(1);
680
681 ctx->last_buffer_index = index;
32b46093 682
a77754a7 683 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
837596a6
CL		 684}
685
7a39d8b8 686static void ar_context_release(struct ar_context *ctx)
837596a6 687{
7a39d8b8 688 unsigned int i;
837596a6 689
7a39d8b8
CL		 690 if (ctx->buffer)
691 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 692
7a39d8b8
CL		 693 for (i = 0; i < AR_BUFFERS; i++)
694 if (ctx->pages[i]) {
695 dma_unmap_page(ctx->ohci->card.device,
696 ar_buffer_bus(ctx, i),
697 PAGE_SIZE, DMA_FROM_DEVICE);
698 __free_page(ctx->pages[i]);
699 }
ed568912
KH		 700}
701
7a39d8b8 702static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 703{
64d21720 704 struct fw_ohci *ohci = ctx->ohci;
a55709ba 705
64d21720
SR		 706 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
707 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
708 flush_writes(ohci);
a55709ba 709
de97cb64 710 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
a55709ba 711 }
7a39d8b8
CL		 712 /* FIXME: restart? */
713}
714
715static inline unsigned int ar_next_buffer_index(unsigned int index)
716{
717 return (index + 1) % AR_BUFFERS;
718}
719
720static inline unsigned int ar_prev_buffer_index(unsigned int index)
721{
722 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
723}
724
725static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
726{
727 return ar_next_buffer_index(ctx->last_buffer_index);
728}
729
730/*
731 * We search for the buffer that contains the last AR packet DMA data written
732 * by the controller.
733 */
734static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
735 unsigned int *buffer_offset)
736{
737 unsigned int i, next_i, last = ctx->last_buffer_index;
738 __le16 res_count, next_res_count;
739
740 i = ar_first_buffer_index(ctx);
741 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
742
743 /* A buffer that is not yet completely filled must be the last one. */
744 while (i != last && res_count == 0) {
745
746 /* Peek at the next descriptor. */
747 next_i = ar_next_buffer_index(i);
748 rmb(); /* read descriptors in order */
749 next_res_count = ACCESS_ONCE(
750 ctx->descriptors[next_i].res_count);
751 /*
752 * If the next descriptor is still empty, we must stop at this
753 * descriptor.
754 */
755 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
756 /*
757 * The exception is when the DMA data for one packet is
758 * split over three buffers; in this case, the middle
759 * buffer's descriptor might be never updated by the
760 * controller and look still empty, and we have to peek
761 * at the third one.
762 */
763 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
764 next_i = ar_next_buffer_index(next_i);
765 rmb();
766 next_res_count = ACCESS_ONCE(
767 ctx->descriptors[next_i].res_count);
768 if (next_res_count != cpu_to_le16(PAGE_SIZE))
769 goto next_buffer_is_active;
770 }
771
772 break;
773 }
774
775next_buffer_is_active:
776 i = next_i;
777 res_count = next_res_count;
778 }
779
780 rmb(); /* read res_count before the DMA data */
781
782 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
783 if (*buffer_offset > PAGE_SIZE) {
784 *buffer_offset = 0;
785 ar_context_abort(ctx, "corrupted descriptor");
786 }
787
788 return i;
789}
790
791static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
792 unsigned int end_buffer_index,
793 unsigned int end_buffer_offset)
794{
795 unsigned int i;
796
797 i = ar_first_buffer_index(ctx);
798 while (i != end_buffer_index) {
799 dma_sync_single_for_cpu(ctx->ohci->card.device,
800 ar_buffer_bus(ctx, i),
801 PAGE_SIZE, DMA_FROM_DEVICE);
802 i = ar_next_buffer_index(i);
803 }
804 if (end_buffer_offset > 0)
805 dma_sync_single_for_cpu(ctx->ohci->card.device,
806 ar_buffer_bus(ctx, i),
807 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 808}
809
11bf20ad
SR		 810#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
811#define cond_le32_to_cpu(v) \
4a635593 812 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 813#else
814#define cond_le32_to_cpu(v) le32_to_cpu(v)
815#endif
816
32b46093 817static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 818{
ed568912 819 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 820 struct fw_packet p;
821 u32 status, length, tcode;
43286568 822 int evt;
2639a6fb 823
11bf20ad
SR		 824 p.header[0] = cond_le32_to_cpu(buffer[0]);
825 p.header[1] = cond_le32_to_cpu(buffer[1]);
826 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 827
828 tcode = (p.header[0] >> 4) & 0x0f;
829 switch (tcode) {
830 case TCODE_WRITE_QUADLET_REQUEST:
831 case TCODE_READ_QUADLET_RESPONSE:
32b46093 832 p.header[3] = (__force __u32) buffer[3];
2639a6fb 833 p.header_length = 16;
32b46093 834 p.payload_length = 0;
2639a6fb
KH		 835 break;
836
2639a6fb 837 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 838 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 839 p.header_length = 16;
840 p.payload_length = 0;
841 break;
842
843 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 844 case TCODE_READ_BLOCK_RESPONSE:
845 case TCODE_LOCK_REQUEST:
846 case TCODE_LOCK_RESPONSE:
11bf20ad 847 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 848 p.header_length = 16;
32b46093 849 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 850 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
851 ar_context_abort(ctx, "invalid packet length");
852 return NULL;
853 }
2639a6fb
KH		 854 break;
855
856 case TCODE_WRITE_RESPONSE:
857 case TCODE_READ_QUADLET_REQUEST:
32b46093 858 case OHCI_TCODE_PHY_PACKET:
2639a6fb 859 p.header_length = 12;
32b46093 860 p.payload_length = 0;
2639a6fb 861 break;
ccff9629
SR		 862
863 default:
7a39d8b8
CL		 864 ar_context_abort(ctx, "invalid tcode");
865 return NULL;
2639a6fb 866 }
ed568912 867
32b46093
KH		 868 p.payload = (void *) buffer + p.header_length;
869
870 /* FIXME: What to do about evt_* errors? */
871 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 872 status = cond_le32_to_cpu(buffer[length]);
43286568 873 evt = (status >> 16) & 0x1f;
32b46093 874
43286568 875 p.ack = evt - 16;
32b46093
KH		 876 p.speed = (status >> 21) & 0x7;
877 p.timestamp = status & 0xffff;
878 p.generation = ohci->request_generation;
ed568912 879
64d21720 880 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
ad3c0fe8 881
c781c06d 882 /*
a4dc090b
SR		 883 * Several controllers, notably from NEC and VIA, forget to
884 * write ack_complete status at PHY packet reception.
885 */
886 if (evt == OHCI1394_evt_no_status &&
887 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
888 p.ack = ACK_COMPLETE;
889
890 /*
891 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 892 * the new generation number when a bus reset happens (see
893 * section 8.4.2.3). This helps us determine when a request
894 * was received and make sure we send the response in the same
895 * generation. We only need this for requests; for responses
896 * we use the unique tlabel for finding the matching
c781c06d 897 * request.
d34316a4
SR		 898 *
899 * Alas some chips sometimes emit bus reset packets with a
900 * wrong generation. We set the correct generation for these
2d7a36e2 901 * at a slightly incorrect time (in bus_reset_work).
c781c06d 902 */
d34316a4 903 if (evt == OHCI1394_evt_bus_reset) {
4a635593 904 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 905 ohci->request_generation = (p.header[2] >> 16) & 0xff;
906 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 907 fw_core_handle_request(&ohci->card, &p);
d34316a4 908 } else {
2639a6fb 909 fw_core_handle_response(&ohci->card, &p);
d34316a4 910 }
ed568912 911
32b46093
KH		 912 return buffer + length + 1;
913}
ed568912 914
7a39d8b8
CL		 915static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
916{
917 void *next;
918
919 while (p < end) {
920 next = handle_ar_packet(ctx, p);
921 if (!next)
922 return p;
923 p = next;
924 }
925
926 return p;
927}
928
929static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
930{
931 unsigned int i;
932
933 i = ar_first_buffer_index(ctx);
934 while (i != end_buffer) {
935 dma_sync_single_for_device(ctx->ohci->card.device,
936 ar_buffer_bus(ctx, i),
937 PAGE_SIZE, DMA_FROM_DEVICE);
938 ar_context_link_page(ctx, i);
939 i = ar_next_buffer_index(i);
940 }
941}
942
32b46093
KH		 943static void ar_context_tasklet(unsigned long data)
944{
945 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 946 unsigned int end_buffer_index, end_buffer_offset;
947 void *p, *end;
32b46093 948
7a39d8b8
CL		 949 p = ctx->pointer;
950 if (!p)
951 return;
32b46093 952
7a39d8b8
CL		 953 end_buffer_index = ar_search_last_active_buffer(ctx,
954 &end_buffer_offset);
955 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
956 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 957
7a39d8b8 958 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 959 /*
7a39d8b8
CL		 960 * The filled part of the overall buffer wraps around; handle
961 * all packets up to the buffer end here. If the last packet
962 * wraps around, its tail will be visible after the buffer end
963 * because the buffer start pages are mapped there again.
c781c06d 964 */
7a39d8b8
CL		 965 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
966 p = handle_ar_packets(ctx, p, buffer_end);
967 if (p < buffer_end)
968 goto error;
969 /* adjust p to point back into the actual buffer */
970 p -= AR_BUFFERS * PAGE_SIZE;
971 }
32b46093 972
7a39d8b8
CL		 973 p = handle_ar_packets(ctx, p, end);
974 if (p != end) {
975 if (p > end)
976 ar_context_abort(ctx, "inconsistent descriptor");
977 goto error;
978 }
32b46093 979
7a39d8b8
CL		 980 ctx->pointer = p;
981 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 982
7a39d8b8 983 return;
a1f805e5 984
7a39d8b8
CL		 985error:
986 ctx->pointer = NULL;
ed568912
KH		 987}
988
ec766a79
CL		 989static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
990 unsigned int descriptors_offset, u32 regs)
ed568912 991{
7a39d8b8
CL		 992 unsigned int i;
993 dma_addr_t dma_addr;
994 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
995 struct descriptor *d;
ed568912 996
72e318e0
KH		 997 ctx->regs = regs;
998 ctx->ohci = ohci;
ed568912
KH		 999 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
1000
7a39d8b8
CL		 1001 for (i = 0; i < AR_BUFFERS; i++) {
1002 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
1003 if (!ctx->pages[i])
1004 goto out_of_memory;
1005 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1006 0, PAGE_SIZE, DMA_FROM_DEVICE);
1007 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1008 __free_page(ctx->pages[i]);
1009 ctx->pages[i] = NULL;
1010 goto out_of_memory;
1011 }
1012 set_page_private(ctx->pages[i], dma_addr);
1013 }
1014
1015 for (i = 0; i < AR_BUFFERS; i++)
1016 pages[i] = ctx->pages[i];
1017 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1018 pages[AR_BUFFERS + i] = ctx->pages[i];
1019 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
14271304 1020 -1, PAGE_KERNEL);
7a39d8b8
CL		 1021 if (!ctx->buffer)
1022 goto out_of_memory;
1023
ec766a79
CL		 1024 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1025 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 1026
1027 for (i = 0; i < AR_BUFFERS; i++) {
1028 d = &ctx->descriptors[i];
1029 d->req_count = cpu_to_le16(PAGE_SIZE);
1030 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1031 DESCRIPTOR_STATUS |
1032 DESCRIPTOR_BRANCH_ALWAYS);
1033 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1034 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1035 ar_next_buffer_index(i) * sizeof(struct descriptor));
1036 }
32b46093 1037
2aef469a 1038 return 0;
7a39d8b8
CL		 1039
1040out_of_memory:
1041 ar_context_release(ctx);
1042
1043 return -ENOMEM;
2aef469a
KH		 1044}
1045
1046static void ar_context_run(struct ar_context *ctx)
1047{
7a39d8b8
CL		 1048 unsigned int i;
1049
1050 for (i = 0; i < AR_BUFFERS; i++)
1051 ar_context_link_page(ctx, i);
2aef469a 1052
7a39d8b8 1053 ctx->pointer = ctx->buffer;
2aef469a 1054
7a39d8b8 1055 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1056 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
ed568912 1057}
373b2edd 1058
53dca511 1059static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1060{
0ff8fbc6 1061 __le16 branch;
a186b4a6 1062
0ff8fbc6 1063 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1064
1065 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1066 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1067 return d;
1068 else
1069 return d + z - 1;
1070}
1071
30200739
KH		 1072static void context_tasklet(unsigned long data)
1073{
1074 struct context *ctx = (struct context *) data;
30200739
KH		 1075 struct descriptor *d, *last;
1076 u32 address;
1077 int z;
fe5ca634 1078 struct descriptor_buffer *desc;
30200739 1079
fe5ca634
DM		 1080 desc = list_entry(ctx->buffer_list.next,
1081 struct descriptor_buffer, list);
1082 last = ctx->last;
30200739 1083 while (last->branch_address != 0) {
fe5ca634 1084 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1085 address = le32_to_cpu(last->branch_address);
1086 z = address & 0xf;
fe5ca634 1087 address &= ~0xf;
a572e688 1088 ctx->current_bus = address;
fe5ca634
DM		 1089
1090 /* If the branch address points to a buffer outside of the
1091 * current buffer, advance to the next buffer. */
1092 if (address < desc->buffer_bus ||
1093 address >= desc->buffer_bus + desc->used)
1094 desc = list_entry(desc->list.next,
1095 struct descriptor_buffer, list);
1096 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1097 last = find_branch_descriptor(d, z);
30200739
KH		 1098
1099 if (!ctx->callback(ctx, d, last))
1100 break;
1101
fe5ca634
DM		 1102 if (old_desc != desc) {
1103 /* If we've advanced to the next buffer, move the
1104 * previous buffer to the free list. */
1105 unsigned long flags;
1106 old_desc->used = 0;
1107 spin_lock_irqsave(&ctx->ohci->lock, flags);
1108 list_move_tail(&old_desc->list, &ctx->buffer_list);
1109 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1110 }
1111 ctx->last = last;
30200739
KH		 1112 }
1113}
1114
fe5ca634
DM		 1115/*
1116 * Allocate a new buffer and add it to the list of free buffers for this
1117 * context. Must be called with ohci->lock held.
1118 */
53dca511 1119static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1120{
1121 struct descriptor_buffer *desc;
f5101d58 1122 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1123 int offset;
1124
1125 /*
1126 * 16MB of descriptors should be far more than enough for any DMA
1127 * program. This will catch run-away userspace or DoS attacks.
1128 */
1129 if (ctx->total_allocation >= 16*1024*1024)
1130 return -ENOMEM;
1131
1132 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1133 &bus_addr, GFP_ATOMIC);
1134 if (!desc)
1135 return -ENOMEM;
1136
1137 offset = (void *)&desc->buffer - (void *)desc;
1138 desc->buffer_size = PAGE_SIZE - offset;
1139 desc->buffer_bus = bus_addr + offset;
1140 desc->used = 0;
1141
1142 list_add_tail(&desc->list, &ctx->buffer_list);
1143 ctx->total_allocation += PAGE_SIZE;
1144
1145 return 0;
1146}
1147
53dca511
SR		 1148static int context_init(struct context *ctx, struct fw_ohci *ohci,
1149 u32 regs, descriptor_callback_t callback)
30200739
KH		 1150{
1151 ctx->ohci = ohci;
1152 ctx->regs = regs;
fe5ca634
DM		 1153 ctx->total_allocation = 0;
1154
1155 INIT_LIST_HEAD(&ctx->buffer_list);
1156 if (context_add_buffer(ctx) < 0)
30200739
KH		 1157 return -ENOMEM;
1158
fe5ca634
DM		 1159 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1160 struct descriptor_buffer, list);
1161
30200739
KH		 1162 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1163 ctx->callback = callback;
1164
c781c06d
KH		 1165 /*
1166 * We put a dummy descriptor in the buffer that has a NULL
30200739 1167 * branch address and looks like it's been sent. That way we
fe5ca634 1168 * have a descriptor to append DMA programs to.
c781c06d 1169 */
fe5ca634
DM		 1170 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1171 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1172 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1173 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1174 ctx->last = ctx->buffer_tail->buffer;
1175 ctx->prev = ctx->buffer_tail->buffer;
be8dcab9 1176 ctx->prev_z = 1;
30200739
KH		 1177
1178 return 0;
1179}
1180
53dca511 1181static void context_release(struct context *ctx)
30200739
KH		 1182{
1183 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1184 struct descriptor_buffer *desc, *tmp;
30200739 1185
fe5ca634
DM		 1186 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1187 dma_free_coherent(card->device, PAGE_SIZE, desc,
1188 desc->buffer_bus -
1189 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1190}
1191
fe5ca634 1192/* Must be called with ohci->lock held */
53dca511
SR		 1193static struct descriptor *context_get_descriptors(struct context *ctx,
1194 int z, dma_addr_t *d_bus)
30200739 1195{
fe5ca634
DM		 1196 struct descriptor *d = NULL;
1197 struct descriptor_buffer *desc = ctx->buffer_tail;
1198
1199 if (z * sizeof(*d) > desc->buffer_size)
1200 return NULL;
1201
1202 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1203 /* No room for the descriptor in this buffer, so advance to the
1204 * next one. */
30200739 1205
fe5ca634
DM		 1206 if (desc->list.next == &ctx->buffer_list) {
1207 /* If there is no free buffer next in the list,
1208 * allocate one. */
1209 if (context_add_buffer(ctx) < 0)
1210 return NULL;
1211 }
1212 desc = list_entry(desc->list.next,
1213 struct descriptor_buffer, list);
1214 ctx->buffer_tail = desc;
1215 }
30200739 1216
fe5ca634 1217 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1218 memset(d, 0, z * sizeof(*d));
fe5ca634 1219 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1220
1221 return d;
1222}
1223
295e3feb 1224static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1225{
1226 struct fw_ohci *ohci = ctx->ohci;
1227
a77754a7 1228 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1229 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1230 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1231 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1232 ctx->running = true;
30200739
KH		 1233 flush_writes(ohci);
1234}
1235
1236static void context_append(struct context *ctx,
1237 struct descriptor *d, int z, int extra)
1238{
1239 dma_addr_t d_bus;
fe5ca634 1240 struct descriptor_buffer *desc = ctx->buffer_tail;
be8dcab9 1241 struct descriptor *d_branch;
30200739 1242
fe5ca634 1243 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1244
fe5ca634 1245 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1246
1247 wmb(); /* finish init of new descriptors before branch_address update */
be8dcab9
AL		 1248
1249 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1250 d_branch->branch_address = cpu_to_le32(d_bus | z);
1251
1252 /*
1253 * VT6306 incorrectly checks only the single descriptor at the
1254 * CommandPtr when the wake bit is written, so if it's a
1255 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1256 * the branch address in the first descriptor.
1257 *
1258 * Not doing this for transmit contexts since not sure how it interacts
1259 * with skip addresses.
1260 */
1261 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1262 d_branch != ctx->prev &&
1263 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1264 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1265 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1266 }
1267
1268 ctx->prev = d;
1269 ctx->prev_z = z;
30200739
KH		 1270}
1271
1272static void context_stop(struct context *ctx)
1273{
64d21720 1274 struct fw_ohci *ohci = ctx->ohci;
30200739 1275 u32 reg;
b8295668 1276 int i;
30200739 1277
64d21720 1278 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1279 ctx->running = false;
30200739 1280
9ef28ccd 1281 for (i = 0; i < 1000; i++) {
64d21720 1282 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
b8295668 1283 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1284 return;
b8295668 1285
9ef28ccd
SR		 1286 if (i)
1287 udelay(10);
b8295668 1288 }
de97cb64 1289 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
30200739 1290}
ed568912 1291
f319b6a0 1292struct driver_data {
da28947e 1293 u8 inline_data[8];
f319b6a0
KH		 1294 struct fw_packet *packet;
1295};
ed568912 1296
c781c06d
KH		 1297/*
1298 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1299 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1300 * generation handling and locking around packet queue manipulation.
1301 */
53dca511
SR		 1302static int at_context_queue_packet(struct context *ctx,
1303 struct fw_packet *packet)
ed568912 1304{
ed568912 1305 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1306 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1307 struct driver_data *driver_data;
1308 struct descriptor *d, *last;
1309 __le32 *header;
ed568912
KH		 1310 int z, tcode;
1311
f319b6a0
KH		 1312 d = context_get_descriptors(ctx, 4, &d_bus);
1313 if (d == NULL) {
1314 packet->ack = RCODE_SEND_ERROR;
1315 return -1;
ed568912
KH		 1316 }
1317
a77754a7 1318 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1319 d[0].res_count = cpu_to_le16(packet->timestamp);
1320
c781c06d 1321 /*
b3834be5 1322 * The DMA format for asynchronous link packets is different
ed568912 1323 * from the IEEE1394 layout, so shift the fields around
5b06db16 1324 * accordingly.
c781c06d 1325 */
f319b6a0 1326
5b06db16 1327 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1328 header = (__le32 *) &d[1];
5b06db16
CL		 1329 switch (tcode) {
1330 case TCODE_WRITE_QUADLET_REQUEST:
1331 case TCODE_WRITE_BLOCK_REQUEST:
1332 case TCODE_WRITE_RESPONSE:
1333 case TCODE_READ_QUADLET_REQUEST:
1334 case TCODE_READ_BLOCK_REQUEST:
1335 case TCODE_READ_QUADLET_RESPONSE:
1336 case TCODE_READ_BLOCK_RESPONSE:
1337 case TCODE_LOCK_REQUEST:
1338 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1339 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1340 (packet->speed << 16));
1341 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1342 (packet->header[0] & 0xffff0000));
1343 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1344
ed568912 1345 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1346 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1347 else
f319b6a0
KH		 1348 header[3] = (__force __le32) packet->header[3];
1349
1350 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1351 break;
1352
5b06db16 1353 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1354 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1355 (packet->speed << 16));
5b06db16
CL		 1356 header[1] = cpu_to_le32(packet->header[1]);
1357 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1358 d[0].req_count = cpu_to_le16(12);
cc550216 1359
5b06db16 1360 if (is_ping_packet(&packet->header[1]))
cc550216 1361 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1362 break;
1363
5b06db16 1364 case TCODE_STREAM_DATA:
f8c2287c
JF		 1365 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1366 (packet->speed << 16));
1367 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1368 d[0].req_count = cpu_to_le16(8);
1369 break;
1370
1371 default:
1372 /* BUG(); */
1373 packet->ack = RCODE_SEND_ERROR;
1374 return -1;
ed568912
KH		 1375 }
1376
da28947e 1377 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1378 driver_data = (struct driver_data *) &d[3];
1379 driver_data->packet = packet;
20d11673 1380 packet->driver_data = driver_data;
a186b4a6 1381
f319b6a0 1382 if (packet->payload_length > 0) {
da28947e
CL		 1383 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1384 payload_bus = dma_map_single(ohci->card.device,
1385 packet->payload,
1386 packet->payload_length,
1387 DMA_TO_DEVICE);
1388 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1389 packet->ack = RCODE_SEND_ERROR;
1390 return -1;
1391 }
1392 packet->payload_bus = payload_bus;
1393 packet->payload_mapped = true;
1394 } else {
1395 memcpy(driver_data->inline_data, packet->payload,
1396 packet->payload_length);
1397 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1398 }
1399
1400 d[2].req_count = cpu_to_le16(packet->payload_length);
1401 d[2].data_address = cpu_to_le32(payload_bus);
1402 last = &d[2];
1403 z = 3;
ed568912 1404 } else {
f319b6a0
KH		 1405 last = &d[0];
1406 z = 2;
ed568912 1407 }
ed568912 1408
a77754a7
KH		 1409 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1410 DESCRIPTOR_IRQ_ALWAYS |
1411 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1412
b6258fc1
SR		 1413 /* FIXME: Document how the locking works. */
1414 if (ohci->generation != packet->generation) {
19593ffd 1415 if (packet->payload_mapped)
ab88ca48
SR		 1416 dma_unmap_single(ohci->card.device, payload_bus,
1417 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1418 packet->ack = RCODE_GENERATION;
1419 return -1;
1420 }
1421
1422 context_append(ctx, d, z, 4 - z);
ed568912 1423
dd6254e5 1424 if (ctx->running)
13882a82 1425 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
dd6254e5 1426 else
f319b6a0
KH		 1427 context_run(ctx, 0);
1428
1429 return 0;
ed568912
KH		 1430}
1431
82b662dc
CL		 1432static void at_context_flush(struct context *ctx)
1433{
1434 tasklet_disable(&ctx->tasklet);
1435
1436 ctx->flushing = true;
1437 context_tasklet((unsigned long)ctx);
1438 ctx->flushing = false;
1439
1440 tasklet_enable(&ctx->tasklet);
1441}
1442
f319b6a0
KH		 1443static int handle_at_packet(struct context *context,
1444 struct descriptor *d,
1445 struct descriptor *last)
ed568912 1446{
f319b6a0 1447 struct driver_data *driver_data;
ed568912 1448 struct fw_packet *packet;
f319b6a0 1449 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1450 int evt;
1451
82b662dc 1452 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1453 /* This descriptor isn't done yet, stop iteration. */
1454 return 0;
ed568912 1455
f319b6a0
KH		 1456 driver_data = (struct driver_data *) &d[3];
1457 packet = driver_data->packet;
1458 if (packet == NULL)
1459 /* This packet was cancelled, just continue. */
1460 return 1;
730c32f5 1461
19593ffd 1462 if (packet->payload_mapped)
1d1dc5e8 1463 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1464 packet->payload_length, DMA_TO_DEVICE);
ed568912 1465
f319b6a0
KH		 1466 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1467 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1468
64d21720 1469 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
ad3c0fe8 1470
f319b6a0
KH		 1471 switch (evt) {
1472 case OHCI1394_evt_timeout:
1473 /* Async response transmit timed out. */
1474 packet->ack = RCODE_CANCELLED;
1475 break;
ed568912 1476
f319b6a0 1477 case OHCI1394_evt_flushed:
c781c06d
KH		 1478 /*
1479 * The packet was flushed should give same error as
1480 * when we try to use a stale generation count.
1481 */
f319b6a0
KH		 1482 packet->ack = RCODE_GENERATION;
1483 break;
ed568912 1484
f319b6a0 1485 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1486 if (context->flushing)
1487 packet->ack = RCODE_GENERATION;
1488 else {
1489 /*
1490 * Using a valid (current) generation count, but the
1491 * node is not on the bus or not sending acks.
1492 */
1493 packet->ack = RCODE_NO_ACK;
1494 }
f319b6a0 1495 break;
ed568912 1496
f319b6a0
KH		 1497 case ACK_COMPLETE + 0x10:
1498 case ACK_PENDING + 0x10:
1499 case ACK_BUSY_X + 0x10:
1500 case ACK_BUSY_A + 0x10:
1501 case ACK_BUSY_B + 0x10:
1502 case ACK_DATA_ERROR + 0x10:
1503 case ACK_TYPE_ERROR + 0x10:
1504 packet->ack = evt - 0x10;
1505 break;
ed568912 1506
82b662dc
CL		 1507 case OHCI1394_evt_no_status:
1508 if (context->flushing) {
1509 packet->ack = RCODE_GENERATION;
1510 break;
1511 }
1512 /* fall through */
1513
f319b6a0
KH		 1514 default:
1515 packet->ack = RCODE_SEND_ERROR;
1516 break;
1517 }
ed568912 1518
f319b6a0 1519 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1520
f319b6a0 1521 return 1;
ed568912
KH		 1522}
1523
a77754a7
KH		 1524#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1525#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1526#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1527#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1528#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1529
53dca511
SR		 1530static void handle_local_rom(struct fw_ohci *ohci,
1531 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1532{
1533 struct fw_packet response;
1534 int tcode, length, i;
1535
a77754a7 1536 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1537 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1538 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1539 else
1540 length = 4;
1541
1542 i = csr - CSR_CONFIG_ROM;
1543 if (i + length > CONFIG_ROM_SIZE) {
1544 fw_fill_response(&response, packet->header,
1545 RCODE_ADDRESS_ERROR, NULL, 0);
1546 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1547 fw_fill_response(&response, packet->header,
1548 RCODE_TYPE_ERROR, NULL, 0);
1549 } else {
1550 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1551 (void *) ohci->config_rom + i, length);
1552 }
1553
1554 fw_core_handle_response(&ohci->card, &response);
1555}
1556
53dca511
SR		 1557static void handle_local_lock(struct fw_ohci *ohci,
1558 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1559{
1560 struct fw_packet response;
e1393667 1561 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1562 __be32 *payload, lock_old;
1563 u32 lock_arg, lock_data;
1564
a77754a7
KH		 1565 tcode = HEADER_GET_TCODE(packet->header[0]);
1566 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1567 payload = packet->payload;
a77754a7 1568 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1569
1570 if (tcode == TCODE_LOCK_REQUEST &&
1571 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1572 lock_arg = be32_to_cpu(payload[0]);
1573 lock_data = be32_to_cpu(payload[1]);
1574 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1575 lock_arg = 0;
1576 lock_data = 0;
1577 } else {
1578 fw_fill_response(&response, packet->header,
1579 RCODE_TYPE_ERROR, NULL, 0);
1580 goto out;
1581 }
1582
1583 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1584 reg_write(ohci, OHCI1394_CSRData, lock_data);
1585 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1586 reg_write(ohci, OHCI1394_CSRControl, sel);
1587
e1393667
CL		 1588 for (try = 0; try < 20; try++)
1589 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1590 lock_old = cpu_to_be32(reg_read(ohci,
1591 OHCI1394_CSRData));
1592 fw_fill_response(&response, packet->header,
1593 RCODE_COMPLETE,
1594 &lock_old, sizeof(lock_old));
1595 goto out;
1596 }
1597
de97cb64 1598 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
e1393667 1599 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1600
93c4cceb
KH		 1601 out:
1602 fw_core_handle_response(&ohci->card, &response);
1603}
1604
53dca511 1605static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1606{
2608203d 1607 u64 offset, csr;
93c4cceb 1608
473d28c7
KH		 1609 if (ctx == &ctx->ohci->at_request_ctx) {
1610 packet->ack = ACK_PENDING;
1611 packet->callback(packet, &ctx->ohci->card, packet->ack);
1612 }
93c4cceb
KH		 1613
1614 offset =
1615 ((unsigned long long)
a77754a7 1616 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1617 packet->header[2];
1618 csr = offset - CSR_REGISTER_BASE;
1619
1620 /* Handle config rom reads. */
1621 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1622 handle_local_rom(ctx->ohci, packet, csr);
1623 else switch (csr) {
1624 case CSR_BUS_MANAGER_ID:
1625 case CSR_BANDWIDTH_AVAILABLE:
1626 case CSR_CHANNELS_AVAILABLE_HI:
1627 case CSR_CHANNELS_AVAILABLE_LO:
1628 handle_local_lock(ctx->ohci, packet, csr);
1629 break;
1630 default:
1631 if (ctx == &ctx->ohci->at_request_ctx)
1632 fw_core_handle_request(&ctx->ohci->card, packet);
1633 else
1634 fw_core_handle_response(&ctx->ohci->card, packet);
1635 break;
1636 }
473d28c7
KH		 1637
1638 if (ctx == &ctx->ohci->at_response_ctx) {
1639 packet->ack = ACK_COMPLETE;
1640 packet->callback(packet, &ctx->ohci->card, packet->ack);
1641 }
93c4cceb 1642}
e636fe25 1643
53dca511 1644static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1645{
ed568912 1646 unsigned long flags;
2dbd7d7e 1647 int ret;
ed568912
KH		 1648
1649 spin_lock_irqsave(&ctx->ohci->lock, flags);
1650
a77754a7 1651 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1652 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1653 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1654 handle_local_request(ctx, packet);
1655 return;
e636fe25 1656 }
ed568912 1657
2dbd7d7e 1658 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1659 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1660
2dbd7d7e 1661 if (ret < 0)
f319b6a0 1662 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1663
ed568912
KH		 1664}
1665
f117a3e3
CL		 1666static void detect_dead_context(struct fw_ohci *ohci,
1667 const char *name, unsigned int regs)
1668{
1669 u32 ctl;
1670
1671 ctl = reg_read(ohci, CONTROL_SET(regs));
cfda62ba 1672 if (ctl & CONTEXT_DEAD)
de97cb64 1673 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
64d21720 1674 name, evts[ctl & 0x1f]);
f117a3e3
CL		 1675}
1676
1677static void handle_dead_contexts(struct fw_ohci *ohci)
1678{
1679 unsigned int i;
1680 char name[8];
1681
1682 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1683 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1684 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1685 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1686 for (i = 0; i < 32; ++i) {
1687 if (!(ohci->it_context_support & (1 << i)))
1688 continue;
1689 sprintf(name, "IT%u", i);
1690 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1691 }
1692 for (i = 0; i < 32; ++i) {
1693 if (!(ohci->ir_context_support & (1 << i)))
1694 continue;
1695 sprintf(name, "IR%u", i);
1696 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1697 }
1698 /* TODO: maybe try to flush and restart the dead contexts */
1699}
1700
a48777e0
CL		 1701static u32 cycle_timer_ticks(u32 cycle_timer)
1702{
1703 u32 ticks;
1704
1705 ticks = cycle_timer & 0xfff;
1706 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1707 ticks += (3072 * 8000) * (cycle_timer >> 25);
1708
1709 return ticks;
1710}
1711
1712/*
1713 * Some controllers exhibit one or more of the following bugs when updating the
1714 * iso cycle timer register:
1715 * - When the lowest six bits are wrapping around to zero, a read that happens
1716 * at the same time will return garbage in the lowest ten bits.
1717 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1718 * not incremented for about 60 ns.
1719 * - Occasionally, the entire register reads zero.
1720 *
1721 * To catch these, we read the register three times and ensure that the
1722 * difference between each two consecutive reads is approximately the same, i.e.
1723 * less than twice the other. Furthermore, any negative difference indicates an
1724 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1725 * execute, so we have enough precision to compute the ratio of the differences.)
1726 */
1727static u32 get_cycle_time(struct fw_ohci *ohci)
1728{
1729 u32 c0, c1, c2;
1730 u32 t0, t1, t2;
1731 s32 diff01, diff12;
1732 int i;
1733
1734 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1735
1736 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1737 i = 0;
1738 c1 = c2;
1739 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1740 do {
1741 c0 = c1;
1742 c1 = c2;
1743 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1744 t0 = cycle_timer_ticks(c0);
1745 t1 = cycle_timer_ticks(c1);
1746 t2 = cycle_timer_ticks(c2);
1747 diff01 = t1 - t0;
1748 diff12 = t2 - t1;
1749 } while ((diff01 <= 0 || diff12 <= 0 ||
1750 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1751 && i++ < 20);
1752 }
1753
1754 return c2;
1755}
1756
1757/*
1758 * This function has to be called at least every 64 seconds. The bus_time
1759 * field stores not only the upper 25 bits of the BUS_TIME register but also
1760 * the most significant bit of the cycle timer in bit 6 so that we can detect
1761 * changes in this bit.
1762 */
1763static u32 update_bus_time(struct fw_ohci *ohci)
1764{
1765 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1766
9d60ef2b
CL		 1767 if (unlikely(!ohci->bus_time_running)) {
1768 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1769 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1770 (cycle_time_seconds & 0x40);
1771 ohci->bus_time_running = true;
1772 }
1773
a48777e0
CL		 1774 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1775 ohci->bus_time += 0x40;
1776
1777 return ohci->bus_time | cycle_time_seconds;
1778}
1779
25935ebe
SG		 1780static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1781{
1782 int reg;
1783
1784 mutex_lock(&ohci->phy_reg_mutex);
1785 reg = write_phy_reg(ohci, 7, port_index);
28897fb7
SR		 1786 if (reg >= 0)
1787 reg = read_phy_reg(ohci, 8);
25935ebe
SG		 1788 mutex_unlock(&ohci->phy_reg_mutex);
1789 if (reg < 0)
1790 return reg;
1791
1792 switch (reg & 0x0f) {
1793 case 0x06:
1794 return 2; /* is child node (connected to parent node) */
1795 case 0x0e:
1796 return 3; /* is parent node (connected to child node) */
1797 }
1798 return 1; /* not connected */
1799}
1800
1801static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1802 int self_id_count)
1803{
1804 int i;
1805 u32 entry;
28897fb7 1806
25935ebe
SG		 1807 for (i = 0; i < self_id_count; i++) {
1808 entry = ohci->self_id_buffer[i];
1809 if ((self_id & 0xff000000) == (entry & 0xff000000))
1810 return -1;
1811 if ((self_id & 0xff000000) < (entry & 0xff000000))
1812 return i;
1813 }
1814 return i;
1815}
1816
52439d60
SG		 1817static int initiated_reset(struct fw_ohci *ohci)
1818{
1819 int reg;
1820 int ret = 0;
1821
1822 mutex_lock(&ohci->phy_reg_mutex);
1823 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1824 if (reg >= 0) {
1825 reg = read_phy_reg(ohci, 8);
1826 reg |= 0x40;
1827 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1828 if (reg >= 0) {
1829 reg = read_phy_reg(ohci, 12); /* read register 12 */
1830 if (reg >= 0) {
1831 if ((reg & 0x08) == 0x08) {
1832 /* bit 3 indicates "initiated reset" */
1833 ret = 0x2;
1834 }
1835 }
1836 }
1837 }
1838 mutex_unlock(&ohci->phy_reg_mutex);
1839 return ret;
1840}
1841
25935ebe 1842/*
28897fb7
SR		 1843 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1844 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1845 * Construct the selfID from phy register contents.
25935ebe 1846 */
25935ebe
SG		 1847static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1848{
28897fb7
SR		 1849 int reg, i, pos, status;
1850 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1851 u32 self_id = 0x8040c800;
25935ebe
SG		 1852
1853 reg = reg_read(ohci, OHCI1394_NodeID);
1854 if (!(reg & OHCI1394_NodeID_idValid)) {
de97cb64
PH		 1855 ohci_notice(ohci,
1856 "node ID not valid, new bus reset in progress\n");
25935ebe
SG		 1857 return -EBUSY;
1858 }
1859 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1860
28897fb7 1861 reg = ohci_read_phy_reg(&ohci->card, 4);
25935ebe
SG		 1862 if (reg < 0)
1863 return reg;
1864 self_id |= ((reg & 0x07) << 8); /* power class */
1865
28897fb7 1866 reg = ohci_read_phy_reg(&ohci->card, 1);
25935ebe
SG		 1867 if (reg < 0)
1868 return reg;
1869 self_id |= ((reg & 0x3f) << 16); /* gap count */
1870
1871 for (i = 0; i < 3; i++) {
1872 status = get_status_for_port(ohci, i);
1873 if (status < 0)
1874 return status;
1875 self_id |= ((status & 0x3) << (6 - (i * 2)));
1876 }
1877
52439d60
SG		 1878 self_id |= initiated_reset(ohci);
1879
25935ebe
SG		 1880 pos = get_self_id_pos(ohci, self_id, self_id_count);
1881 if (pos >= 0) {
1882 memmove(&(ohci->self_id_buffer[pos+1]),
1883 &(ohci->self_id_buffer[pos]),
1884 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1885 ohci->self_id_buffer[pos] = self_id;
1886 self_id_count++;
1887 }
1888 return self_id_count;
1889}
1890
2d7a36e2 1891static void bus_reset_work(struct work_struct *work)
ed568912 1892{
2d7a36e2
SG		 1893 struct fw_ohci *ohci =
1894 container_of(work, struct fw_ohci, bus_reset_work);
d713dfa7
SR		 1895 int self_id_count, generation, new_generation, i, j;
1896 u32 reg;
4eaff7d6
SR		 1897 void *free_rom = NULL;
1898 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1899 bool is_new_root;
ed568912
KH		 1900
1901 reg = reg_read(ohci, OHCI1394_NodeID);
1902 if (!(reg & OHCI1394_NodeID_idValid)) {
de97cb64
PH		 1903 ohci_notice(ohci,
1904 "node ID not valid, new bus reset in progress\n");
ed568912
KH		 1905 return;
1906 }
02ff8f8e 1907 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
de97cb64 1908 ohci_notice(ohci, "malconfigured bus\n");
02ff8f8e
SR		 1909 return;
1910 }
1911 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1912 OHCI1394_NodeID_nodeNumber);
ed568912 1913
4ffb7a6a
CL		 1914 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1915 if (!(ohci->is_root && is_new_root))
1916 reg_write(ohci, OHCI1394_LinkControlSet,
1917 OHCI1394_LinkControl_cycleMaster);
1918 ohci->is_root = is_new_root;
1919
c8a9a498
SR		 1920 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1921 if (reg & OHCI1394_SelfIDCount_selfIDError) {
67672134 1922 ohci_notice(ohci, "self ID receive error\n");
c8a9a498
SR		 1923 return;
1924 }
c781c06d
KH		 1925 /*
1926 * The count in the SelfIDCount register is the number of
ed568912
KH		 1927 * bytes in the self ID receive buffer. Since we also receive
1928 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1929 * bit extra to get the actual number of self IDs.
1930 */
928ec5f1 1931 self_id_count = (reg >> 3) & 0xff;
25935ebe
SG		 1932
1933 if (self_id_count > 252) {
67672134 1934 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
016bf3df
SR		 1935 return;
1936 }
25935ebe 1937
af53122a 1938 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
ee71c2f9 1939 rmb();
ed568912
KH		 1940
1941 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
af53122a
SR		 1942 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1943 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
67672134
PH		 1944
1945 if (id != ~id2) {
32eaeae1
CL		 1946 /*
1947 * If the invalid data looks like a cycle start packet,
1948 * it's likely to be the result of the cycle master
1949 * having a wrong gap count. In this case, the self IDs
1950 * so far are valid and should be processed so that the
1951 * bus manager can then correct the gap count.
1952 */
67672134
PH		 1953 if (id == 0xffff008f) {
1954 ohci_notice(ohci, "ignoring spurious self IDs\n");
32eaeae1
CL		 1955 self_id_count = j;
1956 break;
32eaeae1 1957 }
67672134
PH		 1958
1959 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1960 j, self_id_count, id, id2);
1961 return;
c8a9a498 1962 }
67672134 1963 ohci->self_id_buffer[j] = id;
ed568912 1964 }
25935ebe
SG		 1965
1966 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1967 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1968 if (self_id_count < 0) {
de97cb64
PH		 1969 ohci_notice(ohci,
1970 "could not construct local self ID\n");
25935ebe
SG		 1971 return;
1972 }
1973 }
1974
1975 if (self_id_count == 0) {
67672134 1976 ohci_notice(ohci, "no self IDs\n");
25935ebe
SG		 1977 return;
1978 }
ee71c2f9 1979 rmb();
ed568912 1980
c781c06d
KH		 1981 /*
1982 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1983 * problem we face is that a new bus reset can start while we
1984 * read out the self IDs from the DMA buffer. If this happens,
1985 * the DMA buffer will be overwritten with new self IDs and we
1986 * will read out inconsistent data. The OHCI specification
1987 * (section 11.2) recommends a technique similar to
1988 * linux/seqlock.h, where we remember the generation of the
1989 * self IDs in the buffer before reading them out and compare
1990 * it to the current generation after reading them out. If
1991 * the two generations match we know we have a consistent set
c781c06d
KH		 1992 * of self IDs.
1993 */
ed568912
KH		 1994
1995 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1996 if (new_generation != generation) {
de97cb64 1997 ohci_notice(ohci, "new bus reset, discarding self ids\n");
ed568912
KH		 1998 return;
1999 }
2000
2001 /* FIXME: Document how the locking works. */
8a8c4736 2002 spin_lock_irq(&ohci->lock);
ed568912 2003
82b662dc 2004 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 2005 context_stop(&ohci->at_request_ctx);
2006 context_stop(&ohci->at_response_ctx);
82b662dc 2007
8a8c4736 2008 spin_unlock_irq(&ohci->lock);
82b662dc 2009
78dec56d
SR		 2010 /*
2011 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2012 * packets in the AT queues and software needs to drain them.
2013 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2014 */
82b662dc
CL		 2015 at_context_flush(&ohci->at_request_ctx);
2016 at_context_flush(&ohci->at_response_ctx);
2017
8a8c4736 2018 spin_lock_irq(&ohci->lock);
82b662dc
CL		 2019
2020 ohci->generation = generation;
ed568912
KH		 2021 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2022
4a635593 2023 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 2024 ohci->request_generation = generation;
2025
c781c06d
KH		 2026 /*
2027 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 2028 * have to do it under the spinlock also. If a new config rom
2029 * was set up before this reset, the old one is now no longer
2030 * in use and we can free it. Update the config rom pointers
2031 * to point to the current config rom and clear the
88393161 2032 * next_config_rom pointer so a new update can take place.
c781c06d 2033 */
ed568912
KH		 2034
2035 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 2036 if (ohci->next_config_rom != ohci->config_rom) {
2037 free_rom = ohci->config_rom;
2038 free_rom_bus = ohci->config_rom_bus;
2039 }
ed568912
KH		 2040 ohci->config_rom = ohci->next_config_rom;
2041 ohci->config_rom_bus = ohci->next_config_rom_bus;
2042 ohci->next_config_rom = NULL;
2043
c781c06d
KH		 2044 /*
2045 * Restore config_rom image and manually update
ed568912
KH		 2046 * config_rom registers. Writing the header quadlet
2047 * will indicate that the config rom is ready, so we
c781c06d
KH		 2048 * do that last.
2049 */
ed568912
KH		 2050 reg_write(ohci, OHCI1394_BusOptions,
2051 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 2052 ohci->config_rom[0] = ohci->next_header;
2053 reg_write(ohci, OHCI1394_ConfigROMhdr,
2054 be32_to_cpu(ohci->next_header));
ed568912
KH		 2055 }
2056
8bc588e0
LR		 2057 if (param_remote_dma) {
2058 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2059 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2060 }
080de8c2 2061
8a8c4736 2062 spin_unlock_irq(&ohci->lock);
ed568912 2063
4eaff7d6
SR		 2064 if (free_rom)
2065 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2066 free_rom, free_rom_bus);
2067
64d21720 2068 log_selfids(ohci, generation, self_id_count);
ad3c0fe8 2069
e636fe25 2070 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 2071 self_id_count, ohci->self_id_buffer,
2072 ohci->csr_state_setclear_abdicate);
2073 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 2074}
2075
2076static irqreturn_t irq_handler(int irq, void *data)
2077{
2078 struct fw_ohci *ohci = data;
168cf9af 2079 u32 event, iso_event;
ed568912
KH		 2080 int i;
2081
2082 event = reg_read(ohci, OHCI1394_IntEventClear);
2083
a515958d 2084 if (!event || !~event)
ed568912
KH		 2085 return IRQ_NONE;
2086
8327b37b
CL		 2087 /*
2088 * busReset and postedWriteErr must not be cleared yet
2089 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2090 */
2091 reg_write(ohci, OHCI1394_IntEventClear,
2092 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
64d21720 2093 log_irqs(ohci, event);
ed568912
KH		 2094
2095 if (event & OHCI1394_selfIDComplete)
db9ae8fe 2096 queue_work(selfid_workqueue, &ohci->bus_reset_work);
ed568912
KH		 2097
2098 if (event & OHCI1394_RQPkt)
2099 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2100
2101 if (event & OHCI1394_RSPkt)
2102 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2103
2104 if (event & OHCI1394_reqTxComplete)
2105 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2106
2107 if (event & OHCI1394_respTxComplete)
2108 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2109
2dd5bed5
CL		 2110 if (event & OHCI1394_isochRx) {
2111 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2112 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2113
2114 while (iso_event) {
2115 i = ffs(iso_event) - 1;
2116 tasklet_schedule(
2117 &ohci->ir_context_list[i].context.tasklet);
2118 iso_event &= ~(1 << i);
2119 }
ed568912
KH		 2120 }
2121
2dd5bed5
CL		 2122 if (event & OHCI1394_isochTx) {
2123 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2124 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 2125
2dd5bed5
CL		 2126 while (iso_event) {
2127 i = ffs(iso_event) - 1;
2128 tasklet_schedule(
2129 &ohci->it_context_list[i].context.tasklet);
2130 iso_event &= ~(1 << i);
2131 }
ed568912
KH		 2132 }
2133
75f7832e 2134 if (unlikely(event & OHCI1394_regAccessFail))
de97cb64 2135 ohci_err(ohci, "register access failure\n");
75f7832e 2136
8327b37b
CL		 2137 if (unlikely(event & OHCI1394_postedWriteErr)) {
2138 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2139 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2140 reg_write(ohci, OHCI1394_IntEventClear,
2141 OHCI1394_postedWriteErr);
a74477db 2142 if (printk_ratelimit())
de97cb64 2143 ohci_err(ohci, "PCI posted write error\n");
8327b37b 2144 }
e524f616 2145
bb9f2206
SR		 2146 if (unlikely(event & OHCI1394_cycleTooLong)) {
2147 if (printk_ratelimit())
de97cb64 2148 ohci_notice(ohci, "isochronous cycle too long\n");
bb9f2206
SR		 2149 reg_write(ohci, OHCI1394_LinkControlSet,
2150 OHCI1394_LinkControl_cycleMaster);
2151 }
2152
5ed1f321
JF		 2153 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2154 /*
2155 * We need to clear this event bit in order to make
2156 * cycleMatch isochronous I/O work. In theory we should
2157 * stop active cycleMatch iso contexts now and restart
2158 * them at least two cycles later. (FIXME?)
2159 */
2160 if (printk_ratelimit())
de97cb64 2161 ohci_notice(ohci, "isochronous cycle inconsistent\n");
5ed1f321
JF		 2162 }
2163
f117a3e3
CL		 2164 if (unlikely(event & OHCI1394_unrecoverableError))
2165 handle_dead_contexts(ohci);
2166
a48777e0
CL		 2167 if (event & OHCI1394_cycle64Seconds) {
2168 spin_lock(&ohci->lock);
2169 update_bus_time(ohci);
2170 spin_unlock(&ohci->lock);
e597e989
CL		 2171 } else
2172 flush_writes(ohci);
a48777e0 2173
ed568912
KH		 2174 return IRQ_HANDLED;
2175}
2176
2aef469a
KH		 2177static int software_reset(struct fw_ohci *ohci)
2178{
9f426173 2179 u32 val;
2aef469a
KH		 2180 int i;
2181
2182 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
9f426173
SR		 2183 for (i = 0; i < 500; i++) {
2184 val = reg_read(ohci, OHCI1394_HCControlSet);
2185 if (!~val)
2186 return -ENODEV; /* Card was ejected. */
2aef469a 2187
9f426173 2188 if (!(val & OHCI1394_HCControl_softReset))
2aef469a 2189 return 0;
9f426173 2190
2aef469a
KH		 2191 msleep(1);
2192 }
2193
2194 return -EBUSY;
2195}
2196
8e85973e
SR		 2197static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2198{
2199 size_t size = length * 4;
2200
2201 memcpy(dest, src, size);
2202 if (size < CONFIG_ROM_SIZE)
2203 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2204}
2205
925e7a65
CL		 2206static int configure_1394a_enhancements(struct fw_ohci *ohci)
2207{
2208 bool enable_1394a;
35d999b1 2209 int ret, clear, set, offset;
925e7a65
CL		 2210
2211 /* Check if the driver should configure link and PHY. */
2212 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2213 OHCI1394_HCControl_programPhyEnable))
2214 return 0;
2215
2216 /* Paranoia: check whether the PHY supports 1394a, too. */
2217 enable_1394a = false;
35d999b1
SR		 2218 ret = read_phy_reg(ohci, 2);
2219 if (ret < 0)
2220 return ret;
2221 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2222 ret = read_paged_phy_reg(ohci, 1, 8);
2223 if (ret < 0)
2224 return ret;
2225 if (ret >= 1)
925e7a65
CL		 2226 enable_1394a = true;
2227 }
2228
2229 if (ohci->quirks & QUIRK_NO_1394A)
2230 enable_1394a = false;
2231
2232 /* Configure PHY and link consistently. */
2233 if (enable_1394a) {
2234 clear = 0;
2235 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2236 } else {
2237 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2238 set = 0;
2239 }
02d37bed 2240 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2241 if (ret < 0)
2242 return ret;
925e7a65
CL		 2243
2244 if (enable_1394a)
2245 offset = OHCI1394_HCControlSet;
2246 else
2247 offset = OHCI1394_HCControlClear;
2248 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2249
2250 /* Clean up: configuration has been taken care of. */
2251 reg_write(ohci, OHCI1394_HCControlClear,
2252 OHCI1394_HCControl_programPhyEnable);
2253
2254 return 0;
2255}
2256
25935ebe
SG		 2257static int probe_tsb41ba3d(struct fw_ohci *ohci)
2258{
b810e4ae
SR		 2259 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2260 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2261 int reg, i;
25935ebe
SG		 2262
2263 reg = read_phy_reg(ohci, 2);
2264 if (reg < 0)
2265 return reg;
b810e4ae
SR		 2266 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2267 return 0;
25935ebe 2268
b810e4ae
SR		 2269 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2270 reg = read_paged_phy_reg(ohci, 1, i + 10);
2271 if (reg < 0)
2272 return reg;
2273 if (reg != id[i])
2274 return 0;
25935ebe 2275 }
b810e4ae 2276 return 1;
25935ebe
SG		 2277}
2278
8e85973e
SR		 2279static int ohci_enable(struct fw_card *card,
2280 const __be32 *config_rom, size_t length)
ed568912
KH		 2281{
2282 struct fw_ohci *ohci = fw_ohci(card);
9d60ef2b 2283 u32 lps, version, irqs;
28897fb7 2284 int i, ret;
ed568912 2285
2aef469a 2286 if (software_reset(ohci)) {
de97cb64 2287 ohci_err(ohci, "failed to reset ohci card\n");
2aef469a
KH		 2288 return -EBUSY;
2289 }
2290
2291 /*
2292 * Now enable LPS, which we need in order to start accessing
2293 * most of the registers. In fact, on some cards (ALI M5251),
2294 * accessing registers in the SClk domain without LPS enabled
2295 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2296 * full link enabled. However, with some cards (well, at least
2297 * a JMicron PCIe card), we have to try again sometimes.
bd972688
PH		 2298 *
2299 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2300 * cannot actually use the phy at that time. These need tens of
2301 * millisecods pause between LPS write and first phy access too.
2302 *
2303 * But do not wait for 50msec on Agere/LSI cards. Their phy
2304 * arbitration state machine may time out during such a long wait.
2aef469a 2305 */
bd972688 2306
2aef469a
KH		 2307 reg_write(ohci, OHCI1394_HCControlSet,
2308 OHCI1394_HCControl_LPS |
2309 OHCI1394_HCControl_postedWriteEnable);
2310 flush_writes(ohci);
02214724 2311
bd972688 2312 if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT))
02214724 2313 msleep(50);
bd972688
PH		 2314
2315 for (lps = 0, i = 0; !lps && i < 150; i++) {
2316 msleep(1);
02214724
JW		 2317 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2318 OHCI1394_HCControl_LPS;
2319 }
2320
2321 if (!lps) {
de97cb64 2322 ohci_err(ohci, "failed to set Link Power Status\n");
02214724
JW		 2323 return -EIO;
2324 }
2aef469a 2325
25935ebe 2326 if (ohci->quirks & QUIRK_TI_SLLZ059) {
28897fb7
SR		 2327 ret = probe_tsb41ba3d(ohci);
2328 if (ret < 0)
2329 return ret;
2330 if (ret)
de97cb64 2331 ohci_notice(ohci, "local TSB41BA3D phy\n");
28897fb7 2332 else
25935ebe 2333 ohci->quirks &= ~QUIRK_TI_SLLZ059;
25935ebe
SG		 2334 }
2335
2aef469a
KH		 2336 reg_write(ohci, OHCI1394_HCControlClear,
2337 OHCI1394_HCControl_noByteSwapData);
2338
affc9c24 2339 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2340 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2341 OHCI1394_LinkControl_cycleTimerEnable |
2342 OHCI1394_LinkControl_cycleMaster);
2343
2344 reg_write(ohci, OHCI1394_ATRetries,
2345 OHCI1394_MAX_AT_REQ_RETRIES |
2346 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2347 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2348 (200 << 16));
2aef469a 2349
9d60ef2b 2350 ohci->bus_time_running = false;
a48777e0 2351
e18907cc
CL		 2352 for (i = 0; i < 32; i++)
2353 if (ohci->ir_context_support & (1 << i))
2354 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2355 IR_CONTEXT_MULTI_CHANNEL_MODE);
2356
e91b2787
CL		 2357 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2358 if (version >= OHCI_VERSION_1_1) {
2359 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2360 0xfffffffe);
db3c9cc1 2361 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2362 }
2363
a1a1132b
CL		 2364 /* Get implemented bits of the priority arbitration request counter. */
2365 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2366 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2367 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2368 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2369
2aef469a
KH		 2370 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2371 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2372 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2373
35d999b1
SR		 2374 ret = configure_1394a_enhancements(ohci);
2375 if (ret < 0)
2376 return ret;
925e7a65 2377
2aef469a 2378 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2379 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2380 if (ret < 0)
2381 return ret;
2aef469a 2382
c781c06d
KH		 2383 /*
2384 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2385 * update mechanism described below in ohci_set_config_rom()
2386 * is not active. We have to update ConfigRomHeader and
2387 * BusOptions manually, and the write to ConfigROMmap takes
2388 * effect immediately. We tie this to the enabling of the
2389 * link, so we have a valid config rom before enabling - the
2390 * OHCI requires that ConfigROMhdr and BusOptions have valid
2391 * values before enabling.
2392 *
2393 * However, when the ConfigROMmap is written, some controllers
2394 * always read back quadlets 0 and 2 from the config rom to
2395 * the ConfigRomHeader and BusOptions registers on bus reset.
2396 * They shouldn't do that in this initial case where the link
2397 * isn't enabled. This means we have to use the same
2398 * workaround here, setting the bus header to 0 and then write
2399 * the right values in the bus reset tasklet.
2400 */
2401
0bd243c4
KH		 2402 if (config_rom) {
2403 ohci->next_config_rom =
2404 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2405 &ohci->next_config_rom_bus,
2406 GFP_KERNEL);
2407 if (ohci->next_config_rom == NULL)
2408 return -ENOMEM;
ed568912 2409
8e85973e 2410 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2411 } else {
2412 /*
2413 * In the suspend case, config_rom is NULL, which
2414 * means that we just reuse the old config rom.
2415 */
2416 ohci->next_config_rom = ohci->config_rom;
2417 ohci->next_config_rom_bus = ohci->config_rom_bus;
2418 }
ed568912 2419
8e85973e 2420 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2421 ohci->next_config_rom[0] = 0;
2422 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2423 reg_write(ohci, OHCI1394_BusOptions,
2424 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2425 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2426
2427 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2428
148c7866
SR		 2429 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2430 OHCI1394_RQPkt | OHCI1394_RSPkt |
2431 OHCI1394_isochTx | OHCI1394_isochRx |
2432 OHCI1394_postedWriteErr |
2433 OHCI1394_selfIDComplete |
2434 OHCI1394_regAccessFail |
f117a3e3
CL		 2435 OHCI1394_cycleInconsistent |
2436 OHCI1394_unrecoverableError |
2437 OHCI1394_cycleTooLong |
148c7866
SR		 2438 OHCI1394_masterIntEnable;
2439 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2440 irqs |= OHCI1394_busReset;
2441 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2442
ed568912
KH		 2443 reg_write(ohci, OHCI1394_HCControlSet,
2444 OHCI1394_HCControl_linkEnable |
2445 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2446
2447 reg_write(ohci, OHCI1394_LinkControlSet,
2448 OHCI1394_LinkControl_rcvSelfID |
2449 OHCI1394_LinkControl_rcvPhyPkt);
2450
2451 ar_context_run(&ohci->ar_request_ctx);
dd6254e5
CL		 2452 ar_context_run(&ohci->ar_response_ctx);
2453
2454 flush_writes(ohci);
ed568912 2455
02d37bed
SR		 2456 /* We are ready to go, reset bus to finish initialization. */
2457 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2458
2459 return 0;
2460}
2461
53dca511 2462static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2463 const __be32 *config_rom, size_t length)
ed568912
KH		 2464{
2465 struct fw_ohci *ohci;
ed568912 2466 __be32 *next_config_rom;
f5101d58 2467 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2468
2469 ohci = fw_ohci(card);
2470
c781c06d
KH		 2471 /*
2472 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2473 * mechanism is a bit tricky, but easy enough to use. See
2474 * section 5.5.6 in the OHCI specification.
2475 *
2476 * The OHCI controller caches the new config rom address in a
2477 * shadow register (ConfigROMmapNext) and needs a bus reset
2478 * for the changes to take place. When the bus reset is
2479 * detected, the controller loads the new values for the
2480 * ConfigRomHeader and BusOptions registers from the specified
2481 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2482 * shadow register. All automatically and atomically.
2483 *
2484 * Now, there's a twist to this story. The automatic load of
2485 * ConfigRomHeader and BusOptions doesn't honor the
2486 * noByteSwapData bit, so with a be32 config rom, the
2487 * controller will load be32 values in to these registers
2488 * during the atomic update, even on litte endian
2489 * architectures. The workaround we use is to put a 0 in the
2490 * header quadlet; 0 is endian agnostic and means that the
2491 * config rom isn't ready yet. In the bus reset tasklet we
2492 * then set up the real values for the two registers.
2493 *
2494 * We use ohci->lock to avoid racing with the code that sets
2d7a36e2 2495 * ohci->next_config_rom to NULL (see bus_reset_work).
ed568912
KH		 2496 */
2497
2498 next_config_rom =
2499 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2500 &next_config_rom_bus, GFP_KERNEL);
2501 if (next_config_rom == NULL)
2502 return -ENOMEM;
2503
8a8c4736 2504 spin_lock_irq(&ohci->lock);
ed568912 2505
2e053a27
B		 2506 /*
2507 * If there is not an already pending config_rom update,
2508 * push our new allocation into the ohci->next_config_rom
2509 * and then mark the local variable as null so that we
2510 * won't deallocate the new buffer.
2511 *
2512 * OTOH, if there is a pending config_rom update, just
2513 * use that buffer with the new config_rom data, and
2514 * let this routine free the unused DMA allocation.
2515 */
2516
ed568912
KH		 2517 if (ohci->next_config_rom == NULL) {
2518 ohci->next_config_rom = next_config_rom;
2519 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2520 next_config_rom = NULL;
2521 }
ed568912 2522
2e053a27 2523 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2524
2e053a27
B		 2525 ohci->next_header = config_rom[0];
2526 ohci->next_config_rom[0] = 0;
ed568912 2527
2e053a27 2528 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912 2529
8a8c4736 2530 spin_unlock_irq(&ohci->lock);
ed568912 2531
2e053a27
B		 2532 /* If we didn't use the DMA allocation, delete it. */
2533 if (next_config_rom != NULL)
2534 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2535 next_config_rom, next_config_rom_bus);
2536
c781c06d
KH		 2537 /*
2538 * Now initiate a bus reset to have the changes take
ed568912
KH		 2539 * effect. We clean up the old config rom memory and DMA
2540 * mappings in the bus reset tasklet, since the OHCI
2541 * controller could need to access it before the bus reset
c781c06d
KH		 2542 * takes effect.
2543 */
ed568912 2544
2e053a27
B		 2545 fw_schedule_bus_reset(&ohci->card, true, true);
2546
2547 return 0;
ed568912
KH		 2548}
2549
2550static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2551{
2552 struct fw_ohci *ohci = fw_ohci(card);
2553
2554 at_context_transmit(&ohci->at_request_ctx, packet);
2555}
2556
2557static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2558{
2559 struct fw_ohci *ohci = fw_ohci(card);
2560
2561 at_context_transmit(&ohci->at_response_ctx, packet);
2562}
2563
730c32f5
KH		 2564static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2565{
2566 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2567 struct context *ctx = &ohci->at_request_ctx;
2568 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2569 int ret = -ENOENT;
730c32f5 2570
f319b6a0 2571 tasklet_disable(&ctx->tasklet);
730c32f5 2572
f319b6a0
KH		 2573 if (packet->ack != 0)
2574 goto out;
730c32f5 2575
19593ffd 2576 if (packet->payload_mapped)
1d1dc5e8
SR		 2577 dma_unmap_single(ohci->card.device, packet->payload_bus,
2578 packet->payload_length, DMA_TO_DEVICE);
2579
64d21720 2580 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2581 driver_data->packet = NULL;
2582 packet->ack = RCODE_CANCELLED;
2583 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2584 ret = 0;
f319b6a0
KH		 2585 out:
2586 tasklet_enable(&ctx->tasklet);
730c32f5 2587
2dbd7d7e 2588 return ret;
730c32f5
KH		 2589}
2590
53dca511
SR		 2591static int ohci_enable_phys_dma(struct fw_card *card,
2592 int node_id, int generation)
ed568912
KH		 2593{
2594 struct fw_ohci *ohci = fw_ohci(card);
2595 unsigned long flags;
2dbd7d7e 2596 int n, ret = 0;
ed568912 2597
8bc588e0
LR		 2598 if (param_remote_dma)
2599 return 0;
2600
c781c06d
KH		 2601 /*
2602 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2603 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2604 */
ed568912
KH		 2605
2606 spin_lock_irqsave(&ohci->lock, flags);
2607
2608 if (ohci->generation != generation) {
2dbd7d7e 2609 ret = -ESTALE;
ed568912
KH		 2610 goto out;
2611 }
2612
c781c06d
KH		 2613 /*
2614 * Note, if the node ID contains a non-local bus ID, physical DMA is
2615 * enabled for _all_ nodes on remote buses.
2616 */
907293d7
SR		 2617
2618 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2619 if (n < 32)
2620 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2621 else
2622 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2623
ed568912 2624 flush_writes(ohci);
ed568912 2625 out:
6cad95fe 2626 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2627
2628 return ret;
ed568912 2629}
373b2edd 2630
0fcff4e3 2631static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2632{
60d32970 2633 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2634 unsigned long flags;
2635 u32 value;
60d32970
CL		 2636
2637 switch (csr_offset) {
4ffb7a6a
CL		 2638 case CSR_STATE_CLEAR:
2639 case CSR_STATE_SET:
4ffb7a6a
CL		 2640 if (ohci->is_root &&
2641 (reg_read(ohci, OHCI1394_LinkControlSet) &
2642 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2643 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2644 else
c8a94ded
SR		 2645 value = 0;
2646 if (ohci->csr_state_setclear_abdicate)
2647 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2648
c8a94ded 2649 return value;
4a9bde9b 2650
506f1a31
CL		 2651 case CSR_NODE_IDS:
2652 return reg_read(ohci, OHCI1394_NodeID) << 16;
2653
60d32970
CL		 2654 case CSR_CYCLE_TIME:
2655 return get_cycle_time(ohci);
2656
a48777e0
CL		 2657 case CSR_BUS_TIME:
2658 /*
2659 * We might be called just after the cycle timer has wrapped
2660 * around but just before the cycle64Seconds handler, so we
2661 * better check here, too, if the bus time needs to be updated.
2662 */
2663 spin_lock_irqsave(&ohci->lock, flags);
2664 value = update_bus_time(ohci);
2665 spin_unlock_irqrestore(&ohci->lock, flags);
2666 return value;
2667
27a2329f
CL		 2668 case CSR_BUSY_TIMEOUT:
2669 value = reg_read(ohci, OHCI1394_ATRetries);
2670 return (value >> 4) & 0x0ffff00f;
2671
a1a1132b
CL		 2672 case CSR_PRIORITY_BUDGET:
2673 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2674 (ohci->pri_req_max << 8);
2675
60d32970
CL		 2676 default:
2677 WARN_ON(1);
2678 return 0;
2679 }
b677532b
CL		 2680}
2681
0fcff4e3 2682static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2683{
2684 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2685 unsigned long flags;
d60d7f1d 2686
506f1a31 2687 switch (csr_offset) {
4ffb7a6a 2688 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2689 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2690 reg_write(ohci, OHCI1394_LinkControlClear,
2691 OHCI1394_LinkControl_cycleMaster);
2692 flush_writes(ohci);
2693 }
c8a94ded
SR		 2694 if (value & CSR_STATE_BIT_ABDICATE)
2695 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2696 break;
4a9bde9b 2697
4ffb7a6a
CL		 2698 case CSR_STATE_SET:
2699 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2700 reg_write(ohci, OHCI1394_LinkControlSet,
2701 OHCI1394_LinkControl_cycleMaster);
2702 flush_writes(ohci);
2703 }
c8a94ded
SR		 2704 if (value & CSR_STATE_BIT_ABDICATE)
2705 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2706 break;
d60d7f1d 2707
506f1a31
CL		 2708 case CSR_NODE_IDS:
2709 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2710 flush_writes(ohci);
2711 break;
2712
9ab5071c
CL		 2713 case CSR_CYCLE_TIME:
2714 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2715 reg_write(ohci, OHCI1394_IntEventSet,
2716 OHCI1394_cycleInconsistent);
2717 flush_writes(ohci);
2718 break;
2719
a48777e0
CL		 2720 case CSR_BUS_TIME:
2721 spin_lock_irqsave(&ohci->lock, flags);
9d60ef2b
CL		 2722 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2723 (value & ~0x7f);
a48777e0
CL		 2724 spin_unlock_irqrestore(&ohci->lock, flags);
2725 break;
2726
27a2329f
CL		 2727 case CSR_BUSY_TIMEOUT:
2728 value = (value & 0xf) | ((value & 0xf) << 4) |
2729 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2730 reg_write(ohci, OHCI1394_ATRetries, value);
2731 flush_writes(ohci);
2732 break;
2733
a1a1132b
CL		 2734 case CSR_PRIORITY_BUDGET:
2735 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2736 flush_writes(ohci);
2737 break;
2738
506f1a31
CL		 2739 default:
2740 WARN_ON(1);
2741 break;
2742 }
d60d7f1d
KH		 2743}
2744
910e76c6 2745static void flush_iso_completions(struct iso_context *ctx)
1aa292bb 2746{
910e76c6
CL		 2747 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2748 ctx->header_length, ctx->header,
2749 ctx->base.callback_data);
2750 ctx->header_length = 0;
2751}
1aa292bb 2752
73864012 2753static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
1aa292bb 2754{
73864012 2755 u32 *ctx_hdr;
1aa292bb 2756
0699a73a
CL		 2757 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2758 if (ctx->base.drop_overflow_headers)
2759 return;
18d62711 2760 flush_iso_completions(ctx);
0699a73a 2761 }
1aa292bb 2762
73864012 2763 ctx_hdr = ctx->header + ctx->header_length;
910e76c6 2764 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
1aa292bb
DM		 2765
2766 /*
32c507f7
CL		 2767 * The two iso header quadlets are byteswapped to little
2768 * endian by the controller, but we want to present them
2769 * as big endian for consistency with the bus endianness.
1aa292bb
DM		 2770 */
2771 if (ctx->base.header_size > 0)
73864012 2772 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
1aa292bb 2773 if (ctx->base.header_size > 4)
73864012 2774 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
1aa292bb 2775 if (ctx->base.header_size > 8)
73864012 2776 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
1aa292bb
DM		 2777 ctx->header_length += ctx->base.header_size;
2778}
2779
a186b4a6
JW		 2780static int handle_ir_packet_per_buffer(struct context *context,
2781 struct descriptor *d,
2782 struct descriptor *last)
2783{
2784 struct iso_context *ctx =
2785 container_of(context, struct iso_context, context);
bcee893c 2786 struct descriptor *pd;
a572e688 2787 u32 buffer_dma;
a186b4a6 2788
872e330e 2789 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2790 if (pd->transfer_status)
2791 break;
bcee893c 2792 if (pd > last)
a186b4a6
JW		 2793 /* Descriptor(s) not done yet, stop iteration */
2794 return 0;
2795
a572e688
CL		 2796 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2797 d++;
2798 buffer_dma = le32_to_cpu(d->data_address);
2799 dma_sync_single_range_for_cpu(context->ohci->card.device,
2800 buffer_dma & PAGE_MASK,
2801 buffer_dma & ~PAGE_MASK,
2802 le16_to_cpu(d->req_count),
2803 DMA_FROM_DEVICE);
2804 }
2805
910e76c6 2806 copy_iso_headers(ctx, (u32 *) (last + 1));
a186b4a6 2807
910e76c6
CL		 2808 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2809 flush_iso_completions(ctx);
a186b4a6 2810
a186b4a6
JW		 2811 return 1;
2812}
2813
872e330e
SR		 2814/* d == last because each descriptor block is only a single descriptor. */
2815static int handle_ir_buffer_fill(struct context *context,
2816 struct descriptor *d,
2817 struct descriptor *last)
2818{
2819 struct iso_context *ctx =
2820 container_of(context, struct iso_context, context);
d1bbd209 2821 unsigned int req_count, res_count, completed;
a572e688 2822 u32 buffer_dma;
872e330e 2823
d1bbd209
CL		 2824 req_count = le16_to_cpu(last->req_count);
2825 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2826 completed = req_count - res_count;
2827 buffer_dma = le32_to_cpu(last->data_address);
2828
2829 if (completed > 0) {
2830 ctx->mc_buffer_bus = buffer_dma;
2831 ctx->mc_completed = completed;
2832 }
2833
2834 if (res_count != 0)
872e330e
SR		 2835 /* Descriptor(s) not done yet, stop iteration */
2836 return 0;
2837
a572e688
CL		 2838 dma_sync_single_range_for_cpu(context->ohci->card.device,
2839 buffer_dma & PAGE_MASK,
2840 buffer_dma & ~PAGE_MASK,
d1bbd209 2841 completed, DMA_FROM_DEVICE);
a572e688 2842
d1bbd209 2843 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
872e330e 2844 ctx->base.callback.mc(&ctx->base,
d1bbd209 2845 buffer_dma + completed,
872e330e 2846 ctx->base.callback_data);
d1bbd209
CL		 2847 ctx->mc_completed = 0;
2848 }
872e330e
SR		 2849
2850 return 1;
2851}
2852
d1bbd209
CL		 2853static void flush_ir_buffer_fill(struct iso_context *ctx)
2854{
2855 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2856 ctx->mc_buffer_bus & PAGE_MASK,
2857 ctx->mc_buffer_bus & ~PAGE_MASK,
2858 ctx->mc_completed, DMA_FROM_DEVICE);
2859
2860 ctx->base.callback.mc(&ctx->base,
2861 ctx->mc_buffer_bus + ctx->mc_completed,
2862 ctx->base.callback_data);
2863 ctx->mc_completed = 0;
2864}
2865
a572e688
CL		 2866static inline void sync_it_packet_for_cpu(struct context *context,
2867 struct descriptor *pd)
2868{
2869 __le16 control;
2870 u32 buffer_dma;
2871
2872 /* only packets beginning with OUTPUT_MORE* have data buffers */
2873 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2874 return;
2875
2876 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2877 pd += 2;
2878
2879 /*
2880 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2881 * data buffer is in the context program's coherent page and must not
2882 * be synced.
2883 */
2884 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2885 (context->current_bus & PAGE_MASK)) {
2886 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2887 return;
2888 pd++;
2889 }
2890
2891 do {
2892 buffer_dma = le32_to_cpu(pd->data_address);
2893 dma_sync_single_range_for_cpu(context->ohci->card.device,
2894 buffer_dma & PAGE_MASK,
2895 buffer_dma & ~PAGE_MASK,
2896 le16_to_cpu(pd->req_count),
2897 DMA_TO_DEVICE);
2898 control = pd->control;
2899 pd++;
2900 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2901}
2902
30200739
KH		 2903static int handle_it_packet(struct context *context,
2904 struct descriptor *d,
2905 struct descriptor *last)
ed568912 2906{
30200739
KH		 2907 struct iso_context *ctx =
2908 container_of(context, struct iso_context, context);
31769cef 2909 struct descriptor *pd;
73864012 2910 __be32 *ctx_hdr;
373b2edd 2911
31769cef
JF		 2912 for (pd = d; pd <= last; pd++)
2913 if (pd->transfer_status)
2914 break;
2915 if (pd > last)
2916 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2917 return 0;
2918
a572e688
CL		 2919 sync_it_packet_for_cpu(context, d);
2920
0699a73a
CL		 2921 if (ctx->header_length + 4 > PAGE_SIZE) {
2922 if (ctx->base.drop_overflow_headers)
2923 return 1;
18d62711 2924 flush_iso_completions(ctx);
0699a73a 2925 }
910e76c6 2926
18d62711 2927 ctx_hdr = ctx->header + ctx->header_length;
910e76c6 2928 ctx->last_timestamp = le16_to_cpu(last->res_count);
18d62711
CL		 2929 /* Present this value as big-endian to match the receive code */
2930 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2931 le16_to_cpu(pd->res_count));
2932 ctx->header_length += 4;
2933
910e76c6
CL		 2934 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2935 flush_iso_completions(ctx);
2936
30200739 2937 return 1;
ed568912
KH		 2938}
2939
872e330e
SR		 2940static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2941{
2942 u32 hi = channels >> 32, lo = channels;
2943
2944 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2945 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2946 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2947 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2948 mmiowb();
2949 ohci->mc_channels = channels;
2950}
2951
53dca511 2952static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2953 int type, int channel, size_t header_size)
ed568912
KH		 2954{
2955 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2956 struct iso_context *uninitialized_var(ctx);
2957 descriptor_callback_t uninitialized_var(callback);
2958 u64 *uninitialized_var(channels);
2959 u32 *uninitialized_var(mask), uninitialized_var(regs);
872e330e 2960 int index, ret = -EBUSY;
ed568912 2961
8a8c4736 2962 spin_lock_irq(&ohci->lock);
ed568912 2963
872e330e
SR		 2964 switch (type) {
2965 case FW_ISO_CONTEXT_TRANSMIT:
2966 mask = &ohci->it_context_mask;
30200739 2967 callback = handle_it_packet;
872e330e
SR		 2968 index = ffs(*mask) - 1;
2969 if (index >= 0) {
2970 *mask &= ~(1 << index);
2971 regs = OHCI1394_IsoXmitContextBase(index);
2972 ctx = &ohci->it_context_list[index];
2973 }
2974 break;
2975
2976 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2977 channels = &ohci->ir_context_channels;
872e330e 2978 mask = &ohci->ir_context_mask;
6498ba04 2979 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2980 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2981 if (index >= 0) {
2982 *channels &= ~(1ULL << channel);
2983 *mask &= ~(1 << index);
2984 regs = OHCI1394_IsoRcvContextBase(index);
2985 ctx = &ohci->ir_context_list[index];
2986 }
2987 break;
ed568912 2988
872e330e
SR		 2989 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2990 mask = &ohci->ir_context_mask;
2991 callback = handle_ir_buffer_fill;
2992 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2993 if (index >= 0) {
2994 ohci->mc_allocated = true;
2995 *mask &= ~(1 << index);
2996 regs = OHCI1394_IsoRcvContextBase(index);
2997 ctx = &ohci->ir_context_list[index];
2998 }
2999 break;
3000
3001 default:
3002 index = -1;
3003 ret = -ENOSYS;
4817ed24 3004 }
872e330e 3005
8a8c4736 3006 spin_unlock_irq(&ohci->lock);
ed568912
KH		 3007
3008 if (index < 0)
872e330e 3009 return ERR_PTR(ret);
373b2edd 3010
2d826cc5 3011 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 3012 ctx->header_length = 0;
3013 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 3014 if (ctx->header == NULL) {
3015 ret = -ENOMEM;
9b32d5f3 3016 goto out;
872e330e 3017 }
2dbd7d7e
SR		 3018 ret = context_init(&ctx->context, ohci, regs, callback);
3019 if (ret < 0)
9b32d5f3 3020 goto out_with_header;
ed568912 3021
d1bbd209 3022 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
872e330e 3023 set_multichannel_mask(ohci, 0);
d1bbd209
CL		 3024 ctx->mc_completed = 0;
3025 }
872e330e 3026
ed568912 3027 return &ctx->base;
9b32d5f3
KH		 3028
3029 out_with_header:
3030 free_page((unsigned long)ctx->header);
3031 out:
8a8c4736 3032 spin_lock_irq(&ohci->lock);
872e330e
SR		 3033
3034 switch (type) {
3035 case FW_ISO_CONTEXT_RECEIVE:
3036 *channels |= 1ULL << channel;
3037 break;
3038
3039 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3040 ohci->mc_allocated = false;
3041 break;
3042 }
9b32d5f3 3043 *mask |= 1 << index;
872e330e 3044
8a8c4736 3045 spin_unlock_irq(&ohci->lock);
9b32d5f3 3046
2dbd7d7e 3047 return ERR_PTR(ret);
ed568912
KH		 3048}
3049
eb0306ea
KH		 3050static int ohci_start_iso(struct fw_iso_context *base,
3051 s32 cycle, u32 sync, u32 tags)
ed568912 3052{
373b2edd 3053 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 3054 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 3055 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 3056 int index;
3057
44b74d90
CL		 3058 /* the controller cannot start without any queued packets */
3059 if (ctx->context.last->branch_address == 0)
3060 return -ENODATA;
3061
872e330e
SR		 3062 switch (ctx->base.type) {
3063 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 3064 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 3065 match = 0;
3066 if (cycle >= 0)
3067 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 3068 (cycle & 0x7fff) << 16;
21efb3cf 3069
295e3feb
KH		 3070 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3071 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 3072 context_run(&ctx->context, match);
872e330e
SR		 3073 break;
3074
3075 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3076 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3077 /* fall through */
3078 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 3079 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 3080 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3081 if (cycle >= 0) {
3082 match |= (cycle & 0x07fff) << 12;
3083 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3084 }
ed568912 3085
295e3feb
KH		 3086 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3087 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 3088 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 3089 context_run(&ctx->context, control);
dd23736e
ML		 3090
3091 ctx->sync = sync;
3092 ctx->tags = tags;
3093
872e330e 3094 break;
295e3feb 3095 }
ed568912
KH		 3096
3097 return 0;
3098}
3099
b8295668
KH		 3100static int ohci_stop_iso(struct fw_iso_context *base)
3101{
3102 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3103 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 3104 int index;
3105
872e330e
SR		 3106 switch (ctx->base.type) {
3107 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 3108 index = ctx - ohci->it_context_list;
3109 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 3110 break;
3111
3112 case FW_ISO_CONTEXT_RECEIVE:
3113 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 3114 index = ctx - ohci->ir_context_list;
3115 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 3116 break;
b8295668
KH		 3117 }
3118 flush_writes(ohci);
3119 context_stop(&ctx->context);
e81cbebd 3120 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 3121
3122 return 0;
3123}
3124
ed568912
KH		 3125static void ohci_free_iso_context(struct fw_iso_context *base)
3126{
3127 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3128 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 3129 unsigned long flags;
3130 int index;
3131
b8295668
KH		 3132 ohci_stop_iso(base);
3133 context_release(&ctx->context);
9b32d5f3 3134 free_page((unsigned long)ctx->header);
b8295668 3135
ed568912
KH		 3136 spin_lock_irqsave(&ohci->lock, flags);
3137
872e330e
SR		 3138 switch (base->type) {
3139 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 3140 index = ctx - ohci->it_context_list;
ed568912 3141 ohci->it_context_mask |= 1 << index;
872e330e
SR		 3142 break;
3143
3144 case FW_ISO_CONTEXT_RECEIVE:
ed568912 3145 index = ctx - ohci->ir_context_list;
ed568912 3146 ohci->ir_context_mask |= 1 << index;
4817ed24 3147 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 3148 break;
3149
3150 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3151 index = ctx - ohci->ir_context_list;
3152 ohci->ir_context_mask |= 1 << index;
3153 ohci->ir_context_channels |= ohci->mc_channels;
3154 ohci->mc_channels = 0;
3155 ohci->mc_allocated = false;
3156 break;
ed568912 3157 }
ed568912
KH		 3158
3159 spin_unlock_irqrestore(&ohci->lock, flags);
3160}
3161
872e330e
SR		 3162static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3163{
3164 struct fw_ohci *ohci = fw_ohci(base->card);
3165 unsigned long flags;
3166 int ret;
3167
3168 switch (base->type) {
3169 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3170
3171 spin_lock_irqsave(&ohci->lock, flags);
3172
3173 /* Don't allow multichannel to grab other contexts' channels. */
3174 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3175 *channels = ohci->ir_context_channels;
3176 ret = -EBUSY;
3177 } else {
3178 set_multichannel_mask(ohci, *channels);
3179 ret = 0;
3180 }
3181
3182 spin_unlock_irqrestore(&ohci->lock, flags);
3183
3184 break;
3185 default:
3186 ret = -EINVAL;
3187 }
3188
3189 return ret;
3190}
3191
dd23736e
ML		 3192#ifdef CONFIG_PM
3193static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3194{
3195 int i;
3196 struct iso_context *ctx;
3197
3198 for (i = 0 ; i < ohci->n_ir ; i++) {
3199 ctx = &ohci->ir_context_list[i];
693a50b5 3200 if (ctx->context.running)
dd23736e
ML		 3201 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3202 }
3203
3204 for (i = 0 ; i < ohci->n_it ; i++) {
3205 ctx = &ohci->it_context_list[i];
693a50b5 3206 if (ctx->context.running)
dd23736e
ML		 3207 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3208 }
3209}
3210#endif
3211
872e330e
SR		 3212static int queue_iso_transmit(struct iso_context *ctx,
3213 struct fw_iso_packet *packet,
3214 struct fw_iso_buffer *buffer,
3215 unsigned long payload)
ed568912 3216{
30200739 3217 struct descriptor *d, *last, *pd;
ed568912
KH		 3218 struct fw_iso_packet *p;
3219 __le32 *header;
9aad8125 3220 dma_addr_t d_bus, page_bus;
ed568912
KH		 3221 u32 z, header_z, payload_z, irq;
3222 u32 payload_index, payload_end_index, next_page_index;
30200739 3223 int page, end_page, i, length, offset;
ed568912 3224
ed568912 3225 p = packet;
9aad8125 3226 payload_index = payload;
ed568912
KH		 3227
3228 if (p->skip)
3229 z = 1;
3230 else
3231 z = 2;
3232 if (p->header_length > 0)
3233 z++;
3234
3235 /* Determine the first page the payload isn't contained in. */
3236 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3237 if (p->payload_length > 0)
3238 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3239 else
3240 payload_z = 0;
3241
3242 z += payload_z;
3243
3244 /* Get header size in number of descriptors. */
2d826cc5 3245 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 3246
30200739
KH		 3247 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3248 if (d == NULL)
3249 return -ENOMEM;
ed568912
KH		 3250
3251 if (!p->skip) {
a77754a7 3252 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 3253 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 3254 /*
3255 * Link the skip address to this descriptor itself. This causes
3256 * a context to skip a cycle whenever lost cycles or FIFO
3257 * overruns occur, without dropping the data. The application
3258 * should then decide whether this is an error condition or not.
3259 * FIXME: Make the context's cycle-lost behaviour configurable?
3260 */
3261 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 3262
3263 header = (__le32 *) &d[1];
a77754a7
KH		 3264 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3265 IT_HEADER_TAG(p->tag) |
3266 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3267 IT_HEADER_CHANNEL(ctx->base.channel) |
3268 IT_HEADER_SPEED(ctx->base.speed));
ed568912 3269 header[1] =
a77754a7 3270 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 3271 p->payload_length));
3272 }
3273
3274 if (p->header_length > 0) {
3275 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 3276 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 3277 memcpy(&d[z], p->header, p->header_length);
3278 }
3279
3280 pd = d + z - payload_z;
3281 payload_end_index = payload_index + p->payload_length;
3282 for (i = 0; i < payload_z; i++) {
3283 page = payload_index >> PAGE_SHIFT;
3284 offset = payload_index & ~PAGE_MASK;
3285 next_page_index = (page + 1) << PAGE_SHIFT;
3286 length =
3287 min(next_page_index, payload_end_index) - payload_index;
3288 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 3289
3290 page_bus = page_private(buffer->pages[page]);
3291 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912 3292
a572e688
CL		 3293 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3294 page_bus, offset, length,
3295 DMA_TO_DEVICE);
3296
ed568912
KH		 3297 payload_index += length;
3298 }
3299
ed568912 3300 if (p->interrupt)
a77754a7 3301 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 3302 else
a77754a7 3303 irq = DESCRIPTOR_NO_IRQ;
ed568912 3304
30200739 3305 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 3306 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3307 DESCRIPTOR_STATUS |
3308 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 3309 irq);
ed568912 3310
30200739 3311 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 3312
3313 return 0;
3314}
373b2edd 3315
872e330e
SR		 3316static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3317 struct fw_iso_packet *packet,
3318 struct fw_iso_buffer *buffer,
3319 unsigned long payload)
a186b4a6 3320{
a572e688 3321 struct device *device = ctx->context.ohci->card.device;
8c0c0cc2 3322 struct descriptor *d, *pd;
a186b4a6
JW		 3323 dma_addr_t d_bus, page_bus;
3324 u32 z, header_z, rest;
bcee893c
DM		 3325 int i, j, length;
3326 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 3327
3328 /*
1aa292bb
DM		 3329 * The OHCI controller puts the isochronous header and trailer in the
3330 * buffer, so we need at least 8 bytes.
a186b4a6 3331 */
872e330e 3332 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 3333 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 3334
3335 /* Get header size in number of descriptors. */
3336 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3337 page = payload >> PAGE_SHIFT;
3338 offset = payload & ~PAGE_MASK;
872e330e 3339 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 3340
3341 for (i = 0; i < packet_count; i++) {
3342 /* d points to the header descriptor */
bcee893c 3343 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 3344 d = context_get_descriptors(&ctx->context,
bcee893c 3345 z + header_z, &d_bus);
a186b4a6
JW		 3346 if (d == NULL)
3347 return -ENOMEM;
3348
bcee893c
DM		 3349 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3350 DESCRIPTOR_INPUT_MORE);
872e330e 3351 if (packet->skip && i == 0)
bcee893c 3352 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3353 d->req_count = cpu_to_le16(header_size);
3354 d->res_count = d->req_count;
bcee893c 3355 d->transfer_status = 0;
a186b4a6
JW		 3356 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3357
bcee893c 3358 rest = payload_per_buffer;
8c0c0cc2 3359 pd = d;
bcee893c 3360 for (j = 1; j < z; j++) {
8c0c0cc2 3361 pd++;
bcee893c
DM		 3362 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3363 DESCRIPTOR_INPUT_MORE);
3364
3365 if (offset + rest < PAGE_SIZE)
3366 length = rest;
3367 else
3368 length = PAGE_SIZE - offset;
3369 pd->req_count = cpu_to_le16(length);
3370 pd->res_count = pd->req_count;
3371 pd->transfer_status = 0;
3372
3373 page_bus = page_private(buffer->pages[page]);
3374 pd->data_address = cpu_to_le32(page_bus + offset);
3375
a572e688
CL		 3376 dma_sync_single_range_for_device(device, page_bus,
3377 offset, length,
3378 DMA_FROM_DEVICE);
3379
bcee893c
DM		 3380 offset = (offset + length) & ~PAGE_MASK;
3381 rest -= length;
3382 if (offset == 0)
3383 page++;
3384 }
a186b4a6
JW		 3385 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3386 DESCRIPTOR_INPUT_LAST |
3387 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3388 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3389 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3390
a186b4a6
JW		 3391 context_append(&ctx->context, d, z, header_z);
3392 }
3393
3394 return 0;
3395}
3396
872e330e
SR		 3397static int queue_iso_buffer_fill(struct iso_context *ctx,
3398 struct fw_iso_packet *packet,
3399 struct fw_iso_buffer *buffer,
3400 unsigned long payload)
3401{
3402 struct descriptor *d;
3403 dma_addr_t d_bus, page_bus;
3404 int page, offset, rest, z, i, length;
3405
3406 page = payload >> PAGE_SHIFT;
3407 offset = payload & ~PAGE_MASK;
3408 rest = packet->payload_length;
3409
3410 /* We need one descriptor for each page in the buffer. */
3411 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3412
3413 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3414 return -EFAULT;
3415
3416 for (i = 0; i < z; i++) {
3417 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3418 if (d == NULL)
3419 return -ENOMEM;
3420
3421 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3422 DESCRIPTOR_BRANCH_ALWAYS);
3423 if (packet->skip && i == 0)
3424 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3425 if (packet->interrupt && i == z - 1)
3426 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3427
3428 if (offset + rest < PAGE_SIZE)
3429 length = rest;
3430 else
3431 length = PAGE_SIZE - offset;
3432 d->req_count = cpu_to_le16(length);
3433 d->res_count = d->req_count;
3434 d->transfer_status = 0;
3435
3436 page_bus = page_private(buffer->pages[page]);
3437 d->data_address = cpu_to_le32(page_bus + offset);
3438
a572e688
CL		 3439 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3440 page_bus, offset, length,
3441 DMA_FROM_DEVICE);
3442
872e330e
SR		 3443 rest -= length;
3444 offset = 0;
3445 page++;
3446
3447 context_append(&ctx->context, d, 1, 0);
3448 }
3449
3450 return 0;
3451}
3452
53dca511
SR		 3453static int ohci_queue_iso(struct fw_iso_context *base,
3454 struct fw_iso_packet *packet,
3455 struct fw_iso_buffer *buffer,
3456 unsigned long payload)
295e3feb 3457{
e364cf4e 3458 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3459 unsigned long flags;
872e330e 3460 int ret = -ENOSYS;
e364cf4e 3461
fe5ca634 3462 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3463 switch (base->type) {
3464 case FW_ISO_CONTEXT_TRANSMIT:
3465 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3466 break;
3467 case FW_ISO_CONTEXT_RECEIVE:
3468 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3469 break;
3470 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3471 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3472 break;
3473 }
fe5ca634
DM		 3474 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3475
2dbd7d7e 3476 return ret;
295e3feb
KH		 3477}
3478
13882a82
CL		 3479static void ohci_flush_queue_iso(struct fw_iso_context *base)
3480{
3481 struct context *ctx =
3482 &container_of(base, struct iso_context, base)->context;
3483
3484 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
13882a82
CL		 3485}
3486
d1bbd209
CL		 3487static int ohci_flush_iso_completions(struct fw_iso_context *base)
3488{
3489 struct iso_context *ctx = container_of(base, struct iso_context, base);
3490 int ret = 0;
3491
3492 tasklet_disable(&ctx->context.tasklet);
3493
3494 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3495 context_tasklet((unsigned long)&ctx->context);
3496
3497 switch (base->type) {
3498 case FW_ISO_CONTEXT_TRANSMIT:
3499 case FW_ISO_CONTEXT_RECEIVE:
3500 if (ctx->header_length != 0)
3501 flush_iso_completions(ctx);
3502 break;
3503 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3504 if (ctx->mc_completed != 0)
3505 flush_ir_buffer_fill(ctx);
3506 break;
3507 default:
3508 ret = -ENOSYS;
3509 }
3510
3511 clear_bit_unlock(0, &ctx->flushing_completions);
3512 smp_mb__after_clear_bit();
3513 }
3514
3515 tasklet_enable(&ctx->context.tasklet);
3516
3517 return ret;
3518}
3519
21ebcd12 3520static const struct fw_card_driver ohci_driver = {
ed568912 3521 .enable = ohci_enable,
02d37bed 3522 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3523 .update_phy_reg = ohci_update_phy_reg,
3524 .set_config_rom = ohci_set_config_rom,
3525 .send_request = ohci_send_request,
3526 .send_response = ohci_send_response,
730c32f5 3527 .cancel_packet = ohci_cancel_packet,
ed568912 3528 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3529 .read_csr = ohci_read_csr,
3530 .write_csr = ohci_write_csr,
ed568912
KH		 3531
3532 .allocate_iso_context = ohci_allocate_iso_context,
3533 .free_iso_context = ohci_free_iso_context,
872e330e 3534 .set_iso_channels = ohci_set_iso_channels,
ed568912 3535 .queue_iso = ohci_queue_iso,
13882a82 3536 .flush_queue_iso = ohci_flush_queue_iso,
d1bbd209 3537 .flush_iso_completions = ohci_flush_iso_completions,
69cdb726 3538 .start_iso = ohci_start_iso,
b8295668 3539 .stop_iso = ohci_stop_iso,
ed568912
KH		 3540};
3541
ea8d006b 3542#ifdef CONFIG_PPC_PMAC
5da3dac8 3543static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3544{
ea8d006b
SR		 3545 if (machine_is(powermac)) {
3546 struct device_node *ofn = pci_device_to_OF_node(dev);
3547
3548 if (ofn) {
3549 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3550 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3551 }
3552 }
2ed0f181
SR		 3553}
3554
5da3dac8 3555static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3556{
3557 if (machine_is(powermac)) {
3558 struct device_node *ofn = pci_device_to_OF_node(dev);
3559
3560 if (ofn) {
3561 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3562 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3563 }
3564 }
3565}
3566#else
5da3dac8
SR		 3567static inline void pmac_ohci_on(struct pci_dev *dev) {}
3568static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3569#endif /* CONFIG_PPC_PMAC */
3570
03f94c0f 3571static int pci_probe(struct pci_dev *dev,
53dca511 3572 const struct pci_device_id *ent)
2ed0f181
SR		 3573{
3574 struct fw_ohci *ohci;
aa0170ff 3575 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3576 u64 guid;
dd23736e 3577 int i, err;
2ed0f181
SR		 3578 size_t size;
3579
7f7e3711
SR		 3580 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3581 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3582 return -ENOSYS;
3583 }
3584
2d826cc5 3585 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3586 if (ohci == NULL) {
7007a076
SR		 3587 err = -ENOMEM;
3588 goto fail;
ed568912
KH		 3589 }
3590
3591 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3592
5da3dac8 3593 pmac_ohci_on(dev);
130d5496 3594
d79406dd
KH		 3595 err = pci_enable_device(dev);
3596 if (err) {
64d21720 3597 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
bd7dee63 3598 goto fail_free;
ed568912
KH		 3599 }
3600
3601 pci_set_master(dev);
3602 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3603 pci_set_drvdata(dev, ohci);
3604
3605 spin_lock_init(&ohci->lock);
02d37bed 3606 mutex_init(&ohci->phy_reg_mutex);
ed568912 3607
2d7a36e2 3608 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
ed568912 3609
7baab9ac
CL		 3610 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3611 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
de97cb64 3612 ohci_err(ohci, "invalid MMIO resource\n");
7baab9ac
CL		 3613 err = -ENXIO;
3614 goto fail_disable;
3615 }
3616
d79406dd
KH		 3617 err = pci_request_region(dev, 0, ohci_driver_name);
3618 if (err) {
de97cb64 3619 ohci_err(ohci, "MMIO resource unavailable\n");
d79406dd 3620 goto fail_disable;
ed568912
KH		 3621 }
3622
3623 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3624 if (ohci->registers == NULL) {
de97cb64 3625 ohci_err(ohci, "failed to remap registers\n");
d79406dd
KH		 3626 err = -ENXIO;
3627 goto fail_iomem;
ed568912
KH		 3628 }
3629
4a635593 3630 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3631 if ((ohci_quirks[i].vendor == dev->vendor) &&
3632 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3633 ohci_quirks[i].device == dev->device) &&
3634 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3635 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3636 ohci->quirks = ohci_quirks[i].flags;
3637 break;
3638 }
3e9cc2f3
SR		 3639 if (param_quirks)
3640 ohci->quirks = param_quirks;
b677532b 3641
ec766a79
CL		 3642 /*
3643 * Because dma_alloc_coherent() allocates at least one page,
3644 * we save space by using a common buffer for the AR request/
3645 * response descriptors and the self IDs buffer.
3646 */
3647 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3648 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3649 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3650 PAGE_SIZE,
3651 &ohci->misc_buffer_bus,
3652 GFP_KERNEL);
3653 if (!ohci->misc_buffer) {
3654 err = -ENOMEM;
3655 goto fail_iounmap;
3656 }
3657
3658 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3659 OHCI1394_AsReqRcvContextControlSet);
3660 if (err < 0)
ec766a79 3661 goto fail_misc_buf;
ed568912 3662
ec766a79 3663 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3664 OHCI1394_AsRspRcvContextControlSet);
3665 if (err < 0)
3666 goto fail_arreq_ctx;
ed568912 3667
c088ab30
CL		 3668 err = context_init(&ohci->at_request_ctx, ohci,
3669 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3670 if (err < 0)
3671 goto fail_arrsp_ctx;
ed568912 3672
c088ab30
CL		 3673 err = context_init(&ohci->at_response_ctx, ohci,
3674 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3675 if (err < 0)
3676 goto fail_atreq_ctx;
ed568912 3677
ed568912 3678 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3679 ohci->ir_context_channels = ~0ULL;
f117a3e3 3680 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3681 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3682 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3683 ohci->n_ir = hweight32(ohci->ir_context_mask);
3684 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3685 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3686
3687 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3688 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3689 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3690 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3691 ohci->n_it = hweight32(ohci->it_context_mask);
3692 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3693 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3694
3695 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3696 err = -ENOMEM;
7007a076 3697 goto fail_contexts;
ed568912
KH		 3698 }
3699
af53122a 3700 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
ec766a79 3701 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3702
ed568912
KH		 3703 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3704 max_receive = (bus_options >> 12) & 0xf;
3705 link_speed = bus_options & 0x7;
3706 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3707 reg_read(ohci, OHCI1394_GUIDLo);
3708
247fd50b
PH		 3709 if (!(ohci->quirks & QUIRK_NO_MSI))
3710 pci_enable_msi(dev);
3711 if (request_irq(dev->irq, irq_handler,
3712 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3713 ohci_driver_name, ohci)) {
de97cb64 3714 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
247fd50b
PH		 3715 err = -EIO;
3716 goto fail_msi;
3717 }
3718
d79406dd 3719 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3720 if (err)
247fd50b 3721 goto fail_irq;
ed568912 3722
6fdb2ee2 3723 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
de97cb64
PH		 3724 ohci_notice(ohci,
3725 "added OHCI v%x.%x device as card %d, "
3726 "%d IR + %d IT contexts, quirks 0x%x\n",
3727 version >> 16, version & 0xff, ohci->card.index,
3728 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3729
ed568912 3730 return 0;
d79406dd 3731
247fd50b
PH		 3732 fail_irq:
3733 free_irq(dev->irq, ohci);
3734 fail_msi:
3735 pci_disable_msi(dev);
7007a076 3736 fail_contexts:
d79406dd 3737 kfree(ohci->ir_context_list);
7007a076
SR		 3738 kfree(ohci->it_context_list);
3739 context_release(&ohci->at_response_ctx);
c088ab30 3740 fail_atreq_ctx:
7007a076 3741 context_release(&ohci->at_request_ctx);
c088ab30 3742 fail_arrsp_ctx:
7007a076 3743 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3744 fail_arreq_ctx:
7007a076 3745 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3746 fail_misc_buf:
3747 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3748 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3749 fail_iounmap:
d79406dd
KH		 3750 pci_iounmap(dev, ohci->registers);
3751 fail_iomem:
3752 pci_release_region(dev, 0);
3753 fail_disable:
3754 pci_disable_device(dev);
bd7dee63 3755 fail_free:
d838d2c0 3756 kfree(ohci);
5da3dac8 3757 pmac_ohci_off(dev);
7007a076 3758 fail:
d79406dd 3759 return err;
ed568912
KH		 3760}
3761
3762static void pci_remove(struct pci_dev *dev)
3763{
8db49149 3764 struct fw_ohci *ohci = pci_get_drvdata(dev);
ed568912 3765
8db49149
PH		 3766 /*
3767 * If the removal is happening from the suspend state, LPS won't be
3768 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3769 */
3770 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3771 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3772 flush_writes(ohci);
3773 }
2d7a36e2 3774 cancel_work_sync(&ohci->bus_reset_work);
ed568912
KH		 3775 fw_core_remove_card(&ohci->card);
3776
c781c06d
KH		 3777 /*
3778 * FIXME: Fail all pending packets here, now that the upper
3779 * layers can't queue any more.
3780 */
ed568912
KH		 3781
3782 software_reset(ohci);
3783 free_irq(dev->irq, ohci);
a55709ba
JF		 3784
3785 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3786 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3787 ohci->next_config_rom, ohci->next_config_rom_bus);
3788 if (ohci->config_rom)
3789 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3790 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3791 ar_context_release(&ohci->ar_request_ctx);
3792 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3793 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3794 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3795 context_release(&ohci->at_request_ctx);
3796 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3797 kfree(ohci->it_context_list);
3798 kfree(ohci->ir_context_list);
262444ee 3799 pci_disable_msi(dev);
d79406dd
KH		 3800 pci_iounmap(dev, ohci->registers);
3801 pci_release_region(dev, 0);
3802 pci_disable_device(dev);
d838d2c0 3803 kfree(ohci);
5da3dac8 3804 pmac_ohci_off(dev);
ea8d006b 3805
64d21720 3806 dev_notice(&dev->dev, "removed fw-ohci device\n");
ed568912
KH		 3807}
3808
2aef469a 3809#ifdef CONFIG_PM
2ed0f181 3810static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3811{
2ed0f181 3812 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3813 int err;
3814
3815 software_reset(ohci);
2ed0f181 3816 err = pci_save_state(dev);
2aef469a 3817 if (err) {
de97cb64 3818 ohci_err(ohci, "pci_save_state failed\n");
2aef469a
KH		 3819 return err;
3820 }
2ed0f181 3821 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428 3822 if (err)
de97cb64 3823 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
5da3dac8 3824 pmac_ohci_off(dev);
ea8d006b 3825
2aef469a
KH		 3826 return 0;
3827}
3828
2ed0f181 3829static int pci_resume(struct pci_dev *dev)
2aef469a 3830{
2ed0f181 3831 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3832 int err;
3833
5da3dac8 3834 pmac_ohci_on(dev);
2ed0f181
SR		 3835 pci_set_power_state(dev, PCI_D0);
3836 pci_restore_state(dev);
3837 err = pci_enable_device(dev);
2aef469a 3838 if (err) {
de97cb64 3839 ohci_err(ohci, "pci_enable_device failed\n");
2aef469a
KH		 3840 return err;
3841 }
3842
8662b6b0
ML		 3843 /* Some systems don't setup GUID register on resume from ram */
3844 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3845 !reg_read(ohci, OHCI1394_GUIDHi)) {
3846 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3847 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3848 }
3849
dd23736e 3850 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3851 if (err)
3852 return err;
3853
3854 ohci_resume_iso_dma(ohci);
693a50b5 3855
dd23736e 3856 return 0;
2aef469a
KH		 3857}
3858#endif
3859
a67483d2 3860static const struct pci_device_id pci_table[] = {
ed568912
KH		 3861 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3862 { }
3863};
3864
3865MODULE_DEVICE_TABLE(pci, pci_table);
3866
3867static struct pci_driver fw_ohci_pci_driver = {
3868 .name = ohci_driver_name,
3869 .id_table = pci_table,
3870 .probe = pci_probe,
3871 .remove = pci_remove,
2aef469a
KH		 3872#ifdef CONFIG_PM
3873 .resume = pci_resume,
3874 .suspend = pci_suspend,
3875#endif
ed568912
KH		 3876};
3877
7a723c6e
SG		 3878static int __init fw_ohci_init(void)
3879{
db9ae8fe
SG		 3880 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3881 if (!selfid_workqueue)
3882 return -ENOMEM;
3883
7a723c6e
SG		 3884 return pci_register_driver(&fw_ohci_pci_driver);
3885}
3886
3887static void __exit fw_ohci_cleanup(void)
3888{
3889 pci_unregister_driver(&fw_ohci_pci_driver);
db9ae8fe 3890 destroy_workqueue(selfid_workqueue);
7a723c6e
SG		 3891}
3892
3893module_init(fw_ohci_init);
3894module_exit(fw_ohci_cleanup);
fe2af11c 3895
ed568912
KH		 3896MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3897MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3898MODULE_LICENSE("GPL");
3899
1e4c7b0d 3900/* Provide a module alias so root-on-sbp2 initrds don't break. */
1e4c7b0d 3901MODULE_ALIAS("ohci1394");
Linux kernel - Deliverables
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