projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
firewire: tone down some diagnostic log messages
[deliverable/linux.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
2d7a36e2 45#include <linux/workqueue.h>
cf3e72fd 46
e8ca9702 47#include <asm/byteorder.h>
c26f0234 48#include <asm/page.h>
ee71c2f9 49#include <asm/system.h>
ed568912 50
ea8d006b
SR		 51#ifdef CONFIG_PPC_PMAC
52#include <asm/pmac_feature.h>
53#endif
54
77c9a5da
SR		 55#include "core.h"
56#include "ohci.h"
ed568912 57
a77754a7
KH		 58#define DESCRIPTOR_OUTPUT_MORE 0
59#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
60#define DESCRIPTOR_INPUT_MORE (2 << 12)
61#define DESCRIPTOR_INPUT_LAST (3 << 12)
62#define DESCRIPTOR_STATUS (1 << 11)
63#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
64#define DESCRIPTOR_PING (1 << 7)
65#define DESCRIPTOR_YY (1 << 6)
66#define DESCRIPTOR_NO_IRQ (0 << 4)
67#define DESCRIPTOR_IRQ_ERROR (1 << 4)
68#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
69#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
70#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 71
72struct descriptor {
73 __le16 req_count;
74 __le16 control;
75 __le32 data_address;
76 __le32 branch_address;
77 __le16 res_count;
78 __le16 transfer_status;
79} __attribute__((aligned(16)));
80
a77754a7
KH		 81#define CONTROL_SET(regs) (regs)
82#define CONTROL_CLEAR(regs) ((regs) + 4)
83#define COMMAND_PTR(regs) ((regs) + 12)
84#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 85
7a39d8b8
CL		 86#define AR_BUFFER_SIZE (32*1024)
87#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
88/* we need at least two pages for proper list management */
89#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
90
91#define MAX_ASYNC_PAYLOAD 4096
92#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
93#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 94
32b46093
KH		 95struct ar_context {
96 struct fw_ohci *ohci;
7a39d8b8
CL		 97 struct page *pages[AR_BUFFERS];
98 void *buffer;
99 struct descriptor *descriptors;
100 dma_addr_t descriptors_bus;
32b46093 101 void *pointer;
7a39d8b8 102 unsigned int last_buffer_index;
72e318e0 103 u32 regs;
ed568912
KH		 104 struct tasklet_struct tasklet;
105};
106
30200739
KH		 107struct context;
108
109typedef int (*descriptor_callback_t)(struct context *ctx,
110 struct descriptor *d,
111 struct descriptor *last);
fe5ca634
DM		 112
113/*
114 * A buffer that contains a block of DMA-able coherent memory used for
115 * storing a portion of a DMA descriptor program.
116 */
117struct descriptor_buffer {
118 struct list_head list;
119 dma_addr_t buffer_bus;
120 size_t buffer_size;
121 size_t used;
122 struct descriptor buffer[0];
123};
124
30200739 125struct context {
373b2edd 126 struct fw_ohci *ohci;
30200739 127 u32 regs;
fe5ca634 128 int total_allocation;
a572e688 129 u32 current_bus;
386a4153 130 bool running;
82b662dc 131 bool flushing;
373b2edd 132
fe5ca634
DM		 133 /*
134 * List of page-sized buffers for storing DMA descriptors.
135 * Head of list contains buffers in use and tail of list contains
136 * free buffers.
137 */
138 struct list_head buffer_list;
139
140 /*
141 * Pointer to a buffer inside buffer_list that contains the tail
142 * end of the current DMA program.
143 */
144 struct descriptor_buffer *buffer_tail;
145
146 /*
147 * The descriptor containing the branch address of the first
148 * descriptor that has not yet been filled by the device.
149 */
150 struct descriptor *last;
151
152 /*
153 * The last descriptor in the DMA program. It contains the branch
154 * address that must be updated upon appending a new descriptor.
155 */
156 struct descriptor *prev;
30200739
KH		 157
158 descriptor_callback_t callback;
159
373b2edd 160 struct tasklet_struct tasklet;
30200739 161};
30200739 162
a77754a7
KH		 163#define IT_HEADER_SY(v) ((v) << 0)
164#define IT_HEADER_TCODE(v) ((v) << 4)
165#define IT_HEADER_CHANNEL(v) ((v) << 8)
166#define IT_HEADER_TAG(v) ((v) << 14)
167#define IT_HEADER_SPEED(v) ((v) << 16)
168#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 169
170struct iso_context {
171 struct fw_iso_context base;
30200739 172 struct context context;
0642b657 173 int excess_bytes;
9b32d5f3
KH		 174 void *header;
175 size_t header_length;
dd23736e
ML		 176
177 u8 sync;
178 u8 tags;
ed568912
KH		 179};
180
181#define CONFIG_ROM_SIZE 1024
182
183struct fw_ohci {
184 struct fw_card card;
185
186 __iomem char *registers;
e636fe25 187 int node_id;
ed568912 188 int generation;
e09770db 189 int request_generation; /* for timestamping incoming requests */
4a635593 190 unsigned quirks;
a1a1132b 191 unsigned int pri_req_max;
a48777e0 192 u32 bus_time;
4ffb7a6a 193 bool is_root;
c8a94ded 194 bool csr_state_setclear_abdicate;
dd23736e
ML		 195 int n_ir;
196 int n_it;
c781c06d
KH		 197 /*
198 * Spinlock for accessing fw_ohci data. Never call out of
199 * this driver with this lock held.
200 */
ed568912 201 spinlock_t lock;
ed568912 202
02d37bed
SR		 203 struct mutex phy_reg_mutex;
204
ec766a79
CL		 205 void *misc_buffer;
206 dma_addr_t misc_buffer_bus;
207
ed568912
KH		 208 struct ar_context ar_request_ctx;
209 struct ar_context ar_response_ctx;
f319b6a0
KH		 210 struct context at_request_ctx;
211 struct context at_response_ctx;
ed568912 212
f117a3e3 213 u32 it_context_support;
872e330e 214 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 215 struct iso_context *it_context_list;
872e330e 216 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 217 u32 ir_context_support;
872e330e 218 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 219 struct iso_context *ir_context_list;
872e330e
SR		 220 u64 mc_channels; /* channels in use by the multichannel IR context */
221 bool mc_allocated;
ecb1cf9c
SR		 222
223 __be32 *config_rom;
224 dma_addr_t config_rom_bus;
225 __be32 *next_config_rom;
226 dma_addr_t next_config_rom_bus;
227 __be32 next_header;
228
229 __le32 *self_id_cpu;
230 dma_addr_t self_id_bus;
2d7a36e2 231 struct work_struct bus_reset_work;
ecb1cf9c
SR		 232
233 u32 self_id_buffer[512];
ed568912
KH		 234};
235
95688e97 236static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 237{
238 return container_of(card, struct fw_ohci, card);
239}
240
295e3feb
KH		 241#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
242#define IR_CONTEXT_BUFFER_FILL 0x80000000
243#define IR_CONTEXT_ISOCH_HEADER 0x40000000
244#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
245#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
246#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 247
248#define CONTEXT_RUN 0x8000
249#define CONTEXT_WAKE 0x1000
250#define CONTEXT_DEAD 0x0800
251#define CONTEXT_ACTIVE 0x0400
252
8b7b6afa 253#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 254#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
255#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
256
ed568912 257#define OHCI1394_REGISTER_SIZE 0x800
ed568912
KH		 258#define OHCI1394_PCI_HCI_Control 0x40
259#define SELF_ID_BUF_SIZE 0x800
32b46093 260#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 261#define OHCI_VERSION_1_1 0x010010
0edeefd9 262
ed568912
KH		 263static char ohci_driver_name[] = KBUILD_MODNAME;
264
9993e0fe 265#define PCI_DEVICE_ID_AGERE_FW643 0x5901
262444ee 266#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b 267#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
25935ebe
SG		 268#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
269#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
7f7e3711 270#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
8301b91b 271
4a635593
SR		 272#define QUIRK_CYCLE_TIMER 1
273#define QUIRK_RESET_PACKET 2
274#define QUIRK_BE_HEADERS 4
925e7a65 275#define QUIRK_NO_1394A 8
262444ee 276#define QUIRK_NO_MSI 16
25935ebe 277#define QUIRK_TI_SLLZ059 32
4a635593
SR		 278
279/* In case of multiple matches in ohci_quirks[], only the first one is used. */
280static const struct {
9993e0fe 281 unsigned short vendor, device, revision, flags;
4a635593 282} ohci_quirks[] = {
9993e0fe
SR		 283 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
284 QUIRK_CYCLE_TIMER},
285
286 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
287 QUIRK_BE_HEADERS},
288
289 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
290 QUIRK_NO_MSI},
291
292 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
293 QUIRK_NO_MSI},
294
295 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
296 QUIRK_CYCLE_TIMER},
297
f39aa30d
ML		 298 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
299 QUIRK_NO_MSI},
300
9993e0fe
SR		 301 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
302 QUIRK_CYCLE_TIMER},
303
304 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
305 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
306
25935ebe
SG		 307 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
308 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
309
310 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
311 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
312
9993e0fe
SR		 313 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
314 QUIRK_RESET_PACKET},
315
316 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
317 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 318};
319
3e9cc2f3
SR		 320/* This overrides anything that was found in ohci_quirks[]. */
321static int param_quirks;
322module_param_named(quirks, param_quirks, int, 0644);
323MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
324 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
325 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
326 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 327 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 328 ", disable MSI = " __stringify(QUIRK_NO_MSI)
28897fb7 329 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
3e9cc2f3
SR		 330 ")");
331
a007bb85 332#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 333#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 334#define OHCI_PARAM_DEBUG_IRQS 4
335#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8 336
5da3dac8
SR		 337#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
338
ad3c0fe8
SR		 339static int param_debug;
340module_param_named(debug, param_debug, int, 0644);
341MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 342 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 343 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
344 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
345 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 346 ", or a combination, or all = -1)");
347
64d21720 348static void log_irqs(struct fw_ohci *ohci, u32 evt)
ad3c0fe8 349{
a007bb85
SR		 350 if (likely(!(param_debug &
351 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
352 return;
353
354 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
355 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 356 return;
357
64d21720
SR		 358 dev_notice(ohci->card.device,
359 "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 360 evt & OHCI1394_selfIDComplete ? " selfID" : "",
361 evt & OHCI1394_RQPkt ? " AR_req" : "",
362 evt & OHCI1394_RSPkt ? " AR_resp" : "",
363 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
364 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
365 evt & OHCI1394_isochRx ? " IR" : "",
366 evt & OHCI1394_isochTx ? " IT" : "",
367 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
368 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 369 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 370 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 371 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 372 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 373 evt & OHCI1394_busReset ? " busReset" : "",
374 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
375 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
376 OHCI1394_respTxComplete | OHCI1394_isochRx |
377 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 378 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
379 OHCI1394_cycleInconsistent |
161b96e7 380 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 381 ? " ?" : "");
382}
383
384static const char *speed[] = {
385 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
386};
387static const char *power[] = {
388 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
389 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
390};
391static const char port[] = { '.', '-', 'p', 'c', };
392
393static char _p(u32 *s, int shift)
394{
395 return port[*s >> shift & 3];
396}
397
64d21720 398static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
ad3c0fe8 399{
64d21720
SR		 400 u32 *s;
401
ad3c0fe8
SR		 402 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
403 return;
404
64d21720
SR		 405 dev_notice(ohci->card.device,
406 "%d selfIDs, generation %d, local node ID %04x\n",
407 self_id_count, generation, ohci->node_id);
ad3c0fe8 408
64d21720 409 for (s = ohci->self_id_buffer; self_id_count--; ++s)
ad3c0fe8 410 if ((*s & 1 << 23) == 0)
64d21720
SR		 411 dev_notice(ohci->card.device,
412 "selfID 0: %08x, phy %d [%c%c%c] "
161b96e7
SR		 413 "%s gc=%d %s %s%s%s\n",
414 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
415 speed[*s >> 14 & 3], *s >> 16 & 63,
416 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
417 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 418 else
64d21720
SR		 419 dev_notice(ohci->card.device,
420 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
161b96e7
SR		 421 *s, *s >> 24 & 63,
422 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
423 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 424}
425
426static const char *evts[] = {
427 [0x00] = "evt_no_status", [0x01] = "-reserved-",
428 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
429 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
430 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
431 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
432 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
433 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
434 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
435 [0x10] = "-reserved-", [0x11] = "ack_complete",
436 [0x12] = "ack_pending ", [0x13] = "-reserved-",
437 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
438 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
439 [0x18] = "-reserved-", [0x19] = "-reserved-",
440 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
441 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
442 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
443 [0x20] = "pending/cancelled",
444};
445static const char *tcodes[] = {
446 [0x0] = "QW req", [0x1] = "BW req",
447 [0x2] = "W resp", [0x3] = "-reserved-",
448 [0x4] = "QR req", [0x5] = "BR req",
449 [0x6] = "QR resp", [0x7] = "BR resp",
450 [0x8] = "cycle start", [0x9] = "Lk req",
451 [0xa] = "async stream packet", [0xb] = "Lk resp",
452 [0xc] = "-reserved-", [0xd] = "-reserved-",
453 [0xe] = "link internal", [0xf] = "-reserved-",
454};
ad3c0fe8 455
64d21720
SR		 456static void log_ar_at_event(struct fw_ohci *ohci,
457 char dir, int speed, u32 *header, int evt)
ad3c0fe8
SR		 458{
459 int tcode = header[0] >> 4 & 0xf;
460 char specific[12];
461
462 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
463 return;
464
465 if (unlikely(evt >= ARRAY_SIZE(evts)))
466 evt = 0x1f;
467
08ddb2f4 468 if (evt == OHCI1394_evt_bus_reset) {
64d21720
SR		 469 dev_notice(ohci->card.device,
470 "A%c evt_bus_reset, generation %d\n",
471 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 472 return;
473 }
474
ad3c0fe8
SR		 475 switch (tcode) {
476 case 0x0: case 0x6: case 0x8:
477 snprintf(specific, sizeof(specific), " = %08x",
478 be32_to_cpu((__force __be32)header[3]));
479 break;
480 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
481 snprintf(specific, sizeof(specific), " %x,%x",
482 header[3] >> 16, header[3] & 0xffff);
483 break;
484 default:
485 specific[0] = '\0';
486 }
487
488 switch (tcode) {
5b06db16 489 case 0xa:
64d21720
SR		 490 dev_notice(ohci->card.device,
491 "A%c %s, %s\n",
492 dir, evts[evt], tcodes[tcode]);
ad3c0fe8 493 break;
5b06db16 494 case 0xe:
64d21720
SR		 495 dev_notice(ohci->card.device,
496 "A%c %s, PHY %08x %08x\n",
497 dir, evts[evt], header[1], header[2]);
5b06db16 498 break;
ad3c0fe8 499 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
64d21720
SR		 500 dev_notice(ohci->card.device,
501 "A%c spd %x tl %02x, "
502 "%04x -> %04x, %s, "
503 "%s, %04x%08x%s\n",
504 dir, speed, header[0] >> 10 & 0x3f,
505 header[1] >> 16, header[0] >> 16, evts[evt],
506 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 507 break;
508 default:
64d21720
SR		 509 dev_notice(ohci->card.device,
510 "A%c spd %x tl %02x, "
511 "%04x -> %04x, %s, "
512 "%s%s\n",
513 dir, speed, header[0] >> 10 & 0x3f,
514 header[1] >> 16, header[0] >> 16, evts[evt],
515 tcodes[tcode], specific);
ad3c0fe8
SR		 516 }
517}
518
519#else
520
5da3dac8 521#define param_debug 0
64d21720
SR		 522static inline void log_irqs(struct fw_ohci *ohci, u32 evt) {}
523static inline void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) {}
524static inline void log_ar_at_event(struct fw_ohci *ohci, char dir, int speed, u32 *header, int evt) {}
ad3c0fe8
SR		 525
526#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
527
95688e97 528static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 529{
530 writel(data, ohci->registers + offset);
531}
532
95688e97 533static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 534{
535 return readl(ohci->registers + offset);
536}
537
95688e97 538static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 539{
540 /* Do a dummy read to flush writes. */
541 reg_read(ohci, OHCI1394_Version);
542}
543
b14c369d
SR		 544/*
545 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
546 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
547 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
548 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
549 */
35d999b1 550static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 551{
4a96b4fc 552 u32 val;
35d999b1 553 int i;
ed568912
KH		 554
555 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 556 for (i = 0; i < 3 + 100; i++) {
35d999b1 557 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 558 if (!~val)
559 return -ENODEV; /* Card was ejected. */
560
35d999b1
SR		 561 if (val & OHCI1394_PhyControl_ReadDone)
562 return OHCI1394_PhyControl_ReadData(val);
563
153e3979
CL		 564 /*
565 * Try a few times without waiting. Sleeping is necessary
566 * only when the link/PHY interface is busy.
567 */
568 if (i >= 3)
569 msleep(1);
ed568912 570 }
64d21720 571 dev_err(ohci->card.device, "failed to read phy reg\n");
ed568912 572
35d999b1
SR		 573 return -EBUSY;
574}
4a96b4fc 575
35d999b1
SR		 576static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
577{
578 int i;
ed568912 579
ed568912 580 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 581 OHCI1394_PhyControl_Write(addr, val));
153e3979 582 for (i = 0; i < 3 + 100; i++) {
35d999b1 583 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 584 if (!~val)
585 return -ENODEV; /* Card was ejected. */
586
35d999b1
SR		 587 if (!(val & OHCI1394_PhyControl_WritePending))
588 return 0;
ed568912 589
153e3979
CL		 590 if (i >= 3)
591 msleep(1);
35d999b1 592 }
64d21720 593 dev_err(ohci->card.device, "failed to write phy reg\n");
35d999b1
SR		 594
595 return -EBUSY;
4a96b4fc
CL		 596}
597
02d37bed
SR		 598static int update_phy_reg(struct fw_ohci *ohci, int addr,
599 int clear_bits, int set_bits)
4a96b4fc 600{
02d37bed 601 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 602 if (ret < 0)
603 return ret;
4a96b4fc 604
e7014dad
CL		 605 /*
606 * The interrupt status bits are cleared by writing a one bit.
607 * Avoid clearing them unless explicitly requested in set_bits.
608 */
609 if (addr == 5)
610 clear_bits |= PHY_INT_STATUS_BITS;
611
35d999b1 612 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 613}
614
35d999b1 615static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 616{
35d999b1 617 int ret;
925e7a65 618
02d37bed 619 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 620 if (ret < 0)
621 return ret;
925e7a65 622
35d999b1 623 return read_phy_reg(ohci, addr);
ed568912
KH		 624}
625
02d37bed
SR		 626static int ohci_read_phy_reg(struct fw_card *card, int addr)
627{
628 struct fw_ohci *ohci = fw_ohci(card);
629 int ret;
630
631 mutex_lock(&ohci->phy_reg_mutex);
632 ret = read_phy_reg(ohci, addr);
633 mutex_unlock(&ohci->phy_reg_mutex);
634
635 return ret;
636}
637
638static int ohci_update_phy_reg(struct fw_card *card, int addr,
639 int clear_bits, int set_bits)
640{
641 struct fw_ohci *ohci = fw_ohci(card);
642 int ret;
643
644 mutex_lock(&ohci->phy_reg_mutex);
645 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
646 mutex_unlock(&ohci->phy_reg_mutex);
647
648 return ret;
ed568912
KH		 649}
650
7a39d8b8
CL		 651static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
652{
653 return page_private(ctx->pages[i]);
654}
655
656static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 657{
7a39d8b8 658 struct descriptor *d;
32b46093 659
7a39d8b8
CL		 660 d = &ctx->descriptors[index];
661 d->branch_address &= cpu_to_le32(~0xf);
662 d->res_count = cpu_to_le16(PAGE_SIZE);
663 d->transfer_status = 0;
32b46093 664
071595eb 665 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 666 d = &ctx->descriptors[ctx->last_buffer_index];
667 d->branch_address |= cpu_to_le32(1);
668
669 ctx->last_buffer_index = index;
32b46093 670
a77754a7 671 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
837596a6
CL		 672}
673
7a39d8b8 674static void ar_context_release(struct ar_context *ctx)
837596a6 675{
7a39d8b8 676 unsigned int i;
837596a6 677
7a39d8b8
CL		 678 if (ctx->buffer)
679 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 680
7a39d8b8
CL		 681 for (i = 0; i < AR_BUFFERS; i++)
682 if (ctx->pages[i]) {
683 dma_unmap_page(ctx->ohci->card.device,
684 ar_buffer_bus(ctx, i),
685 PAGE_SIZE, DMA_FROM_DEVICE);
686 __free_page(ctx->pages[i]);
687 }
ed568912
KH		 688}
689
7a39d8b8 690static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 691{
64d21720 692 struct fw_ohci *ohci = ctx->ohci;
a55709ba 693
64d21720
SR		 694 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
695 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
696 flush_writes(ohci);
697
698 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
699 error_msg);
a55709ba 700 }
7a39d8b8
CL		 701 /* FIXME: restart? */
702}
703
704static inline unsigned int ar_next_buffer_index(unsigned int index)
705{
706 return (index + 1) % AR_BUFFERS;
707}
708
709static inline unsigned int ar_prev_buffer_index(unsigned int index)
710{
711 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
712}
713
714static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
715{
716 return ar_next_buffer_index(ctx->last_buffer_index);
717}
718
719/*
720 * We search for the buffer that contains the last AR packet DMA data written
721 * by the controller.
722 */
723static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
724 unsigned int *buffer_offset)
725{
726 unsigned int i, next_i, last = ctx->last_buffer_index;
727 __le16 res_count, next_res_count;
728
729 i = ar_first_buffer_index(ctx);
730 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
731
732 /* A buffer that is not yet completely filled must be the last one. */
733 while (i != last && res_count == 0) {
734
735 /* Peek at the next descriptor. */
736 next_i = ar_next_buffer_index(i);
737 rmb(); /* read descriptors in order */
738 next_res_count = ACCESS_ONCE(
739 ctx->descriptors[next_i].res_count);
740 /*
741 * If the next descriptor is still empty, we must stop at this
742 * descriptor.
743 */
744 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
745 /*
746 * The exception is when the DMA data for one packet is
747 * split over three buffers; in this case, the middle
748 * buffer's descriptor might be never updated by the
749 * controller and look still empty, and we have to peek
750 * at the third one.
751 */
752 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
753 next_i = ar_next_buffer_index(next_i);
754 rmb();
755 next_res_count = ACCESS_ONCE(
756 ctx->descriptors[next_i].res_count);
757 if (next_res_count != cpu_to_le16(PAGE_SIZE))
758 goto next_buffer_is_active;
759 }
760
761 break;
762 }
763
764next_buffer_is_active:
765 i = next_i;
766 res_count = next_res_count;
767 }
768
769 rmb(); /* read res_count before the DMA data */
770
771 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
772 if (*buffer_offset > PAGE_SIZE) {
773 *buffer_offset = 0;
774 ar_context_abort(ctx, "corrupted descriptor");
775 }
776
777 return i;
778}
779
780static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
781 unsigned int end_buffer_index,
782 unsigned int end_buffer_offset)
783{
784 unsigned int i;
785
786 i = ar_first_buffer_index(ctx);
787 while (i != end_buffer_index) {
788 dma_sync_single_for_cpu(ctx->ohci->card.device,
789 ar_buffer_bus(ctx, i),
790 PAGE_SIZE, DMA_FROM_DEVICE);
791 i = ar_next_buffer_index(i);
792 }
793 if (end_buffer_offset > 0)
794 dma_sync_single_for_cpu(ctx->ohci->card.device,
795 ar_buffer_bus(ctx, i),
796 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 797}
798
11bf20ad
SR		 799#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
800#define cond_le32_to_cpu(v) \
4a635593 801 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 802#else
803#define cond_le32_to_cpu(v) le32_to_cpu(v)
804#endif
805
32b46093 806static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 807{
ed568912 808 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 809 struct fw_packet p;
810 u32 status, length, tcode;
43286568 811 int evt;
2639a6fb 812
11bf20ad
SR		 813 p.header[0] = cond_le32_to_cpu(buffer[0]);
814 p.header[1] = cond_le32_to_cpu(buffer[1]);
815 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 816
817 tcode = (p.header[0] >> 4) & 0x0f;
818 switch (tcode) {
819 case TCODE_WRITE_QUADLET_REQUEST:
820 case TCODE_READ_QUADLET_RESPONSE:
32b46093 821 p.header[3] = (__force __u32) buffer[3];
2639a6fb 822 p.header_length = 16;
32b46093 823 p.payload_length = 0;
2639a6fb
KH		 824 break;
825
2639a6fb 826 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 827 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 828 p.header_length = 16;
829 p.payload_length = 0;
830 break;
831
832 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 833 case TCODE_READ_BLOCK_RESPONSE:
834 case TCODE_LOCK_REQUEST:
835 case TCODE_LOCK_RESPONSE:
11bf20ad 836 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 837 p.header_length = 16;
32b46093 838 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 839 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
840 ar_context_abort(ctx, "invalid packet length");
841 return NULL;
842 }
2639a6fb
KH		 843 break;
844
845 case TCODE_WRITE_RESPONSE:
846 case TCODE_READ_QUADLET_REQUEST:
32b46093 847 case OHCI_TCODE_PHY_PACKET:
2639a6fb 848 p.header_length = 12;
32b46093 849 p.payload_length = 0;
2639a6fb 850 break;
ccff9629
SR		 851
852 default:
7a39d8b8
CL		 853 ar_context_abort(ctx, "invalid tcode");
854 return NULL;
2639a6fb 855 }
ed568912 856
32b46093
KH		 857 p.payload = (void *) buffer + p.header_length;
858
859 /* FIXME: What to do about evt_* errors? */
860 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 861 status = cond_le32_to_cpu(buffer[length]);
43286568 862 evt = (status >> 16) & 0x1f;
32b46093 863
43286568 864 p.ack = evt - 16;
32b46093
KH		 865 p.speed = (status >> 21) & 0x7;
866 p.timestamp = status & 0xffff;
867 p.generation = ohci->request_generation;
ed568912 868
64d21720 869 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
ad3c0fe8 870
c781c06d 871 /*
a4dc090b
SR		 872 * Several controllers, notably from NEC and VIA, forget to
873 * write ack_complete status at PHY packet reception.
874 */
875 if (evt == OHCI1394_evt_no_status &&
876 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
877 p.ack = ACK_COMPLETE;
878
879 /*
880 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 881 * the new generation number when a bus reset happens (see
882 * section 8.4.2.3). This helps us determine when a request
883 * was received and make sure we send the response in the same
884 * generation. We only need this for requests; for responses
885 * we use the unique tlabel for finding the matching
c781c06d 886 * request.
d34316a4
SR		 887 *
888 * Alas some chips sometimes emit bus reset packets with a
889 * wrong generation. We set the correct generation for these
2d7a36e2 890 * at a slightly incorrect time (in bus_reset_work).
c781c06d 891 */
d34316a4 892 if (evt == OHCI1394_evt_bus_reset) {
4a635593 893 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 894 ohci->request_generation = (p.header[2] >> 16) & 0xff;
895 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 896 fw_core_handle_request(&ohci->card, &p);
d34316a4 897 } else {
2639a6fb 898 fw_core_handle_response(&ohci->card, &p);
d34316a4 899 }
ed568912 900
32b46093
KH		 901 return buffer + length + 1;
902}
ed568912 903
7a39d8b8
CL		 904static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
905{
906 void *next;
907
908 while (p < end) {
909 next = handle_ar_packet(ctx, p);
910 if (!next)
911 return p;
912 p = next;
913 }
914
915 return p;
916}
917
918static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
919{
920 unsigned int i;
921
922 i = ar_first_buffer_index(ctx);
923 while (i != end_buffer) {
924 dma_sync_single_for_device(ctx->ohci->card.device,
925 ar_buffer_bus(ctx, i),
926 PAGE_SIZE, DMA_FROM_DEVICE);
927 ar_context_link_page(ctx, i);
928 i = ar_next_buffer_index(i);
929 }
930}
931
32b46093
KH		 932static void ar_context_tasklet(unsigned long data)
933{
934 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 935 unsigned int end_buffer_index, end_buffer_offset;
936 void *p, *end;
32b46093 937
7a39d8b8
CL		 938 p = ctx->pointer;
939 if (!p)
940 return;
32b46093 941
7a39d8b8
CL		 942 end_buffer_index = ar_search_last_active_buffer(ctx,
943 &end_buffer_offset);
944 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
945 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 946
7a39d8b8 947 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 948 /*
7a39d8b8
CL		 949 * The filled part of the overall buffer wraps around; handle
950 * all packets up to the buffer end here. If the last packet
951 * wraps around, its tail will be visible after the buffer end
952 * because the buffer start pages are mapped there again.
c781c06d 953 */
7a39d8b8
CL		 954 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
955 p = handle_ar_packets(ctx, p, buffer_end);
956 if (p < buffer_end)
957 goto error;
958 /* adjust p to point back into the actual buffer */
959 p -= AR_BUFFERS * PAGE_SIZE;
960 }
32b46093 961
7a39d8b8
CL		 962 p = handle_ar_packets(ctx, p, end);
963 if (p != end) {
964 if (p > end)
965 ar_context_abort(ctx, "inconsistent descriptor");
966 goto error;
967 }
32b46093 968
7a39d8b8
CL		 969 ctx->pointer = p;
970 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 971
7a39d8b8 972 return;
a1f805e5 973
7a39d8b8
CL		 974error:
975 ctx->pointer = NULL;
ed568912
KH		 976}
977
ec766a79
CL		 978static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
979 unsigned int descriptors_offset, u32 regs)
ed568912 980{
7a39d8b8
CL		 981 unsigned int i;
982 dma_addr_t dma_addr;
983 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
984 struct descriptor *d;
ed568912 985
72e318e0
KH		 986 ctx->regs = regs;
987 ctx->ohci = ohci;
ed568912
KH		 988 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
989
7a39d8b8
CL		 990 for (i = 0; i < AR_BUFFERS; i++) {
991 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
992 if (!ctx->pages[i])
993 goto out_of_memory;
994 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
995 0, PAGE_SIZE, DMA_FROM_DEVICE);
996 if (dma_mapping_error(ohci->card.device, dma_addr)) {
997 __free_page(ctx->pages[i]);
998 ctx->pages[i] = NULL;
999 goto out_of_memory;
1000 }
1001 set_page_private(ctx->pages[i], dma_addr);
1002 }
1003
1004 for (i = 0; i < AR_BUFFERS; i++)
1005 pages[i] = ctx->pages[i];
1006 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1007 pages[AR_BUFFERS + i] = ctx->pages[i];
1008 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
14271304 1009 -1, PAGE_KERNEL);
7a39d8b8
CL		 1010 if (!ctx->buffer)
1011 goto out_of_memory;
1012
ec766a79
CL		 1013 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1014 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 1015
1016 for (i = 0; i < AR_BUFFERS; i++) {
1017 d = &ctx->descriptors[i];
1018 d->req_count = cpu_to_le16(PAGE_SIZE);
1019 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1020 DESCRIPTOR_STATUS |
1021 DESCRIPTOR_BRANCH_ALWAYS);
1022 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1023 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1024 ar_next_buffer_index(i) * sizeof(struct descriptor));
1025 }
32b46093 1026
2aef469a 1027 return 0;
7a39d8b8
CL		 1028
1029out_of_memory:
1030 ar_context_release(ctx);
1031
1032 return -ENOMEM;
2aef469a
KH		 1033}
1034
1035static void ar_context_run(struct ar_context *ctx)
1036{
7a39d8b8
CL		 1037 unsigned int i;
1038
1039 for (i = 0; i < AR_BUFFERS; i++)
1040 ar_context_link_page(ctx, i);
2aef469a 1041
7a39d8b8 1042 ctx->pointer = ctx->buffer;
2aef469a 1043
7a39d8b8 1044 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1045 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
ed568912 1046}
373b2edd 1047
53dca511 1048static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1049{
0ff8fbc6 1050 __le16 branch;
a186b4a6 1051
0ff8fbc6 1052 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1053
1054 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1055 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1056 return d;
1057 else
1058 return d + z - 1;
1059}
1060
30200739
KH		 1061static void context_tasklet(unsigned long data)
1062{
1063 struct context *ctx = (struct context *) data;
30200739
KH		 1064 struct descriptor *d, *last;
1065 u32 address;
1066 int z;
fe5ca634 1067 struct descriptor_buffer *desc;
30200739 1068
fe5ca634
DM		 1069 desc = list_entry(ctx->buffer_list.next,
1070 struct descriptor_buffer, list);
1071 last = ctx->last;
30200739 1072 while (last->branch_address != 0) {
fe5ca634 1073 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1074 address = le32_to_cpu(last->branch_address);
1075 z = address & 0xf;
fe5ca634 1076 address &= ~0xf;
a572e688 1077 ctx->current_bus = address;
fe5ca634
DM		 1078
1079 /* If the branch address points to a buffer outside of the
1080 * current buffer, advance to the next buffer. */
1081 if (address < desc->buffer_bus ||
1082 address >= desc->buffer_bus + desc->used)
1083 desc = list_entry(desc->list.next,
1084 struct descriptor_buffer, list);
1085 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1086 last = find_branch_descriptor(d, z);
30200739
KH		 1087
1088 if (!ctx->callback(ctx, d, last))
1089 break;
1090
fe5ca634
DM		 1091 if (old_desc != desc) {
1092 /* If we've advanced to the next buffer, move the
1093 * previous buffer to the free list. */
1094 unsigned long flags;
1095 old_desc->used = 0;
1096 spin_lock_irqsave(&ctx->ohci->lock, flags);
1097 list_move_tail(&old_desc->list, &ctx->buffer_list);
1098 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1099 }
1100 ctx->last = last;
30200739
KH		 1101 }
1102}
1103
fe5ca634
DM		 1104/*
1105 * Allocate a new buffer and add it to the list of free buffers for this
1106 * context. Must be called with ohci->lock held.
1107 */
53dca511 1108static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1109{
1110 struct descriptor_buffer *desc;
f5101d58 1111 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1112 int offset;
1113
1114 /*
1115 * 16MB of descriptors should be far more than enough for any DMA
1116 * program. This will catch run-away userspace or DoS attacks.
1117 */
1118 if (ctx->total_allocation >= 16*1024*1024)
1119 return -ENOMEM;
1120
1121 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1122 &bus_addr, GFP_ATOMIC);
1123 if (!desc)
1124 return -ENOMEM;
1125
1126 offset = (void *)&desc->buffer - (void *)desc;
1127 desc->buffer_size = PAGE_SIZE - offset;
1128 desc->buffer_bus = bus_addr + offset;
1129 desc->used = 0;
1130
1131 list_add_tail(&desc->list, &ctx->buffer_list);
1132 ctx->total_allocation += PAGE_SIZE;
1133
1134 return 0;
1135}
1136
53dca511
SR		 1137static int context_init(struct context *ctx, struct fw_ohci *ohci,
1138 u32 regs, descriptor_callback_t callback)
30200739
KH		 1139{
1140 ctx->ohci = ohci;
1141 ctx->regs = regs;
fe5ca634
DM		 1142 ctx->total_allocation = 0;
1143
1144 INIT_LIST_HEAD(&ctx->buffer_list);
1145 if (context_add_buffer(ctx) < 0)
30200739
KH		 1146 return -ENOMEM;
1147
fe5ca634
DM		 1148 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1149 struct descriptor_buffer, list);
1150
30200739
KH		 1151 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1152 ctx->callback = callback;
1153
c781c06d
KH		 1154 /*
1155 * We put a dummy descriptor in the buffer that has a NULL
30200739 1156 * branch address and looks like it's been sent. That way we
fe5ca634 1157 * have a descriptor to append DMA programs to.
c781c06d 1158 */
fe5ca634
DM		 1159 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1160 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1161 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1162 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1163 ctx->last = ctx->buffer_tail->buffer;
1164 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1165
1166 return 0;
1167}
1168
53dca511 1169static void context_release(struct context *ctx)
30200739
KH		 1170{
1171 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1172 struct descriptor_buffer *desc, *tmp;
30200739 1173
fe5ca634
DM		 1174 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1175 dma_free_coherent(card->device, PAGE_SIZE, desc,
1176 desc->buffer_bus -
1177 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1178}
1179
fe5ca634 1180/* Must be called with ohci->lock held */
53dca511
SR		 1181static struct descriptor *context_get_descriptors(struct context *ctx,
1182 int z, dma_addr_t *d_bus)
30200739 1183{
fe5ca634
DM		 1184 struct descriptor *d = NULL;
1185 struct descriptor_buffer *desc = ctx->buffer_tail;
1186
1187 if (z * sizeof(*d) > desc->buffer_size)
1188 return NULL;
1189
1190 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1191 /* No room for the descriptor in this buffer, so advance to the
1192 * next one. */
30200739 1193
fe5ca634
DM		 1194 if (desc->list.next == &ctx->buffer_list) {
1195 /* If there is no free buffer next in the list,
1196 * allocate one. */
1197 if (context_add_buffer(ctx) < 0)
1198 return NULL;
1199 }
1200 desc = list_entry(desc->list.next,
1201 struct descriptor_buffer, list);
1202 ctx->buffer_tail = desc;
1203 }
30200739 1204
fe5ca634 1205 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1206 memset(d, 0, z * sizeof(*d));
fe5ca634 1207 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1208
1209 return d;
1210}
1211
295e3feb 1212static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1213{
1214 struct fw_ohci *ohci = ctx->ohci;
1215
a77754a7 1216 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1217 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1218 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1219 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1220 ctx->running = true;
30200739
KH		 1221 flush_writes(ohci);
1222}
1223
1224static void context_append(struct context *ctx,
1225 struct descriptor *d, int z, int extra)
1226{
1227 dma_addr_t d_bus;
fe5ca634 1228 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1229
fe5ca634 1230 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1231
fe5ca634 1232 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1233
1234 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1235 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1236 ctx->prev = find_branch_descriptor(d, z);
30200739
KH		 1237}
1238
1239static void context_stop(struct context *ctx)
1240{
64d21720 1241 struct fw_ohci *ohci = ctx->ohci;
30200739 1242 u32 reg;
b8295668 1243 int i;
30200739 1244
64d21720 1245 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1246 ctx->running = false;
30200739 1247
9ef28ccd 1248 for (i = 0; i < 1000; i++) {
64d21720 1249 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
b8295668 1250 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1251 return;
b8295668 1252
9ef28ccd
SR		 1253 if (i)
1254 udelay(10);
b8295668 1255 }
64d21720 1256 dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
30200739 1257}
ed568912 1258
f319b6a0 1259struct driver_data {
da28947e 1260 u8 inline_data[8];
f319b6a0
KH		 1261 struct fw_packet *packet;
1262};
ed568912 1263
c781c06d
KH		 1264/*
1265 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1266 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1267 * generation handling and locking around packet queue manipulation.
1268 */
53dca511
SR		 1269static int at_context_queue_packet(struct context *ctx,
1270 struct fw_packet *packet)
ed568912 1271{
ed568912 1272 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1273 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1274 struct driver_data *driver_data;
1275 struct descriptor *d, *last;
1276 __le32 *header;
ed568912
KH		 1277 int z, tcode;
1278
f319b6a0
KH		 1279 d = context_get_descriptors(ctx, 4, &d_bus);
1280 if (d == NULL) {
1281 packet->ack = RCODE_SEND_ERROR;
1282 return -1;
ed568912
KH		 1283 }
1284
a77754a7 1285 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1286 d[0].res_count = cpu_to_le16(packet->timestamp);
1287
c781c06d
KH		 1288 /*
1289 * The DMA format for asyncronous link packets is different
ed568912 1290 * from the IEEE1394 layout, so shift the fields around
5b06db16 1291 * accordingly.
c781c06d 1292 */
f319b6a0 1293
5b06db16 1294 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1295 header = (__le32 *) &d[1];
5b06db16
CL		 1296 switch (tcode) {
1297 case TCODE_WRITE_QUADLET_REQUEST:
1298 case TCODE_WRITE_BLOCK_REQUEST:
1299 case TCODE_WRITE_RESPONSE:
1300 case TCODE_READ_QUADLET_REQUEST:
1301 case TCODE_READ_BLOCK_REQUEST:
1302 case TCODE_READ_QUADLET_RESPONSE:
1303 case TCODE_READ_BLOCK_RESPONSE:
1304 case TCODE_LOCK_REQUEST:
1305 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1306 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1307 (packet->speed << 16));
1308 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1309 (packet->header[0] & 0xffff0000));
1310 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1311
ed568912 1312 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1313 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1314 else
f319b6a0
KH		 1315 header[3] = (__force __le32) packet->header[3];
1316
1317 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1318 break;
1319
5b06db16 1320 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1321 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1322 (packet->speed << 16));
5b06db16
CL		 1323 header[1] = cpu_to_le32(packet->header[1]);
1324 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1325 d[0].req_count = cpu_to_le16(12);
cc550216 1326
5b06db16 1327 if (is_ping_packet(&packet->header[1]))
cc550216 1328 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1329 break;
1330
5b06db16 1331 case TCODE_STREAM_DATA:
f8c2287c
JF		 1332 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1333 (packet->speed << 16));
1334 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1335 d[0].req_count = cpu_to_le16(8);
1336 break;
1337
1338 default:
1339 /* BUG(); */
1340 packet->ack = RCODE_SEND_ERROR;
1341 return -1;
ed568912
KH		 1342 }
1343
da28947e 1344 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1345 driver_data = (struct driver_data *) &d[3];
1346 driver_data->packet = packet;
20d11673 1347 packet->driver_data = driver_data;
a186b4a6 1348
f319b6a0 1349 if (packet->payload_length > 0) {
da28947e
CL		 1350 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1351 payload_bus = dma_map_single(ohci->card.device,
1352 packet->payload,
1353 packet->payload_length,
1354 DMA_TO_DEVICE);
1355 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1356 packet->ack = RCODE_SEND_ERROR;
1357 return -1;
1358 }
1359 packet->payload_bus = payload_bus;
1360 packet->payload_mapped = true;
1361 } else {
1362 memcpy(driver_data->inline_data, packet->payload,
1363 packet->payload_length);
1364 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1365 }
1366
1367 d[2].req_count = cpu_to_le16(packet->payload_length);
1368 d[2].data_address = cpu_to_le32(payload_bus);
1369 last = &d[2];
1370 z = 3;
ed568912 1371 } else {
f319b6a0
KH		 1372 last = &d[0];
1373 z = 2;
ed568912 1374 }
ed568912 1375
a77754a7
KH		 1376 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1377 DESCRIPTOR_IRQ_ALWAYS |
1378 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1379
b6258fc1
SR		 1380 /* FIXME: Document how the locking works. */
1381 if (ohci->generation != packet->generation) {
19593ffd 1382 if (packet->payload_mapped)
ab88ca48
SR		 1383 dma_unmap_single(ohci->card.device, payload_bus,
1384 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1385 packet->ack = RCODE_GENERATION;
1386 return -1;
1387 }
1388
1389 context_append(ctx, d, z, 4 - z);
ed568912 1390
dd6254e5 1391 if (ctx->running)
13882a82 1392 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
dd6254e5 1393 else
f319b6a0
KH		 1394 context_run(ctx, 0);
1395
1396 return 0;
ed568912
KH		 1397}
1398
82b662dc
CL		 1399static void at_context_flush(struct context *ctx)
1400{
1401 tasklet_disable(&ctx->tasklet);
1402
1403 ctx->flushing = true;
1404 context_tasklet((unsigned long)ctx);
1405 ctx->flushing = false;
1406
1407 tasklet_enable(&ctx->tasklet);
1408}
1409
f319b6a0
KH		 1410static int handle_at_packet(struct context *context,
1411 struct descriptor *d,
1412 struct descriptor *last)
ed568912 1413{
f319b6a0 1414 struct driver_data *driver_data;
ed568912 1415 struct fw_packet *packet;
f319b6a0 1416 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1417 int evt;
1418
82b662dc 1419 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1420 /* This descriptor isn't done yet, stop iteration. */
1421 return 0;
ed568912 1422
f319b6a0
KH		 1423 driver_data = (struct driver_data *) &d[3];
1424 packet = driver_data->packet;
1425 if (packet == NULL)
1426 /* This packet was cancelled, just continue. */
1427 return 1;
730c32f5 1428
19593ffd 1429 if (packet->payload_mapped)
1d1dc5e8 1430 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1431 packet->payload_length, DMA_TO_DEVICE);
ed568912 1432
f319b6a0
KH		 1433 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1434 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1435
64d21720 1436 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
ad3c0fe8 1437
f319b6a0
KH		 1438 switch (evt) {
1439 case OHCI1394_evt_timeout:
1440 /* Async response transmit timed out. */
1441 packet->ack = RCODE_CANCELLED;
1442 break;
ed568912 1443
f319b6a0 1444 case OHCI1394_evt_flushed:
c781c06d
KH		 1445 /*
1446 * The packet was flushed should give same error as
1447 * when we try to use a stale generation count.
1448 */
f319b6a0
KH		 1449 packet->ack = RCODE_GENERATION;
1450 break;
ed568912 1451
f319b6a0 1452 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1453 if (context->flushing)
1454 packet->ack = RCODE_GENERATION;
1455 else {
1456 /*
1457 * Using a valid (current) generation count, but the
1458 * node is not on the bus or not sending acks.
1459 */
1460 packet->ack = RCODE_NO_ACK;
1461 }
f319b6a0 1462 break;
ed568912 1463
f319b6a0
KH		 1464 case ACK_COMPLETE + 0x10:
1465 case ACK_PENDING + 0x10:
1466 case ACK_BUSY_X + 0x10:
1467 case ACK_BUSY_A + 0x10:
1468 case ACK_BUSY_B + 0x10:
1469 case ACK_DATA_ERROR + 0x10:
1470 case ACK_TYPE_ERROR + 0x10:
1471 packet->ack = evt - 0x10;
1472 break;
ed568912 1473
82b662dc
CL		 1474 case OHCI1394_evt_no_status:
1475 if (context->flushing) {
1476 packet->ack = RCODE_GENERATION;
1477 break;
1478 }
1479 /* fall through */
1480
f319b6a0
KH		 1481 default:
1482 packet->ack = RCODE_SEND_ERROR;
1483 break;
1484 }
ed568912 1485
f319b6a0 1486 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1487
f319b6a0 1488 return 1;
ed568912
KH		 1489}
1490
a77754a7
KH		 1491#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1492#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1493#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1494#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1495#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1496
53dca511
SR		 1497static void handle_local_rom(struct fw_ohci *ohci,
1498 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1499{
1500 struct fw_packet response;
1501 int tcode, length, i;
1502
a77754a7 1503 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1504 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1505 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1506 else
1507 length = 4;
1508
1509 i = csr - CSR_CONFIG_ROM;
1510 if (i + length > CONFIG_ROM_SIZE) {
1511 fw_fill_response(&response, packet->header,
1512 RCODE_ADDRESS_ERROR, NULL, 0);
1513 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1514 fw_fill_response(&response, packet->header,
1515 RCODE_TYPE_ERROR, NULL, 0);
1516 } else {
1517 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1518 (void *) ohci->config_rom + i, length);
1519 }
1520
1521 fw_core_handle_response(&ohci->card, &response);
1522}
1523
53dca511
SR		 1524static void handle_local_lock(struct fw_ohci *ohci,
1525 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1526{
1527 struct fw_packet response;
e1393667 1528 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1529 __be32 *payload, lock_old;
1530 u32 lock_arg, lock_data;
1531
a77754a7
KH		 1532 tcode = HEADER_GET_TCODE(packet->header[0]);
1533 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1534 payload = packet->payload;
a77754a7 1535 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1536
1537 if (tcode == TCODE_LOCK_REQUEST &&
1538 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1539 lock_arg = be32_to_cpu(payload[0]);
1540 lock_data = be32_to_cpu(payload[1]);
1541 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1542 lock_arg = 0;
1543 lock_data = 0;
1544 } else {
1545 fw_fill_response(&response, packet->header,
1546 RCODE_TYPE_ERROR, NULL, 0);
1547 goto out;
1548 }
1549
1550 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1551 reg_write(ohci, OHCI1394_CSRData, lock_data);
1552 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1553 reg_write(ohci, OHCI1394_CSRControl, sel);
1554
e1393667
CL		 1555 for (try = 0; try < 20; try++)
1556 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1557 lock_old = cpu_to_be32(reg_read(ohci,
1558 OHCI1394_CSRData));
1559 fw_fill_response(&response, packet->header,
1560 RCODE_COMPLETE,
1561 &lock_old, sizeof(lock_old));
1562 goto out;
1563 }
1564
64d21720 1565 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
e1393667 1566 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1567
93c4cceb
KH		 1568 out:
1569 fw_core_handle_response(&ohci->card, &response);
1570}
1571
53dca511 1572static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1573{
2608203d 1574 u64 offset, csr;
93c4cceb 1575
473d28c7
KH		 1576 if (ctx == &ctx->ohci->at_request_ctx) {
1577 packet->ack = ACK_PENDING;
1578 packet->callback(packet, &ctx->ohci->card, packet->ack);
1579 }
93c4cceb
KH		 1580
1581 offset =
1582 ((unsigned long long)
a77754a7 1583 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1584 packet->header[2];
1585 csr = offset - CSR_REGISTER_BASE;
1586
1587 /* Handle config rom reads. */
1588 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1589 handle_local_rom(ctx->ohci, packet, csr);
1590 else switch (csr) {
1591 case CSR_BUS_MANAGER_ID:
1592 case CSR_BANDWIDTH_AVAILABLE:
1593 case CSR_CHANNELS_AVAILABLE_HI:
1594 case CSR_CHANNELS_AVAILABLE_LO:
1595 handle_local_lock(ctx->ohci, packet, csr);
1596 break;
1597 default:
1598 if (ctx == &ctx->ohci->at_request_ctx)
1599 fw_core_handle_request(&ctx->ohci->card, packet);
1600 else
1601 fw_core_handle_response(&ctx->ohci->card, packet);
1602 break;
1603 }
473d28c7
KH		 1604
1605 if (ctx == &ctx->ohci->at_response_ctx) {
1606 packet->ack = ACK_COMPLETE;
1607 packet->callback(packet, &ctx->ohci->card, packet->ack);
1608 }
93c4cceb 1609}
e636fe25 1610
53dca511 1611static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1612{
ed568912 1613 unsigned long flags;
2dbd7d7e 1614 int ret;
ed568912
KH		 1615
1616 spin_lock_irqsave(&ctx->ohci->lock, flags);
1617
a77754a7 1618 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1619 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1620 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1621 handle_local_request(ctx, packet);
1622 return;
e636fe25 1623 }
ed568912 1624
2dbd7d7e 1625 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1626 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1627
2dbd7d7e 1628 if (ret < 0)
f319b6a0 1629 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1630
ed568912
KH		 1631}
1632
f117a3e3
CL		 1633static void detect_dead_context(struct fw_ohci *ohci,
1634 const char *name, unsigned int regs)
1635{
1636 u32 ctl;
1637
1638 ctl = reg_read(ohci, CONTROL_SET(regs));
1639 if (ctl & CONTEXT_DEAD) {
1640#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
64d21720
SR		 1641 dev_err(ohci->card.device,
1642 "DMA context %s has stopped, error code: %s\n",
1643 name, evts[ctl & 0x1f]);
f117a3e3 1644#else
64d21720
SR		 1645 dev_err(ohci->card.device,
1646 "DMA context %s has stopped, error code: %#x\n",
1647 name, ctl & 0x1f);
f117a3e3
CL		 1648#endif
1649 }
1650}
1651
1652static void handle_dead_contexts(struct fw_ohci *ohci)
1653{
1654 unsigned int i;
1655 char name[8];
1656
1657 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1658 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1659 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1660 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1661 for (i = 0; i < 32; ++i) {
1662 if (!(ohci->it_context_support & (1 << i)))
1663 continue;
1664 sprintf(name, "IT%u", i);
1665 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1666 }
1667 for (i = 0; i < 32; ++i) {
1668 if (!(ohci->ir_context_support & (1 << i)))
1669 continue;
1670 sprintf(name, "IR%u", i);
1671 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1672 }
1673 /* TODO: maybe try to flush and restart the dead contexts */
1674}
1675
a48777e0
CL		 1676static u32 cycle_timer_ticks(u32 cycle_timer)
1677{
1678 u32 ticks;
1679
1680 ticks = cycle_timer & 0xfff;
1681 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1682 ticks += (3072 * 8000) * (cycle_timer >> 25);
1683
1684 return ticks;
1685}
1686
1687/*
1688 * Some controllers exhibit one or more of the following bugs when updating the
1689 * iso cycle timer register:
1690 * - When the lowest six bits are wrapping around to zero, a read that happens
1691 * at the same time will return garbage in the lowest ten bits.
1692 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1693 * not incremented for about 60 ns.
1694 * - Occasionally, the entire register reads zero.
1695 *
1696 * To catch these, we read the register three times and ensure that the
1697 * difference between each two consecutive reads is approximately the same, i.e.
1698 * less than twice the other. Furthermore, any negative difference indicates an
1699 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1700 * execute, so we have enough precision to compute the ratio of the differences.)
1701 */
1702static u32 get_cycle_time(struct fw_ohci *ohci)
1703{
1704 u32 c0, c1, c2;
1705 u32 t0, t1, t2;
1706 s32 diff01, diff12;
1707 int i;
1708
1709 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1710
1711 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1712 i = 0;
1713 c1 = c2;
1714 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1715 do {
1716 c0 = c1;
1717 c1 = c2;
1718 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1719 t0 = cycle_timer_ticks(c0);
1720 t1 = cycle_timer_ticks(c1);
1721 t2 = cycle_timer_ticks(c2);
1722 diff01 = t1 - t0;
1723 diff12 = t2 - t1;
1724 } while ((diff01 <= 0 || diff12 <= 0 ||
1725 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1726 && i++ < 20);
1727 }
1728
1729 return c2;
1730}
1731
1732/*
1733 * This function has to be called at least every 64 seconds. The bus_time
1734 * field stores not only the upper 25 bits of the BUS_TIME register but also
1735 * the most significant bit of the cycle timer in bit 6 so that we can detect
1736 * changes in this bit.
1737 */
1738static u32 update_bus_time(struct fw_ohci *ohci)
1739{
1740 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1741
1742 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1743 ohci->bus_time += 0x40;
1744
1745 return ohci->bus_time | cycle_time_seconds;
1746}
1747
25935ebe
SG		 1748static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1749{
1750 int reg;
1751
1752 mutex_lock(&ohci->phy_reg_mutex);
1753 reg = write_phy_reg(ohci, 7, port_index);
28897fb7
SR		 1754 if (reg >= 0)
1755 reg = read_phy_reg(ohci, 8);
25935ebe
SG		 1756 mutex_unlock(&ohci->phy_reg_mutex);
1757 if (reg < 0)
1758 return reg;
1759
1760 switch (reg & 0x0f) {
1761 case 0x06:
1762 return 2; /* is child node (connected to parent node) */
1763 case 0x0e:
1764 return 3; /* is parent node (connected to child node) */
1765 }
1766 return 1; /* not connected */
1767}
1768
1769static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1770 int self_id_count)
1771{
1772 int i;
1773 u32 entry;
28897fb7 1774
25935ebe
SG		 1775 for (i = 0; i < self_id_count; i++) {
1776 entry = ohci->self_id_buffer[i];
1777 if ((self_id & 0xff000000) == (entry & 0xff000000))
1778 return -1;
1779 if ((self_id & 0xff000000) < (entry & 0xff000000))
1780 return i;
1781 }
1782 return i;
1783}
1784
1785/*
28897fb7
SR		 1786 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1787 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1788 * Construct the selfID from phy register contents.
1789 * FIXME: How to determine the selfID.i flag?
25935ebe 1790 */
25935ebe
SG		 1791static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1792{
28897fb7
SR		 1793 int reg, i, pos, status;
1794 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1795 u32 self_id = 0x8040c800;
25935ebe
SG		 1796
1797 reg = reg_read(ohci, OHCI1394_NodeID);
1798 if (!(reg & OHCI1394_NodeID_idValid)) {
64d21720
SR		 1799 dev_notice(ohci->card.device,
1800 "node ID not valid, new bus reset in progress\n");
25935ebe
SG		 1801 return -EBUSY;
1802 }
1803 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1804
28897fb7 1805 reg = ohci_read_phy_reg(&ohci->card, 4);
25935ebe
SG		 1806 if (reg < 0)
1807 return reg;
1808 self_id |= ((reg & 0x07) << 8); /* power class */
1809
28897fb7 1810 reg = ohci_read_phy_reg(&ohci->card, 1);
25935ebe
SG		 1811 if (reg < 0)
1812 return reg;
1813 self_id |= ((reg & 0x3f) << 16); /* gap count */
1814
1815 for (i = 0; i < 3; i++) {
1816 status = get_status_for_port(ohci, i);
1817 if (status < 0)
1818 return status;
1819 self_id |= ((status & 0x3) << (6 - (i * 2)));
1820 }
1821
1822 pos = get_self_id_pos(ohci, self_id, self_id_count);
1823 if (pos >= 0) {
1824 memmove(&(ohci->self_id_buffer[pos+1]),
1825 &(ohci->self_id_buffer[pos]),
1826 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1827 ohci->self_id_buffer[pos] = self_id;
1828 self_id_count++;
1829 }
1830 return self_id_count;
1831}
1832
2d7a36e2 1833static void bus_reset_work(struct work_struct *work)
ed568912 1834{
2d7a36e2
SG		 1835 struct fw_ohci *ohci =
1836 container_of(work, struct fw_ohci, bus_reset_work);
e636fe25 1837 int self_id_count, i, j, reg;
ed568912
KH		 1838 int generation, new_generation;
1839 unsigned long flags;
4eaff7d6
SR		 1840 void *free_rom = NULL;
1841 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1842 bool is_new_root;
ed568912
KH		 1843
1844 reg = reg_read(ohci, OHCI1394_NodeID);
1845 if (!(reg & OHCI1394_NodeID_idValid)) {
64d21720
SR		 1846 dev_notice(ohci->card.device,
1847 "node ID not valid, new bus reset in progress\n");
ed568912
KH		 1848 return;
1849 }
02ff8f8e 1850 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
64d21720 1851 dev_notice(ohci->card.device, "malconfigured bus\n");
02ff8f8e
SR		 1852 return;
1853 }
1854 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1855 OHCI1394_NodeID_nodeNumber);
ed568912 1856
4ffb7a6a
CL		 1857 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1858 if (!(ohci->is_root && is_new_root))
1859 reg_write(ohci, OHCI1394_LinkControlSet,
1860 OHCI1394_LinkControl_cycleMaster);
1861 ohci->is_root = is_new_root;
1862
c8a9a498
SR		 1863 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1864 if (reg & OHCI1394_SelfIDCount_selfIDError) {
64d21720 1865 dev_notice(ohci->card.device, "inconsistent self IDs\n");
c8a9a498
SR		 1866 return;
1867 }
c781c06d
KH		 1868 /*
1869 * The count in the SelfIDCount register is the number of
ed568912
KH		 1870 * bytes in the self ID receive buffer. Since we also receive
1871 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1872 * bit extra to get the actual number of self IDs.
1873 */
928ec5f1 1874 self_id_count = (reg >> 3) & 0xff;
25935ebe
SG		 1875
1876 if (self_id_count > 252) {
64d21720 1877 dev_notice(ohci->card.device, "inconsistent self IDs\n");
016bf3df
SR		 1878 return;
1879 }
25935ebe 1880
11bf20ad 1881 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1882 rmb();
ed568912
KH		 1883
1884 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498 1885 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
32eaeae1
CL		 1886 /*
1887 * If the invalid data looks like a cycle start packet,
1888 * it's likely to be the result of the cycle master
1889 * having a wrong gap count. In this case, the self IDs
1890 * so far are valid and should be processed so that the
1891 * bus manager can then correct the gap count.
1892 */
1893 if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1894 == 0xffff008f) {
64d21720
SR		 1895 dev_notice(ohci->card.device,
1896 "ignoring spurious self IDs\n");
32eaeae1
CL		 1897 self_id_count = j;
1898 break;
1899 } else {
64d21720
SR		 1900 dev_notice(ohci->card.device,
1901 "inconsistent self IDs\n");
32eaeae1
CL		 1902 return;
1903 }
c8a9a498 1904 }
11bf20ad
SR		 1905 ohci->self_id_buffer[j] =
1906 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1907 }
25935ebe
SG		 1908
1909 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1910 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1911 if (self_id_count < 0) {
64d21720
SR		 1912 dev_notice(ohci->card.device,
1913 "could not construct local self ID\n");
25935ebe
SG		 1914 return;
1915 }
1916 }
1917
1918 if (self_id_count == 0) {
64d21720 1919 dev_notice(ohci->card.device, "inconsistent self IDs\n");
25935ebe
SG		 1920 return;
1921 }
ee71c2f9 1922 rmb();
ed568912 1923
c781c06d
KH		 1924 /*
1925 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1926 * problem we face is that a new bus reset can start while we
1927 * read out the self IDs from the DMA buffer. If this happens,
1928 * the DMA buffer will be overwritten with new self IDs and we
1929 * will read out inconsistent data. The OHCI specification
1930 * (section 11.2) recommends a technique similar to
1931 * linux/seqlock.h, where we remember the generation of the
1932 * self IDs in the buffer before reading them out and compare
1933 * it to the current generation after reading them out. If
1934 * the two generations match we know we have a consistent set
c781c06d
KH		 1935 * of self IDs.
1936 */
ed568912
KH		 1937
1938 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1939 if (new_generation != generation) {
64d21720
SR		 1940 dev_notice(ohci->card.device,
1941 "new bus reset, discarding self ids\n");
ed568912
KH		 1942 return;
1943 }
1944
1945 /* FIXME: Document how the locking works. */
1946 spin_lock_irqsave(&ohci->lock, flags);
1947
82b662dc 1948 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 1949 context_stop(&ohci->at_request_ctx);
1950 context_stop(&ohci->at_response_ctx);
82b662dc
CL		 1951
1952 spin_unlock_irqrestore(&ohci->lock, flags);
1953
78dec56d
SR		 1954 /*
1955 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1956 * packets in the AT queues and software needs to drain them.
1957 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1958 */
82b662dc
CL		 1959 at_context_flush(&ohci->at_request_ctx);
1960 at_context_flush(&ohci->at_response_ctx);
1961
1962 spin_lock_irqsave(&ohci->lock, flags);
1963
1964 ohci->generation = generation;
ed568912
KH		 1965 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1966
4a635593 1967 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1968 ohci->request_generation = generation;
1969
c781c06d
KH		 1970 /*
1971 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1972 * have to do it under the spinlock also. If a new config rom
1973 * was set up before this reset, the old one is now no longer
1974 * in use and we can free it. Update the config rom pointers
1975 * to point to the current config rom and clear the
88393161 1976 * next_config_rom pointer so a new update can take place.
c781c06d 1977 */
ed568912
KH		 1978
1979 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 1980 if (ohci->next_config_rom != ohci->config_rom) {
1981 free_rom = ohci->config_rom;
1982 free_rom_bus = ohci->config_rom_bus;
1983 }
ed568912
KH		 1984 ohci->config_rom = ohci->next_config_rom;
1985 ohci->config_rom_bus = ohci->next_config_rom_bus;
1986 ohci->next_config_rom = NULL;
1987
c781c06d
KH		 1988 /*
1989 * Restore config_rom image and manually update
ed568912
KH		 1990 * config_rom registers. Writing the header quadlet
1991 * will indicate that the config rom is ready, so we
c781c06d
KH		 1992 * do that last.
1993 */
ed568912
KH		 1994 reg_write(ohci, OHCI1394_BusOptions,
1995 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 1996 ohci->config_rom[0] = ohci->next_header;
1997 reg_write(ohci, OHCI1394_ConfigROMhdr,
1998 be32_to_cpu(ohci->next_header));
ed568912
KH		 1999 }
2000
080de8c2
SR		 2001#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2002 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2003 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2004#endif
2005
ed568912
KH		 2006 spin_unlock_irqrestore(&ohci->lock, flags);
2007
4eaff7d6
SR		 2008 if (free_rom)
2009 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2010 free_rom, free_rom_bus);
2011
64d21720 2012 log_selfids(ohci, generation, self_id_count);
ad3c0fe8 2013
e636fe25 2014 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 2015 self_id_count, ohci->self_id_buffer,
2016 ohci->csr_state_setclear_abdicate);
2017 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 2018}
2019
2020static irqreturn_t irq_handler(int irq, void *data)
2021{
2022 struct fw_ohci *ohci = data;
168cf9af 2023 u32 event, iso_event;
ed568912
KH		 2024 int i;
2025
2026 event = reg_read(ohci, OHCI1394_IntEventClear);
2027
a515958d 2028 if (!event || !~event)
ed568912
KH		 2029 return IRQ_NONE;
2030
8327b37b
CL		 2031 /*
2032 * busReset and postedWriteErr must not be cleared yet
2033 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2034 */
2035 reg_write(ohci, OHCI1394_IntEventClear,
2036 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
64d21720 2037 log_irqs(ohci, event);
ed568912
KH		 2038
2039 if (event & OHCI1394_selfIDComplete)
2d7a36e2 2040 queue_work(fw_workqueue, &ohci->bus_reset_work);
ed568912
KH		 2041
2042 if (event & OHCI1394_RQPkt)
2043 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2044
2045 if (event & OHCI1394_RSPkt)
2046 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2047
2048 if (event & OHCI1394_reqTxComplete)
2049 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2050
2051 if (event & OHCI1394_respTxComplete)
2052 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2053
2dd5bed5
CL		 2054 if (event & OHCI1394_isochRx) {
2055 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2056 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2057
2058 while (iso_event) {
2059 i = ffs(iso_event) - 1;
2060 tasklet_schedule(
2061 &ohci->ir_context_list[i].context.tasklet);
2062 iso_event &= ~(1 << i);
2063 }
ed568912
KH		 2064 }
2065
2dd5bed5
CL		 2066 if (event & OHCI1394_isochTx) {
2067 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2068 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 2069
2dd5bed5
CL		 2070 while (iso_event) {
2071 i = ffs(iso_event) - 1;
2072 tasklet_schedule(
2073 &ohci->it_context_list[i].context.tasklet);
2074 iso_event &= ~(1 << i);
2075 }
ed568912
KH		 2076 }
2077
75f7832e 2078 if (unlikely(event & OHCI1394_regAccessFail))
98466cc4 2079 dev_err(ohci->card.device, "register access failure\n");
75f7832e 2080
8327b37b
CL		 2081 if (unlikely(event & OHCI1394_postedWriteErr)) {
2082 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2083 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2084 reg_write(ohci, OHCI1394_IntEventClear,
2085 OHCI1394_postedWriteErr);
a74477db 2086 if (printk_ratelimit())
64d21720 2087 dev_err(ohci->card.device, "PCI posted write error\n");
8327b37b 2088 }
e524f616 2089
bb9f2206
SR		 2090 if (unlikely(event & OHCI1394_cycleTooLong)) {
2091 if (printk_ratelimit())
64d21720
SR		 2092 dev_notice(ohci->card.device,
2093 "isochronous cycle too long\n");
bb9f2206
SR		 2094 reg_write(ohci, OHCI1394_LinkControlSet,
2095 OHCI1394_LinkControl_cycleMaster);
2096 }
2097
5ed1f321
JF		 2098 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2099 /*
2100 * We need to clear this event bit in order to make
2101 * cycleMatch isochronous I/O work. In theory we should
2102 * stop active cycleMatch iso contexts now and restart
2103 * them at least two cycles later. (FIXME?)
2104 */
2105 if (printk_ratelimit())
64d21720
SR		 2106 dev_notice(ohci->card.device,
2107 "isochronous cycle inconsistent\n");
5ed1f321
JF		 2108 }
2109
f117a3e3
CL		 2110 if (unlikely(event & OHCI1394_unrecoverableError))
2111 handle_dead_contexts(ohci);
2112
a48777e0
CL		 2113 if (event & OHCI1394_cycle64Seconds) {
2114 spin_lock(&ohci->lock);
2115 update_bus_time(ohci);
2116 spin_unlock(&ohci->lock);
e597e989
CL		 2117 } else
2118 flush_writes(ohci);
a48777e0 2119
ed568912
KH		 2120 return IRQ_HANDLED;
2121}
2122
2aef469a
KH		 2123static int software_reset(struct fw_ohci *ohci)
2124{
9f426173 2125 u32 val;
2aef469a
KH		 2126 int i;
2127
2128 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
9f426173
SR		 2129 for (i = 0; i < 500; i++) {
2130 val = reg_read(ohci, OHCI1394_HCControlSet);
2131 if (!~val)
2132 return -ENODEV; /* Card was ejected. */
2aef469a 2133
9f426173 2134 if (!(val & OHCI1394_HCControl_softReset))
2aef469a 2135 return 0;
9f426173 2136
2aef469a
KH		 2137 msleep(1);
2138 }
2139
2140 return -EBUSY;
2141}
2142
8e85973e
SR		 2143static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2144{
2145 size_t size = length * 4;
2146
2147 memcpy(dest, src, size);
2148 if (size < CONFIG_ROM_SIZE)
2149 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2150}
2151
925e7a65
CL		 2152static int configure_1394a_enhancements(struct fw_ohci *ohci)
2153{
2154 bool enable_1394a;
35d999b1 2155 int ret, clear, set, offset;
925e7a65
CL		 2156
2157 /* Check if the driver should configure link and PHY. */
2158 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2159 OHCI1394_HCControl_programPhyEnable))
2160 return 0;
2161
2162 /* Paranoia: check whether the PHY supports 1394a, too. */
2163 enable_1394a = false;
35d999b1
SR		 2164 ret = read_phy_reg(ohci, 2);
2165 if (ret < 0)
2166 return ret;
2167 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2168 ret = read_paged_phy_reg(ohci, 1, 8);
2169 if (ret < 0)
2170 return ret;
2171 if (ret >= 1)
925e7a65
CL		 2172 enable_1394a = true;
2173 }
2174
2175 if (ohci->quirks & QUIRK_NO_1394A)
2176 enable_1394a = false;
2177
2178 /* Configure PHY and link consistently. */
2179 if (enable_1394a) {
2180 clear = 0;
2181 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2182 } else {
2183 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2184 set = 0;
2185 }
02d37bed 2186 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2187 if (ret < 0)
2188 return ret;
925e7a65
CL		 2189
2190 if (enable_1394a)
2191 offset = OHCI1394_HCControlSet;
2192 else
2193 offset = OHCI1394_HCControlClear;
2194 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2195
2196 /* Clean up: configuration has been taken care of. */
2197 reg_write(ohci, OHCI1394_HCControlClear,
2198 OHCI1394_HCControl_programPhyEnable);
2199
2200 return 0;
2201}
2202
25935ebe
SG		 2203static int probe_tsb41ba3d(struct fw_ohci *ohci)
2204{
b810e4ae
SR		 2205 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2206 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2207 int reg, i;
25935ebe
SG		 2208
2209 reg = read_phy_reg(ohci, 2);
2210 if (reg < 0)
2211 return reg;
b810e4ae
SR		 2212 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2213 return 0;
25935ebe 2214
b810e4ae
SR		 2215 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2216 reg = read_paged_phy_reg(ohci, 1, i + 10);
2217 if (reg < 0)
2218 return reg;
2219 if (reg != id[i])
2220 return 0;
25935ebe 2221 }
b810e4ae 2222 return 1;
25935ebe
SG		 2223}
2224
8e85973e
SR		 2225static int ohci_enable(struct fw_card *card,
2226 const __be32 *config_rom, size_t length)
ed568912
KH		 2227{
2228 struct fw_ohci *ohci = fw_ohci(card);
2229 struct pci_dev *dev = to_pci_dev(card->device);
e91b2787 2230 u32 lps, seconds, version, irqs;
28897fb7 2231 int i, ret;
ed568912 2232
2aef469a 2233 if (software_reset(ohci)) {
64d21720 2234 dev_err(card->device, "failed to reset ohci card\n");
2aef469a
KH		 2235 return -EBUSY;
2236 }
2237
2238 /*
2239 * Now enable LPS, which we need in order to start accessing
2240 * most of the registers. In fact, on some cards (ALI M5251),
2241 * accessing registers in the SClk domain without LPS enabled
2242 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2243 * full link enabled. However, with some cards (well, at least
2244 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 2245 */
2246 reg_write(ohci, OHCI1394_HCControlSet,
2247 OHCI1394_HCControl_LPS |
2248 OHCI1394_HCControl_postedWriteEnable);
2249 flush_writes(ohci);
02214724
JW		 2250
2251 for (lps = 0, i = 0; !lps && i < 3; i++) {
2252 msleep(50);
2253 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2254 OHCI1394_HCControl_LPS;
2255 }
2256
2257 if (!lps) {
64d21720 2258 dev_err(card->device, "failed to set Link Power Status\n");
02214724
JW		 2259 return -EIO;
2260 }
2aef469a 2261
25935ebe 2262 if (ohci->quirks & QUIRK_TI_SLLZ059) {
28897fb7
SR		 2263 ret = probe_tsb41ba3d(ohci);
2264 if (ret < 0)
2265 return ret;
2266 if (ret)
64d21720 2267 dev_notice(card->device, "local TSB41BA3D phy\n");
28897fb7 2268 else
25935ebe 2269 ohci->quirks &= ~QUIRK_TI_SLLZ059;
25935ebe
SG		 2270 }
2271
2aef469a
KH		 2272 reg_write(ohci, OHCI1394_HCControlClear,
2273 OHCI1394_HCControl_noByteSwapData);
2274
affc9c24 2275 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2276 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2277 OHCI1394_LinkControl_cycleTimerEnable |
2278 OHCI1394_LinkControl_cycleMaster);
2279
2280 reg_write(ohci, OHCI1394_ATRetries,
2281 OHCI1394_MAX_AT_REQ_RETRIES |
2282 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2283 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2284 (200 << 16));
2aef469a 2285
a48777e0
CL		 2286 seconds = lower_32_bits(get_seconds());
2287 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2288 ohci->bus_time = seconds & ~0x3f;
2289
e91b2787
CL		 2290 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2291 if (version >= OHCI_VERSION_1_1) {
2292 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2293 0xfffffffe);
db3c9cc1 2294 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2295 }
2296
a1a1132b
CL		 2297 /* Get implemented bits of the priority arbitration request counter. */
2298 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2299 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2300 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2301 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2302
2aef469a
KH		 2303 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2304 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2305 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2306
35d999b1
SR		 2307 ret = configure_1394a_enhancements(ohci);
2308 if (ret < 0)
2309 return ret;
925e7a65 2310
2aef469a 2311 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2312 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2313 if (ret < 0)
2314 return ret;
2aef469a 2315
c781c06d
KH		 2316 /*
2317 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2318 * update mechanism described below in ohci_set_config_rom()
2319 * is not active. We have to update ConfigRomHeader and
2320 * BusOptions manually, and the write to ConfigROMmap takes
2321 * effect immediately. We tie this to the enabling of the
2322 * link, so we have a valid config rom before enabling - the
2323 * OHCI requires that ConfigROMhdr and BusOptions have valid
2324 * values before enabling.
2325 *
2326 * However, when the ConfigROMmap is written, some controllers
2327 * always read back quadlets 0 and 2 from the config rom to
2328 * the ConfigRomHeader and BusOptions registers on bus reset.
2329 * They shouldn't do that in this initial case where the link
2330 * isn't enabled. This means we have to use the same
2331 * workaround here, setting the bus header to 0 and then write
2332 * the right values in the bus reset tasklet.
2333 */
2334
0bd243c4
KH		 2335 if (config_rom) {
2336 ohci->next_config_rom =
2337 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2338 &ohci->next_config_rom_bus,
2339 GFP_KERNEL);
2340 if (ohci->next_config_rom == NULL)
2341 return -ENOMEM;
ed568912 2342
8e85973e 2343 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2344 } else {
2345 /*
2346 * In the suspend case, config_rom is NULL, which
2347 * means that we just reuse the old config rom.
2348 */
2349 ohci->next_config_rom = ohci->config_rom;
2350 ohci->next_config_rom_bus = ohci->config_rom_bus;
2351 }
ed568912 2352
8e85973e 2353 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2354 ohci->next_config_rom[0] = 0;
2355 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2356 reg_write(ohci, OHCI1394_BusOptions,
2357 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2358 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2359
2360 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2361
262444ee
CL		 2362 if (!(ohci->quirks & QUIRK_NO_MSI))
2363 pci_enable_msi(dev);
ed568912 2364 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2365 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2366 ohci_driver_name, ohci)) {
64d21720
SR		 2367 dev_err(card->device, "failed to allocate interrupt %d\n",
2368 dev->irq);
262444ee 2369 pci_disable_msi(dev);
a01e8360
SR		 2370
2371 if (config_rom) {
2372 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2373 ohci->next_config_rom,
2374 ohci->next_config_rom_bus);
2375 ohci->next_config_rom = NULL;
2376 }
ed568912
KH		 2377 return -EIO;
2378 }
2379
148c7866
SR		 2380 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2381 OHCI1394_RQPkt | OHCI1394_RSPkt |
2382 OHCI1394_isochTx | OHCI1394_isochRx |
2383 OHCI1394_postedWriteErr |
2384 OHCI1394_selfIDComplete |
2385 OHCI1394_regAccessFail |
a48777e0 2386 OHCI1394_cycle64Seconds |
f117a3e3
CL		 2387 OHCI1394_cycleInconsistent |
2388 OHCI1394_unrecoverableError |
2389 OHCI1394_cycleTooLong |
148c7866
SR		 2390 OHCI1394_masterIntEnable;
2391 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2392 irqs |= OHCI1394_busReset;
2393 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2394
ed568912
KH		 2395 reg_write(ohci, OHCI1394_HCControlSet,
2396 OHCI1394_HCControl_linkEnable |
2397 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2398
2399 reg_write(ohci, OHCI1394_LinkControlSet,
2400 OHCI1394_LinkControl_rcvSelfID |
2401 OHCI1394_LinkControl_rcvPhyPkt);
2402
2403 ar_context_run(&ohci->ar_request_ctx);
dd6254e5
CL		 2404 ar_context_run(&ohci->ar_response_ctx);
2405
2406 flush_writes(ohci);
ed568912 2407
02d37bed
SR		 2408 /* We are ready to go, reset bus to finish initialization. */
2409 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2410
2411 return 0;
2412}
2413
53dca511 2414static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2415 const __be32 *config_rom, size_t length)
ed568912
KH		 2416{
2417 struct fw_ohci *ohci;
2418 unsigned long flags;
ed568912 2419 __be32 *next_config_rom;
f5101d58 2420 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2421
2422 ohci = fw_ohci(card);
2423
c781c06d
KH		 2424 /*
2425 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2426 * mechanism is a bit tricky, but easy enough to use. See
2427 * section 5.5.6 in the OHCI specification.
2428 *
2429 * The OHCI controller caches the new config rom address in a
2430 * shadow register (ConfigROMmapNext) and needs a bus reset
2431 * for the changes to take place. When the bus reset is
2432 * detected, the controller loads the new values for the
2433 * ConfigRomHeader and BusOptions registers from the specified
2434 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2435 * shadow register. All automatically and atomically.
2436 *
2437 * Now, there's a twist to this story. The automatic load of
2438 * ConfigRomHeader and BusOptions doesn't honor the
2439 * noByteSwapData bit, so with a be32 config rom, the
2440 * controller will load be32 values in to these registers
2441 * during the atomic update, even on litte endian
2442 * architectures. The workaround we use is to put a 0 in the
2443 * header quadlet; 0 is endian agnostic and means that the
2444 * config rom isn't ready yet. In the bus reset tasklet we
2445 * then set up the real values for the two registers.
2446 *
2447 * We use ohci->lock to avoid racing with the code that sets
2d7a36e2 2448 * ohci->next_config_rom to NULL (see bus_reset_work).
ed568912
KH		 2449 */
2450
2451 next_config_rom =
2452 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2453 &next_config_rom_bus, GFP_KERNEL);
2454 if (next_config_rom == NULL)
2455 return -ENOMEM;
2456
2457 spin_lock_irqsave(&ohci->lock, flags);
2458
2e053a27
B		 2459 /*
2460 * If there is not an already pending config_rom update,
2461 * push our new allocation into the ohci->next_config_rom
2462 * and then mark the local variable as null so that we
2463 * won't deallocate the new buffer.
2464 *
2465 * OTOH, if there is a pending config_rom update, just
2466 * use that buffer with the new config_rom data, and
2467 * let this routine free the unused DMA allocation.
2468 */
2469
ed568912
KH		 2470 if (ohci->next_config_rom == NULL) {
2471 ohci->next_config_rom = next_config_rom;
2472 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2473 next_config_rom = NULL;
2474 }
ed568912 2475
2e053a27 2476 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2477
2e053a27
B		 2478 ohci->next_header = config_rom[0];
2479 ohci->next_config_rom[0] = 0;
ed568912 2480
2e053a27 2481 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912
KH		 2482
2483 spin_unlock_irqrestore(&ohci->lock, flags);
2484
2e053a27
B		 2485 /* If we didn't use the DMA allocation, delete it. */
2486 if (next_config_rom != NULL)
2487 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2488 next_config_rom, next_config_rom_bus);
2489
c781c06d
KH		 2490 /*
2491 * Now initiate a bus reset to have the changes take
ed568912
KH		 2492 * effect. We clean up the old config rom memory and DMA
2493 * mappings in the bus reset tasklet, since the OHCI
2494 * controller could need to access it before the bus reset
c781c06d
KH		 2495 * takes effect.
2496 */
ed568912 2497
2e053a27
B		 2498 fw_schedule_bus_reset(&ohci->card, true, true);
2499
2500 return 0;
ed568912
KH		 2501}
2502
2503static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2504{
2505 struct fw_ohci *ohci = fw_ohci(card);
2506
2507 at_context_transmit(&ohci->at_request_ctx, packet);
2508}
2509
2510static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2511{
2512 struct fw_ohci *ohci = fw_ohci(card);
2513
2514 at_context_transmit(&ohci->at_response_ctx, packet);
2515}
2516
730c32f5
KH		 2517static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2518{
2519 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2520 struct context *ctx = &ohci->at_request_ctx;
2521 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2522 int ret = -ENOENT;
730c32f5 2523
f319b6a0 2524 tasklet_disable(&ctx->tasklet);
730c32f5 2525
f319b6a0
KH		 2526 if (packet->ack != 0)
2527 goto out;
730c32f5 2528
19593ffd 2529 if (packet->payload_mapped)
1d1dc5e8
SR		 2530 dma_unmap_single(ohci->card.device, packet->payload_bus,
2531 packet->payload_length, DMA_TO_DEVICE);
2532
64d21720 2533 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2534 driver_data->packet = NULL;
2535 packet->ack = RCODE_CANCELLED;
2536 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2537 ret = 0;
f319b6a0
KH		 2538 out:
2539 tasklet_enable(&ctx->tasklet);
730c32f5 2540
2dbd7d7e 2541 return ret;
730c32f5
KH		 2542}
2543
53dca511
SR		 2544static int ohci_enable_phys_dma(struct fw_card *card,
2545 int node_id, int generation)
ed568912 2546{
080de8c2
SR		 2547#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2548 return 0;
2549#else
ed568912
KH		 2550 struct fw_ohci *ohci = fw_ohci(card);
2551 unsigned long flags;
2dbd7d7e 2552 int n, ret = 0;
ed568912 2553
c781c06d
KH		 2554 /*
2555 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2556 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2557 */
ed568912
KH		 2558
2559 spin_lock_irqsave(&ohci->lock, flags);
2560
2561 if (ohci->generation != generation) {
2dbd7d7e 2562 ret = -ESTALE;
ed568912
KH		 2563 goto out;
2564 }
2565
c781c06d
KH		 2566 /*
2567 * Note, if the node ID contains a non-local bus ID, physical DMA is
2568 * enabled for _all_ nodes on remote buses.
2569 */
907293d7
SR		 2570
2571 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2572 if (n < 32)
2573 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2574 else
2575 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2576
ed568912 2577 flush_writes(ohci);
ed568912 2578 out:
6cad95fe 2579 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2580
2581 return ret;
080de8c2 2582#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2583}
373b2edd 2584
0fcff4e3 2585static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2586{
60d32970 2587 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2588 unsigned long flags;
2589 u32 value;
60d32970
CL		 2590
2591 switch (csr_offset) {
4ffb7a6a
CL		 2592 case CSR_STATE_CLEAR:
2593 case CSR_STATE_SET:
4ffb7a6a
CL		 2594 if (ohci->is_root &&
2595 (reg_read(ohci, OHCI1394_LinkControlSet) &
2596 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2597 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2598 else
c8a94ded
SR		 2599 value = 0;
2600 if (ohci->csr_state_setclear_abdicate)
2601 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2602
c8a94ded 2603 return value;
4a9bde9b 2604
506f1a31
CL		 2605 case CSR_NODE_IDS:
2606 return reg_read(ohci, OHCI1394_NodeID) << 16;
2607
60d32970
CL		 2608 case CSR_CYCLE_TIME:
2609 return get_cycle_time(ohci);
2610
a48777e0
CL		 2611 case CSR_BUS_TIME:
2612 /*
2613 * We might be called just after the cycle timer has wrapped
2614 * around but just before the cycle64Seconds handler, so we
2615 * better check here, too, if the bus time needs to be updated.
2616 */
2617 spin_lock_irqsave(&ohci->lock, flags);
2618 value = update_bus_time(ohci);
2619 spin_unlock_irqrestore(&ohci->lock, flags);
2620 return value;
2621
27a2329f
CL		 2622 case CSR_BUSY_TIMEOUT:
2623 value = reg_read(ohci, OHCI1394_ATRetries);
2624 return (value >> 4) & 0x0ffff00f;
2625
a1a1132b
CL		 2626 case CSR_PRIORITY_BUDGET:
2627 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2628 (ohci->pri_req_max << 8);
2629
60d32970
CL		 2630 default:
2631 WARN_ON(1);
2632 return 0;
2633 }
b677532b
CL		 2634}
2635
0fcff4e3 2636static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2637{
2638 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2639 unsigned long flags;
d60d7f1d 2640
506f1a31 2641 switch (csr_offset) {
4ffb7a6a 2642 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2643 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2644 reg_write(ohci, OHCI1394_LinkControlClear,
2645 OHCI1394_LinkControl_cycleMaster);
2646 flush_writes(ohci);
2647 }
c8a94ded
SR		 2648 if (value & CSR_STATE_BIT_ABDICATE)
2649 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2650 break;
4a9bde9b 2651
4ffb7a6a
CL		 2652 case CSR_STATE_SET:
2653 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2654 reg_write(ohci, OHCI1394_LinkControlSet,
2655 OHCI1394_LinkControl_cycleMaster);
2656 flush_writes(ohci);
2657 }
c8a94ded
SR		 2658 if (value & CSR_STATE_BIT_ABDICATE)
2659 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2660 break;
d60d7f1d 2661
506f1a31
CL		 2662 case CSR_NODE_IDS:
2663 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2664 flush_writes(ohci);
2665 break;
2666
9ab5071c
CL		 2667 case CSR_CYCLE_TIME:
2668 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2669 reg_write(ohci, OHCI1394_IntEventSet,
2670 OHCI1394_cycleInconsistent);
2671 flush_writes(ohci);
2672 break;
2673
a48777e0
CL		 2674 case CSR_BUS_TIME:
2675 spin_lock_irqsave(&ohci->lock, flags);
2676 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2677 spin_unlock_irqrestore(&ohci->lock, flags);
2678 break;
2679
27a2329f
CL		 2680 case CSR_BUSY_TIMEOUT:
2681 value = (value & 0xf) | ((value & 0xf) << 4) |
2682 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2683 reg_write(ohci, OHCI1394_ATRetries, value);
2684 flush_writes(ohci);
2685 break;
2686
a1a1132b
CL		 2687 case CSR_PRIORITY_BUDGET:
2688 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2689 flush_writes(ohci);
2690 break;
2691
506f1a31
CL		 2692 default:
2693 WARN_ON(1);
2694 break;
2695 }
d60d7f1d
KH		 2696}
2697
1aa292bb
DM		 2698static void copy_iso_headers(struct iso_context *ctx, void *p)
2699{
2700 int i = ctx->header_length;
2701
2702 if (i + ctx->base.header_size > PAGE_SIZE)
2703 return;
2704
2705 /*
2706 * The iso header is byteswapped to little endian by
2707 * the controller, but the remaining header quadlets
2708 * are big endian. We want to present all the headers
2709 * as big endian, so we have to swap the first quadlet.
2710 */
2711 if (ctx->base.header_size > 0)
2712 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2713 if (ctx->base.header_size > 4)
2714 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2715 if (ctx->base.header_size > 8)
2716 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2717 ctx->header_length += ctx->base.header_size;
2718}
2719
a186b4a6
JW		 2720static int handle_ir_packet_per_buffer(struct context *context,
2721 struct descriptor *d,
2722 struct descriptor *last)
2723{
2724 struct iso_context *ctx =
2725 container_of(context, struct iso_context, context);
bcee893c 2726 struct descriptor *pd;
a572e688 2727 u32 buffer_dma;
a186b4a6 2728 __le32 *ir_header;
bcee893c 2729 void *p;
a186b4a6 2730
872e330e 2731 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2732 if (pd->transfer_status)
2733 break;
bcee893c 2734 if (pd > last)
a186b4a6
JW		 2735 /* Descriptor(s) not done yet, stop iteration */
2736 return 0;
2737
a572e688
CL		 2738 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2739 d++;
2740 buffer_dma = le32_to_cpu(d->data_address);
2741 dma_sync_single_range_for_cpu(context->ohci->card.device,
2742 buffer_dma & PAGE_MASK,
2743 buffer_dma & ~PAGE_MASK,
2744 le16_to_cpu(d->req_count),
2745 DMA_FROM_DEVICE);
2746 }
2747
1aa292bb
DM		 2748 p = last + 1;
2749 copy_iso_headers(ctx, p);
a186b4a6 2750
bcee893c
DM		 2751 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2752 ir_header = (__le32 *) p;
872e330e
SR		 2753 ctx->base.callback.sc(&ctx->base,
2754 le32_to_cpu(ir_header[0]) & 0xffff,
2755 ctx->header_length, ctx->header,
2756 ctx->base.callback_data);
a186b4a6
JW		 2757 ctx->header_length = 0;
2758 }
2759
a186b4a6
JW		 2760 return 1;
2761}
2762
872e330e
SR		 2763/* d == last because each descriptor block is only a single descriptor. */
2764static int handle_ir_buffer_fill(struct context *context,
2765 struct descriptor *d,
2766 struct descriptor *last)
2767{
2768 struct iso_context *ctx =
2769 container_of(context, struct iso_context, context);
a572e688 2770 u32 buffer_dma;
872e330e
SR		 2771
2772 if (!last->transfer_status)
2773 /* Descriptor(s) not done yet, stop iteration */
2774 return 0;
2775
a572e688
CL		 2776 buffer_dma = le32_to_cpu(last->data_address);
2777 dma_sync_single_range_for_cpu(context->ohci->card.device,
2778 buffer_dma & PAGE_MASK,
2779 buffer_dma & ~PAGE_MASK,
2780 le16_to_cpu(last->req_count),
2781 DMA_FROM_DEVICE);
2782
872e330e
SR		 2783 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2784 ctx->base.callback.mc(&ctx->base,
2785 le32_to_cpu(last->data_address) +
2786 le16_to_cpu(last->req_count) -
2787 le16_to_cpu(last->res_count),
2788 ctx->base.callback_data);
2789
2790 return 1;
2791}
2792
a572e688
CL		 2793static inline void sync_it_packet_for_cpu(struct context *context,
2794 struct descriptor *pd)
2795{
2796 __le16 control;
2797 u32 buffer_dma;
2798
2799 /* only packets beginning with OUTPUT_MORE* have data buffers */
2800 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2801 return;
2802
2803 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2804 pd += 2;
2805
2806 /*
2807 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2808 * data buffer is in the context program's coherent page and must not
2809 * be synced.
2810 */
2811 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2812 (context->current_bus & PAGE_MASK)) {
2813 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2814 return;
2815 pd++;
2816 }
2817
2818 do {
2819 buffer_dma = le32_to_cpu(pd->data_address);
2820 dma_sync_single_range_for_cpu(context->ohci->card.device,
2821 buffer_dma & PAGE_MASK,
2822 buffer_dma & ~PAGE_MASK,
2823 le16_to_cpu(pd->req_count),
2824 DMA_TO_DEVICE);
2825 control = pd->control;
2826 pd++;
2827 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2828}
2829
30200739
KH		 2830static int handle_it_packet(struct context *context,
2831 struct descriptor *d,
2832 struct descriptor *last)
ed568912 2833{
30200739
KH		 2834 struct iso_context *ctx =
2835 container_of(context, struct iso_context, context);
31769cef
JF		 2836 int i;
2837 struct descriptor *pd;
373b2edd 2838
31769cef
JF		 2839 for (pd = d; pd <= last; pd++)
2840 if (pd->transfer_status)
2841 break;
2842 if (pd > last)
2843 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2844 return 0;
2845
a572e688
CL		 2846 sync_it_packet_for_cpu(context, d);
2847
31769cef
JF		 2848 i = ctx->header_length;
2849 if (i + 4 < PAGE_SIZE) {
2850 /* Present this value as big-endian to match the receive code */
2851 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2852 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2853 le16_to_cpu(pd->res_count));
2854 ctx->header_length += 4;
2855 }
2856 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
872e330e
SR		 2857 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2858 ctx->header_length, ctx->header,
2859 ctx->base.callback_data);
31769cef
JF		 2860 ctx->header_length = 0;
2861 }
30200739 2862 return 1;
ed568912
KH		 2863}
2864
872e330e
SR		 2865static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2866{
2867 u32 hi = channels >> 32, lo = channels;
2868
2869 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2870 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2871 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2872 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2873 mmiowb();
2874 ohci->mc_channels = channels;
2875}
2876
53dca511 2877static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2878 int type, int channel, size_t header_size)
ed568912
KH		 2879{
2880 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2881 struct iso_context *uninitialized_var(ctx);
2882 descriptor_callback_t uninitialized_var(callback);
2883 u64 *uninitialized_var(channels);
2884 u32 *uninitialized_var(mask), uninitialized_var(regs);
ed568912 2885 unsigned long flags;
872e330e 2886 int index, ret = -EBUSY;
ed568912 2887
872e330e 2888 spin_lock_irqsave(&ohci->lock, flags);
ed568912 2889
872e330e
SR		 2890 switch (type) {
2891 case FW_ISO_CONTEXT_TRANSMIT:
2892 mask = &ohci->it_context_mask;
30200739 2893 callback = handle_it_packet;
872e330e
SR		 2894 index = ffs(*mask) - 1;
2895 if (index >= 0) {
2896 *mask &= ~(1 << index);
2897 regs = OHCI1394_IsoXmitContextBase(index);
2898 ctx = &ohci->it_context_list[index];
2899 }
2900 break;
2901
2902 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2903 channels = &ohci->ir_context_channels;
872e330e 2904 mask = &ohci->ir_context_mask;
6498ba04 2905 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2906 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2907 if (index >= 0) {
2908 *channels &= ~(1ULL << channel);
2909 *mask &= ~(1 << index);
2910 regs = OHCI1394_IsoRcvContextBase(index);
2911 ctx = &ohci->ir_context_list[index];
2912 }
2913 break;
ed568912 2914
872e330e
SR		 2915 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2916 mask = &ohci->ir_context_mask;
2917 callback = handle_ir_buffer_fill;
2918 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2919 if (index >= 0) {
2920 ohci->mc_allocated = true;
2921 *mask &= ~(1 << index);
2922 regs = OHCI1394_IsoRcvContextBase(index);
2923 ctx = &ohci->ir_context_list[index];
2924 }
2925 break;
2926
2927 default:
2928 index = -1;
2929 ret = -ENOSYS;
4817ed24 2930 }
872e330e 2931
ed568912
KH		 2932 spin_unlock_irqrestore(&ohci->lock, flags);
2933
2934 if (index < 0)
872e330e 2935 return ERR_PTR(ret);
373b2edd 2936
2d826cc5 2937 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2938 ctx->header_length = 0;
2939 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2940 if (ctx->header == NULL) {
2941 ret = -ENOMEM;
9b32d5f3 2942 goto out;
872e330e 2943 }
2dbd7d7e
SR		 2944 ret = context_init(&ctx->context, ohci, regs, callback);
2945 if (ret < 0)
9b32d5f3 2946 goto out_with_header;
ed568912 2947
872e330e
SR		 2948 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2949 set_multichannel_mask(ohci, 0);
2950
ed568912 2951 return &ctx->base;
9b32d5f3
KH		 2952
2953 out_with_header:
2954 free_page((unsigned long)ctx->header);
2955 out:
2956 spin_lock_irqsave(&ohci->lock, flags);
872e330e
SR		 2957
2958 switch (type) {
2959 case FW_ISO_CONTEXT_RECEIVE:
2960 *channels |= 1ULL << channel;
2961 break;
2962
2963 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2964 ohci->mc_allocated = false;
2965 break;
2966 }
9b32d5f3 2967 *mask |= 1 << index;
872e330e 2968
9b32d5f3
KH		 2969 spin_unlock_irqrestore(&ohci->lock, flags);
2970
2dbd7d7e 2971 return ERR_PTR(ret);
ed568912
KH		 2972}
2973
eb0306ea
KH		 2974static int ohci_start_iso(struct fw_iso_context *base,
2975 s32 cycle, u32 sync, u32 tags)
ed568912 2976{
373b2edd 2977 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 2978 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 2979 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 2980 int index;
2981
44b74d90
CL		 2982 /* the controller cannot start without any queued packets */
2983 if (ctx->context.last->branch_address == 0)
2984 return -ENODATA;
2985
872e330e
SR		 2986 switch (ctx->base.type) {
2987 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 2988 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 2989 match = 0;
2990 if (cycle >= 0)
2991 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 2992 (cycle & 0x7fff) << 16;
21efb3cf 2993
295e3feb
KH		 2994 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2995 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 2996 context_run(&ctx->context, match);
872e330e
SR		 2997 break;
2998
2999 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3000 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3001 /* fall through */
3002 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 3003 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 3004 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3005 if (cycle >= 0) {
3006 match |= (cycle & 0x07fff) << 12;
3007 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3008 }
ed568912 3009
295e3feb
KH		 3010 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3011 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 3012 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 3013 context_run(&ctx->context, control);
dd23736e
ML		 3014
3015 ctx->sync = sync;
3016 ctx->tags = tags;
3017
872e330e 3018 break;
295e3feb 3019 }
ed568912
KH		 3020
3021 return 0;
3022}
3023
b8295668
KH		 3024static int ohci_stop_iso(struct fw_iso_context *base)
3025{
3026 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3027 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 3028 int index;
3029
872e330e
SR		 3030 switch (ctx->base.type) {
3031 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 3032 index = ctx - ohci->it_context_list;
3033 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 3034 break;
3035
3036 case FW_ISO_CONTEXT_RECEIVE:
3037 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 3038 index = ctx - ohci->ir_context_list;
3039 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 3040 break;
b8295668
KH		 3041 }
3042 flush_writes(ohci);
3043 context_stop(&ctx->context);
e81cbebd 3044 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 3045
3046 return 0;
3047}
3048
ed568912
KH		 3049static void ohci_free_iso_context(struct fw_iso_context *base)
3050{
3051 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3052 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 3053 unsigned long flags;
3054 int index;
3055
b8295668
KH		 3056 ohci_stop_iso(base);
3057 context_release(&ctx->context);
9b32d5f3 3058 free_page((unsigned long)ctx->header);
b8295668 3059
ed568912
KH		 3060 spin_lock_irqsave(&ohci->lock, flags);
3061
872e330e
SR		 3062 switch (base->type) {
3063 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 3064 index = ctx - ohci->it_context_list;
ed568912 3065 ohci->it_context_mask |= 1 << index;
872e330e
SR		 3066 break;
3067
3068 case FW_ISO_CONTEXT_RECEIVE:
ed568912 3069 index = ctx - ohci->ir_context_list;
ed568912 3070 ohci->ir_context_mask |= 1 << index;
4817ed24 3071 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 3072 break;
3073
3074 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3075 index = ctx - ohci->ir_context_list;
3076 ohci->ir_context_mask |= 1 << index;
3077 ohci->ir_context_channels |= ohci->mc_channels;
3078 ohci->mc_channels = 0;
3079 ohci->mc_allocated = false;
3080 break;
ed568912 3081 }
ed568912
KH		 3082
3083 spin_unlock_irqrestore(&ohci->lock, flags);
3084}
3085
872e330e
SR		 3086static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3087{
3088 struct fw_ohci *ohci = fw_ohci(base->card);
3089 unsigned long flags;
3090 int ret;
3091
3092 switch (base->type) {
3093 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3094
3095 spin_lock_irqsave(&ohci->lock, flags);
3096
3097 /* Don't allow multichannel to grab other contexts' channels. */
3098 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3099 *channels = ohci->ir_context_channels;
3100 ret = -EBUSY;
3101 } else {
3102 set_multichannel_mask(ohci, *channels);
3103 ret = 0;
3104 }
3105
3106 spin_unlock_irqrestore(&ohci->lock, flags);
3107
3108 break;
3109 default:
3110 ret = -EINVAL;
3111 }
3112
3113 return ret;
3114}
3115
dd23736e
ML		 3116#ifdef CONFIG_PM
3117static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3118{
3119 int i;
3120 struct iso_context *ctx;
3121
3122 for (i = 0 ; i < ohci->n_ir ; i++) {
3123 ctx = &ohci->ir_context_list[i];
693a50b5 3124 if (ctx->context.running)
dd23736e
ML		 3125 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3126 }
3127
3128 for (i = 0 ; i < ohci->n_it ; i++) {
3129 ctx = &ohci->it_context_list[i];
693a50b5 3130 if (ctx->context.running)
dd23736e
ML		 3131 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3132 }
3133}
3134#endif
3135
872e330e
SR		 3136static int queue_iso_transmit(struct iso_context *ctx,
3137 struct fw_iso_packet *packet,
3138 struct fw_iso_buffer *buffer,
3139 unsigned long payload)
ed568912 3140{
30200739 3141 struct descriptor *d, *last, *pd;
ed568912
KH		 3142 struct fw_iso_packet *p;
3143 __le32 *header;
9aad8125 3144 dma_addr_t d_bus, page_bus;
ed568912
KH		 3145 u32 z, header_z, payload_z, irq;
3146 u32 payload_index, payload_end_index, next_page_index;
30200739 3147 int page, end_page, i, length, offset;
ed568912 3148
ed568912 3149 p = packet;
9aad8125 3150 payload_index = payload;
ed568912
KH		 3151
3152 if (p->skip)
3153 z = 1;
3154 else
3155 z = 2;
3156 if (p->header_length > 0)
3157 z++;
3158
3159 /* Determine the first page the payload isn't contained in. */
3160 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3161 if (p->payload_length > 0)
3162 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3163 else
3164 payload_z = 0;
3165
3166 z += payload_z;
3167
3168 /* Get header size in number of descriptors. */
2d826cc5 3169 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 3170
30200739
KH		 3171 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3172 if (d == NULL)
3173 return -ENOMEM;
ed568912
KH		 3174
3175 if (!p->skip) {
a77754a7 3176 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 3177 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 3178 /*
3179 * Link the skip address to this descriptor itself. This causes
3180 * a context to skip a cycle whenever lost cycles or FIFO
3181 * overruns occur, without dropping the data. The application
3182 * should then decide whether this is an error condition or not.
3183 * FIXME: Make the context's cycle-lost behaviour configurable?
3184 */
3185 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 3186
3187 header = (__le32 *) &d[1];
a77754a7
KH		 3188 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3189 IT_HEADER_TAG(p->tag) |
3190 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3191 IT_HEADER_CHANNEL(ctx->base.channel) |
3192 IT_HEADER_SPEED(ctx->base.speed));
ed568912 3193 header[1] =
a77754a7 3194 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 3195 p->payload_length));
3196 }
3197
3198 if (p->header_length > 0) {
3199 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 3200 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 3201 memcpy(&d[z], p->header, p->header_length);
3202 }
3203
3204 pd = d + z - payload_z;
3205 payload_end_index = payload_index + p->payload_length;
3206 for (i = 0; i < payload_z; i++) {
3207 page = payload_index >> PAGE_SHIFT;
3208 offset = payload_index & ~PAGE_MASK;
3209 next_page_index = (page + 1) << PAGE_SHIFT;
3210 length =
3211 min(next_page_index, payload_end_index) - payload_index;
3212 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 3213
3214 page_bus = page_private(buffer->pages[page]);
3215 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912 3216
a572e688
CL		 3217 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3218 page_bus, offset, length,
3219 DMA_TO_DEVICE);
3220
ed568912
KH		 3221 payload_index += length;
3222 }
3223
ed568912 3224 if (p->interrupt)
a77754a7 3225 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 3226 else
a77754a7 3227 irq = DESCRIPTOR_NO_IRQ;
ed568912 3228
30200739 3229 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 3230 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3231 DESCRIPTOR_STATUS |
3232 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 3233 irq);
ed568912 3234
30200739 3235 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 3236
3237 return 0;
3238}
373b2edd 3239
872e330e
SR		 3240static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3241 struct fw_iso_packet *packet,
3242 struct fw_iso_buffer *buffer,
3243 unsigned long payload)
a186b4a6 3244{
a572e688 3245 struct device *device = ctx->context.ohci->card.device;
8c0c0cc2 3246 struct descriptor *d, *pd;
a186b4a6
JW		 3247 dma_addr_t d_bus, page_bus;
3248 u32 z, header_z, rest;
bcee893c
DM		 3249 int i, j, length;
3250 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 3251
3252 /*
1aa292bb
DM		 3253 * The OHCI controller puts the isochronous header and trailer in the
3254 * buffer, so we need at least 8 bytes.
a186b4a6 3255 */
872e330e 3256 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 3257 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 3258
3259 /* Get header size in number of descriptors. */
3260 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3261 page = payload >> PAGE_SHIFT;
3262 offset = payload & ~PAGE_MASK;
872e330e 3263 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 3264
3265 for (i = 0; i < packet_count; i++) {
3266 /* d points to the header descriptor */
bcee893c 3267 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 3268 d = context_get_descriptors(&ctx->context,
bcee893c 3269 z + header_z, &d_bus);
a186b4a6
JW		 3270 if (d == NULL)
3271 return -ENOMEM;
3272
bcee893c
DM		 3273 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3274 DESCRIPTOR_INPUT_MORE);
872e330e 3275 if (packet->skip && i == 0)
bcee893c 3276 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3277 d->req_count = cpu_to_le16(header_size);
3278 d->res_count = d->req_count;
bcee893c 3279 d->transfer_status = 0;
a186b4a6
JW		 3280 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3281
bcee893c 3282 rest = payload_per_buffer;
8c0c0cc2 3283 pd = d;
bcee893c 3284 for (j = 1; j < z; j++) {
8c0c0cc2 3285 pd++;
bcee893c
DM		 3286 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3287 DESCRIPTOR_INPUT_MORE);
3288
3289 if (offset + rest < PAGE_SIZE)
3290 length = rest;
3291 else
3292 length = PAGE_SIZE - offset;
3293 pd->req_count = cpu_to_le16(length);
3294 pd->res_count = pd->req_count;
3295 pd->transfer_status = 0;
3296
3297 page_bus = page_private(buffer->pages[page]);
3298 pd->data_address = cpu_to_le32(page_bus + offset);
3299
a572e688
CL		 3300 dma_sync_single_range_for_device(device, page_bus,
3301 offset, length,
3302 DMA_FROM_DEVICE);
3303
bcee893c
DM		 3304 offset = (offset + length) & ~PAGE_MASK;
3305 rest -= length;
3306 if (offset == 0)
3307 page++;
3308 }
a186b4a6
JW		 3309 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3310 DESCRIPTOR_INPUT_LAST |
3311 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3312 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3313 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3314
a186b4a6
JW		 3315 context_append(&ctx->context, d, z, header_z);
3316 }
3317
3318 return 0;
3319}
3320
872e330e
SR		 3321static int queue_iso_buffer_fill(struct iso_context *ctx,
3322 struct fw_iso_packet *packet,
3323 struct fw_iso_buffer *buffer,
3324 unsigned long payload)
3325{
3326 struct descriptor *d;
3327 dma_addr_t d_bus, page_bus;
3328 int page, offset, rest, z, i, length;
3329
3330 page = payload >> PAGE_SHIFT;
3331 offset = payload & ~PAGE_MASK;
3332 rest = packet->payload_length;
3333
3334 /* We need one descriptor for each page in the buffer. */
3335 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3336
3337 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3338 return -EFAULT;
3339
3340 for (i = 0; i < z; i++) {
3341 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3342 if (d == NULL)
3343 return -ENOMEM;
3344
3345 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3346 DESCRIPTOR_BRANCH_ALWAYS);
3347 if (packet->skip && i == 0)
3348 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3349 if (packet->interrupt && i == z - 1)
3350 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3351
3352 if (offset + rest < PAGE_SIZE)
3353 length = rest;
3354 else
3355 length = PAGE_SIZE - offset;
3356 d->req_count = cpu_to_le16(length);
3357 d->res_count = d->req_count;
3358 d->transfer_status = 0;
3359
3360 page_bus = page_private(buffer->pages[page]);
3361 d->data_address = cpu_to_le32(page_bus + offset);
3362
a572e688
CL		 3363 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3364 page_bus, offset, length,
3365 DMA_FROM_DEVICE);
3366
872e330e
SR		 3367 rest -= length;
3368 offset = 0;
3369 page++;
3370
3371 context_append(&ctx->context, d, 1, 0);
3372 }
3373
3374 return 0;
3375}
3376
53dca511
SR		 3377static int ohci_queue_iso(struct fw_iso_context *base,
3378 struct fw_iso_packet *packet,
3379 struct fw_iso_buffer *buffer,
3380 unsigned long payload)
295e3feb 3381{
e364cf4e 3382 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3383 unsigned long flags;
872e330e 3384 int ret = -ENOSYS;
e364cf4e 3385
fe5ca634 3386 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3387 switch (base->type) {
3388 case FW_ISO_CONTEXT_TRANSMIT:
3389 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3390 break;
3391 case FW_ISO_CONTEXT_RECEIVE:
3392 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3393 break;
3394 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3395 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3396 break;
3397 }
fe5ca634
DM		 3398 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3399
2dbd7d7e 3400 return ret;
295e3feb
KH		 3401}
3402
13882a82
CL		 3403static void ohci_flush_queue_iso(struct fw_iso_context *base)
3404{
3405 struct context *ctx =
3406 &container_of(base, struct iso_context, base)->context;
3407
3408 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
13882a82
CL		 3409}
3410
21ebcd12 3411static const struct fw_card_driver ohci_driver = {
ed568912 3412 .enable = ohci_enable,
02d37bed 3413 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3414 .update_phy_reg = ohci_update_phy_reg,
3415 .set_config_rom = ohci_set_config_rom,
3416 .send_request = ohci_send_request,
3417 .send_response = ohci_send_response,
730c32f5 3418 .cancel_packet = ohci_cancel_packet,
ed568912 3419 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3420 .read_csr = ohci_read_csr,
3421 .write_csr = ohci_write_csr,
ed568912
KH		 3422
3423 .allocate_iso_context = ohci_allocate_iso_context,
3424 .free_iso_context = ohci_free_iso_context,
872e330e 3425 .set_iso_channels = ohci_set_iso_channels,
ed568912 3426 .queue_iso = ohci_queue_iso,
13882a82 3427 .flush_queue_iso = ohci_flush_queue_iso,
69cdb726 3428 .start_iso = ohci_start_iso,
b8295668 3429 .stop_iso = ohci_stop_iso,
ed568912
KH		 3430};
3431
ea8d006b 3432#ifdef CONFIG_PPC_PMAC
5da3dac8 3433static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3434{
ea8d006b
SR		 3435 if (machine_is(powermac)) {
3436 struct device_node *ofn = pci_device_to_OF_node(dev);
3437
3438 if (ofn) {
3439 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3440 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3441 }
3442 }
2ed0f181
SR		 3443}
3444
5da3dac8 3445static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3446{
3447 if (machine_is(powermac)) {
3448 struct device_node *ofn = pci_device_to_OF_node(dev);
3449
3450 if (ofn) {
3451 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3452 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3453 }
3454 }
3455}
3456#else
5da3dac8
SR		 3457static inline void pmac_ohci_on(struct pci_dev *dev) {}
3458static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3459#endif /* CONFIG_PPC_PMAC */
3460
53dca511
SR		 3461static int __devinit pci_probe(struct pci_dev *dev,
3462 const struct pci_device_id *ent)
2ed0f181
SR		 3463{
3464 struct fw_ohci *ohci;
aa0170ff 3465 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3466 u64 guid;
dd23736e 3467 int i, err;
2ed0f181
SR		 3468 size_t size;
3469
7f7e3711
SR		 3470 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3471 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3472 return -ENOSYS;
3473 }
3474
2d826cc5 3475 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3476 if (ohci == NULL) {
7007a076
SR		 3477 err = -ENOMEM;
3478 goto fail;
ed568912
KH		 3479 }
3480
3481 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3482
5da3dac8 3483 pmac_ohci_on(dev);
130d5496 3484
d79406dd
KH		 3485 err = pci_enable_device(dev);
3486 if (err) {
64d21720 3487 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
bd7dee63 3488 goto fail_free;
ed568912
KH		 3489 }
3490
3491 pci_set_master(dev);
3492 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3493 pci_set_drvdata(dev, ohci);
3494
3495 spin_lock_init(&ohci->lock);
02d37bed 3496 mutex_init(&ohci->phy_reg_mutex);
ed568912 3497
2d7a36e2 3498 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
ed568912 3499
d79406dd
KH		 3500 err = pci_request_region(dev, 0, ohci_driver_name);
3501 if (err) {
64d21720 3502 dev_err(&dev->dev, "MMIO resource unavailable\n");
d79406dd 3503 goto fail_disable;
ed568912
KH		 3504 }
3505
3506 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3507 if (ohci->registers == NULL) {
64d21720 3508 dev_err(&dev->dev, "failed to remap registers\n");
d79406dd
KH		 3509 err = -ENXIO;
3510 goto fail_iomem;
ed568912
KH		 3511 }
3512
4a635593 3513 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3514 if ((ohci_quirks[i].vendor == dev->vendor) &&
3515 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3516 ohci_quirks[i].device == dev->device) &&
3517 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3518 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3519 ohci->quirks = ohci_quirks[i].flags;
3520 break;
3521 }
3e9cc2f3
SR		 3522 if (param_quirks)
3523 ohci->quirks = param_quirks;
b677532b 3524
ec766a79
CL		 3525 /*
3526 * Because dma_alloc_coherent() allocates at least one page,
3527 * we save space by using a common buffer for the AR request/
3528 * response descriptors and the self IDs buffer.
3529 */
3530 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3531 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3532 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3533 PAGE_SIZE,
3534 &ohci->misc_buffer_bus,
3535 GFP_KERNEL);
3536 if (!ohci->misc_buffer) {
3537 err = -ENOMEM;
3538 goto fail_iounmap;
3539 }
3540
3541 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3542 OHCI1394_AsReqRcvContextControlSet);
3543 if (err < 0)
ec766a79 3544 goto fail_misc_buf;
ed568912 3545
ec766a79 3546 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3547 OHCI1394_AsRspRcvContextControlSet);
3548 if (err < 0)
3549 goto fail_arreq_ctx;
ed568912 3550
c088ab30
CL		 3551 err = context_init(&ohci->at_request_ctx, ohci,
3552 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3553 if (err < 0)
3554 goto fail_arrsp_ctx;
ed568912 3555
c088ab30
CL		 3556 err = context_init(&ohci->at_response_ctx, ohci,
3557 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3558 if (err < 0)
3559 goto fail_atreq_ctx;
ed568912 3560
ed568912 3561 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3562 ohci->ir_context_channels = ~0ULL;
f117a3e3 3563 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3564 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3565 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3566 ohci->n_ir = hweight32(ohci->ir_context_mask);
3567 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3568 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3569
3570 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3571 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3572 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3573 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3574 ohci->n_it = hweight32(ohci->it_context_mask);
3575 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3576 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3577
3578 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3579 err = -ENOMEM;
7007a076 3580 goto fail_contexts;
ed568912
KH		 3581 }
3582
ec766a79
CL		 3583 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3584 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3585
ed568912
KH		 3586 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3587 max_receive = (bus_options >> 12) & 0xf;
3588 link_speed = bus_options & 0x7;
3589 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3590 reg_read(ohci, OHCI1394_GUIDLo);
3591
d79406dd 3592 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3593 if (err)
ec766a79 3594 goto fail_contexts;
ed568912 3595
6fdb2ee2 3596 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
64d21720
SR		 3597 dev_notice(&dev->dev,
3598 "added OHCI v%x.%x device as card %d, "
6fdb2ee2 3599 "%d IR + %d IT contexts, quirks 0x%x\n",
64d21720 3600 version >> 16, version & 0xff, ohci->card.index,
dd23736e 3601 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3602
ed568912 3603 return 0;
d79406dd 3604
7007a076 3605 fail_contexts:
d79406dd 3606 kfree(ohci->ir_context_list);
7007a076
SR		 3607 kfree(ohci->it_context_list);
3608 context_release(&ohci->at_response_ctx);
c088ab30 3609 fail_atreq_ctx:
7007a076 3610 context_release(&ohci->at_request_ctx);
c088ab30 3611 fail_arrsp_ctx:
7007a076 3612 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3613 fail_arreq_ctx:
7007a076 3614 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3615 fail_misc_buf:
3616 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3617 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3618 fail_iounmap:
d79406dd
KH		 3619 pci_iounmap(dev, ohci->registers);
3620 fail_iomem:
3621 pci_release_region(dev, 0);
3622 fail_disable:
3623 pci_disable_device(dev);
bd7dee63 3624 fail_free:
d838d2c0 3625 kfree(ohci);
5da3dac8 3626 pmac_ohci_off(dev);
7007a076
SR		 3627 fail:
3628 if (err == -ENOMEM)
64d21720 3629 dev_err(&dev->dev, "out of memory\n");
d79406dd
KH		 3630
3631 return err;
ed568912
KH		 3632}
3633
3634static void pci_remove(struct pci_dev *dev)
3635{
3636 struct fw_ohci *ohci;
3637
3638 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3639 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3640 flush_writes(ohci);
2d7a36e2 3641 cancel_work_sync(&ohci->bus_reset_work);
ed568912
KH		 3642 fw_core_remove_card(&ohci->card);
3643
c781c06d
KH		 3644 /*
3645 * FIXME: Fail all pending packets here, now that the upper
3646 * layers can't queue any more.
3647 */
ed568912
KH		 3648
3649 software_reset(ohci);
3650 free_irq(dev->irq, ohci);
a55709ba
JF		 3651
3652 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3653 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3654 ohci->next_config_rom, ohci->next_config_rom_bus);
3655 if (ohci->config_rom)
3656 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3657 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3658 ar_context_release(&ohci->ar_request_ctx);
3659 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3660 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3661 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3662 context_release(&ohci->at_request_ctx);
3663 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3664 kfree(ohci->it_context_list);
3665 kfree(ohci->ir_context_list);
262444ee 3666 pci_disable_msi(dev);
d79406dd
KH		 3667 pci_iounmap(dev, ohci->registers);
3668 pci_release_region(dev, 0);
3669 pci_disable_device(dev);
d838d2c0 3670 kfree(ohci);
5da3dac8 3671 pmac_ohci_off(dev);
ea8d006b 3672
64d21720 3673 dev_notice(&dev->dev, "removed fw-ohci device\n");
ed568912
KH		 3674}
3675
2aef469a 3676#ifdef CONFIG_PM
2ed0f181 3677static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3678{
2ed0f181 3679 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3680 int err;
3681
3682 software_reset(ohci);
2ed0f181 3683 free_irq(dev->irq, ohci);
262444ee 3684 pci_disable_msi(dev);
2ed0f181 3685 err = pci_save_state(dev);
2aef469a 3686 if (err) {
64d21720 3687 dev_err(&dev->dev, "pci_save_state failed\n");
2aef469a
KH		 3688 return err;
3689 }
2ed0f181 3690 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428 3691 if (err)
64d21720 3692 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
5da3dac8 3693 pmac_ohci_off(dev);
ea8d006b 3694
2aef469a
KH		 3695 return 0;
3696}
3697
2ed0f181 3698static int pci_resume(struct pci_dev *dev)
2aef469a 3699{
2ed0f181 3700 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3701 int err;
3702
5da3dac8 3703 pmac_ohci_on(dev);
2ed0f181
SR		 3704 pci_set_power_state(dev, PCI_D0);
3705 pci_restore_state(dev);
3706 err = pci_enable_device(dev);
2aef469a 3707 if (err) {
64d21720 3708 dev_err(&dev->dev, "pci_enable_device failed\n");
2aef469a
KH		 3709 return err;
3710 }
3711
8662b6b0
ML		 3712 /* Some systems don't setup GUID register on resume from ram */
3713 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3714 !reg_read(ohci, OHCI1394_GUIDHi)) {
3715 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3716 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3717 }
3718
dd23736e 3719 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3720 if (err)
3721 return err;
3722
3723 ohci_resume_iso_dma(ohci);
693a50b5 3724
dd23736e 3725 return 0;
2aef469a
KH		 3726}
3727#endif
3728
a67483d2 3729static const struct pci_device_id pci_table[] = {
ed568912
KH		 3730 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3731 { }
3732};
3733
3734MODULE_DEVICE_TABLE(pci, pci_table);
3735
3736static struct pci_driver fw_ohci_pci_driver = {
3737 .name = ohci_driver_name,
3738 .id_table = pci_table,
3739 .probe = pci_probe,
3740 .remove = pci_remove,
2aef469a
KH		 3741#ifdef CONFIG_PM
3742 .resume = pci_resume,
3743 .suspend = pci_suspend,
3744#endif
ed568912
KH		 3745};
3746
3747MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3748MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3749MODULE_LICENSE("GPL");
3750
1e4c7b0d
OH		 3751/* Provide a module alias so root-on-sbp2 initrds don't break. */
3752#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3753MODULE_ALIAS("ohci1394");
3754#endif
3755
ed568912
KH		 3756static int __init fw_ohci_init(void)
3757{
3758 return pci_register_driver(&fw_ohci_pci_driver);
3759}
3760
3761static void __exit fw_ohci_cleanup(void)
3762{
3763 pci_unregister_driver(&fw_ohci_pci_driver);
3764}
3765
3766module_init(fw_ohci_init);
3767module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
This page took 0.532773 seconds and 5 git commands to generate.