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9626b699 | 1 | /* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved. |
b6a1dfbc KG |
2 | * Copyright (C) 2015 Linaro Ltd. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
16 | * 02110-1301, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/slab.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/mutex.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/qcom_scm.h> | |
26 | ||
27 | #include <asm/outercache.h> | |
28 | #include <asm/cacheflush.h> | |
29 | ||
30 | #include "qcom_scm.h" | |
31 | ||
32 | #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 | |
33 | #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 | |
34 | #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 | |
35 | #define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20 | |
36 | ||
37 | #define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04 | |
38 | #define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02 | |
39 | #define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10 | |
40 | #define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40 | |
41 | ||
42 | struct qcom_scm_entry { | |
43 | int flag; | |
44 | void *entry; | |
45 | }; | |
46 | ||
47 | static struct qcom_scm_entry qcom_scm_wb[] = { | |
48 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 }, | |
49 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 }, | |
50 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 }, | |
51 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 }, | |
52 | }; | |
53 | ||
54 | static DEFINE_MUTEX(qcom_scm_lock); | |
55 | ||
56 | /** | |
57 | * struct qcom_scm_command - one SCM command buffer | |
58 | * @len: total available memory for command and response | |
59 | * @buf_offset: start of command buffer | |
60 | * @resp_hdr_offset: start of response buffer | |
61 | * @id: command to be executed | |
62 | * @buf: buffer returned from qcom_scm_get_command_buffer() | |
63 | * | |
64 | * An SCM command is laid out in memory as follows: | |
65 | * | |
66 | * ------------------- <--- struct qcom_scm_command | |
67 | * | command header | | |
68 | * ------------------- <--- qcom_scm_get_command_buffer() | |
69 | * | command buffer | | |
70 | * ------------------- <--- struct qcom_scm_response and | |
71 | * | response header | qcom_scm_command_to_response() | |
72 | * ------------------- <--- qcom_scm_get_response_buffer() | |
73 | * | response buffer | | |
74 | * ------------------- | |
75 | * | |
76 | * There can be arbitrary padding between the headers and buffers so | |
77 | * you should always use the appropriate qcom_scm_get_*_buffer() routines | |
78 | * to access the buffers in a safe manner. | |
79 | */ | |
80 | struct qcom_scm_command { | |
81 | __le32 len; | |
82 | __le32 buf_offset; | |
83 | __le32 resp_hdr_offset; | |
84 | __le32 id; | |
85 | __le32 buf[0]; | |
86 | }; | |
87 | ||
88 | /** | |
89 | * struct qcom_scm_response - one SCM response buffer | |
90 | * @len: total available memory for response | |
91 | * @buf_offset: start of response data relative to start of qcom_scm_response | |
92 | * @is_complete: indicates if the command has finished processing | |
93 | */ | |
94 | struct qcom_scm_response { | |
95 | __le32 len; | |
96 | __le32 buf_offset; | |
97 | __le32 is_complete; | |
98 | }; | |
99 | ||
100 | /** | |
101 | * alloc_qcom_scm_command() - Allocate an SCM command | |
102 | * @cmd_size: size of the command buffer | |
103 | * @resp_size: size of the response buffer | |
104 | * | |
105 | * Allocate an SCM command, including enough room for the command | |
106 | * and response headers as well as the command and response buffers. | |
107 | * | |
108 | * Returns a valid &qcom_scm_command on success or %NULL if the allocation fails. | |
109 | */ | |
110 | static struct qcom_scm_command *alloc_qcom_scm_command(size_t cmd_size, size_t resp_size) | |
111 | { | |
112 | struct qcom_scm_command *cmd; | |
113 | size_t len = sizeof(*cmd) + sizeof(struct qcom_scm_response) + cmd_size + | |
114 | resp_size; | |
115 | u32 offset; | |
116 | ||
117 | cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL); | |
118 | if (cmd) { | |
119 | cmd->len = cpu_to_le32(len); | |
120 | offset = offsetof(struct qcom_scm_command, buf); | |
121 | cmd->buf_offset = cpu_to_le32(offset); | |
122 | cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size); | |
123 | } | |
124 | return cmd; | |
125 | } | |
126 | ||
127 | /** | |
128 | * free_qcom_scm_command() - Free an SCM command | |
129 | * @cmd: command to free | |
130 | * | |
131 | * Free an SCM command. | |
132 | */ | |
133 | static inline void free_qcom_scm_command(struct qcom_scm_command *cmd) | |
134 | { | |
135 | kfree(cmd); | |
136 | } | |
137 | ||
138 | /** | |
139 | * qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response | |
140 | * @cmd: command | |
141 | * | |
142 | * Returns a pointer to a response for a command. | |
143 | */ | |
144 | static inline struct qcom_scm_response *qcom_scm_command_to_response( | |
145 | const struct qcom_scm_command *cmd) | |
146 | { | |
147 | return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset); | |
148 | } | |
149 | ||
150 | /** | |
151 | * qcom_scm_get_command_buffer() - Get a pointer to a command buffer | |
152 | * @cmd: command | |
153 | * | |
154 | * Returns a pointer to the command buffer of a command. | |
155 | */ | |
156 | static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd) | |
157 | { | |
158 | return (void *)cmd->buf; | |
159 | } | |
160 | ||
161 | /** | |
162 | * qcom_scm_get_response_buffer() - Get a pointer to a response buffer | |
163 | * @rsp: response | |
164 | * | |
165 | * Returns a pointer to a response buffer of a response. | |
166 | */ | |
167 | static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp) | |
168 | { | |
169 | return (void *)rsp + le32_to_cpu(rsp->buf_offset); | |
170 | } | |
171 | ||
172 | static int qcom_scm_remap_error(int err) | |
173 | { | |
174 | pr_err("qcom_scm_call failed with error code %d\n", err); | |
175 | switch (err) { | |
176 | case QCOM_SCM_ERROR: | |
177 | return -EIO; | |
178 | case QCOM_SCM_EINVAL_ADDR: | |
179 | case QCOM_SCM_EINVAL_ARG: | |
180 | return -EINVAL; | |
181 | case QCOM_SCM_EOPNOTSUPP: | |
182 | return -EOPNOTSUPP; | |
183 | case QCOM_SCM_ENOMEM: | |
184 | return -ENOMEM; | |
185 | } | |
186 | return -EINVAL; | |
187 | } | |
188 | ||
189 | static u32 smc(u32 cmd_addr) | |
190 | { | |
191 | int context_id; | |
192 | register u32 r0 asm("r0") = 1; | |
193 | register u32 r1 asm("r1") = (u32)&context_id; | |
194 | register u32 r2 asm("r2") = cmd_addr; | |
195 | do { | |
196 | asm volatile( | |
197 | __asmeq("%0", "r0") | |
198 | __asmeq("%1", "r0") | |
199 | __asmeq("%2", "r1") | |
200 | __asmeq("%3", "r2") | |
201 | #ifdef REQUIRES_SEC | |
202 | ".arch_extension sec\n" | |
203 | #endif | |
204 | "smc #0 @ switch to secure world\n" | |
205 | : "=r" (r0) | |
206 | : "r" (r0), "r" (r1), "r" (r2) | |
207 | : "r3"); | |
208 | } while (r0 == QCOM_SCM_INTERRUPTED); | |
209 | ||
210 | return r0; | |
211 | } | |
212 | ||
213 | static int __qcom_scm_call(const struct qcom_scm_command *cmd) | |
214 | { | |
215 | int ret; | |
216 | u32 cmd_addr = virt_to_phys(cmd); | |
217 | ||
218 | /* | |
219 | * Flush the command buffer so that the secure world sees | |
220 | * the correct data. | |
221 | */ | |
222 | __cpuc_flush_dcache_area((void *)cmd, cmd->len); | |
223 | outer_flush_range(cmd_addr, cmd_addr + cmd->len); | |
224 | ||
225 | ret = smc(cmd_addr); | |
226 | if (ret < 0) | |
227 | ret = qcom_scm_remap_error(ret); | |
228 | ||
229 | return ret; | |
230 | } | |
231 | ||
232 | static void qcom_scm_inv_range(unsigned long start, unsigned long end) | |
233 | { | |
234 | u32 cacheline_size, ctr; | |
235 | ||
236 | asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); | |
237 | cacheline_size = 4 << ((ctr >> 16) & 0xf); | |
238 | ||
239 | start = round_down(start, cacheline_size); | |
240 | end = round_up(end, cacheline_size); | |
241 | outer_inv_range(start, end); | |
242 | while (start < end) { | |
243 | asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) | |
244 | : "memory"); | |
245 | start += cacheline_size; | |
246 | } | |
247 | dsb(); | |
248 | isb(); | |
249 | } | |
250 | ||
251 | /** | |
252 | * qcom_scm_call() - Send an SCM command | |
253 | * @svc_id: service identifier | |
254 | * @cmd_id: command identifier | |
255 | * @cmd_buf: command buffer | |
256 | * @cmd_len: length of the command buffer | |
257 | * @resp_buf: response buffer | |
258 | * @resp_len: length of the response buffer | |
259 | * | |
260 | * Sends a command to the SCM and waits for the command to finish processing. | |
261 | * | |
262 | * A note on cache maintenance: | |
263 | * Note that any buffers that are expected to be accessed by the secure world | |
264 | * must be flushed before invoking qcom_scm_call and invalidated in the cache | |
265 | * immediately after qcom_scm_call returns. Cache maintenance on the command | |
266 | * and response buffers is taken care of by qcom_scm_call; however, callers are | |
267 | * responsible for any other cached buffers passed over to the secure world. | |
268 | */ | |
269 | static int qcom_scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, | |
270 | size_t cmd_len, void *resp_buf, size_t resp_len) | |
271 | { | |
272 | int ret; | |
273 | struct qcom_scm_command *cmd; | |
274 | struct qcom_scm_response *rsp; | |
275 | unsigned long start, end; | |
276 | ||
277 | cmd = alloc_qcom_scm_command(cmd_len, resp_len); | |
278 | if (!cmd) | |
279 | return -ENOMEM; | |
280 | ||
281 | cmd->id = cpu_to_le32((svc_id << 10) | cmd_id); | |
282 | if (cmd_buf) | |
283 | memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len); | |
284 | ||
285 | mutex_lock(&qcom_scm_lock); | |
286 | ret = __qcom_scm_call(cmd); | |
287 | mutex_unlock(&qcom_scm_lock); | |
288 | if (ret) | |
289 | goto out; | |
290 | ||
291 | rsp = qcom_scm_command_to_response(cmd); | |
292 | start = (unsigned long)rsp; | |
293 | ||
294 | do { | |
295 | qcom_scm_inv_range(start, start + sizeof(*rsp)); | |
296 | } while (!rsp->is_complete); | |
297 | ||
298 | end = (unsigned long)qcom_scm_get_response_buffer(rsp) + resp_len; | |
299 | qcom_scm_inv_range(start, end); | |
300 | ||
301 | if (resp_buf) | |
302 | memcpy(resp_buf, qcom_scm_get_response_buffer(rsp), resp_len); | |
303 | out: | |
304 | free_qcom_scm_command(cmd); | |
305 | return ret; | |
306 | } | |
307 | ||
308 | #define SCM_CLASS_REGISTER (0x2 << 8) | |
309 | #define SCM_MASK_IRQS BIT(5) | |
310 | #define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \ | |
311 | SCM_CLASS_REGISTER | \ | |
312 | SCM_MASK_IRQS | \ | |
313 | (n & 0xf)) | |
314 | ||
315 | /** | |
316 | * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument | |
317 | * @svc_id: service identifier | |
318 | * @cmd_id: command identifier | |
319 | * @arg1: first argument | |
320 | * | |
321 | * This shall only be used with commands that are guaranteed to be | |
322 | * uninterruptable, atomic and SMP safe. | |
323 | */ | |
324 | static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) | |
325 | { | |
326 | int context_id; | |
327 | ||
328 | register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1); | |
329 | register u32 r1 asm("r1") = (u32)&context_id; | |
330 | register u32 r2 asm("r2") = arg1; | |
331 | ||
332 | asm volatile( | |
333 | __asmeq("%0", "r0") | |
334 | __asmeq("%1", "r0") | |
335 | __asmeq("%2", "r1") | |
336 | __asmeq("%3", "r2") | |
337 | #ifdef REQUIRES_SEC | |
338 | ".arch_extension sec\n" | |
339 | #endif | |
340 | "smc #0 @ switch to secure world\n" | |
341 | : "=r" (r0) | |
342 | : "r" (r0), "r" (r1), "r" (r2) | |
343 | : "r3"); | |
344 | return r0; | |
345 | } | |
346 | ||
347 | u32 qcom_scm_get_version(void) | |
348 | { | |
349 | int context_id; | |
350 | static u32 version = -1; | |
351 | register u32 r0 asm("r0"); | |
352 | register u32 r1 asm("r1"); | |
353 | ||
354 | if (version != -1) | |
355 | return version; | |
356 | ||
357 | mutex_lock(&qcom_scm_lock); | |
358 | ||
359 | r0 = 0x1 << 8; | |
360 | r1 = (u32)&context_id; | |
361 | do { | |
362 | asm volatile( | |
363 | __asmeq("%0", "r0") | |
364 | __asmeq("%1", "r1") | |
365 | __asmeq("%2", "r0") | |
366 | __asmeq("%3", "r1") | |
367 | #ifdef REQUIRES_SEC | |
368 | ".arch_extension sec\n" | |
369 | #endif | |
370 | "smc #0 @ switch to secure world\n" | |
371 | : "=r" (r0), "=r" (r1) | |
372 | : "r" (r0), "r" (r1) | |
373 | : "r2", "r3"); | |
374 | } while (r0 == QCOM_SCM_INTERRUPTED); | |
375 | ||
376 | version = r1; | |
377 | mutex_unlock(&qcom_scm_lock); | |
378 | ||
379 | return version; | |
380 | } | |
381 | EXPORT_SYMBOL(qcom_scm_get_version); | |
382 | ||
383 | /* | |
384 | * Set the cold/warm boot address for one of the CPU cores. | |
385 | */ | |
386 | static int qcom_scm_set_boot_addr(u32 addr, int flags) | |
387 | { | |
388 | struct { | |
389 | __le32 flags; | |
390 | __le32 addr; | |
391 | } cmd; | |
392 | ||
393 | cmd.addr = cpu_to_le32(addr); | |
394 | cmd.flags = cpu_to_le32(flags); | |
395 | return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, | |
396 | &cmd, sizeof(cmd), NULL, 0); | |
397 | } | |
398 | ||
399 | /** | |
400 | * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus | |
401 | * @entry: Entry point function for the cpus | |
402 | * @cpus: The cpumask of cpus that will use the entry point | |
403 | * | |
404 | * Set the cold boot address of the cpus. Any cpu outside the supported | |
405 | * range would be removed from the cpu present mask. | |
406 | */ | |
407 | int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) | |
408 | { | |
409 | int flags = 0; | |
410 | int cpu; | |
411 | int scm_cb_flags[] = { | |
412 | QCOM_SCM_FLAG_COLDBOOT_CPU0, | |
413 | QCOM_SCM_FLAG_COLDBOOT_CPU1, | |
414 | QCOM_SCM_FLAG_COLDBOOT_CPU2, | |
415 | QCOM_SCM_FLAG_COLDBOOT_CPU3, | |
416 | }; | |
417 | ||
418 | if (!cpus || (cpus && cpumask_empty(cpus))) | |
419 | return -EINVAL; | |
420 | ||
421 | for_each_cpu(cpu, cpus) { | |
422 | if (cpu < ARRAY_SIZE(scm_cb_flags)) | |
423 | flags |= scm_cb_flags[cpu]; | |
424 | else | |
425 | set_cpu_present(cpu, false); | |
426 | } | |
427 | ||
428 | return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); | |
429 | } | |
430 | ||
431 | /** | |
432 | * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus | |
433 | * @entry: Entry point function for the cpus | |
434 | * @cpus: The cpumask of cpus that will use the entry point | |
435 | * | |
436 | * Set the Linux entry point for the SCM to transfer control to when coming | |
437 | * out of a power down. CPU power down may be executed on cpuidle or hotplug. | |
438 | */ | |
439 | int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) | |
440 | { | |
441 | int ret; | |
442 | int flags = 0; | |
443 | int cpu; | |
444 | ||
445 | /* | |
446 | * Reassign only if we are switching from hotplug entry point | |
447 | * to cpuidle entry point or vice versa. | |
448 | */ | |
449 | for_each_cpu(cpu, cpus) { | |
450 | if (entry == qcom_scm_wb[cpu].entry) | |
451 | continue; | |
452 | flags |= qcom_scm_wb[cpu].flag; | |
453 | } | |
454 | ||
455 | /* No change in entry function */ | |
456 | if (!flags) | |
457 | return 0; | |
458 | ||
459 | ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); | |
460 | if (!ret) { | |
461 | for_each_cpu(cpu, cpus) | |
462 | qcom_scm_wb[cpu].entry = entry; | |
463 | } | |
464 | ||
465 | return ret; | |
466 | } | |
467 | ||
468 | /** | |
469 | * qcom_scm_cpu_power_down() - Power down the cpu | |
470 | * @flags - Flags to flush cache | |
471 | * | |
472 | * This is an end point to power down cpu. If there was a pending interrupt, | |
473 | * the control would return from this function, otherwise, the cpu jumps to the | |
474 | * warm boot entry point set for this cpu upon reset. | |
475 | */ | |
476 | void __qcom_scm_cpu_power_down(u32 flags) | |
477 | { | |
478 | qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, | |
479 | flags & QCOM_SCM_FLUSH_FLAG_MASK); | |
480 | } | |
9626b699 | 481 | |
482 | int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id) | |
483 | { | |
484 | int ret; | |
485 | u32 svc_cmd = (svc_id << 10) | cmd_id; | |
486 | u32 ret_val = 0; | |
487 | ||
488 | ret = qcom_scm_call(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, &svc_cmd, | |
489 | sizeof(svc_cmd), &ret_val, sizeof(ret_val)); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | return ret_val; | |
494 | } | |
495 | ||
496 | int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) | |
497 | { | |
498 | if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) | |
499 | return -ERANGE; | |
500 | ||
501 | return qcom_scm_call(QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, | |
502 | req, req_cnt * sizeof(*req), resp, sizeof(*resp)); | |
503 | } |