[deliverable/linux.git] / drivers / gpio / gpio-ath79.c

/*
 *  Atheros AR71XX/AR724X/AR913X GPIO API support
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/gpio/driver.h>
#include <linux/platform_data/gpio-ath79.h>
#include <linux/of_device.h>

#include <asm/mach-ath79/ar71xx_regs.h>

struct ath79_gpio_ctrl {
	struct gpio_chip chip;
	void __iomem *base;
	spinlock_t lock;
};

#define to_ath79_gpio_ctrl(c) container_of(c, struct ath79_gpio_ctrl, chip)

static void ath79_gpio_set_value(struct gpio_chip *chip,
				unsigned gpio, int value)
{
	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);

	if (value)
		__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET);
	else
		__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR);
}

static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);

	return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
}

static int ath79_gpio_direction_input(struct gpio_chip *chip,
				       unsigned offset)
{
	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static int ath79_gpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	if (value)
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
	else
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	if (value)
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
	else
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static const struct gpio_chip ath79_gpio_chip = {
	.label			= "ath79",
	.get			= ath79_gpio_get_value,
	.set			= ath79_gpio_set_value,
	.direction_input	= ath79_gpio_direction_input,
	.direction_output	= ath79_gpio_direction_output,
	.base			= 0,
};

static const struct of_device_id ath79_gpio_of_match[] = {
	{ .compatible = "qca,ar7100-gpio" },
	{ .compatible = "qca,ar9340-gpio" },
	{},
};

static int ath79_gpio_probe(struct platform_device *pdev)
{
	struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
	struct device_node *np = pdev->dev.of_node;
	struct ath79_gpio_ctrl *ctrl;
	struct resource *res;
	u32 ath79_gpio_count;
	bool oe_inverted;
	int err;

	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl)
		return -ENOMEM;

	if (np) {
		err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
		if (err) {
			dev_err(&pdev->dev, "ngpios property is not valid\n");
			return err;
		}
		if (ath79_gpio_count >= 32) {
			dev_err(&pdev->dev, "ngpios must be less than 32\n");
			return -EINVAL;
		}
		oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	} else if (pdata) {
		ath79_gpio_count = pdata->ngpios;
		oe_inverted = pdata->oe_inverted;
	} else {
		dev_err(&pdev->dev, "No DT node or platform data found\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ctrl->base = devm_ioremap_nocache(
		&pdev->dev, res->start, resource_size(res));
	if (!ctrl->base)
		return -ENOMEM;

	spin_lock_init(&ctrl->lock);
	memcpy(&ctrl->chip, &ath79_gpio_chip, sizeof(ctrl->chip));
	ctrl->chip.dev = &pdev->dev;
	ctrl->chip.ngpio = ath79_gpio_count;
	if (oe_inverted) {
		ctrl->chip.direction_input = ar934x_gpio_direction_input;
		ctrl->chip.direction_output = ar934x_gpio_direction_output;
	}

	err = gpiochip_add(&ctrl->chip);
	if (err) {
		dev_err(&pdev->dev,
			"cannot add AR71xx GPIO chip, error=%d", err);
		return err;
	}

	return 0;
}

static struct platform_driver ath79_gpio_driver = {
	.driver = {
		.name = "ath79-gpio",
		.of_match_table	= ath79_gpio_of_match,
	},
	.probe = ath79_gpio_probe,
};

module_platform_driver(ath79_gpio_driver);
Commit	Line	Data
6eae43c5 GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X GPIO API support
	3	*
5b5b544e GJ	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5b5b544e GJ	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6eae43c5 GJ	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6eae43c5 GJ	7	*
5b5b544e GJ	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
5b5b544e GJ	9	*
6eae43c5 GJ	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
49a5bd88	15	#include <linux/gpio/driver.h>
2ddf3a79 AB	16	#include <linux/platform_data/gpio-ath79.h>
2ddf3a79 AB	17	#include <linux/of_device.h>
6eae43c5 GJ	18
6eae43c5 GJ	19	#include <asm/mach-ath79/ar71xx_regs.h>
6eae43c5	20
49a5bd88 AB	21	struct ath79_gpio_ctrl {
	22	struct gpio_chip chip;
	23	void __iomem *base;
	24	spinlock_t lock;
	25	};
	26
	27	#define to_ath79_gpio_ctrl(c) container_of(c, struct ath79_gpio_ctrl, chip)
6eae43c5	28
49a5bd88 AB	29	static void ath79_gpio_set_value(struct gpio_chip *chip,
49a5bd88 AB	30	unsigned gpio, int value)
6eae43c5	31	{
49a5bd88	32	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
6eae43c5 GJ	33
6eae43c5 GJ	34	if (value)
49a5bd88	35	__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET);
6eae43c5	36	else
49a5bd88	37	__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR);
6eae43c5 GJ	38	}
6eae43c5 GJ	39
49a5bd88	40	static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
6eae43c5	41	{
49a5bd88	42	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
6eae43c5	43
49a5bd88	44	return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
6eae43c5 GJ	45	}
	46
	47	static int ath79_gpio_direction_input(struct gpio_chip *chip,
	48	unsigned offset)
	49	{
49a5bd88	50	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
6eae43c5 GJ	51	unsigned long flags;
6eae43c5 GJ	52
49a5bd88	53	spin_lock_irqsave(&ctrl->lock, flags);
6eae43c5	54
49a5bd88 AB	55	__raw_writel(
	56	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
	57	ctrl->base + AR71XX_GPIO_REG_OE);
6eae43c5	58
49a5bd88	59	spin_unlock_irqrestore(&ctrl->lock, flags);
6eae43c5 GJ	60
	61	return 0;
	62	}
	63
	64	static int ath79_gpio_direction_output(struct gpio_chip *chip,
	65	unsigned offset, int value)
	66	{
49a5bd88	67	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
6eae43c5 GJ	68	unsigned long flags;
6eae43c5 GJ	69
49a5bd88	70	spin_lock_irqsave(&ctrl->lock, flags);
6eae43c5 GJ	71
6eae43c5 GJ	72	if (value)
49a5bd88	73	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
6eae43c5	74	else
49a5bd88	75	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
6eae43c5	76
49a5bd88 AB	77	__raw_writel(
	78	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) \| BIT(offset),
	79	ctrl->base + AR71XX_GPIO_REG_OE);
6eae43c5	80
49a5bd88	81	spin_unlock_irqrestore(&ctrl->lock, flags);
6eae43c5 GJ	82
	83	return 0;
	84	}
	85
5b5b544e GJ	86	static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
5b5b544e GJ	87	{
49a5bd88	88	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
5b5b544e GJ	89	unsigned long flags;
5b5b544e GJ	90
49a5bd88	91	spin_lock_irqsave(&ctrl->lock, flags);
5b5b544e	92
49a5bd88 AB	93	__raw_writel(
	94	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) \| BIT(offset),
	95	ctrl->base + AR71XX_GPIO_REG_OE);
5b5b544e	96
49a5bd88	97	spin_unlock_irqrestore(&ctrl->lock, flags);
5b5b544e GJ	98
	99	return 0;
	100	}
	101
	102	static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	103	int value)
	104	{
49a5bd88	105	struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
5b5b544e GJ	106	unsigned long flags;
5b5b544e GJ	107
49a5bd88	108	spin_lock_irqsave(&ctrl->lock, flags);
5b5b544e GJ	109
5b5b544e GJ	110	if (value)
49a5bd88	111	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
5b5b544e	112	else
49a5bd88	113	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
5b5b544e	114
49a5bd88 AB	115	__raw_writel(
	116	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & BIT(offset),
	117	ctrl->base + AR71XX_GPIO_REG_OE);
5b5b544e	118
49a5bd88	119	spin_unlock_irqrestore(&ctrl->lock, flags);
5b5b544e GJ	120
	121	return 0;
	122	}
	123
49a5bd88	124	static const struct gpio_chip ath79_gpio_chip = {
6eae43c5 GJ	125	.label = "ath79",
	126	.get = ath79_gpio_get_value,
	127	.set = ath79_gpio_set_value,
	128	.direction_input = ath79_gpio_direction_input,
	129	.direction_output = ath79_gpio_direction_output,
	130	.base = 0,
	131	};
	132
2ddf3a79 AB	133	static const struct of_device_id ath79_gpio_of_match[] = {
	134	{ .compatible = "qca,ar7100-gpio" },
	135	{ .compatible = "qca,ar9340-gpio" },
	136	{},
	137	};
	138
	139	static int ath79_gpio_probe(struct platform_device *pdev)
6eae43c5	140	{
2ddf3a79 AB	141	struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
2ddf3a79 AB	142	struct device_node *np = pdev->dev.of_node;
49a5bd88	143	struct ath79_gpio_ctrl *ctrl;
2ddf3a79	144	struct resource *res;
49a5bd88	145	u32 ath79_gpio_count;
2ddf3a79	146	bool oe_inverted;
6eae43c5 GJ	147	int err;
6eae43c5 GJ	148
49a5bd88 AB	149	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
	150	if (!ctrl)
	151	return -ENOMEM;
	152
2ddf3a79 AB	153	if (np) {
	154	err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
	155	if (err) {
	156	dev_err(&pdev->dev, "ngpios property is not valid\n");
	157	return err;
	158	}
	159	if (ath79_gpio_count >= 32) {
	160	dev_err(&pdev->dev, "ngpios must be less than 32\n");
	161	return -EINVAL;
	162	}
	163	oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	164	} else if (pdata) {
	165	ath79_gpio_count = pdata->ngpios;
	166	oe_inverted = pdata->oe_inverted;
	167	} else {
	168	dev_err(&pdev->dev, "No DT node or platform data found\n");
	169	return -EINVAL;
	170	}
	171
	172	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
49a5bd88	173	ctrl->base = devm_ioremap_nocache(
2ddf3a79	174	&pdev->dev, res->start, resource_size(res));
49a5bd88	175	if (!ctrl->base)
2ddf3a79	176	return -ENOMEM;
6eae43c5	177
49a5bd88 AB	178	spin_lock_init(&ctrl->lock);
	179	memcpy(&ctrl->chip, &ath79_gpio_chip, sizeof(ctrl->chip));
	180	ctrl->chip.dev = &pdev->dev;
	181	ctrl->chip.ngpio = ath79_gpio_count;
2ddf3a79	182	if (oe_inverted) {
49a5bd88 AB	183	ctrl->chip.direction_input = ar934x_gpio_direction_input;
49a5bd88 AB	184	ctrl->chip.direction_output = ar934x_gpio_direction_output;
5b5b544e	185	}
6eae43c5	186
49a5bd88	187	err = gpiochip_add(&ctrl->chip);
2ddf3a79 AB	188	if (err) {
	189	dev_err(&pdev->dev,
	190	"cannot add AR71xx GPIO chip, error=%d", err);
	191	return err;
	192	}
	193
	194	return 0;
6eae43c5 GJ	195	}
6eae43c5 GJ	196
2ddf3a79 AB	197	static struct platform_driver ath79_gpio_driver = {
	198	.driver = {
	199	.name = "ath79-gpio",
	200	.of_match_table = ath79_gpio_of_match,
	201	},
	202	.probe = ath79_gpio_probe,
	203	};
	204
	205	module_platform_driver(ath79_gpio_driver);