[deliverable/linux.git] / drivers / gpio / gpio-crystalcove.c

/*
 * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
 *
 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Author: Yang, Bin <bin.yang@intel.com>
 */

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/seq_file.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/mfd/intel_soc_pmic.h>

#define CRYSTALCOVE_GPIO_NUM	16
#define CRYSTALCOVE_VGPIO_NUM	95

#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define GPIO0IRQ		0x0b
#define GPIO1IRQ		0x0c
#define MGPIO0IRQS0		0x19
#define MGPIO1IRQS0		0x1a
#define MGPIO0IRQSX		0x1b
#define MGPIO1IRQSX		0x1c
#define GPIO0P0CTLO		0x2b
#define GPIO0P0CTLI		0x33
#define GPIO1P0CTLO		0x3b
#define GPIO1P0CTLI		0x43
#define GPIOPANELCTL		0x52

#define CTLI_INTCNT_DIS		(0)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_CMOS		(0)
#define CTLO_DRV_OD		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDW		(0)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDW		(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
};

/**
 * struct crystalcove_gpio - Crystal Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @regmap: the regmap from the parent device.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt_value: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct crystalcove_gpio {
	struct mutex buslock; /* irq_bus_lock */
	struct gpio_chip chip;
	struct regmap *regmap;
	int update;
	int intcnt_value;
	bool set_irq_mask;
};

static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
{
	return container_of(gc, struct crystalcove_gpio, chip);
}

static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
	int reg;

	if (gpio == 94) {
		return GPIOPANELCTL;
	}

	if (reg_type == CTRL_IN) {
		if (gpio < 8)
			reg = GPIO0P0CTLI;
		else
			reg = GPIO1P0CTLI;
	} else {
		if (gpio < 8)
			reg = GPIO0P0CTLO;
		else
			reg = GPIO1P0CTLO;
	}

	return reg + gpio % 8;
}

static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
					int gpio)
{
	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	int mask = BIT(gpio % 8);

	if (cg->set_irq_mask)
		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
	else
		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
}

static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
{
	int reg = to_reg(gpio, CTRL_IN);

	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
}

static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
{
	struct crystalcove_gpio *cg = to_cg(chip);

	if (gpio > CRYSTALCOVE_VGPIO_NUM)
		return 0;

	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
			    CTLO_INPUT_SET);
}

static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
				    int value)
{
	struct crystalcove_gpio *cg = to_cg(chip);

	if (gpio > CRYSTALCOVE_VGPIO_NUM)
		return 0;

	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
			    CTLO_OUTPUT_SET | value);
}

static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
	struct crystalcove_gpio *cg = to_cg(chip);
	int ret;
	unsigned int val;

	if (gpio > CRYSTALCOVE_VGPIO_NUM)
		return 0;

	ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void crystalcove_gpio_set(struct gpio_chip *chip,
				 unsigned gpio, int value)
{
	struct crystalcove_gpio *cg = to_cg(chip);

	if (gpio > CRYSTALCOVE_VGPIO_NUM)
		return;

	if (value)
		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
	else
		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
}

static int crystalcove_irq_type(struct irq_data *data, unsigned type)
{
	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));

	switch (type) {
	case IRQ_TYPE_NONE:
		cg->intcnt_value = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		cg->intcnt_value = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		cg->intcnt_value = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		cg->intcnt_value = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	cg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void crystalcove_bus_lock(struct irq_data *data)
{
	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));

	mutex_lock(&cg->buslock);
}

static void crystalcove_bus_sync_unlock(struct irq_data *data)
{
	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
	int gpio = data->hwirq;

	if (cg->update & UPDATE_IRQ_TYPE)
		crystalcove_update_irq_ctrl(cg, gpio);
	if (cg->update & UPDATE_IRQ_MASK)
		crystalcove_update_irq_mask(cg, gpio);
	cg->update = 0;

	mutex_unlock(&cg->buslock);
}

static void crystalcove_irq_unmask(struct irq_data *data)
{
	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));

	cg->set_irq_mask = false;
	cg->update |= UPDATE_IRQ_MASK;
}

static void crystalcove_irq_mask(struct irq_data *data)
{
	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));

	cg->set_irq_mask = true;
	cg->update |= UPDATE_IRQ_MASK;
}

static struct irq_chip crystalcove_irqchip = {
	.name			= "Crystal Cove",
	.irq_mask		= crystalcove_irq_mask,
	.irq_unmask		= crystalcove_irq_unmask,
	.irq_set_type		= crystalcove_irq_type,
	.irq_bus_lock		= crystalcove_bus_lock,
	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
};

static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
{
	struct crystalcove_gpio *cg = data;
	unsigned int p0, p1;
	int pending;
	int gpio;
	unsigned int virq;

	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
		return IRQ_NONE;

	regmap_write(cg->regmap, GPIO0IRQ, p0);
	regmap_write(cg->regmap, GPIO1IRQ, p1);

	pending = p0 | p1 << 8;

	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
		if (pending & BIT(gpio)) {
			virq = irq_find_mapping(cg->chip.irqdomain, gpio);
			handle_nested_irq(virq);
		}
	}

	return IRQ_HANDLED;
}

static void crystalcove_gpio_dbg_show(struct seq_file *s,
				      struct gpio_chip *chip)
{
	struct crystalcove_gpio *cg = to_cg(chip);
	int gpio, offset;
	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;

	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
			    &mirqs0);
		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
			    &mirqsx);
		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
			    &irq);

		offset = gpio % 8;
		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
			   irq & BIT(offset) ? "pending" : "       ");
	}
}

static int crystalcove_gpio_probe(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct crystalcove_gpio *cg;
	int retval;
	struct device *dev = pdev->dev.parent;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	if (irq < 0)
		return irq;

	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
	if (!cg)
		return -ENOMEM;

	platform_set_drvdata(pdev, cg);

	mutex_init(&cg->buslock);
	cg->chip.label = KBUILD_MODNAME;
	cg->chip.direction_input = crystalcove_gpio_dir_in;
	cg->chip.direction_output = crystalcove_gpio_dir_out;
	cg->chip.get = crystalcove_gpio_get;
	cg->chip.set = crystalcove_gpio_set;
	cg->chip.base = -1;
	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
	cg->chip.can_sleep = true;
	cg->chip.dev = dev;
	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
	cg->regmap = pmic->regmap;

	retval = gpiochip_add(&cg->chip);
	if (retval) {
		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
		return retval;
	}

	gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
			     handle_simple_irq, IRQ_TYPE_NONE);

	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
				      IRQF_ONESHOT, KBUILD_MODNAME, cg);

	if (retval) {
		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
		goto out_remove_gpio;
	}

	return 0;

out_remove_gpio:
	gpiochip_remove(&cg->chip);
	return retval;
}

static int crystalcove_gpio_remove(struct platform_device *pdev)
{
	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
	int irq = platform_get_irq(pdev, 0);

	gpiochip_remove(&cg->chip);
	if (irq >= 0)
		free_irq(irq, cg);
	return 0;
}

static struct platform_driver crystalcove_gpio_driver = {
	.probe = crystalcove_gpio_probe,
	.remove = crystalcove_gpio_remove,
	.driver = {
		.name = "crystal_cove_gpio",
	},
};

module_platform_driver(crystalcove_gpio_driver);

MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
104fb1d5 ZL	1	/*
	2	* gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
	3	*
	4	* Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License version
	8	* 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* Author: Yang, Bin <bin.yang@intel.com>
	16	*/
	17
	18	#include <linux/interrupt.h>
ade52af9	19	#include <linux/module.h>
104fb1d5 ZL	20	#include <linux/platform_device.h>
104fb1d5 ZL	21	#include <linux/gpio.h>
8dbf2aa3	22	#include <linux/seq_file.h>
104fb1d5 ZL	23	#include <linux/bitops.h>
	24	#include <linux/regmap.h>
	25	#include <linux/mfd/intel_soc_pmic.h>
	26
	27	#define CRYSTALCOVE_GPIO_NUM 16
e189ca56	28	#define CRYSTALCOVE_VGPIO_NUM 95
104fb1d5 ZL	29
	30	#define UPDATE_IRQ_TYPE BIT(0)
	31	#define UPDATE_IRQ_MASK BIT(1)
	32
	33	#define GPIO0IRQ 0x0b
	34	#define GPIO1IRQ 0x0c
	35	#define MGPIO0IRQS0 0x19
	36	#define MGPIO1IRQS0 0x1a
	37	#define MGPIO0IRQSX 0x1b
	38	#define MGPIO1IRQSX 0x1c
	39	#define GPIO0P0CTLO 0x2b
	40	#define GPIO0P0CTLI 0x33
	41	#define GPIO1P0CTLO 0x3b
	42	#define GPIO1P0CTLI 0x43
e189ca56	43	#define GPIOPANELCTL 0x52
104fb1d5 ZL	44
	45	#define CTLI_INTCNT_DIS (0)
	46	#define CTLI_INTCNT_NE (1 << 1)
	47	#define CTLI_INTCNT_PE (2 << 1)
	48	#define CTLI_INTCNT_BE (3 << 1)
	49
	50	#define CTLO_DIR_IN (0)
	51	#define CTLO_DIR_OUT (1 << 5)
	52
	53	#define CTLO_DRV_CMOS (0)
	54	#define CTLO_DRV_OD (1 << 4)
	55
	56	#define CTLO_DRV_REN (1 << 3)
	57
	58	#define CTLO_RVAL_2KDW (0)
	59	#define CTLO_RVAL_2KUP (1 << 1)
	60	#define CTLO_RVAL_50KDW (2 << 1)
	61	#define CTLO_RVAL_50KUP (3 << 1)
	62
	63	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
	64	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
	65
	66	enum ctrl_register {
	67	CTRL_IN,
	68	CTRL_OUT,
	69	};
	70
	71	/**
	72	* struct crystalcove_gpio - Crystal Cove GPIO controller
	73	* @buslock: for bus lock/sync and unlock.
	74	* @chip: the abstract gpio_chip structure.
	75	* @regmap: the regmap from the parent device.
	76	* @update: pending IRQ setting update, to be written to the chip upon unlock.
	77	* @intcnt_value: the Interrupt Detect value to be written.
	78	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
	79	*/
	80	struct crystalcove_gpio {
	81	struct mutex buslock; /* irq_bus_lock */
	82	struct gpio_chip chip;
	83	struct regmap *regmap;
	84	int update;
	85	int intcnt_value;
	86	bool set_irq_mask;
	87	};
	88
	89	static inline struct crystalcove_gpio to_cg(struct gpio_chip gc)
	90	{
	91	return container_of(gc, struct crystalcove_gpio, chip);
	92	}
	93
	94	static inline int to_reg(int gpio, enum ctrl_register reg_type)
	95	{
	96	int reg;
	97
e189ca56 SK	98	if (gpio == 94) {
	99	return GPIOPANELCTL;
	100	}
	101
104fb1d5 ZL	102	if (reg_type == CTRL_IN) {
	103	if (gpio < 8)
	104	reg = GPIO0P0CTLI;
	105	else
	106	reg = GPIO1P0CTLI;
	107	} else {
	108	if (gpio < 8)
	109	reg = GPIO0P0CTLO;
	110	else
	111	reg = GPIO1P0CTLO;
	112	}
	113
	114	return reg + gpio % 8;
	115	}
	116
	117	static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
	118	int gpio)
	119	{
	120	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	121	int mask = BIT(gpio % 8);
	122
	123	if (cg->set_irq_mask)
	124	regmap_update_bits(cg->regmap, mirqs0, mask, mask);
	125	else
	126	regmap_update_bits(cg->regmap, mirqs0, mask, 0);
	127	}
	128
	129	static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
	130	{
	131	int reg = to_reg(gpio, CTRL_IN);
	132
	133	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
	134	}
	135
	136	static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
	137	{
	138	struct crystalcove_gpio *cg = to_cg(chip);
	139
dcdc3018 AL	140	if (gpio > CRYSTALCOVE_VGPIO_NUM)
	141	return 0;
	142
104fb1d5 ZL	143	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
	144	CTLO_INPUT_SET);
	145	}
	146
	147	static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
	148	int value)
	149	{
	150	struct crystalcove_gpio *cg = to_cg(chip);
	151
dcdc3018 AL	152	if (gpio > CRYSTALCOVE_VGPIO_NUM)
	153	return 0;
	154
104fb1d5 ZL	155	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
	156	CTLO_OUTPUT_SET \| value);
	157	}
	158
	159	static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
	160	{
	161	struct crystalcove_gpio *cg = to_cg(chip);
	162	int ret;
	163	unsigned int val;
	164
dcdc3018 AL	165	if (gpio > CRYSTALCOVE_VGPIO_NUM)
	166	return 0;
	167
104fb1d5 ZL	168	ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
	169	if (ret)
	170	return ret;
	171
	172	return val & 0x1;
	173	}
	174
	175	static void crystalcove_gpio_set(struct gpio_chip *chip,
	176	unsigned gpio, int value)
	177	{
	178	struct crystalcove_gpio *cg = to_cg(chip);
	179
dcdc3018 AL	180	if (gpio > CRYSTALCOVE_VGPIO_NUM)
	181	return;
	182
104fb1d5 ZL	183	if (value)
	184	regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
	185	else
	186	regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
	187	}
	188
	189	static int crystalcove_irq_type(struct irq_data *data, unsigned type)
	190	{
	191	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
	192
	193	switch (type) {
	194	case IRQ_TYPE_NONE:
	195	cg->intcnt_value = CTLI_INTCNT_DIS;
	196	break;
	197	case IRQ_TYPE_EDGE_BOTH:
	198	cg->intcnt_value = CTLI_INTCNT_BE;
	199	break;
	200	case IRQ_TYPE_EDGE_RISING:
	201	cg->intcnt_value = CTLI_INTCNT_PE;
	202	break;
	203	case IRQ_TYPE_EDGE_FALLING:
	204	cg->intcnt_value = CTLI_INTCNT_NE;
	205	break;
	206	default:
	207	return -EINVAL;
	208	}
	209
	210	cg->update \|= UPDATE_IRQ_TYPE;
	211
	212	return 0;
	213	}
	214
	215	static void crystalcove_bus_lock(struct irq_data *data)
	216	{
	217	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
	218
	219	mutex_lock(&cg->buslock);
	220	}
	221
	222	static void crystalcove_bus_sync_unlock(struct irq_data *data)
	223	{
	224	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
	225	int gpio = data->hwirq;
	226
	227	if (cg->update & UPDATE_IRQ_TYPE)
	228	crystalcove_update_irq_ctrl(cg, gpio);
	229	if (cg->update & UPDATE_IRQ_MASK)
	230	crystalcove_update_irq_mask(cg, gpio);
	231	cg->update = 0;
	232
	233	mutex_unlock(&cg->buslock);
	234	}
	235
	236	static void crystalcove_irq_unmask(struct irq_data *data)
	237	{
	238	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
	239
	240	cg->set_irq_mask = false;
	241	cg->update \|= UPDATE_IRQ_MASK;
	242	}
	243
	244	static void crystalcove_irq_mask(struct irq_data *data)
	245	{
	246	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
247
248	cg->set_irq_mask = true;
249	cg->update \|= UPDATE_IRQ_MASK;
250	}
251
252	static struct irq_chip crystalcove_irqchip = {
253	.name = "Crystal Cove",
254	.irq_mask = crystalcove_irq_mask,
255	.irq_unmask = crystalcove_irq_unmask,
256	.irq_set_type = crystalcove_irq_type,
257	.irq_bus_lock = crystalcove_bus_lock,
258	.irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
259	};
260
261	static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
262	{
263	struct crystalcove_gpio *cg = data;
264	unsigned int p0, p1;
265	int pending;
266	int gpio;
267	unsigned int virq;
268
269	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) \|\|
270	regmap_read(cg->regmap, GPIO1IRQ, &p1))
271	return IRQ_NONE;
272
273	regmap_write(cg->regmap, GPIO0IRQ, p0);
274	regmap_write(cg->regmap, GPIO1IRQ, p1);
275
276	pending = p0 \| p1 << 8;
277
dcdc3018	278	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
104fb1d5 ZL	279	if (pending & BIT(gpio)) {
104fb1d5 ZL	280	virq = irq_find_mapping(cg->chip.irqdomain, gpio);
e733a2fb	281	handle_nested_irq(virq);
104fb1d5 ZL	282	}
	283	}
	284
	285	return IRQ_HANDLED;
	286	}
	287
	288	static void crystalcove_gpio_dbg_show(struct seq_file *s,
	289	struct gpio_chip *chip)
	290	{
	291	struct crystalcove_gpio *cg = to_cg(chip);
	292	int gpio, offset;
	293	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
	294
dcdc3018	295	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
104fb1d5 ZL	296	regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
	297	regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
	298	regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
	299	&mirqs0);
	300	regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
	301	&mirqsx);
	302	regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
	303	&irq);
	304
	305	offset = gpio % 8;
	306	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
	307	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
	308	ctli & 0x1 ? "hi" : "lo",
	309	ctli & CTLI_INTCNT_NE ? "fall" : " ",
	310	ctli & CTLI_INTCNT_PE ? "rise" : " ",
	311	ctlo,
	312	mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
	313	mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
	314	irq & BIT(offset) ? "pending" : " ");
	315	}
	316	}
	317
	318	static int crystalcove_gpio_probe(struct platform_device *pdev)
	319	{
	320	int irq = platform_get_irq(pdev, 0);
	321	struct crystalcove_gpio *cg;
	322	int retval;
	323	struct device *dev = pdev->dev.parent;
	324	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	325
	326	if (irq < 0)
	327	return irq;
	328
	329	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
	330	if (!cg)
	331	return -ENOMEM;
	332
	333	platform_set_drvdata(pdev, cg);
	334
	335	mutex_init(&cg->buslock);
	336	cg->chip.label = KBUILD_MODNAME;
	337	cg->chip.direction_input = crystalcove_gpio_dir_in;
	338	cg->chip.direction_output = crystalcove_gpio_dir_out;
	339	cg->chip.get = crystalcove_gpio_get;
	340	cg->chip.set = crystalcove_gpio_set;
	341	cg->chip.base = -1;
dcdc3018	342	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
104fb1d5 ZL	343	cg->chip.can_sleep = true;
	344	cg->chip.dev = dev;
	345	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
	346	cg->regmap = pmic->regmap;
	347
	348	retval = gpiochip_add(&cg->chip);
	349	if (retval) {
	350	dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
	351	return retval;
	352	}
	353
	354	gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
	355	handle_simple_irq, IRQ_TYPE_NONE);
	356
	357	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
	358	IRQF_ONESHOT, KBUILD_MODNAME, cg);
	359
	360	if (retval) {
	361	dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
	362	goto out_remove_gpio;
	363	}
	364
	365	return 0;
	366
	367	out_remove_gpio:
da26d5d8	368	gpiochip_remove(&cg->chip);
104fb1d5 ZL	369	return retval;
	370	}
	371
	372	static int crystalcove_gpio_remove(struct platform_device *pdev)
	373	{
	374	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
	375	int irq = platform_get_irq(pdev, 0);
104fb1d5	376
da26d5d8	377	gpiochip_remove(&cg->chip);
104fb1d5 ZL	378	if (irq >= 0)
104fb1d5 ZL	379	free_irq(irq, cg);
da26d5d8	380	return 0;
104fb1d5 ZL	381	}
	382
	383	static struct platform_driver crystalcove_gpio_driver = {
	384	.probe = crystalcove_gpio_probe,
	385	.remove = crystalcove_gpio_remove,
	386	.driver = {
	387	.name = "crystal_cove_gpio",
104fb1d5 ZL	388	},
	389	};
	390
	391	module_platform_driver(crystalcove_gpio_driver);
	392
	393	MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
	394	MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
	395	MODULE_LICENSE("GPL v2");