[deliverable/linux.git] / drivers / gpio / gpio-dln2.c

/*
 * Driver for the Diolan DLN-2 USB-GPIO adapter
 *
 * Copyright (c) 2014 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation, version 2.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/mfd/dln2.h>

#define DLN2_GPIO_ID			0x01

#define DLN2_GPIO_GET_PIN_COUNT		DLN2_CMD(0x01, DLN2_GPIO_ID)
#define DLN2_GPIO_SET_DEBOUNCE		DLN2_CMD(0x04, DLN2_GPIO_ID)
#define DLN2_GPIO_GET_DEBOUNCE		DLN2_CMD(0x05, DLN2_GPIO_ID)
#define DLN2_GPIO_PORT_GET_VAL		DLN2_CMD(0x06, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_VAL		DLN2_CMD(0x0B, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_OUT_VAL	DLN2_CMD(0x0C, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_OUT_VAL	DLN2_CMD(0x0D, DLN2_GPIO_ID)
#define DLN2_GPIO_CONDITION_MET_EV	DLN2_CMD(0x0F, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_ENABLE		DLN2_CMD(0x10, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_DISABLE		DLN2_CMD(0x11, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_DIRECTION	DLN2_CMD(0x13, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_DIRECTION	DLN2_CMD(0x14, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_EVENT_CFG	DLN2_CMD(0x1E, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_EVENT_CFG	DLN2_CMD(0x1F, DLN2_GPIO_ID)

#define DLN2_GPIO_EVENT_NONE		0
#define DLN2_GPIO_EVENT_CHANGE		1
#define DLN2_GPIO_EVENT_LVL_HIGH	2
#define DLN2_GPIO_EVENT_LVL_LOW		3
#define DLN2_GPIO_EVENT_CHANGE_RISING	0x11
#define DLN2_GPIO_EVENT_CHANGE_FALLING  0x21
#define DLN2_GPIO_EVENT_MASK		0x0F

#define DLN2_GPIO_MAX_PINS 32

struct dln2_irq_work {
	struct work_struct work;
	struct dln2_gpio *dln2;
	int pin;
	int type;
};

struct dln2_gpio {
	struct platform_device *pdev;
	struct gpio_chip gpio;

	/*
	 * Cache pin direction to save us one transfer, since the hardware has
	 * separate commands to read the in and out values.
	 */
	DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);

	/* active IRQs - not synced to hardware */
	DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
	struct dln2_irq_work *irq_work;
};

struct dln2_gpio_pin {
	__le16 pin;
};

struct dln2_gpio_pin_val {
	__le16 pin __packed;
	u8 value;
};

static int dln2_gpio_get_pin_count(struct platform_device *pdev)
{
	int ret;
	__le16 count;
	int len = sizeof(count);

	ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
	if (ret < 0)
		return ret;
	if (len < sizeof(count))
		return -EPROTO;

	return le16_to_cpu(count);
}

static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
{
	struct dln2_gpio_pin req = {
		.pin = cpu_to_le16(pin),
	};

	return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
}

static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
{
	int ret;
	struct dln2_gpio_pin req = {
		.pin = cpu_to_le16(pin),
	};
	struct dln2_gpio_pin_val rsp;
	int len = sizeof(rsp);

	ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
	if (ret < 0)
		return ret;
	if (len < sizeof(rsp) || req.pin != rsp.pin)
		return -EPROTO;

	return rsp.value;
}

static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
{
	int ret;

	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
	if (ret < 0)
		return ret;
	return !!ret;
}

static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
{
	int ret;

	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
	if (ret < 0)
		return ret;
	return !!ret;
}

static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
				     unsigned int pin, int value)
{
	struct dln2_gpio_pin_val req = {
		.pin = cpu_to_le16(pin),
		.value = value,
	};

	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
				sizeof(req));
}

#define DLN2_GPIO_DIRECTION_IN		0
#define DLN2_GPIO_DIRECTION_OUT		1

static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	struct dln2_gpio_pin req = {
		.pin = cpu_to_le16(offset),
	};
	struct dln2_gpio_pin_val rsp;
	int len = sizeof(rsp);
	int ret;

	ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
	if (ret < 0)
		return ret;

	/* cache the pin direction */
	ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
			    &req, sizeof(req), &rsp, &len);
	if (ret < 0)
		return ret;
	if (len < sizeof(rsp) || req.pin != rsp.pin) {
		ret = -EPROTO;
		goto out_disable;
	}

	switch (rsp.value) {
	case DLN2_GPIO_DIRECTION_IN:
		clear_bit(offset, dln2->output_enabled);
		return 0;
	case DLN2_GPIO_DIRECTION_OUT:
		set_bit(offset, dln2->output_enabled);
		return 0;
	default:
		ret = -EPROTO;
		goto out_disable;
	}

out_disable:
	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
	return ret;
}

static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);

	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
}

static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);

	if (test_bit(offset, dln2->output_enabled))
		return GPIOF_DIR_OUT;

	return GPIOF_DIR_IN;
}

static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	int dir;

	dir = dln2_gpio_get_direction(chip, offset);
	if (dir < 0)
		return dir;

	if (dir == GPIOF_DIR_IN)
		return dln2_gpio_pin_get_in_val(dln2, offset);

	return dln2_gpio_pin_get_out_val(dln2, offset);
}

static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);

	dln2_gpio_pin_set_out_val(dln2, offset, value);
}

static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
				   unsigned dir)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	struct dln2_gpio_pin_val req = {
		.pin = cpu_to_le16(offset),
		.value = dir,
	};
	int ret;

	ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
			       &req, sizeof(req));
	if (ret < 0)
		return ret;

	if (dir == DLN2_GPIO_DIRECTION_OUT)
		set_bit(offset, dln2->output_enabled);
	else
		clear_bit(offset, dln2->output_enabled);

	return ret;
}

static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
}

static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	int ret;

	ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
	if (ret < 0)
		return ret;

	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
}

static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
				  unsigned debounce)
{
	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	__le32 duration = cpu_to_le32(debounce);

	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
				&duration, sizeof(duration));
}

static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
				   unsigned type, unsigned period)
{
	struct {
		__le16 pin;
		u8 type;
		__le16 period;
	} __packed req = {
		.pin = cpu_to_le16(pin),
		.type = type,
		.period = cpu_to_le16(period),
	};

	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
				&req, sizeof(req));
}

static void dln2_irq_work(struct work_struct *w)
{
	struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
	struct dln2_gpio *dln2 = iw->dln2;
	u8 type = iw->type & DLN2_GPIO_EVENT_MASK;

	if (test_bit(iw->pin, dln2->unmasked_irqs))
		dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
	else
		dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
}

static void dln2_irq_unmask(struct irq_data *irqd)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	set_bit(pin, dln2->unmasked_irqs);
	schedule_work(&dln2->irq_work[pin].work);
}

static void dln2_irq_mask(struct irq_data *irqd)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	clear_bit(pin, dln2->unmasked_irqs);
	schedule_work(&dln2->irq_work[pin].work);
}

static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	int pin = irqd_to_hwirq(irqd);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip dln2_gpio_irqchip = {
	.name = "dln2-irq",
	.irq_mask = dln2_irq_mask,
	.irq_unmask = dln2_irq_unmask,
	.irq_set_type = dln2_irq_set_type,
};

static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
			    const void *data, int len)
{
	int pin, irq;
	const struct {
		__le16 count;
		__u8 type;
		__le16 pin;
		__u8 value;
	} __packed *event = data;
	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);

	if (len < sizeof(*event)) {
		dev_err(dln2->gpio.dev, "short event message\n");
		return;
	}

	pin = le16_to_cpu(event->pin);
	if (pin >= dln2->gpio.ngpio) {
		dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
		return;
	}

	irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
	if (!irq) {
		dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
		return;
	}

	switch (dln2->irq_work[pin].type) {
	case DLN2_GPIO_EVENT_CHANGE_RISING:
		if (event->value)
			generic_handle_irq(irq);
		break;
	case DLN2_GPIO_EVENT_CHANGE_FALLING:
		if (!event->value)
			generic_handle_irq(irq);
		break;
	default:
		generic_handle_irq(irq);
	}
}

static int dln2_gpio_probe(struct platform_device *pdev)
{
	struct dln2_gpio *dln2;
	struct device *dev = &pdev->dev;
	int pins;
	int i, ret;

	pins = dln2_gpio_get_pin_count(pdev);
	if (pins < 0) {
		dev_err(dev, "failed to get pin count: %d\n", pins);
		return pins;
	}
	if (pins > DLN2_GPIO_MAX_PINS) {
		pins = DLN2_GPIO_MAX_PINS;
		dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
	}

	dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
	if (!dln2)
		return -ENOMEM;

	dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
				      sizeof(struct dln2_irq_work), GFP_KERNEL);
	if (!dln2->irq_work)
		return -ENOMEM;
	for (i = 0; i < pins; i++) {
		INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
		dln2->irq_work[i].pin = i;
		dln2->irq_work[i].dln2 = dln2;
	}

	dln2->pdev = pdev;

	dln2->gpio.label = "dln2";
	dln2->gpio.dev = dev;
	dln2->gpio.owner = THIS_MODULE;
	dln2->gpio.base = -1;
	dln2->gpio.ngpio = pins;
	dln2->gpio.exported = true;
	dln2->gpio.can_sleep = true;
	dln2->gpio.irq_not_threaded = true;
	dln2->gpio.set = dln2_gpio_set;
	dln2->gpio.get = dln2_gpio_get;
	dln2->gpio.request = dln2_gpio_request;
	dln2->gpio.free = dln2_gpio_free;
	dln2->gpio.get_direction = dln2_gpio_get_direction;
	dln2->gpio.direction_input = dln2_gpio_direction_input;
	dln2->gpio.direction_output = dln2_gpio_direction_output;
	dln2->gpio.set_debounce = dln2_gpio_set_debounce;

	platform_set_drvdata(pdev, dln2);

	ret = gpiochip_add(&dln2->gpio);
	if (ret < 0) {
		dev_err(dev, "failed to add gpio chip: %d\n", ret);
		goto out;
	}

	ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
				   handle_simple_irq, IRQ_TYPE_NONE);
	if (ret < 0) {
		dev_err(dev, "failed to add irq chip: %d\n", ret);
		goto out_gpiochip_remove;
	}

	ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
				     dln2_gpio_event);
	if (ret) {
		dev_err(dev, "failed to register event cb: %d\n", ret);
		goto out_gpiochip_remove;
	}

	return 0;

out_gpiochip_remove:
	gpiochip_remove(&dln2->gpio);
out:
	return ret;
}

static int dln2_gpio_remove(struct platform_device *pdev)
{
	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
	int i;

	dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
	for (i = 0; i < dln2->gpio.ngpio; i++)
		flush_work(&dln2->irq_work[i].work);
	gpiochip_remove(&dln2->gpio);

	return 0;
}

static struct platform_driver dln2_gpio_driver = {
	.driver.name	= "dln2-gpio",
	.probe		= dln2_gpio_probe,
	.remove		= dln2_gpio_remove,
};

module_platform_driver(dln2_gpio_driver);

MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dln2-gpio");
Commit	Line	Data
6732127f DB	1	/*
	2	* Driver for the Diolan DLN-2 USB-GPIO adapter
	3	*
	4	* Copyright (c) 2014 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation, version 2.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/slab.h>
	14	#include <linux/types.h>
	15	#include <linux/irqdomain.h>
	16	#include <linux/irq.h>
	17	#include <linux/irqchip/chained_irq.h>
	18	#include <linux/gpio.h>
	19	#include <linux/gpio/driver.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/mfd/dln2.h>
	22
	23	#define DLN2_GPIO_ID 0x01
	24
	25	#define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
	26	#define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
	27	#define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
	28	#define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
	29	#define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
	30	#define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
	31	#define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
	32	#define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
	33	#define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
	34	#define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
	35	#define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
	36	#define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
	37	#define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
	38	#define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
	39
	40	#define DLN2_GPIO_EVENT_NONE 0
	41	#define DLN2_GPIO_EVENT_CHANGE 1
	42	#define DLN2_GPIO_EVENT_LVL_HIGH 2
	43	#define DLN2_GPIO_EVENT_LVL_LOW 3
	44	#define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
	45	#define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
	46	#define DLN2_GPIO_EVENT_MASK 0x0F
	47
	48	#define DLN2_GPIO_MAX_PINS 32
	49
	50	struct dln2_irq_work {
	51	struct work_struct work;
	52	struct dln2_gpio *dln2;
	53	int pin;
	54	int type;
	55	};
	56
	57	struct dln2_gpio {
	58	struct platform_device *pdev;
	59	struct gpio_chip gpio;
	60
	61	/*
	62	* Cache pin direction to save us one transfer, since the hardware has
	63	* separate commands to read the in and out values.
	64	*/
65	DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
66
0acb0e71 OP	67	/* active IRQs - not synced to hardware */
0acb0e71 OP	68	DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
6732127f DB	69	struct dln2_irq_work *irq_work;
	70	};
	71
	72	struct dln2_gpio_pin {
	73	__le16 pin;
	74	};
	75
	76	struct dln2_gpio_pin_val {
	77	__le16 pin __packed;
	78	u8 value;
	79	};
	80
	81	static int dln2_gpio_get_pin_count(struct platform_device *pdev)
	82	{
	83	int ret;
	84	__le16 count;
	85	int len = sizeof(count);
	86
	87	ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
	88	if (ret < 0)
	89	return ret;
	90	if (len < sizeof(count))
	91	return -EPROTO;
	92
	93	return le16_to_cpu(count);
	94	}
	95
	96	static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
	97	{
	98	struct dln2_gpio_pin req = {
	99	.pin = cpu_to_le16(pin),
	100	};
	101
	102	return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
	103	}
	104
	105	static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
	106	{
	107	int ret;
	108	struct dln2_gpio_pin req = {
	109	.pin = cpu_to_le16(pin),
	110	};
	111	struct dln2_gpio_pin_val rsp;
	112	int len = sizeof(rsp);
	113
	114	ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
	115	if (ret < 0)
	116	return ret;
	117	if (len < sizeof(rsp) \|\| req.pin != rsp.pin)
	118	return -EPROTO;
	119
	120	return rsp.value;
	121	}
	122
	123	static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
	124	{
	125	int ret;
	126
	127	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
	128	if (ret < 0)
	129	return ret;
	130	return !!ret;
	131	}
	132
133	static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
134	{
135	int ret;
136
137	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
138	if (ret < 0)
139	return ret;
140	return !!ret;
141	}
142
5afb287a AL	143	static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
5afb287a AL	144	unsigned int pin, int value)
6732127f DB	145	{
	146	struct dln2_gpio_pin_val req = {
	147	.pin = cpu_to_le16(pin),
	148	.value = value,
	149	};
	150
5afb287a AL	151	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
5afb287a AL	152	sizeof(req));
6732127f DB	153	}
	154
	155	#define DLN2_GPIO_DIRECTION_IN 0
	156	#define DLN2_GPIO_DIRECTION_OUT 1
	157
	158	static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
	159	{
	160	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	161	struct dln2_gpio_pin req = {
	162	.pin = cpu_to_le16(offset),
	163	};
	164	struct dln2_gpio_pin_val rsp;
	165	int len = sizeof(rsp);
	166	int ret;
	167
	168	ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
	169	if (ret < 0)
	170	return ret;
	171
	172	/* cache the pin direction */
	173	ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
	174	&req, sizeof(req), &rsp, &len);
	175	if (ret < 0)
	176	return ret;
	177	if (len < sizeof(rsp) \|\| req.pin != rsp.pin) {
	178	ret = -EPROTO;
	179	goto out_disable;
	180	}
	181
	182	switch (rsp.value) {
	183	case DLN2_GPIO_DIRECTION_IN:
	184	clear_bit(offset, dln2->output_enabled);
	185	return 0;
	186	case DLN2_GPIO_DIRECTION_OUT:
	187	set_bit(offset, dln2->output_enabled);
	188	return 0;
	189	default:
	190	ret = -EPROTO;
	191	goto out_disable;
	192	}
	193
	194	out_disable:
	195	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
	196	return ret;
	197	}
	198
	199	static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
	200	{
	201	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	202
	203	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
	204	}
	205
	206	static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	207	{
	208	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	209
	210	if (test_bit(offset, dln2->output_enabled))
	211	return GPIOF_DIR_OUT;
	212
	213	return GPIOF_DIR_IN;
	214	}
	215
	216	static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
217	{
218	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
219	int dir;
220
221	dir = dln2_gpio_get_direction(chip, offset);
222	if (dir < 0)
223	return dir;
224
225	if (dir == GPIOF_DIR_IN)
226	return dln2_gpio_pin_get_in_val(dln2, offset);
227
228	return dln2_gpio_pin_get_out_val(dln2, offset);
229	}
230
231	static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
232	{
233	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
234
235	dln2_gpio_pin_set_out_val(dln2, offset, value);
236	}
237
238	static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
239	unsigned dir)
240	{
241	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
242	struct dln2_gpio_pin_val req = {
243	.pin = cpu_to_le16(offset),
244	.value = dir,
245	};
246	int ret;
247
248	ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
249	&req, sizeof(req));
250	if (ret < 0)
251	return ret;
252
253	if (dir == DLN2_GPIO_DIRECTION_OUT)
254	set_bit(offset, dln2->output_enabled);
255	else
256	clear_bit(offset, dln2->output_enabled);
257
258	return ret;
259	}
260
261	static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
262	{
263	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
264	}
265
266	static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
267	int value)
268	{
5afb287a AL	269	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	270	int ret;
	271
	272	ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
	273	if (ret < 0)
	274	return ret;
	275
6732127f DB	276	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
	277	}
	278
	279	static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
	280	unsigned debounce)
	281	{
	282	struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
	283	__le32 duration = cpu_to_le32(debounce);
	284
	285	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
	286	&duration, sizeof(duration));
	287	}
	288
	289	static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
	290	unsigned type, unsigned period)
	291	{
	292	struct {
	293	__le16 pin;
	294	u8 type;
	295	__le16 period;
	296	} __packed req = {
	297	.pin = cpu_to_le16(pin),
	298	.type = type,
	299	.period = cpu_to_le16(period),
	300	};
	301
	302	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
	303	&req, sizeof(req));
	304	}
	305
	306	static void dln2_irq_work(struct work_struct *w)
	307	{
	308	struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
	309	struct dln2_gpio *dln2 = iw->dln2;
	310	u8 type = iw->type & DLN2_GPIO_EVENT_MASK;
	311
0acb0e71	312	if (test_bit(iw->pin, dln2->unmasked_irqs))
6732127f DB	313	dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
	314	else
	315	dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
	316	}
	317
0acb0e71	318	static void dln2_irq_unmask(struct irq_data *irqd)
6732127f DB	319	{
	320	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	321	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	322	int pin = irqd_to_hwirq(irqd);
	323
0acb0e71	324	set_bit(pin, dln2->unmasked_irqs);
6732127f DB	325	schedule_work(&dln2->irq_work[pin].work);
	326	}
	327
	328	static void dln2_irq_mask(struct irq_data *irqd)
	329	{
	330	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	331	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	332	int pin = irqd_to_hwirq(irqd);
	333
0acb0e71 OP	334	clear_bit(pin, dln2->unmasked_irqs);
0acb0e71 OP	335	schedule_work(&dln2->irq_work[pin].work);
6732127f DB	336	}
	337
	338	static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
	339	{
	340	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
	341	struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
	342	int pin = irqd_to_hwirq(irqd);
	343
	344	switch (type) {
	345	case IRQ_TYPE_LEVEL_HIGH:
	346	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
	347	break;
	348	case IRQ_TYPE_LEVEL_LOW:
	349	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
	350	break;
	351	case IRQ_TYPE_EDGE_BOTH:
	352	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
	353	break;
	354	case IRQ_TYPE_EDGE_RISING:
	355	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
	356	break;
	357	case IRQ_TYPE_EDGE_FALLING:
	358	dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
	359	break;
	360	default:
	361	return -EINVAL;
	362	}
	363
	364	return 0;
	365	}
	366
	367	static struct irq_chip dln2_gpio_irqchip = {
	368	.name = "dln2-irq",
6732127f DB	369	.irq_mask = dln2_irq_mask,
	370	.irq_unmask = dln2_irq_unmask,
	371	.irq_set_type = dln2_irq_set_type,
	372	};
	373
	374	static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
	375	const void *data, int len)
	376	{
	377	int pin, irq;
	378	const struct {
	379	__le16 count;
	380	__u8 type;
	381	__le16 pin;
	382	__u8 value;
	383	} __packed *event = data;
	384	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
	385
	386	if (len < sizeof(*event)) {
	387	dev_err(dln2->gpio.dev, "short event message\n");
	388	return;
	389	}
	390
	391	pin = le16_to_cpu(event->pin);
	392	if (pin >= dln2->gpio.ngpio) {
	393	dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
	394	return;
	395	}
	396
	397	irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
	398	if (!irq) {
	399	dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
	400	return;
	401	}
	402
6732127f DB	403	switch (dln2->irq_work[pin].type) {
	404	case DLN2_GPIO_EVENT_CHANGE_RISING:
	405	if (event->value)
	406	generic_handle_irq(irq);
	407	break;
	408	case DLN2_GPIO_EVENT_CHANGE_FALLING:
	409	if (!event->value)
	410	generic_handle_irq(irq);
	411	break;
	412	default:
	413	generic_handle_irq(irq);
	414	}
	415	}
	416
	417	static int dln2_gpio_probe(struct platform_device *pdev)
	418	{
	419	struct dln2_gpio *dln2;
	420	struct device *dev = &pdev->dev;
	421	int pins;
	422	int i, ret;
	423
	424	pins = dln2_gpio_get_pin_count(pdev);
	425	if (pins < 0) {
	426	dev_err(dev, "failed to get pin count: %d\n", pins);
	427	return pins;
	428	}
	429	if (pins > DLN2_GPIO_MAX_PINS) {
	430	pins = DLN2_GPIO_MAX_PINS;
	431	dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
	432	}
	433
	434	dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
	435	if (!dln2)
	436	return -ENOMEM;
	437
	438	dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
	439	sizeof(struct dln2_irq_work), GFP_KERNEL);
	440	if (!dln2->irq_work)
	441	return -ENOMEM;
	442	for (i = 0; i < pins; i++) {
	443	INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
	444	dln2->irq_work[i].pin = i;
	445	dln2->irq_work[i].dln2 = dln2;
	446	}
	447
	448	dln2->pdev = pdev;
	449
	450	dln2->gpio.label = "dln2";
	451	dln2->gpio.dev = dev;
	452	dln2->gpio.owner = THIS_MODULE;
	453	dln2->gpio.base = -1;
	454	dln2->gpio.ngpio = pins;
	455	dln2->gpio.exported = true;
	456	dln2->gpio.can_sleep = true;
	457	dln2->gpio.irq_not_threaded = true;
	458	dln2->gpio.set = dln2_gpio_set;
	459	dln2->gpio.get = dln2_gpio_get;
	460	dln2->gpio.request = dln2_gpio_request;
	461	dln2->gpio.free = dln2_gpio_free;
	462	dln2->gpio.get_direction = dln2_gpio_get_direction;
	463	dln2->gpio.direction_input = dln2_gpio_direction_input;
	464	dln2->gpio.direction_output = dln2_gpio_direction_output;
	465	dln2->gpio.set_debounce = dln2_gpio_set_debounce;
	466
467	platform_set_drvdata(pdev, dln2);
468
469	ret = gpiochip_add(&dln2->gpio);
470	if (ret < 0) {
471	dev_err(dev, "failed to add gpio chip: %d\n", ret);
472	goto out;
473	}
474
475	ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
476	handle_simple_irq, IRQ_TYPE_NONE);
477	if (ret < 0) {
478	dev_err(dev, "failed to add irq chip: %d\n", ret);
479	goto out_gpiochip_remove;
480	}
481
482	ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
483	dln2_gpio_event);
484	if (ret) {
485	dev_err(dev, "failed to register event cb: %d\n", ret);
486	goto out_gpiochip_remove;
487	}
488
489	return 0;
490
491	out_gpiochip_remove:
492	gpiochip_remove(&dln2->gpio);
493	out:
494	return ret;
495	}
496
497	static int dln2_gpio_remove(struct platform_device *pdev)
498	{
499	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
500	int i;
501
502	dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
503	for (i = 0; i < dln2->gpio.ngpio; i++)
504	flush_work(&dln2->irq_work[i].work);
505	gpiochip_remove(&dln2->gpio);
506
507	return 0;
508	}
509
510	static struct platform_driver dln2_gpio_driver = {
511	.driver.name = "dln2-gpio",
512	.probe = dln2_gpio_probe,
513	.remove = dln2_gpio_remove,
514	};
515
516	module_platform_driver(dln2_gpio_driver);
517
518	MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
519	MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
520	MODULE_LICENSE("GPL v2");
521	MODULE_ALIAS("platform:dln2-gpio");