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7779b345 JI |
1 | /* |
2 | * Copyright (c) 2011 Jamie Iles | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * All enquiries to support@picochip.com | |
9 | */ | |
10 | #include <linux/basic_mmio_gpio.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/irqdomain.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/spinlock.h> | |
3d2613c4 WC |
24 | #include <linux/platform_data/gpio-dwapb.h> |
25 | #include <linux/slab.h> | |
7779b345 JI |
26 | |
27 | #define GPIO_SWPORTA_DR 0x00 | |
28 | #define GPIO_SWPORTA_DDR 0x04 | |
29 | #define GPIO_SWPORTB_DR 0x0c | |
30 | #define GPIO_SWPORTB_DDR 0x10 | |
31 | #define GPIO_SWPORTC_DR 0x18 | |
32 | #define GPIO_SWPORTC_DDR 0x1c | |
33 | #define GPIO_SWPORTD_DR 0x24 | |
34 | #define GPIO_SWPORTD_DDR 0x28 | |
35 | #define GPIO_INTEN 0x30 | |
36 | #define GPIO_INTMASK 0x34 | |
37 | #define GPIO_INTTYPE_LEVEL 0x38 | |
38 | #define GPIO_INT_POLARITY 0x3c | |
39 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 40 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
41 | #define GPIO_PORTA_EOI 0x4c |
42 | #define GPIO_EXT_PORTA 0x50 | |
43 | #define GPIO_EXT_PORTB 0x54 | |
44 | #define GPIO_EXT_PORTC 0x58 | |
45 | #define GPIO_EXT_PORTD 0x5c | |
46 | ||
47 | #define DWAPB_MAX_PORTS 4 | |
48 | #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA) | |
49 | #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR) | |
50 | #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR) | |
51 | ||
52 | struct dwapb_gpio; | |
53 | ||
1e960dbb WC |
54 | #ifdef CONFIG_PM_SLEEP |
55 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
56 | struct dwapb_context { | |
57 | u32 data; | |
58 | u32 dir; | |
59 | u32 ext; | |
60 | u32 int_en; | |
61 | u32 int_mask; | |
62 | u32 int_type; | |
63 | u32 int_pol; | |
64 | u32 int_deb; | |
65 | }; | |
66 | #endif | |
67 | ||
7779b345 JI |
68 | struct dwapb_gpio_port { |
69 | struct bgpio_chip bgc; | |
70 | bool is_registered; | |
71 | struct dwapb_gpio *gpio; | |
1e960dbb WC |
72 | #ifdef CONFIG_PM_SLEEP |
73 | struct dwapb_context *ctx; | |
74 | #endif | |
75 | unsigned int idx; | |
7779b345 JI |
76 | }; |
77 | ||
78 | struct dwapb_gpio { | |
79 | struct device *dev; | |
80 | void __iomem *regs; | |
81 | struct dwapb_gpio_port *ports; | |
82 | unsigned int nr_ports; | |
83 | struct irq_domain *domain; | |
84 | }; | |
85 | ||
5d60d9ef WC |
86 | static inline struct dwapb_gpio_port * |
87 | to_dwapb_gpio_port(struct bgpio_chip *bgc) | |
88 | { | |
89 | return container_of(bgc, struct dwapb_gpio_port, bgc); | |
90 | } | |
91 | ||
67809b97 WC |
92 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
93 | { | |
94 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
95 | void __iomem *reg_base = gpio->regs; | |
96 | ||
97 | return bgc->read_reg(reg_base + offset); | |
98 | } | |
99 | ||
100 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
101 | u32 val) | |
102 | { | |
103 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
104 | void __iomem *reg_base = gpio->regs; | |
105 | ||
106 | bgc->write_reg(reg_base + offset, val); | |
107 | } | |
108 | ||
7779b345 JI |
109 | static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
110 | { | |
111 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
5d60d9ef | 112 | struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc); |
7779b345 JI |
113 | struct dwapb_gpio *gpio = port->gpio; |
114 | ||
115 | return irq_find_mapping(gpio->domain, offset); | |
116 | } | |
117 | ||
118 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) | |
119 | { | |
67809b97 | 120 | u32 v = dwapb_read(gpio, GPIO_INT_POLARITY); |
7779b345 JI |
121 | |
122 | if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs)) | |
123 | v &= ~BIT(offs); | |
124 | else | |
125 | v |= BIT(offs); | |
126 | ||
67809b97 | 127 | dwapb_write(gpio, GPIO_INT_POLARITY, v); |
7779b345 JI |
128 | } |
129 | ||
3d2613c4 | 130 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 131 | { |
7779b345 | 132 | u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS); |
3d2613c4 | 133 | u32 ret = irq_status; |
7779b345 JI |
134 | |
135 | while (irq_status) { | |
136 | int hwirq = fls(irq_status) - 1; | |
137 | int gpio_irq = irq_find_mapping(gpio->domain, hwirq); | |
138 | ||
139 | generic_handle_irq(gpio_irq); | |
140 | irq_status &= ~BIT(hwirq); | |
141 | ||
142 | if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) | |
143 | == IRQ_TYPE_EDGE_BOTH) | |
144 | dwapb_toggle_trigger(gpio, hwirq); | |
145 | } | |
146 | ||
3d2613c4 WC |
147 | return ret; |
148 | } | |
149 | ||
bd0b9ac4 | 150 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 151 | { |
476f8b4c | 152 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
153 | struct irq_chip *chip = irq_desc_get_chip(desc); |
154 | ||
155 | dwapb_do_irq(gpio); | |
156 | ||
7779b345 JI |
157 | if (chip->irq_eoi) |
158 | chip->irq_eoi(irq_desc_get_irq_data(desc)); | |
159 | } | |
160 | ||
161 | static void dwapb_irq_enable(struct irq_data *d) | |
162 | { | |
163 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
164 | struct dwapb_gpio *gpio = igc->private; | |
165 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
166 | unsigned long flags; | |
167 | u32 val; | |
168 | ||
169 | spin_lock_irqsave(&bgc->lock, flags); | |
67809b97 | 170 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 171 | val |= BIT(d->hwirq); |
67809b97 | 172 | dwapb_write(gpio, GPIO_INTEN, val); |
7779b345 JI |
173 | spin_unlock_irqrestore(&bgc->lock, flags); |
174 | } | |
175 | ||
176 | static void dwapb_irq_disable(struct irq_data *d) | |
177 | { | |
178 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
179 | struct dwapb_gpio *gpio = igc->private; | |
180 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
181 | unsigned long flags; | |
182 | u32 val; | |
183 | ||
184 | spin_lock_irqsave(&bgc->lock, flags); | |
67809b97 | 185 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 186 | val &= ~BIT(d->hwirq); |
67809b97 | 187 | dwapb_write(gpio, GPIO_INTEN, val); |
7779b345 JI |
188 | spin_unlock_irqrestore(&bgc->lock, flags); |
189 | } | |
190 | ||
57ef0428 | 191 | static int dwapb_irq_reqres(struct irq_data *d) |
7779b345 JI |
192 | { |
193 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
194 | struct dwapb_gpio *gpio = igc->private; | |
195 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
196 | ||
e3a2e878 | 197 | if (gpiochip_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) { |
7779b345 JI |
198 | dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", |
199 | irqd_to_hwirq(d)); | |
57ef0428 LW |
200 | return -EINVAL; |
201 | } | |
7779b345 JI |
202 | return 0; |
203 | } | |
204 | ||
57ef0428 | 205 | static void dwapb_irq_relres(struct irq_data *d) |
7779b345 JI |
206 | { |
207 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
208 | struct dwapb_gpio *gpio = igc->private; | |
209 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
210 | ||
e3a2e878 | 211 | gpiochip_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d)); |
7779b345 JI |
212 | } |
213 | ||
214 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) | |
215 | { | |
216 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
217 | struct dwapb_gpio *gpio = igc->private; | |
218 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
219 | int bit = d->hwirq; | |
220 | unsigned long level, polarity, flags; | |
221 | ||
222 | if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
223 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
224 | return -EINVAL; | |
225 | ||
226 | spin_lock_irqsave(&bgc->lock, flags); | |
67809b97 WC |
227 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
228 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
229 | |
230 | switch (type) { | |
231 | case IRQ_TYPE_EDGE_BOTH: | |
232 | level |= BIT(bit); | |
233 | dwapb_toggle_trigger(gpio, bit); | |
234 | break; | |
235 | case IRQ_TYPE_EDGE_RISING: | |
236 | level |= BIT(bit); | |
237 | polarity |= BIT(bit); | |
238 | break; | |
239 | case IRQ_TYPE_EDGE_FALLING: | |
240 | level |= BIT(bit); | |
241 | polarity &= ~BIT(bit); | |
242 | break; | |
243 | case IRQ_TYPE_LEVEL_HIGH: | |
244 | level &= ~BIT(bit); | |
245 | polarity |= BIT(bit); | |
246 | break; | |
247 | case IRQ_TYPE_LEVEL_LOW: | |
248 | level &= ~BIT(bit); | |
249 | polarity &= ~BIT(bit); | |
250 | break; | |
251 | } | |
252 | ||
6a2f4b7d SAS |
253 | irq_setup_alt_chip(d, type); |
254 | ||
67809b97 WC |
255 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
256 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
7779b345 JI |
257 | spin_unlock_irqrestore(&bgc->lock, flags); |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
5d60d9ef WC |
262 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
263 | unsigned offset, unsigned debounce) | |
264 | { | |
265 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
266 | struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc); | |
267 | struct dwapb_gpio *gpio = port->gpio; | |
268 | unsigned long flags, val_deb; | |
269 | unsigned long mask = bgc->pin2mask(bgc, offset); | |
270 | ||
271 | spin_lock_irqsave(&bgc->lock, flags); | |
272 | ||
273 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
274 | if (debounce) | |
275 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); | |
276 | else | |
277 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); | |
278 | ||
279 | spin_unlock_irqrestore(&bgc->lock, flags); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
3d2613c4 WC |
284 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
285 | { | |
286 | u32 worked; | |
287 | struct dwapb_gpio *gpio = dev_id; | |
288 | ||
289 | worked = dwapb_do_irq(gpio); | |
290 | ||
291 | return worked ? IRQ_HANDLED : IRQ_NONE; | |
292 | } | |
293 | ||
7779b345 | 294 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
295 | struct dwapb_gpio_port *port, |
296 | struct dwapb_port_property *pp) | |
7779b345 JI |
297 | { |
298 | struct gpio_chip *gc = &port->bgc.gc; | |
3d2613c4 WC |
299 | struct device_node *node = pp->node; |
300 | struct irq_chip_generic *irq_gc = NULL; | |
7779b345 JI |
301 | unsigned int hwirq, ngpio = gc->ngpio; |
302 | struct irq_chip_type *ct; | |
3d2613c4 | 303 | int err, i; |
7779b345 JI |
304 | |
305 | gpio->domain = irq_domain_add_linear(node, ngpio, | |
306 | &irq_generic_chip_ops, gpio); | |
307 | if (!gpio->domain) | |
308 | return; | |
309 | ||
6a2f4b7d | 310 | err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, |
7779b345 JI |
311 | "gpio-dwapb", handle_level_irq, |
312 | IRQ_NOREQUEST, 0, | |
313 | IRQ_GC_INIT_NESTED_LOCK); | |
314 | if (err) { | |
315 | dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); | |
316 | irq_domain_remove(gpio->domain); | |
317 | gpio->domain = NULL; | |
318 | return; | |
319 | } | |
320 | ||
321 | irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); | |
322 | if (!irq_gc) { | |
323 | irq_domain_remove(gpio->domain); | |
324 | gpio->domain = NULL; | |
325 | return; | |
326 | } | |
327 | ||
328 | irq_gc->reg_base = gpio->regs; | |
329 | irq_gc->private = gpio; | |
330 | ||
6a2f4b7d SAS |
331 | for (i = 0; i < 2; i++) { |
332 | ct = &irq_gc->chip_types[i]; | |
333 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
334 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
335 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
336 | ct->chip.irq_set_type = dwapb_irq_set_type; | |
337 | ct->chip.irq_enable = dwapb_irq_enable; | |
338 | ct->chip.irq_disable = dwapb_irq_disable; | |
339 | ct->chip.irq_request_resources = dwapb_irq_reqres; | |
340 | ct->chip.irq_release_resources = dwapb_irq_relres; | |
341 | ct->regs.ack = GPIO_PORTA_EOI; | |
342 | ct->regs.mask = GPIO_INTMASK; | |
343 | ct->type = IRQ_TYPE_LEVEL_MASK; | |
344 | } | |
345 | ||
346 | irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | |
347 | irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | |
348 | irq_gc->chip_types[1].handler = handle_edge_irq; | |
7779b345 | 349 | |
3d2613c4 | 350 | if (!pp->irq_shared) { |
6218b88d TG |
351 | irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler, |
352 | gpio); | |
3d2613c4 WC |
353 | } else { |
354 | /* | |
355 | * Request a shared IRQ since where MFD would have devices | |
356 | * using the same irq pin | |
357 | */ | |
358 | err = devm_request_irq(gpio->dev, pp->irq, | |
359 | dwapb_irq_handler_mfd, | |
360 | IRQF_SHARED, "gpio-dwapb-mfd", gpio); | |
361 | if (err) { | |
362 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
363 | irq_domain_remove(gpio->domain); | |
364 | gpio->domain = NULL; | |
365 | return; | |
366 | } | |
367 | } | |
7779b345 JI |
368 | |
369 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
370 | irq_create_mapping(gpio->domain, hwirq); | |
371 | ||
372 | port->bgc.gc.to_irq = dwapb_gpio_to_irq; | |
373 | } | |
374 | ||
375 | static void dwapb_irq_teardown(struct dwapb_gpio *gpio) | |
376 | { | |
377 | struct dwapb_gpio_port *port = &gpio->ports[0]; | |
378 | struct gpio_chip *gc = &port->bgc.gc; | |
379 | unsigned int ngpio = gc->ngpio; | |
380 | irq_hw_number_t hwirq; | |
381 | ||
382 | if (!gpio->domain) | |
383 | return; | |
384 | ||
385 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
386 | irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); | |
387 | ||
388 | irq_domain_remove(gpio->domain); | |
389 | gpio->domain = NULL; | |
390 | } | |
391 | ||
392 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 393 | struct dwapb_port_property *pp, |
7779b345 JI |
394 | unsigned int offs) |
395 | { | |
396 | struct dwapb_gpio_port *port; | |
7779b345 JI |
397 | void __iomem *dat, *set, *dirout; |
398 | int err; | |
399 | ||
7779b345 JI |
400 | port = &gpio->ports[offs]; |
401 | port->gpio = gpio; | |
1e960dbb WC |
402 | port->idx = pp->idx; |
403 | ||
404 | #ifdef CONFIG_PM_SLEEP | |
405 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
406 | if (!port->ctx) | |
407 | return -ENOMEM; | |
408 | #endif | |
7779b345 | 409 | |
3d2613c4 WC |
410 | dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE); |
411 | set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE); | |
7779b345 | 412 | dirout = gpio->regs + GPIO_SWPORTA_DDR + |
3d2613c4 | 413 | (pp->idx * GPIO_SWPORT_DDR_SIZE); |
7779b345 JI |
414 | |
415 | err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout, | |
416 | NULL, false); | |
417 | if (err) { | |
418 | dev_err(gpio->dev, "failed to init gpio chip for %s\n", | |
3d2613c4 | 419 | pp->name); |
7779b345 JI |
420 | return err; |
421 | } | |
422 | ||
3d2613c4 WC |
423 | #ifdef CONFIG_OF_GPIO |
424 | port->bgc.gc.of_node = pp->node; | |
425 | #endif | |
426 | port->bgc.gc.ngpio = pp->ngpio; | |
427 | port->bgc.gc.base = pp->gpio_base; | |
7779b345 | 428 | |
5d60d9ef WC |
429 | /* Only port A support debounce */ |
430 | if (pp->idx == 0) | |
431 | port->bgc.gc.set_debounce = dwapb_gpio_set_debounce; | |
432 | ||
3d2613c4 WC |
433 | if (pp->irq) |
434 | dwapb_configure_irqs(gpio, port, pp); | |
7779b345 JI |
435 | |
436 | err = gpiochip_add(&port->bgc.gc); | |
437 | if (err) | |
438 | dev_err(gpio->dev, "failed to register gpiochip for %s\n", | |
3d2613c4 | 439 | pp->name); |
7779b345 JI |
440 | else |
441 | port->is_registered = true; | |
442 | ||
443 | return err; | |
444 | } | |
445 | ||
446 | static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) | |
447 | { | |
448 | unsigned int m; | |
449 | ||
450 | for (m = 0; m < gpio->nr_ports; ++m) | |
451 | if (gpio->ports[m].is_registered) | |
9f5132ae | 452 | gpiochip_remove(&gpio->ports[m].bgc.gc); |
7779b345 JI |
453 | } |
454 | ||
3d2613c4 WC |
455 | static struct dwapb_platform_data * |
456 | dwapb_gpio_get_pdata_of(struct device *dev) | |
457 | { | |
458 | struct device_node *node, *port_np; | |
459 | struct dwapb_platform_data *pdata; | |
460 | struct dwapb_port_property *pp; | |
461 | int nports; | |
462 | int i; | |
463 | ||
464 | node = dev->of_node; | |
465 | if (!IS_ENABLED(CONFIG_OF_GPIO) || !node) | |
466 | return ERR_PTR(-ENODEV); | |
467 | ||
468 | nports = of_get_child_count(node); | |
469 | if (nports == 0) | |
470 | return ERR_PTR(-ENODEV); | |
471 | ||
da9df93e | 472 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
473 | if (!pdata) |
474 | return ERR_PTR(-ENOMEM); | |
475 | ||
da9df93e AL |
476 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
477 | if (!pdata->properties) | |
3d2613c4 | 478 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
479 | |
480 | pdata->nports = nports; | |
481 | ||
482 | i = 0; | |
483 | for_each_child_of_node(node, port_np) { | |
484 | pp = &pdata->properties[i++]; | |
485 | pp->node = port_np; | |
486 | ||
487 | if (of_property_read_u32(port_np, "reg", &pp->idx) || | |
488 | pp->idx >= DWAPB_MAX_PORTS) { | |
489 | dev_err(dev, "missing/invalid port index for %s\n", | |
490 | port_np->full_name); | |
3d2613c4 WC |
491 | return ERR_PTR(-EINVAL); |
492 | } | |
493 | ||
494 | if (of_property_read_u32(port_np, "snps,nr-gpios", | |
495 | &pp->ngpio)) { | |
496 | dev_info(dev, "failed to get number of gpios for %s\n", | |
497 | port_np->full_name); | |
498 | pp->ngpio = 32; | |
499 | } | |
500 | ||
501 | /* | |
502 | * Only port A can provide interrupts in all configurations of | |
503 | * the IP. | |
504 | */ | |
505 | if (pp->idx == 0 && | |
506 | of_property_read_bool(port_np, "interrupt-controller")) { | |
507 | pp->irq = irq_of_parse_and_map(port_np, 0); | |
508 | if (!pp->irq) { | |
509 | dev_warn(dev, "no irq for bank %s\n", | |
510 | port_np->full_name); | |
511 | } | |
512 | } | |
513 | ||
514 | pp->irq_shared = false; | |
515 | pp->gpio_base = -1; | |
516 | pp->name = port_np->full_name; | |
517 | } | |
518 | ||
519 | return pdata; | |
520 | } | |
521 | ||
7779b345 JI |
522 | static int dwapb_gpio_probe(struct platform_device *pdev) |
523 | { | |
3d2613c4 | 524 | unsigned int i; |
7779b345 JI |
525 | struct resource *res; |
526 | struct dwapb_gpio *gpio; | |
7779b345 | 527 | int err; |
3d2613c4 WC |
528 | struct device *dev = &pdev->dev; |
529 | struct dwapb_platform_data *pdata = dev_get_platdata(dev); | |
3d2613c4 | 530 | |
da9df93e | 531 | if (!pdata) { |
3d2613c4 WC |
532 | pdata = dwapb_gpio_get_pdata_of(dev); |
533 | if (IS_ERR(pdata)) | |
534 | return PTR_ERR(pdata); | |
535 | } | |
7779b345 | 536 | |
da9df93e AL |
537 | if (!pdata->nports) |
538 | return -ENODEV; | |
7779b345 | 539 | |
3d2613c4 | 540 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
541 | if (!gpio) |
542 | return -ENOMEM; | |
543 | ||
3d2613c4 WC |
544 | gpio->dev = &pdev->dev; |
545 | gpio->nr_ports = pdata->nports; | |
546 | ||
547 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, | |
7779b345 | 548 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
549 | if (!gpio->ports) |
550 | return -ENOMEM; | |
7779b345 JI |
551 | |
552 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
553 | gpio->regs = devm_ioremap_resource(&pdev->dev, res); | |
da9df93e AL |
554 | if (IS_ERR(gpio->regs)) |
555 | return PTR_ERR(gpio->regs); | |
7779b345 | 556 | |
3d2613c4 WC |
557 | for (i = 0; i < gpio->nr_ports; i++) { |
558 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 JI |
559 | if (err) |
560 | goto out_unregister; | |
561 | } | |
562 | platform_set_drvdata(pdev, gpio); | |
563 | ||
da9df93e | 564 | return 0; |
7779b345 JI |
565 | |
566 | out_unregister: | |
567 | dwapb_gpio_unregister(gpio); | |
568 | dwapb_irq_teardown(gpio); | |
569 | ||
7779b345 JI |
570 | return err; |
571 | } | |
572 | ||
573 | static int dwapb_gpio_remove(struct platform_device *pdev) | |
574 | { | |
575 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
576 | ||
577 | dwapb_gpio_unregister(gpio); | |
578 | dwapb_irq_teardown(gpio); | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | static const struct of_device_id dwapb_of_match[] = { | |
584 | { .compatible = "snps,dw-apb-gpio" }, | |
585 | { /* Sentinel */ } | |
586 | }; | |
587 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
588 | ||
1e960dbb WC |
589 | #ifdef CONFIG_PM_SLEEP |
590 | static int dwapb_gpio_suspend(struct device *dev) | |
591 | { | |
592 | struct platform_device *pdev = to_platform_device(dev); | |
593 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
594 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
595 | unsigned long flags; | |
596 | int i; | |
597 | ||
598 | spin_lock_irqsave(&bgc->lock, flags); | |
599 | for (i = 0; i < gpio->nr_ports; i++) { | |
600 | unsigned int offset; | |
601 | unsigned int idx = gpio->ports[i].idx; | |
602 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
603 | ||
58a3b92d | 604 | BUG_ON(!ctx); |
1e960dbb WC |
605 | |
606 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
607 | ctx->dir = dwapb_read(gpio, offset); | |
608 | ||
609 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
610 | ctx->data = dwapb_read(gpio, offset); | |
611 | ||
612 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
613 | ctx->ext = dwapb_read(gpio, offset); | |
614 | ||
615 | /* Only port A can provide interrupts */ | |
616 | if (idx == 0) { | |
617 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
618 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
619 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
620 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
621 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
622 | ||
623 | /* Mask out interrupts */ | |
624 | dwapb_write(gpio, GPIO_INTMASK, 0xffffffff); | |
625 | } | |
626 | } | |
627 | spin_unlock_irqrestore(&bgc->lock, flags); | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
632 | static int dwapb_gpio_resume(struct device *dev) | |
633 | { | |
634 | struct platform_device *pdev = to_platform_device(dev); | |
635 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
636 | struct bgpio_chip *bgc = &gpio->ports[0].bgc; | |
637 | unsigned long flags; | |
638 | int i; | |
639 | ||
640 | spin_lock_irqsave(&bgc->lock, flags); | |
641 | for (i = 0; i < gpio->nr_ports; i++) { | |
642 | unsigned int offset; | |
643 | unsigned int idx = gpio->ports[i].idx; | |
644 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
645 | ||
58a3b92d | 646 | BUG_ON(!ctx); |
1e960dbb WC |
647 | |
648 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
649 | dwapb_write(gpio, offset, ctx->data); | |
650 | ||
651 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
652 | dwapb_write(gpio, offset, ctx->dir); | |
653 | ||
654 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
655 | dwapb_write(gpio, offset, ctx->ext); | |
656 | ||
657 | /* Only port A can provide interrupts */ | |
658 | if (idx == 0) { | |
659 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
660 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
661 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
662 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
663 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
664 | ||
665 | /* Clear out spurious interrupts */ | |
666 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
667 | } | |
668 | } | |
669 | spin_unlock_irqrestore(&bgc->lock, flags); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | #endif | |
674 | ||
675 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
676 | dwapb_gpio_resume); | |
677 | ||
7779b345 JI |
678 | static struct platform_driver dwapb_gpio_driver = { |
679 | .driver = { | |
680 | .name = "gpio-dwapb", | |
1e960dbb | 681 | .pm = &dwapb_gpio_pm_ops, |
7779b345 JI |
682 | .of_match_table = of_match_ptr(dwapb_of_match), |
683 | }, | |
684 | .probe = dwapb_gpio_probe, | |
685 | .remove = dwapb_gpio_remove, | |
686 | }; | |
687 | ||
688 | module_platform_driver(dwapb_gpio_driver); | |
689 | ||
690 | MODULE_LICENSE("GPL"); | |
691 | MODULE_AUTHOR("Jamie Iles"); | |
692 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); |