[deliverable/linux.git] / drivers / gpio / gpio-ep93xx.c

/*
 * Generic EP93xx GPIO handling
 *
 * Copyright (c) 2008 Ryan Mallon
 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
 *
 * Based on code originally from:
 *  linux/arch/arm/mach-ep93xx/core.c
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>

#include <mach/hardware.h>
#include <mach/gpio-ep93xx.h>

#define irq_to_gpio(irq)	((irq) - gpio_to_irq(0))

struct ep93xx_gpio {
	void __iomem		*mmio_base;
	struct bgpio_chip	bgc[8];
};

/*************************************************************************
 * Interrupt handling for EP93xx on-chip GPIOs
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

static void ep93xx_gpio_update_int_params(unsigned port)
{
	BUG_ON(port > 2);

	writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));

	writeb_relaxed(gpio_int_type2[port],
		EP93XX_GPIO_REG(int_type2_register_offset[port]));

	writeb_relaxed(gpio_int_type1[port],
		EP93XX_GPIO_REG(int_type1_register_offset[port]));

	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
		EP93XX_GPIO_REG(int_en_register_offset[port]));
}

static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	writeb(gpio_int_debounce[port],
		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
}

static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
{
	unsigned char status;
	int i;

	status = readb(EP93XX_GPIO_A_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}

	status = readb(EP93XX_GPIO_B_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}
}

static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continuous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	 */
	unsigned int irq = irq_desc_get_irq(desc);
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;

	generic_handle_irq(gpio_irq);
}

static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(port);
	}

	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(port);

	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	ep93xx_gpio_update_int_params(port);
}

static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] |= 1 << (line & 7);
	ep93xx_gpio_update_int_params(port);
}

/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	const int gpio = irq_to_gpio(d->irq);
	const int port = gpio >> 3;
	const int port_mask = 1 << (gpio & 7);
	irq_flow_handler_t handler;

	gpio_direction_input(gpio);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gpio_get_value(gpio))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		handler = handle_edge_irq;
		break;
	default:
		return -EINVAL;
	}

	irq_set_handler_locked(d, handler);

	gpio_int_enabled[port] |= port_mask;

	ep93xx_gpio_update_int_params(port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= ep93xx_gpio_irq_ack,
	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
	.irq_mask	= ep93xx_gpio_irq_mask,
	.irq_unmask	= ep93xx_gpio_irq_unmask,
	.irq_set_type	= ep93xx_gpio_irq_type,
};

static void ep93xx_gpio_init_irq(void)
{
	int gpio_irq;

	for (gpio_irq = gpio_to_irq(0);
	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	}

	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
				ep93xx_gpio_ab_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
				ep93xx_gpio_f_irq_handler);
}


/*************************************************************************
 * gpiolib interface for EP93xx on-chip GPIOs
 *************************************************************************/
struct ep93xx_gpio_bank {
	const char	*label;
	int		data;
	int		dir;
	int		base;
	bool		has_debounce;
};

#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce)	\
	{							\
		.label		= _label,			\
		.data		= _data,			\
		.dir		= _dir,				\
		.base		= _base,			\
		.has_debounce	= _debounce,			\
	}

static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
};

static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
				    unsigned offset, unsigned debounce)
{
	int gpio = chip->base + offset;
	int irq = gpio_to_irq(gpio);

	if (irq < 0)
		return -EINVAL;

	ep93xx_gpio_int_debounce(irq, debounce ? true : false);

	return 0;
}

/*
 * Map GPIO A0..A7  (0..7)  to irq 64..71,
 *          B0..B7  (7..15) to irq 72..79, and
 *          F0..F7 (16..24) to irq 80..87.
 */
static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	int gpio = chip->base + offset;

	if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
		return -EINVAL;

	return 64 + gpio;
}

static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
	void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
{
	void __iomem *data = mmio_base + bank->data;
	void __iomem *dir =  mmio_base + bank->dir;
	int err;

	err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
	if (err)
		return err;

	bgc->gc.label = bank->label;
	bgc->gc.base = bank->base;

	if (bank->has_debounce) {
		bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
		bgc->gc.to_irq = ep93xx_gpio_to_irq;
	}

	return gpiochip_add(&bgc->gc);
}

static int ep93xx_gpio_probe(struct platform_device *pdev)
{
	struct ep93xx_gpio *ep93xx_gpio;
	struct resource *res;
	int i;
	struct device *dev = &pdev->dev;

	ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
	if (!ep93xx_gpio)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ep93xx_gpio->mmio_base))
		return PTR_ERR(ep93xx_gpio->mmio_base);

	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
		struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];

		if (ep93xx_gpio_add_bank(bgc, &pdev->dev,
					 ep93xx_gpio->mmio_base, bank))
			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
				bank->label);
	}

	ep93xx_gpio_init_irq();

	return 0;
}

static struct platform_driver ep93xx_gpio_driver = {
	.driver		= {
		.name	= "gpio-ep93xx",
	},
	.probe		= ep93xx_gpio_probe,
};

static int __init ep93xx_gpio_init(void)
{
	return platform_driver_register(&ep93xx_gpio_driver);
}
postcore_initcall(ep93xx_gpio_init);

MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
		"H Hartley Sweeten <hsweeten@visionengravers.com>");
MODULE_DESCRIPTION("EP93XX GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b685004f	1	/*
b685004f RM	2	* Generic EP93xx GPIO handling
b685004f RM	3	*
1c5454ee	4	* Copyright (c) 2008 Ryan Mallon
1e4c8842	5	* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
b685004f RM	6	*
	7	* Based on code originally from:
	8	* linux/arch/arm/mach-ep93xx/core.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
bb207ef1	16	#include <linux/module.h>
1e4c8842	17	#include <linux/platform_device.h>
fced80c7	18	#include <linux/io.h>
ddf4f3d9	19	#include <linux/gpio.h>
595c050d	20	#include <linux/irq.h>
1e4c8842 HS	21	#include <linux/slab.h>
1e4c8842 HS	22	#include <linux/basic_mmio_gpio.h>
b685004f	23
ddf4f3d9	24	#include <mach/hardware.h>
bd5f12a2 LW	25	#include <mach/gpio-ep93xx.h>
	26
	27	#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
b685004f	28
1e4c8842 HS	29	struct ep93xx_gpio {
	30	void __iomem *mmio_base;
	31	struct bgpio_chip bgc[8];
	32	};
	33
d056ab78	34	/*************************************************************************
4742723c	35	* Interrupt handling for EP93xx on-chip GPIOs
d056ab78 HS	36	*************************************************************************/
	37	static unsigned char gpio_int_unmasked[3];
	38	static unsigned char gpio_int_enabled[3];
	39	static unsigned char gpio_int_type1[3];
	40	static unsigned char gpio_int_type2[3];
	41	static unsigned char gpio_int_debounce[3];
	42
	43	/* Port ordering is: A B F */
	44	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	45	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	46	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
	47	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
	48	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
	49
4742723c	50	static void ep93xx_gpio_update_int_params(unsigned port)
d056ab78 HS	51	{
	52	BUG_ON(port > 2);
	53
d27e06ac	54	writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
d056ab78	55
d27e06ac	56	writeb_relaxed(gpio_int_type2[port],
d056ab78 HS	57	EP93XX_GPIO_REG(int_type2_register_offset[port]));
d056ab78 HS	58
d27e06ac	59	writeb_relaxed(gpio_int_type1[port],
d056ab78 HS	60	EP93XX_GPIO_REG(int_type1_register_offset[port]));
d056ab78 HS	61
d27e06ac	62	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
d056ab78 HS	63	EP93XX_GPIO_REG(int_en_register_offset[port]));
	64	}
	65
5d046af0	66	static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
d056ab78 HS	67	{
	68	int line = irq_to_gpio(irq);
	69	int port = line >> 3;
	70	int port_mask = 1 << (line & 7);
	71
	72	if (enable)
	73	gpio_int_debounce[port] \|= port_mask;
	74	else
	75	gpio_int_debounce[port] &= ~port_mask;
	76
d27e06ac	77	writeb(gpio_int_debounce[port],
d056ab78 HS	78	EP93XX_GPIO_REG(int_debounce_register_offset[port]));
d056ab78 HS	79	}
d056ab78	80
bd0b9ac4	81	static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
d056ab78 HS	82	{
	83	unsigned char status;
	84	int i;
	85
d27e06ac	86	status = readb(EP93XX_GPIO_A_INT_STATUS);
d056ab78 HS	87	for (i = 0; i < 8; i++) {
	88	if (status & (1 << i)) {
	89	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
	90	generic_handle_irq(gpio_irq);
	91	}
	92	}
	93
d27e06ac	94	status = readb(EP93XX_GPIO_B_INT_STATUS);
d056ab78 HS	95	for (i = 0; i < 8; i++) {
	96	if (status & (1 << i)) {
	97	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
	98	generic_handle_irq(gpio_irq);
	99	}
	100	}
	101	}
	102
bd0b9ac4	103	static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
d056ab78 HS	104	{
d056ab78 HS	105	/*
25985edc	106	* map discontiguous hw irq range to continuous sw irq range:
d056ab78 HS	107	*
	108	* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	109	*/
e43ea7a7	110	unsigned int irq = irq_desc_get_irq(desc);
d056ab78 HS	111	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	112	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
	113
	114	generic_handle_irq(gpio_irq);
	115	}
	116
c0afc916	117	static void ep93xx_gpio_irq_ack(struct irq_data *d)
d056ab78	118	{
c0afc916	119	int line = irq_to_gpio(d->irq);
d056ab78 HS	120	int port = line >> 3;
	121	int port_mask = 1 << (line & 7);
	122
d1735a2e	123	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
d056ab78 HS	124	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	125	ep93xx_gpio_update_int_params(port);
	126	}
	127
d27e06ac	128	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
d056ab78 HS	129	}
d056ab78 HS	130
c0afc916	131	static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
d056ab78	132	{
c0afc916	133	int line = irq_to_gpio(d->irq);
d056ab78 HS	134	int port = line >> 3;
	135	int port_mask = 1 << (line & 7);
	136
d1735a2e	137	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
d056ab78 HS	138	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	139
	140	gpio_int_unmasked[port] &= ~port_mask;
	141	ep93xx_gpio_update_int_params(port);
	142
d27e06ac	143	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
d056ab78 HS	144	}
d056ab78 HS	145
c0afc916	146	static void ep93xx_gpio_irq_mask(struct irq_data *d)
d056ab78	147	{
c0afc916	148	int line = irq_to_gpio(d->irq);
d056ab78 HS	149	int port = line >> 3;
	150
	151	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	152	ep93xx_gpio_update_int_params(port);
	153	}
	154
c0afc916	155	static void ep93xx_gpio_irq_unmask(struct irq_data *d)
d056ab78	156	{
c0afc916	157	int line = irq_to_gpio(d->irq);
d056ab78 HS	158	int port = line >> 3;
	159
	160	gpio_int_unmasked[port] \|= 1 << (line & 7);
	161	ep93xx_gpio_update_int_params(port);
	162	}
	163
	164	/*
	165	* gpio_int_type1 controls whether the interrupt is level (0) or
	166	* edge (1) triggered, while gpio_int_type2 controls whether it
	167	* triggers on low/falling (0) or high/rising (1).
	168	*/
c0afc916	169	static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
d056ab78	170	{
c0afc916	171	const int gpio = irq_to_gpio(d->irq);
d056ab78 HS	172	const int port = gpio >> 3;
d056ab78 HS	173	const int port_mask = 1 << (gpio & 7);
d1735a2e	174	irq_flow_handler_t handler;
d056ab78 HS	175
	176	gpio_direction_input(gpio);
	177
	178	switch (type) {
	179	case IRQ_TYPE_EDGE_RISING:
	180	gpio_int_type1[port] \|= port_mask;
	181	gpio_int_type2[port] \|= port_mask;
d1735a2e	182	handler = handle_edge_irq;
d056ab78 HS	183	break;
	184	case IRQ_TYPE_EDGE_FALLING:
	185	gpio_int_type1[port] \|= port_mask;
	186	gpio_int_type2[port] &= ~port_mask;
d1735a2e	187	handler = handle_edge_irq;
d056ab78 HS	188	break;
	189	case IRQ_TYPE_LEVEL_HIGH:
	190	gpio_int_type1[port] &= ~port_mask;
	191	gpio_int_type2[port] \|= port_mask;
d1735a2e	192	handler = handle_level_irq;
d056ab78 HS	193	break;
	194	case IRQ_TYPE_LEVEL_LOW:
	195	gpio_int_type1[port] &= ~port_mask;
	196	gpio_int_type2[port] &= ~port_mask;
d1735a2e	197	handler = handle_level_irq;
d056ab78 HS	198	break;
	199	case IRQ_TYPE_EDGE_BOTH:
	200	gpio_int_type1[port] \|= port_mask;
	201	/* set initial polarity based on current input level */
	202	if (gpio_get_value(gpio))
	203	gpio_int_type2[port] &= ~port_mask; /* falling */
	204	else
	205	gpio_int_type2[port] \|= port_mask; /* rising */
d1735a2e	206	handler = handle_edge_irq;
d056ab78 HS	207	break;
d056ab78 HS	208	default:
d056ab78 HS	209	return -EINVAL;
	210	}
	211
72b2a9ef	212	irq_set_handler_locked(d, handler);
d056ab78	213
d1735a2e	214	gpio_int_enabled[port] \|= port_mask;
d056ab78 HS	215
	216	ep93xx_gpio_update_int_params(port);
	217
	218	return 0;
	219	}
	220
	221	static struct irq_chip ep93xx_gpio_irq_chip = {
	222	.name = "GPIO",
c0afc916 LB	223	.irq_ack = ep93xx_gpio_irq_ack,
	224	.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
	225	.irq_mask = ep93xx_gpio_irq_mask,
	226	.irq_unmask = ep93xx_gpio_irq_unmask,
	227	.irq_set_type = ep93xx_gpio_irq_type,
d056ab78 HS	228	};
d056ab78 HS	229
1e4c8842	230	static void ep93xx_gpio_init_irq(void)
d056ab78 HS	231	{
	232	int gpio_irq;
	233
	234	for (gpio_irq = gpio_to_irq(0);
	235	gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
f38c02f3 TG	236	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
f38c02f3 TG	237	handle_level_irq);
23393d49	238	irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
d056ab78 HS	239	}
d056ab78 HS	240
6845664a TG	241	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
	242	ep93xx_gpio_ab_irq_handler);
	243	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
	244	ep93xx_gpio_f_irq_handler);
	245	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
	246	ep93xx_gpio_f_irq_handler);
	247	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
	248	ep93xx_gpio_f_irq_handler);
	249	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
	250	ep93xx_gpio_f_irq_handler);
	251	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
	252	ep93xx_gpio_f_irq_handler);
	253	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
	254	ep93xx_gpio_f_irq_handler);
	255	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
	256	ep93xx_gpio_f_irq_handler);
	257	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
	258	ep93xx_gpio_f_irq_handler);
d056ab78 HS	259	}
	260
	261
	262	/*************************************************************************
	263	* gpiolib interface for EP93xx on-chip GPIOs
	264	*************************************************************************/
1e4c8842 HS	265	struct ep93xx_gpio_bank {
	266	const char *label;
	267	int data;
	268	int dir;
	269	int base;
	270	bool has_debounce;
b685004f RM	271	};
b685004f RM	272
1e4c8842 HS	273	#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
	274	{ \
	275	.label = _label, \
	276	.data = _data, \
	277	.dir = _dir, \
	278	.base = _base, \
	279	.has_debounce = _debounce, \
	280	}
b685004f	281
1e4c8842 HS	282	static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	283	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
	284	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
	285	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	286	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	287	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	288	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
	289	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	290	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
	291	};
	292
	293	static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
	294	unsigned offset, unsigned debounce)
b685004f	295	{
1e4c8842 HS	296	int gpio = chip->base + offset;
1e4c8842 HS	297	int irq = gpio_to_irq(gpio);
b685004f	298
1e4c8842 HS	299	if (irq < 0)
	300	return -EINVAL;
	301
	302	ep93xx_gpio_int_debounce(irq, debounce ? true : false);
b685004f RM	303
	304	return 0;
	305	}
	306
257af9f9 LW	307	/*
	308	* Map GPIO A0..A7 (0..7) to irq 64..71,
	309	* B0..B7 (7..15) to irq 72..79, and
	310	* F0..F7 (16..24) to irq 80..87.
	311	*/
	312	static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	313	{
	314	int gpio = chip->base + offset;
	315
	316	if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
	317	return -EINVAL;
	318
	319	return 64 + gpio;
	320	}
	321
1e4c8842 HS	322	static int ep93xx_gpio_add_bank(struct bgpio_chip bgc, struct device dev,
1e4c8842 HS	323	void __iomem mmio_base, struct ep93xx_gpio_bank bank)
b685004f	324	{
1e4c8842 HS	325	void __iomem *data = mmio_base + bank->data;
	326	void __iomem *dir = mmio_base + bank->dir;
	327	int err;
b685004f	328
3e11f7b8	329	err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
1e4c8842 HS	330	if (err)
1e4c8842 HS	331	return err;
b685004f	332
1e4c8842 HS	333	bgc->gc.label = bank->label;
1e4c8842 HS	334	bgc->gc.base = bank->base;
b685004f	335
257af9f9	336	if (bank->has_debounce) {
1e4c8842	337	bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
257af9f9 LW	338	bgc->gc.to_irq = ep93xx_gpio_to_irq;
257af9f9 LW	339	}
b685004f	340
1e4c8842	341	return gpiochip_add(&bgc->gc);
b685004f RM	342	}
b685004f RM	343
3836309d	344	static int ep93xx_gpio_probe(struct platform_device *pdev)
b685004f	345	{
1e4c8842 HS	346	struct ep93xx_gpio *ep93xx_gpio;
1e4c8842 HS	347	struct resource *res;
1e4c8842	348	int i;
1aeede0b	349	struct device *dev = &pdev->dev;
b685004f	350
1aeede0b	351	ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
1e4c8842 HS	352	if (!ep93xx_gpio)
1e4c8842 HS	353	return -ENOMEM;
b685004f	354
1e4c8842	355	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c829f956	356	ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
1aeede0b	357	if (IS_ERR(ep93xx_gpio->mmio_base))
1aeede0b	358	return PTR_ERR(ep93xx_gpio->mmio_base);
5d046af0	359
1e4c8842 HS	360	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
	361	struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
	362	struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
5d046af0	363
1aeede0b	364	if (ep93xx_gpio_add_bank(bgc, &pdev->dev,
1aeede0b	365	ep93xx_gpio->mmio_base, bank))
1e4c8842 HS	366	dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
1e4c8842 HS	367	bank->label);
b685004f RM	368	}
b685004f RM	369
1e4c8842	370	ep93xx_gpio_init_irq();
b685004f	371
1e4c8842	372	return 0;
1e4c8842	373	}
fd015480	374
1e4c8842 HS	375	static struct platform_driver ep93xx_gpio_driver = {
	376	.driver = {
	377	.name = "gpio-ep93xx",
1e4c8842 HS	378	},
	379	.probe = ep93xx_gpio_probe,
	380	};
	381
	382	static int __init ep93xx_gpio_init(void)
	383	{
1e4c8842	384	return platform_driver_register(&ep93xx_gpio_driver);
b685004f	385	}
1e4c8842 HS	386	postcore_initcall(ep93xx_gpio_init);
	387
	388	MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
	389	"H Hartley Sweeten <hsweeten@visionengravers.com>");
	390	MODULE_DESCRIPTION("EP93XX GPIO driver");
	391	MODULE_LICENSE("GPL");