[deliverable/linux.git] / drivers / gpio / gpio-ep93xx.c

/*
 * Generic EP93xx GPIO handling
 *
 * Copyright (c) 2008 Ryan Mallon
 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
 *
 * Based on code originally from:
 *  linux/arch/arm/mach-ep93xx/core.c
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>

#include <mach/hardware.h>

struct ep93xx_gpio {
	void __iomem		*mmio_base;
	struct bgpio_chip	bgc[8];
};

/*************************************************************************
 * Interrupt handling for EP93xx on-chip GPIOs
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

static void ep93xx_gpio_update_int_params(unsigned port)
{
	BUG_ON(port > 2);

	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));

	__raw_writeb(gpio_int_type2[port],
		EP93XX_GPIO_REG(int_type2_register_offset[port]));

	__raw_writeb(gpio_int_type1[port],
		EP93XX_GPIO_REG(int_type1_register_offset[port]));

	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
		EP93XX_GPIO_REG(int_en_register_offset[port]));
}

static inline void ep93xx_gpio_int_mask(unsigned line)
{
	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
}

static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	__raw_writeb(gpio_int_debounce[port],
		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
}

static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned char status;
	int i;

	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}

	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}
}

static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continuous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	 */
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;

	generic_handle_irq(gpio_irq);
}

static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(port);
	}

	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(port);

	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	ep93xx_gpio_update_int_params(port);
}

static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] |= 1 << (line & 7);
	ep93xx_gpio_update_int_params(port);
}

/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	const int gpio = irq_to_gpio(d->irq);
	const int port = gpio >> 3;
	const int port_mask = 1 << (gpio & 7);
	irq_flow_handler_t handler;

	gpio_direction_input(gpio);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gpio_get_value(gpio))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		handler = handle_edge_irq;
		break;
	default:
		pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
		return -EINVAL;
	}

	__irq_set_handler_locked(d->irq, handler);

	gpio_int_enabled[port] |= port_mask;

	ep93xx_gpio_update_int_params(port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= ep93xx_gpio_irq_ack,
	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
	.irq_mask	= ep93xx_gpio_irq_mask,
	.irq_unmask	= ep93xx_gpio_irq_unmask,
	.irq_set_type	= ep93xx_gpio_irq_type,
};

static void ep93xx_gpio_init_irq(void)
{
	int gpio_irq;

	for (gpio_irq = gpio_to_irq(0);
	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		set_irq_flags(gpio_irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
				ep93xx_gpio_ab_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
				ep93xx_gpio_f_irq_handler);
}


/*************************************************************************
 * gpiolib interface for EP93xx on-chip GPIOs
 *************************************************************************/
struct ep93xx_gpio_bank {
	const char	*label;
	int		data;
	int		dir;
	int		base;
	bool		has_debounce;
};

#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce)	\
	{							\
		.label		= _label,			\
		.data		= _data,			\
		.dir		= _dir,				\
		.base		= _base,			\
		.has_debounce	= _debounce,			\
	}

static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
};

static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
				    unsigned offset, unsigned debounce)
{
	int gpio = chip->base + offset;
	int irq = gpio_to_irq(gpio);

	if (irq < 0)
		return -EINVAL;

	ep93xx_gpio_int_debounce(irq, debounce ? true : false);

	return 0;
}

static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
	void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
{
	void __iomem *data = mmio_base + bank->data;
	void __iomem *dir =  mmio_base + bank->dir;
	int err;

	err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
	if (err)
		return err;

	bgc->gc.label = bank->label;
	bgc->gc.base = bank->base;

	if (bank->has_debounce)
		bgc->gc.set_debounce = ep93xx_gpio_set_debounce;

	return gpiochip_add(&bgc->gc);
}

static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
{
	struct ep93xx_gpio *ep93xx_gpio;
	struct resource *res;
	void __iomem *mmio;
	int i;
	int ret;

	ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
	if (!ep93xx_gpio)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENXIO;
		goto exit_free;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		ret = -EBUSY;
		goto exit_free;
	}

	mmio = ioremap(res->start, resource_size(res));
	if (!mmio) {
		ret = -ENXIO;
		goto exit_release;
	}
	ep93xx_gpio->mmio_base = mmio;

	/* Default all ports to GPIO */
	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
			       EP93XX_SYSCON_DEVCFG_GONK |
			       EP93XX_SYSCON_DEVCFG_EONIDE |
			       EP93XX_SYSCON_DEVCFG_GONIDE |
			       EP93XX_SYSCON_DEVCFG_HONIDE);

	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
		struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];

		if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
				bank->label);
	}

	ep93xx_gpio_init_irq();

	return 0;

exit_release:
	release_mem_region(res->start, resource_size(res));
exit_free:
	kfree(ep93xx_gpio);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
	return ret;
}

static struct platform_driver ep93xx_gpio_driver = {
	.driver		= {
		.name	= "gpio-ep93xx",
		.owner	= THIS_MODULE,
	},
	.probe		= ep93xx_gpio_probe,
};

static int __init ep93xx_gpio_init(void)
{
	return platform_driver_register(&ep93xx_gpio_driver);
}
postcore_initcall(ep93xx_gpio_init);

MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
		"H Hartley Sweeten <hsweeten@visionengravers.com>");
MODULE_DESCRIPTION("EP93XX GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b685004f	1	/*
b685004f RM	2	* Generic EP93xx GPIO handling
b685004f RM	3	*
1c5454ee	4	* Copyright (c) 2008 Ryan Mallon
1e4c8842	5	* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
b685004f RM	6	*
	7	* Based on code originally from:
	8	* linux/arch/arm/mach-ep93xx/core.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
47732cb4	15	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
d056ab78	16
b685004f	17	#include <linux/init.h>
1e4c8842	18	#include <linux/platform_device.h>
fced80c7	19	#include <linux/io.h>
ddf4f3d9	20	#include <linux/gpio.h>
595c050d	21	#include <linux/irq.h>
1e4c8842 HS	22	#include <linux/slab.h>
1e4c8842 HS	23	#include <linux/basic_mmio_gpio.h>
b685004f	24
ddf4f3d9	25	#include <mach/hardware.h>
b685004f	26
1e4c8842 HS	27	struct ep93xx_gpio {
	28	void __iomem *mmio_base;
	29	struct bgpio_chip bgc[8];
	30	};
	31
d056ab78	32	/*************************************************************************
4742723c	33	* Interrupt handling for EP93xx on-chip GPIOs
d056ab78 HS	34	*************************************************************************/
	35	static unsigned char gpio_int_unmasked[3];
	36	static unsigned char gpio_int_enabled[3];
	37	static unsigned char gpio_int_type1[3];
	38	static unsigned char gpio_int_type2[3];
	39	static unsigned char gpio_int_debounce[3];
	40
	41	/* Port ordering is: A B F */
	42	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	43	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	44	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
	45	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
	46	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
	47
4742723c	48	static void ep93xx_gpio_update_int_params(unsigned port)
d056ab78 HS	49	{
	50	BUG_ON(port > 2);
	51
	52	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
	53
	54	__raw_writeb(gpio_int_type2[port],
	55	EP93XX_GPIO_REG(int_type2_register_offset[port]));
	56
	57	__raw_writeb(gpio_int_type1[port],
	58	EP93XX_GPIO_REG(int_type1_register_offset[port]));
	59
	60	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
	61	EP93XX_GPIO_REG(int_en_register_offset[port]));
	62	}
	63
4742723c	64	static inline void ep93xx_gpio_int_mask(unsigned line)
d056ab78 HS	65	{
	66	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
	67	}
	68
5d046af0	69	static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
d056ab78 HS	70	{
	71	int line = irq_to_gpio(irq);
	72	int port = line >> 3;
	73	int port_mask = 1 << (line & 7);
	74
	75	if (enable)
	76	gpio_int_debounce[port] \|= port_mask;
	77	else
	78	gpio_int_debounce[port] &= ~port_mask;
	79
	80	__raw_writeb(gpio_int_debounce[port],
	81	EP93XX_GPIO_REG(int_debounce_register_offset[port]));
	82	}
d056ab78 HS	83
	84	static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
	85	{
	86	unsigned char status;
	87	int i;
	88
	89	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
	90	for (i = 0; i < 8; i++) {
	91	if (status & (1 << i)) {
	92	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
	93	generic_handle_irq(gpio_irq);
	94	}
	95	}
	96
	97	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
	98	for (i = 0; i < 8; i++) {
	99	if (status & (1 << i)) {
	100	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
	101	generic_handle_irq(gpio_irq);
	102	}
	103	}
	104	}
	105
	106	static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
	107	{
	108	/*
25985edc	109	* map discontiguous hw irq range to continuous sw irq range:
d056ab78 HS	110	*
	111	* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	112	*/
	113	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	114	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
	115
	116	generic_handle_irq(gpio_irq);
	117	}
	118
c0afc916	119	static void ep93xx_gpio_irq_ack(struct irq_data *d)
d056ab78	120	{
c0afc916	121	int line = irq_to_gpio(d->irq);
d056ab78 HS	122	int port = line >> 3;
	123	int port_mask = 1 << (line & 7);
	124
d1735a2e	125	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
d056ab78 HS	126	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	127	ep93xx_gpio_update_int_params(port);
	128	}
	129
	130	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
	131	}
	132
c0afc916	133	static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
d056ab78	134	{
c0afc916	135	int line = irq_to_gpio(d->irq);
d056ab78 HS	136	int port = line >> 3;
	137	int port_mask = 1 << (line & 7);
	138
d1735a2e	139	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
d056ab78 HS	140	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	141
	142	gpio_int_unmasked[port] &= ~port_mask;
	143	ep93xx_gpio_update_int_params(port);
	144
	145	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
	146	}
	147
c0afc916	148	static void ep93xx_gpio_irq_mask(struct irq_data *d)
d056ab78	149	{
c0afc916	150	int line = irq_to_gpio(d->irq);
d056ab78 HS	151	int port = line >> 3;
	152
	153	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	154	ep93xx_gpio_update_int_params(port);
	155	}
	156
c0afc916	157	static void ep93xx_gpio_irq_unmask(struct irq_data *d)
d056ab78	158	{
c0afc916	159	int line = irq_to_gpio(d->irq);
d056ab78 HS	160	int port = line >> 3;
	161
	162	gpio_int_unmasked[port] \|= 1 << (line & 7);
	163	ep93xx_gpio_update_int_params(port);
	164	}
	165
	166	/*
	167	* gpio_int_type1 controls whether the interrupt is level (0) or
	168	* edge (1) triggered, while gpio_int_type2 controls whether it
	169	* triggers on low/falling (0) or high/rising (1).
	170	*/
c0afc916	171	static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
d056ab78	172	{
c0afc916	173	const int gpio = irq_to_gpio(d->irq);
d056ab78 HS	174	const int port = gpio >> 3;
d056ab78 HS	175	const int port_mask = 1 << (gpio & 7);
d1735a2e	176	irq_flow_handler_t handler;
d056ab78 HS	177
	178	gpio_direction_input(gpio);
	179
	180	switch (type) {
	181	case IRQ_TYPE_EDGE_RISING:
	182	gpio_int_type1[port] \|= port_mask;
	183	gpio_int_type2[port] \|= port_mask;
d1735a2e	184	handler = handle_edge_irq;
d056ab78 HS	185	break;
	186	case IRQ_TYPE_EDGE_FALLING:
	187	gpio_int_type1[port] \|= port_mask;
	188	gpio_int_type2[port] &= ~port_mask;
d1735a2e	189	handler = handle_edge_irq;
d056ab78 HS	190	break;
	191	case IRQ_TYPE_LEVEL_HIGH:
	192	gpio_int_type1[port] &= ~port_mask;
	193	gpio_int_type2[port] \|= port_mask;
d1735a2e	194	handler = handle_level_irq;
d056ab78 HS	195	break;
	196	case IRQ_TYPE_LEVEL_LOW:
	197	gpio_int_type1[port] &= ~port_mask;
	198	gpio_int_type2[port] &= ~port_mask;
d1735a2e	199	handler = handle_level_irq;
d056ab78 HS	200	break;
	201	case IRQ_TYPE_EDGE_BOTH:
	202	gpio_int_type1[port] \|= port_mask;
	203	/* set initial polarity based on current input level */
	204	if (gpio_get_value(gpio))
	205	gpio_int_type2[port] &= ~port_mask; /* falling */
	206	else
	207	gpio_int_type2[port] \|= port_mask; /* rising */
d1735a2e	208	handler = handle_edge_irq;
d056ab78 HS	209	break;
	210	default:
	211	pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
	212	return -EINVAL;
	213	}
	214
d1735a2e	215	__irq_set_handler_locked(d->irq, handler);
d056ab78	216
d1735a2e	217	gpio_int_enabled[port] \|= port_mask;
d056ab78 HS	218
	219	ep93xx_gpio_update_int_params(port);
	220
	221	return 0;
	222	}
	223
	224	static struct irq_chip ep93xx_gpio_irq_chip = {
	225	.name = "GPIO",
c0afc916 LB	226	.irq_ack = ep93xx_gpio_irq_ack,
	227	.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
	228	.irq_mask = ep93xx_gpio_irq_mask,
	229	.irq_unmask = ep93xx_gpio_irq_unmask,
	230	.irq_set_type = ep93xx_gpio_irq_type,
d056ab78 HS	231	};
d056ab78 HS	232
1e4c8842	233	static void ep93xx_gpio_init_irq(void)
d056ab78 HS	234	{
	235	int gpio_irq;
	236
	237	for (gpio_irq = gpio_to_irq(0);
	238	gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
f38c02f3 TG	239	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
f38c02f3 TG	240	handle_level_irq);
d056ab78 HS	241	set_irq_flags(gpio_irq, IRQF_VALID);
	242	}
	243
6845664a TG	244	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
	245	ep93xx_gpio_ab_irq_handler);
	246	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
	247	ep93xx_gpio_f_irq_handler);
	248	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
	249	ep93xx_gpio_f_irq_handler);
	250	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
	251	ep93xx_gpio_f_irq_handler);
	252	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
	253	ep93xx_gpio_f_irq_handler);
	254	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
	255	ep93xx_gpio_f_irq_handler);
	256	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
	257	ep93xx_gpio_f_irq_handler);
	258	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
	259	ep93xx_gpio_f_irq_handler);
	260	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
	261	ep93xx_gpio_f_irq_handler);
d056ab78 HS	262	}
	263
	264
	265	/*************************************************************************
	266	* gpiolib interface for EP93xx on-chip GPIOs
	267	*************************************************************************/
1e4c8842 HS	268	struct ep93xx_gpio_bank {
	269	const char *label;
	270	int data;
	271	int dir;
	272	int base;
	273	bool has_debounce;
b685004f RM	274	};
b685004f RM	275
1e4c8842 HS	276	#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
	277	{ \
	278	.label = _label, \
	279	.data = _data, \
	280	.dir = _dir, \
	281	.base = _base, \
	282	.has_debounce = _debounce, \
	283	}
b685004f	284
1e4c8842 HS	285	static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	286	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
	287	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
	288	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	289	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	290	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	291	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
	292	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	293	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
	294	};
	295
	296	static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
	297	unsigned offset, unsigned debounce)
b685004f	298	{
1e4c8842 HS	299	int gpio = chip->base + offset;
1e4c8842 HS	300	int irq = gpio_to_irq(gpio);
b685004f	301
1e4c8842 HS	302	if (irq < 0)
	303	return -EINVAL;
	304
	305	ep93xx_gpio_int_debounce(irq, debounce ? true : false);
b685004f RM	306
	307	return 0;
	308	}
	309
1e4c8842 HS	310	static int ep93xx_gpio_add_bank(struct bgpio_chip bgc, struct device dev,
1e4c8842 HS	311	void __iomem mmio_base, struct ep93xx_gpio_bank bank)
b685004f	312	{
1e4c8842 HS	313	void __iomem *data = mmio_base + bank->data;
	314	void __iomem *dir = mmio_base + bank->dir;
	315	int err;
b685004f	316
1e4c8842 HS	317	err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
	318	if (err)
	319	return err;
b685004f	320
1e4c8842 HS	321	bgc->gc.label = bank->label;
1e4c8842 HS	322	bgc->gc.base = bank->base;
b685004f	323
1e4c8842 HS	324	if (bank->has_debounce)
1e4c8842 HS	325	bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
b685004f	326
1e4c8842	327	return gpiochip_add(&bgc->gc);
b685004f RM	328	}
b685004f RM	329
1e4c8842	330	static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
b685004f	331	{
1e4c8842 HS	332	struct ep93xx_gpio *ep93xx_gpio;
	333	struct resource *res;
	334	void __iomem *mmio;
	335	int i;
	336	int ret;
b685004f	337
1e4c8842 HS	338	ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
	339	if (!ep93xx_gpio)
	340	return -ENOMEM;
b685004f	341
1e4c8842 HS	342	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	343	if (!res) {
	344	ret = -ENXIO;
	345	goto exit_free;
	346	}
b685004f	347
1e4c8842 HS	348	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	349	ret = -EBUSY;
	350	goto exit_free;
	351	}
5d046af0	352
1e4c8842 HS	353	mmio = ioremap(res->start, resource_size(res));
	354	if (!mmio) {
	355	ret = -ENXIO;
	356	goto exit_release;
	357	}
	358	ep93xx_gpio->mmio_base = mmio;
5d046af0	359
1e4c8842 HS	360	/* Default all ports to GPIO */
	361	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS \|
	362	EP93XX_SYSCON_DEVCFG_GONK \|
	363	EP93XX_SYSCON_DEVCFG_EONIDE \|
	364	EP93XX_SYSCON_DEVCFG_GONIDE \|
	365	EP93XX_SYSCON_DEVCFG_HONIDE);
5d046af0	366
1e4c8842 HS	367	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
	368	struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
	369	struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
5d046af0	370
1e4c8842 HS	371	if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
	372	dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
	373	bank->label);
b685004f RM	374	}
b685004f RM	375
1e4c8842	376	ep93xx_gpio_init_irq();
b685004f	377
1e4c8842	378	return 0;
b685004f	379
1e4c8842 HS	380	exit_release:
	381	release_mem_region(res->start, resource_size(res));
	382	exit_free:
	383	kfree(ep93xx_gpio);
	384	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
	385	return ret;
	386	}
fd015480	387
1e4c8842 HS	388	static struct platform_driver ep93xx_gpio_driver = {
	389	.driver = {
	390	.name = "gpio-ep93xx",
	391	.owner = THIS_MODULE,
	392	},
	393	.probe = ep93xx_gpio_probe,
	394	};
	395
	396	static int __init ep93xx_gpio_init(void)
	397	{
1e4c8842	398	return platform_driver_register(&ep93xx_gpio_driver);
b685004f	399	}
1e4c8842 HS	400	postcore_initcall(ep93xx_gpio_init);
	401
	402	MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
	403	"H Hartley Sweeten <hsweeten@visionengravers.com>");
	404	MODULE_DESCRIPTION("EP93XX GPIO driver");
	405	MODULE_LICENSE("GPL");