[deliverable/linux.git] / drivers / gpio / gpio-generic.c

/*
 * Generic driver for memory-mapped GPIO controllers.
 *
 * Copyright 2008 MontaVista Software, Inc.
 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
 * ...``                                                         ```````..
 * ..The simplest form of a GPIO controller that the driver supports is``
 *  `.just a single "data" register, where GPIO state can be read and/or `
 *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
 *        `````````
                                    ___
_/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
__________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
                                                 `....trivial..'~`.```.```
 *                                                    ```````
 *  .```````~~~~`..`.``.``.
 * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
 * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
 *  . register the device with -be`. .with a pair of set/clear-bit registers ,
 *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
 *     ``.`.``...```                  ```.. output pins are also supported.`
 *                        ^^             `````.`````````.,``~``~``~~``````
 *                                                   .                  ^^
 *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
 * .. The expectation is that in at least some cases .    ,-~~~-,
 *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
 *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
 *  ..````````......```````````                             \o_
 *                                                           |
 *                              ^^                          / \
 *
 *           ...`````~~`.....``.`..........``````.`.``.```........``.
 *            `  8, 16, 32 and 64 bits registers are supported, and``.
 *            . the number of GPIOs is determined by the width of   ~
 *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
 *               `.......````.```
 */

#include <linux/init.h>
#include <linux/err.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/basic_mmio_gpio.h>

static void bgpio_write8(void __iomem *reg, unsigned long data)
{
	writeb(data, reg);
}

static unsigned long bgpio_read8(void __iomem *reg)
{
	return readb(reg);
}

static void bgpio_write16(void __iomem *reg, unsigned long data)
{
	writew(data, reg);
}

static unsigned long bgpio_read16(void __iomem *reg)
{
	return readw(reg);
}

static void bgpio_write32(void __iomem *reg, unsigned long data)
{
	writel(data, reg);
}

static unsigned long bgpio_read32(void __iomem *reg)
{
	return readl(reg);
}

#if BITS_PER_LONG >= 64
static void bgpio_write64(void __iomem *reg, unsigned long data)
{
	writeq(data, reg);
}

static unsigned long bgpio_read64(void __iomem *reg)
{
	return readq(reg);
}
#endif /* BITS_PER_LONG >= 64 */

static void bgpio_write16be(void __iomem *reg, unsigned long data)
{
	iowrite16be(data, reg);
}

static unsigned long bgpio_read16be(void __iomem *reg)
{
	return ioread16be(reg);
}

static void bgpio_write32be(void __iomem *reg, unsigned long data)
{
	iowrite32be(data, reg);
}

static unsigned long bgpio_read32be(void __iomem *reg)
{
	return ioread32be(reg);
}

static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
{
	return 1 << pin;
}

static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
				       unsigned int pin)
{
	return 1 << (bgc->bits - 1 - pin);
}

static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
}

static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	if (val)
		bgc->data |= mask;
	else
		bgc->data &= ~mask;

	bgc->write_reg(bgc->reg_dat, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
				 int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);

	if (val)
		bgc->write_reg(bgc->reg_set, mask);
	else
		bgc->write_reg(bgc->reg_clr, mask);
}

static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	if (val)
		bgc->data |= mask;
	else
		bgc->data &= ~mask;

	bgc->write_reg(bgc->reg_set, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
				     unsigned long *mask, unsigned long *bits,
				     unsigned long *set_mask,
				     unsigned long *clear_mask)
{
	int i;

	*set_mask = 0;
	*clear_mask = 0;

	for (i = 0; i < bgc->bits; i++) {
		if (*mask == 0)
			break;
		if (__test_and_clear_bit(i, mask)) {
			if (test_bit(i, bits))
				*set_mask |= bgc->pin2mask(bgc, i);
			else
				*clear_mask |= bgc->pin2mask(bgc, i);
		}
	}
}

static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
					  unsigned long *mask,
					  unsigned long *bits,
					  void __iomem *reg)
{
	unsigned long flags;
	unsigned long set_mask, clear_mask;

	spin_lock_irqsave(&bgc->lock, flags);

	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);

	bgc->data |= set_mask;
	bgc->data &= ~clear_mask;

	bgc->write_reg(reg, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
			       unsigned long *bits)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
}

static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
				   unsigned long *bits)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
}

static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
					  unsigned long *mask,
					  unsigned long *bits)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long set_mask, clear_mask;

	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);

	if (set_mask)
		bgc->write_reg(bgc->reg_set, set_mask);
	if (clear_mask)
		bgc->write_reg(bgc->reg_clr, clear_mask);
}

static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	return 0;
}

static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
				int val)
{
	gc->set(gc, gpio, val);

	return 0;
}

static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	gc->set(gc, gpio, val);

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir |= bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir |= bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	gc->set(gc, gpio, val);

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_setup_accessors(struct device *dev,
				 struct bgpio_chip *bgc,
				 bool bit_be,
				 bool byte_be)
{

	switch (bgc->bits) {
	case 8:
		bgc->read_reg	= bgpio_read8;
		bgc->write_reg	= bgpio_write8;
		break;
	case 16:
		if (byte_be) {
			bgc->read_reg	= bgpio_read16be;
			bgc->write_reg	= bgpio_write16be;
		} else {
			bgc->read_reg	= bgpio_read16;
			bgc->write_reg	= bgpio_write16;
		}
		break;
	case 32:
		if (byte_be) {
			bgc->read_reg	= bgpio_read32be;
			bgc->write_reg	= bgpio_write32be;
		} else {
			bgc->read_reg	= bgpio_read32;
			bgc->write_reg	= bgpio_write32;
		}
		break;
#if BITS_PER_LONG >= 64
	case 64:
		if (byte_be) {
			dev_err(dev,
				"64 bit big endian byte order unsupported\n");
			return -EINVAL;
		} else {
			bgc->read_reg	= bgpio_read64;
			bgc->write_reg	= bgpio_write64;
		}
		break;
#endif /* BITS_PER_LONG >= 64 */
	default:
		dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
		return -EINVAL;
	}

	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;

	return 0;
}

/*
 * Create the device and allocate the resources.  For setting GPIO's there are
 * three supported configurations:
 *
 *	- single input/output register resource (named "dat").
 *	- set/clear pair (named "set" and "clr").
 *	- single output register resource and single input resource ("set" and
 *	dat").
 *
 * For the single output register, this drives a 1 by setting a bit and a zero
 * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 * in the set register and clears it by setting a bit in the clear register.
 * The configuration is detected by which resources are present.
 *
 * For setting the GPIO direction, there are three supported configurations:
 *
 *	- simple bidirection GPIO that requires no configuration.
 *	- an output direction register (named "dirout") where a 1 bit
 *	indicates the GPIO is an output.
 *	- an input direction register (named "dirin") where a 1 bit indicates
 *	the GPIO is an input.
 */
static int bgpio_setup_io(struct bgpio_chip *bgc,
			  void __iomem *dat,
			  void __iomem *set,
			  void __iomem *clr)
{

	bgc->reg_dat = dat;
	if (!bgc->reg_dat)
		return -EINVAL;

	if (set && clr) {
		bgc->reg_set = set;
		bgc->reg_clr = clr;
		bgc->gc.set = bgpio_set_with_clear;
		bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
	} else if (set && !clr) {
		bgc->reg_set = set;
		bgc->gc.set = bgpio_set_set;
		bgc->gc.set_multiple = bgpio_set_multiple_set;
	} else {
		bgc->gc.set = bgpio_set;
		bgc->gc.set_multiple = bgpio_set_multiple;
	}

	bgc->gc.get = bgpio_get;

	return 0;
}

static int bgpio_setup_direction(struct bgpio_chip *bgc,
				 void __iomem *dirout,
				 void __iomem *dirin)
{
	if (dirout && dirin) {
		return -EINVAL;
	} else if (dirout) {
		bgc->reg_dir = dirout;
		bgc->gc.direction_output = bgpio_dir_out;
		bgc->gc.direction_input = bgpio_dir_in;
	} else if (dirin) {
		bgc->reg_dir = dirin;
		bgc->gc.direction_output = bgpio_dir_out_inv;
		bgc->gc.direction_input = bgpio_dir_in_inv;
	} else {
		bgc->gc.direction_output = bgpio_simple_dir_out;
		bgc->gc.direction_input = bgpio_simple_dir_in;
	}

	return 0;
}

static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
{
	if (gpio_pin < chip->ngpio)
		return 0;

	return -EINVAL;
}

int bgpio_remove(struct bgpio_chip *bgc)
{
	gpiochip_remove(&bgc->gc);
	return 0;
}
EXPORT_SYMBOL_GPL(bgpio_remove);

int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags)
{
	int ret;

	if (!is_power_of_2(sz))
		return -EINVAL;

	bgc->bits = sz * 8;
	if (bgc->bits > BITS_PER_LONG)
		return -EINVAL;

	spin_lock_init(&bgc->lock);
	bgc->gc.dev = dev;
	bgc->gc.label = dev_name(dev);
	bgc->gc.base = -1;
	bgc->gc.ngpio = bgc->bits;
	bgc->gc.request = bgpio_request;

	ret = bgpio_setup_io(bgc, dat, set, clr);
	if (ret)
		return ret;

	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
				    flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	if (ret)
		return ret;

	ret = bgpio_setup_direction(bgc, dirout, dirin);
	if (ret)
		return ret;

	bgc->data = bgc->read_reg(bgc->reg_dat);
	if (bgc->gc.set == bgpio_set_set &&
			!(flags & BGPIOF_UNREADABLE_REG_SET))
		bgc->data = bgc->read_reg(bgc->reg_set);
	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
		bgc->dir = bgc->read_reg(bgc->reg_dir);

	return ret;
}
EXPORT_SYMBOL_GPL(bgpio_init);

#ifdef CONFIG_GPIO_GENERIC_PLATFORM

static void __iomem *bgpio_map(struct platform_device *pdev,
			       const char *name,
			       resource_size_t sane_sz,
			       int *err)
{
	struct device *dev = &pdev->dev;
	struct resource *r;
	resource_size_t start;
	resource_size_t sz;
	void __iomem *ret;

	*err = 0;

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	if (!r)
		return NULL;

	sz = resource_size(r);
	if (sz != sane_sz) {
		*err = -EINVAL;
		return NULL;
	}

	start = r->start;
	if (!devm_request_mem_region(dev, start, sz, r->name)) {
		*err = -EBUSY;
		return NULL;
	}

	ret = devm_ioremap(dev, start, sz);
	if (!ret) {
		*err = -ENOMEM;
		return NULL;
	}

	return ret;
}

static int bgpio_pdev_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *r;
	void __iomem *dat;
	void __iomem *set;
	void __iomem *clr;
	void __iomem *dirout;
	void __iomem *dirin;
	unsigned long sz;
	unsigned long flags = pdev->id_entry->driver_data;
	int err;
	struct bgpio_chip *bgc;
	struct bgpio_pdata *pdata = dev_get_platdata(dev);

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
	if (!r)
		return -EINVAL;

	sz = resource_size(r);

	dat = bgpio_map(pdev, "dat", sz, &err);
	if (!dat)
		return err ? err : -EINVAL;

	set = bgpio_map(pdev, "set", sz, &err);
	if (err)
		return err;

	clr = bgpio_map(pdev, "clr", sz, &err);
	if (err)
		return err;

	dirout = bgpio_map(pdev, "dirout", sz, &err);
	if (err)
		return err;

	dirin = bgpio_map(pdev, "dirin", sz, &err);
	if (err)
		return err;

	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
	if (!bgc)
		return -ENOMEM;

	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
	if (err)
		return err;

	if (pdata) {
		if (pdata->label)
			bgc->gc.label = pdata->label;
		bgc->gc.base = pdata->base;
		if (pdata->ngpio > 0)
			bgc->gc.ngpio = pdata->ngpio;
	}

	platform_set_drvdata(pdev, bgc);

	return gpiochip_add(&bgc->gc);
}

static int bgpio_pdev_remove(struct platform_device *pdev)
{
	struct bgpio_chip *bgc = platform_get_drvdata(pdev);

	return bgpio_remove(bgc);
}

static const struct platform_device_id bgpio_id_table[] = {
	{
		.name		= "basic-mmio-gpio",
		.driver_data	= 0,
	}, {
		.name		= "basic-mmio-gpio-be",
		.driver_data	= BGPIOF_BIG_ENDIAN,
	},
	{ }
};
MODULE_DEVICE_TABLE(platform, bgpio_id_table);

static struct platform_driver bgpio_driver = {
	.driver = {
		.name = "basic-mmio-gpio",
	},
	.id_table = bgpio_id_table,
	.probe = bgpio_pdev_probe,
	.remove = bgpio_pdev_remove,
};

module_platform_driver(bgpio_driver);

#endif /* CONFIG_GPIO_GENERIC_PLATFORM */

MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
aeec56e3	1	/*
c103de24	2	* Generic driver for memory-mapped GPIO controllers.
aeec56e3 AV	3	*
	4	* Copyright 2008 MontaVista Software, Inc.
	5	* Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	* ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
	13	* ...`` ```````..
	14	* ..The simplest form of a GPIO controller that the driver supports is``
	15	* `.just a single "data" register, where GPIO state can be read and/or `
	16	* `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
	17	* `````````
	18	___
	19	_/~~\|___/~\| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
	20	__________\|~$@~~~ %~ /ooooo*o\ .. Implementing such a GPIO .
	21	o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
	22	`....trivial..'~`.```.```
	23	* ```````
	24	* .```````~~~~`..`.``.``.
	25	* . The driver supports `... ,..```.`~~~```````````````....````.``,,
	26	* . big-endian notation, just`. .. A bit more sophisticated controllers ,
	27	* . register the device with -be`. .with a pair of set/clear-bit registers ,
	28	* `.. suffix. ```~~`````....`.` . affecting the data register and the .`
	29	* ``.`.``...``` ```.. output pins are also supported.`
	30	* ^^ `````.`````````.,``~``~``~~``````
	31	* . ^^
	32	* ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
	33	* .. The expectation is that in at least some cases . ,-~~~-,
	34	* .this will be used with roll-your-own ASIC/FPGA .` \ /
	35	* .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
	36	* ..````````......``````````` \o_
	37	* \|
	38	* ^^ / \
	39	*
	40	* ...`````~~`.....``.`..........``````.`.``.```........``.
	41	* ` 8, 16, 32 and 64 bits registers are supported, and``.
	42	* . the number of GPIOs is determined by the width of ~
	43	* .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
	44	* `.......````.```
	45	*/
	46
	47	#include <linux/init.h>
280df6b3	48	#include <linux/err.h>
aeec56e3 AV	49	#include <linux/bug.h>
	50	#include <linux/kernel.h>
	51	#include <linux/module.h>
	52	#include <linux/spinlock.h>
	53	#include <linux/compiler.h>
	54	#include <linux/types.h>
	55	#include <linux/errno.h>
	56	#include <linux/log2.h>
	57	#include <linux/ioport.h>
	58	#include <linux/io.h>
	59	#include <linux/gpio.h>
	60	#include <linux/slab.h>
	61	#include <linux/platform_device.h>
	62	#include <linux/mod_devicetable.h>
	63	#include <linux/basic_mmio_gpio.h>
	64
8467afec	65	static void bgpio_write8(void __iomem *reg, unsigned long data)
aeec56e3	66	{
fd996235	67	writeb(data, reg);
aeec56e3 AV	68	}
aeec56e3 AV	69
8467afec	70	static unsigned long bgpio_read8(void __iomem *reg)
aeec56e3	71	{
fd996235	72	return readb(reg);
8467afec JI	73	}
	74
	75	static void bgpio_write16(void __iomem *reg, unsigned long data)
	76	{
fd996235	77	writew(data, reg);
8467afec JI	78	}
	79
	80	static unsigned long bgpio_read16(void __iomem *reg)
	81	{
fd996235	82	return readw(reg);
8467afec JI	83	}
	84
	85	static void bgpio_write32(void __iomem *reg, unsigned long data)
	86	{
fd996235	87	writel(data, reg);
8467afec JI	88	}
	89
	90	static unsigned long bgpio_read32(void __iomem *reg)
	91	{
fd996235	92	return readl(reg);
8467afec JI	93	}
8467afec JI	94
aeec56e3	95	#if BITS_PER_LONG >= 64
8467afec JI	96	static void bgpio_write64(void __iomem *reg, unsigned long data)
8467afec JI	97	{
fd996235	98	writeq(data, reg);
8467afec JI	99	}
	100
	101	static unsigned long bgpio_read64(void __iomem *reg)
	102	{
fd996235	103	return readq(reg);
aeec56e3	104	}
8467afec	105	#endif /* BITS_PER_LONG >= 64 */
aeec56e3	106
2b78f1e1 AL	107	static void bgpio_write16be(void __iomem *reg, unsigned long data)
	108	{
	109	iowrite16be(data, reg);
	110	}
	111
	112	static unsigned long bgpio_read16be(void __iomem *reg)
	113	{
	114	return ioread16be(reg);
	115	}
	116
	117	static void bgpio_write32be(void __iomem *reg, unsigned long data)
	118	{
	119	iowrite32be(data, reg);
	120	}
	121
	122	static unsigned long bgpio_read32be(void __iomem *reg)
	123	{
	124	return ioread32be(reg);
	125	}
	126
aeec56e3 AV	127	static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
aeec56e3 AV	128	{
8467afec JI	129	return 1 << pin;
	130	}
	131
	132	static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
	133	unsigned int pin)
	134	{
	135	return 1 << (bgc->bits - 1 - pin);
aeec56e3 AV	136	}
	137
	138	static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
	139	{
	140	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	141
25b35da7	142	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
aeec56e3 AV	143	}
	144
	145	static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	146	{
	147	struct bgpio_chip *bgc = to_bgpio_chip(gc);
8467afec	148	unsigned long mask = bgc->pin2mask(bgc, gpio);
aeec56e3 AV	149	unsigned long flags;
aeec56e3 AV	150
aeec56e3 AV	151	spin_lock_irqsave(&bgc->lock, flags);
	152
	153	if (val)
	154	bgc->data \|= mask;
	155	else
	156	bgc->data &= ~mask;
	157
8467afec	158	bgc->write_reg(bgc->reg_dat, bgc->data);
aeec56e3 AV	159
	160	spin_unlock_irqrestore(&bgc->lock, flags);
	161	}
	162
e027d6f9 JI	163	static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
	164	int val)
	165	{
	166	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	167	unsigned long mask = bgc->pin2mask(bgc, gpio);
	168
	169	if (val)
	170	bgc->write_reg(bgc->reg_set, mask);
	171	else
	172	bgc->write_reg(bgc->reg_clr, mask);
	173	}
	174
dd86a0cc JI	175	static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
	176	{
	177	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	178	unsigned long mask = bgc->pin2mask(bgc, gpio);
	179	unsigned long flags;
	180
	181	spin_lock_irqsave(&bgc->lock, flags);
	182
	183	if (val)
	184	bgc->data \|= mask;
	185	else
	186	bgc->data &= ~mask;
	187
	188	bgc->write_reg(bgc->reg_set, bgc->data);
	189
	190	spin_unlock_irqrestore(&bgc->lock, flags);
	191	}
	192
73c4ceda RI	193	static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
	194	unsigned long mask, unsigned long bits,
	195	unsigned long *set_mask,
	196	unsigned long *clear_mask)
	197	{
	198	int i;
	199
	200	*set_mask = 0;
	201	*clear_mask = 0;
	202
	203	for (i = 0; i < bgc->bits; i++) {
	204	if (*mask == 0)
	205	break;
	206	if (__test_and_clear_bit(i, mask)) {
	207	if (test_bit(i, bits))
	208	*set_mask \|= bgc->pin2mask(bgc, i);
	209	else
	210	*clear_mask \|= bgc->pin2mask(bgc, i);
	211	}
	212	}
	213	}
	214
	215	static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
	216	unsigned long *mask,
	217	unsigned long *bits,
	218	void __iomem *reg)
	219	{
	220	unsigned long flags;
	221	unsigned long set_mask, clear_mask;
	222
	223	spin_lock_irqsave(&bgc->lock, flags);
	224
	225	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
	226
	227	bgc->data \|= set_mask;
	228	bgc->data &= ~clear_mask;
	229
	230	bgc->write_reg(reg, bgc->data);
	231
	232	spin_unlock_irqrestore(&bgc->lock, flags);
	233	}
	234
	235	static void bgpio_set_multiple(struct gpio_chip gc, unsigned long mask,
	236	unsigned long *bits)
	237	{
	238	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	239
	240	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
	241	}
	242
	243	static void bgpio_set_multiple_set(struct gpio_chip gc, unsigned long mask,
	244	unsigned long *bits)
	245	{
	246	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	247
	248	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
	249	}
	250
	251	static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
	252	unsigned long *mask,
	253	unsigned long *bits)
	254	{
	255	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	256	unsigned long set_mask, clear_mask;
257
258	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
259
260	if (set_mask)
261	bgc->write_reg(bgc->reg_set, set_mask);
262	if (clear_mask)
263	bgc->write_reg(bgc->reg_clr, clear_mask);
264	}
265
31029116 JI	266	static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
	267	{
	268	return 0;
	269	}
	270
	271	static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
	272	int val)
	273	{
	274	gc->set(gc, gpio, val);
	275
	276	return 0;
	277	}
	278
aeec56e3 AV	279	static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
aeec56e3 AV	280	{
31029116 JI	281	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	282	unsigned long flags;
	283
	284	spin_lock_irqsave(&bgc->lock, flags);
	285
	286	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	287	bgc->write_reg(bgc->reg_dir, bgc->dir);
	288
	289	spin_unlock_irqrestore(&bgc->lock, flags);
	290
aeec56e3 AV	291	return 0;
	292	}
	293
	294	static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	295	{
31029116 JI	296	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	297	unsigned long flags;
	298
	299	gc->set(gc, gpio, val);
	300
	301	spin_lock_irqsave(&bgc->lock, flags);
	302
	303	bgc->dir \|= bgc->pin2mask(bgc, gpio);
	304	bgc->write_reg(bgc->reg_dir, bgc->dir);
	305
	306	spin_unlock_irqrestore(&bgc->lock, flags);
	307
	308	return 0;
	309	}
	310
	311	static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
	312	{
	313	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	314	unsigned long flags;
	315
	316	spin_lock_irqsave(&bgc->lock, flags);
	317
	318	bgc->dir \|= bgc->pin2mask(bgc, gpio);
	319	bgc->write_reg(bgc->reg_dir, bgc->dir);
	320
	321	spin_unlock_irqrestore(&bgc->lock, flags);
	322
	323	return 0;
	324	}
	325
	326	static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
	327	{
	328	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	329	unsigned long flags;
	330
e027d6f9 JI	331	gc->set(gc, gpio, val);
e027d6f9 JI	332
31029116 JI	333	spin_lock_irqsave(&bgc->lock, flags);
	334
	335	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	336	bgc->write_reg(bgc->reg_dir, bgc->dir);
	337
	338	spin_unlock_irqrestore(&bgc->lock, flags);
	339
aeec56e3 AV	340	return 0;
	341	}
	342
280df6b3 JI	343	static int bgpio_setup_accessors(struct device *dev,
280df6b3 JI	344	struct bgpio_chip *bgc,
2b78f1e1 AL	345	bool bit_be,
2b78f1e1 AL	346	bool byte_be)
aeec56e3	347	{
8467afec JI	348
	349	switch (bgc->bits) {
	350	case 8:
	351	bgc->read_reg = bgpio_read8;
	352	bgc->write_reg = bgpio_write8;
	353	break;
	354	case 16:
2b78f1e1 AL	355	if (byte_be) {
	356	bgc->read_reg = bgpio_read16be;
	357	bgc->write_reg = bgpio_write16be;
	358	} else {
	359	bgc->read_reg = bgpio_read16;
	360	bgc->write_reg = bgpio_write16;
	361	}
8467afec JI	362	break;
8467afec JI	363	case 32:
2b78f1e1 AL	364	if (byte_be) {
	365	bgc->read_reg = bgpio_read32be;
	366	bgc->write_reg = bgpio_write32be;
	367	} else {
	368	bgc->read_reg = bgpio_read32;
	369	bgc->write_reg = bgpio_write32;
	370	}
8467afec JI	371	break;
	372	#if BITS_PER_LONG >= 64
	373	case 64:
2b78f1e1 AL	374	if (byte_be) {
	375	dev_err(dev,
	376	"64 bit big endian byte order unsupported\n");
	377	return -EINVAL;
	378	} else {
	379	bgc->read_reg = bgpio_read64;
	380	bgc->write_reg = bgpio_write64;
	381	}
8467afec JI	382	break;
	383	#endif /* BITS_PER_LONG >= 64 */
	384	default:
280df6b3	385	dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
8467afec JI	386	return -EINVAL;
	387	}
	388
2b78f1e1	389	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
8467afec JI	390
	391	return 0;
	392	}
	393
e027d6f9 JI	394	/*
e027d6f9 JI	395	* Create the device and allocate the resources. For setting GPIO's there are
dd86a0cc	396	* three supported configurations:
e027d6f9	397	*
dd86a0cc	398	* - single input/output register resource (named "dat").
e027d6f9	399	* - set/clear pair (named "set" and "clr").
dd86a0cc JI	400	* - single output register resource and single input resource ("set" and
dd86a0cc JI	401	* dat").
e027d6f9 JI	402	*
	403	* For the single output register, this drives a 1 by setting a bit and a zero
	404	* by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
	405	* in the set register and clears it by setting a bit in the clear register.
	406	* The configuration is detected by which resources are present.
31029116 JI	407	*
	408	* For setting the GPIO direction, there are three supported configurations:
	409	*
	410	* - simple bidirection GPIO that requires no configuration.
	411	* - an output direction register (named "dirout") where a 1 bit
	412	* indicates the GPIO is an output.
	413	* - an input direction register (named "dirin") where a 1 bit indicates
	414	* the GPIO is an input.
e027d6f9	415	*/
280df6b3 JI	416	static int bgpio_setup_io(struct bgpio_chip *bgc,
	417	void __iomem *dat,
	418	void __iomem *set,
	419	void __iomem *clr)
8467afec	420	{
aeec56e3	421
280df6b3	422	bgc->reg_dat = dat;
aeec56e3	423	if (!bgc->reg_dat)
280df6b3	424	return -EINVAL;
e027d6f9	425
280df6b3 JI	426	if (set && clr) {
	427	bgc->reg_set = set;
	428	bgc->reg_clr = clr;
e027d6f9	429	bgc->gc.set = bgpio_set_with_clear;
73c4ceda	430	bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
280df6b3 JI	431	} else if (set && !clr) {
280df6b3 JI	432	bgc->reg_set = set;
dd86a0cc	433	bgc->gc.set = bgpio_set_set;
73c4ceda	434	bgc->gc.set_multiple = bgpio_set_multiple_set;
e027d6f9 JI	435	} else {
e027d6f9 JI	436	bgc->gc.set = bgpio_set;
73c4ceda	437	bgc->gc.set_multiple = bgpio_set_multiple;
aeec56e3 AV	438	}
aeec56e3 AV	439
dd86a0cc JI	440	bgc->gc.get = bgpio_get;
dd86a0cc JI	441
e027d6f9 JI	442	return 0;
	443	}
	444
280df6b3 JI	445	static int bgpio_setup_direction(struct bgpio_chip *bgc,
	446	void __iomem *dirout,
	447	void __iomem *dirin)
31029116	448	{
280df6b3	449	if (dirout && dirin) {
31029116	450	return -EINVAL;
280df6b3 JI	451	} else if (dirout) {
280df6b3 JI	452	bgc->reg_dir = dirout;
31029116 JI	453	bgc->gc.direction_output = bgpio_dir_out;
31029116 JI	454	bgc->gc.direction_input = bgpio_dir_in;
280df6b3 JI	455	} else if (dirin) {
280df6b3 JI	456	bgc->reg_dir = dirin;
31029116 JI	457	bgc->gc.direction_output = bgpio_dir_out_inv;
	458	bgc->gc.direction_input = bgpio_dir_in_inv;
	459	} else {
	460	bgc->gc.direction_output = bgpio_simple_dir_out;
	461	bgc->gc.direction_input = bgpio_simple_dir_in;
	462	}
	463
	464	return 0;
	465	}
	466
7b42e3db AF	467	static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
	468	{
	469	if (gpio_pin < chip->ngpio)
	470	return 0;
	471
	472	return -EINVAL;
	473	}
	474
4f5b0480	475	int bgpio_remove(struct bgpio_chip *bgc)
280df6b3	476	{
9f5132ae	477	gpiochip_remove(&bgc->gc);
9f5132ae	478	return 0;
280df6b3 JI	479	}
	480	EXPORT_SYMBOL_GPL(bgpio_remove);
	481
4f5b0480 RK	482	int bgpio_init(struct bgpio_chip bgc, struct device dev,
	483	unsigned long sz, void __iomem dat, void __iomem set,
	484	void __iomem clr, void __iomem dirout, void __iomem *dirin,
3e11f7b8	485	unsigned long flags)
e027d6f9	486	{
e027d6f9	487	int ret;
e027d6f9	488
280df6b3 JI	489	if (!is_power_of_2(sz))
280df6b3 JI	490	return -EINVAL;
e027d6f9	491
280df6b3 JI	492	bgc->bits = sz * 8;
	493	if (bgc->bits > BITS_PER_LONG)
	494	return -EINVAL;
	495
	496	spin_lock_init(&bgc->lock);
	497	bgc->gc.dev = dev;
	498	bgc->gc.label = dev_name(dev);
	499	bgc->gc.base = -1;
	500	bgc->gc.ngpio = bgc->bits;
7b42e3db	501	bgc->gc.request = bgpio_request;
280df6b3 JI	502
280df6b3 JI	503	ret = bgpio_setup_io(bgc, dat, set, clr);
e027d6f9 JI	504	if (ret)
e027d6f9 JI	505	return ret;
aeec56e3	506
2b78f1e1 AL	507	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
2b78f1e1 AL	508	flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
8467afec JI	509	if (ret)
8467afec JI	510	return ret;
aeec56e3	511
280df6b3	512	ret = bgpio_setup_direction(bgc, dirout, dirin);
31029116 JI	513	if (ret)
	514	return ret;
	515
8467afec	516	bgc->data = bgc->read_reg(bgc->reg_dat);
3e11f7b8 SG	517	if (bgc->gc.set == bgpio_set_set &&
	518	!(flags & BGPIOF_UNREADABLE_REG_SET))
	519	bgc->data = bgc->read_reg(bgc->reg_set);
	520	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
	521	bgc->dir = bgc->read_reg(bgc->reg_dir);
924e7a9f	522
280df6b3 JI	523	return ret;
	524	}
	525	EXPORT_SYMBOL_GPL(bgpio_init);
aeec56e3	526
c103de24	527	#ifdef CONFIG_GPIO_GENERIC_PLATFORM
aeec56e3	528
280df6b3 JI	529	static void __iomem bgpio_map(struct platform_device pdev,
	530	const char *name,
	531	resource_size_t sane_sz,
	532	int *err)
	533	{
	534	struct device *dev = &pdev->dev;
	535	struct resource *r;
	536	resource_size_t start;
	537	resource_size_t sz;
	538	void __iomem *ret;
	539
	540	*err = 0;
	541
	542	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	543	if (!r)
	544	return NULL;
	545
	546	sz = resource_size(r);
	547	if (sz != sane_sz) {
	548	*err = -EINVAL;
	549	return NULL;
	550	}
	551
	552	start = r->start;
	553	if (!devm_request_mem_region(dev, start, sz, r->name)) {
	554	*err = -EBUSY;
	555	return NULL;
	556	}
	557
	558	ret = devm_ioremap(dev, start, sz);
	559	if (!ret) {
	560	*err = -ENOMEM;
	561	return NULL;
	562	}
aeec56e3 AV	563
	564	return ret;
	565	}
	566
3836309d	567	static int bgpio_pdev_probe(struct platform_device *pdev)
280df6b3 JI	568	{
	569	struct device *dev = &pdev->dev;
	570	struct resource *r;
	571	void __iomem *dat;
	572	void __iomem *set;
	573	void __iomem *clr;
	574	void __iomem *dirout;
	575	void __iomem *dirin;
	576	unsigned long sz;
19338530	577	unsigned long flags = pdev->id_entry->driver_data;
280df6b3 JI	578	int err;
	579	struct bgpio_chip *bgc;
	580	struct bgpio_pdata *pdata = dev_get_platdata(dev);
	581
	582	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
	583	if (!r)
	584	return -EINVAL;
	585
	586	sz = resource_size(r);
	587
	588	dat = bgpio_map(pdev, "dat", sz, &err);
	589	if (!dat)
	590	return err ? err : -EINVAL;
	591
	592	set = bgpio_map(pdev, "set", sz, &err);
	593	if (err)
	594	return err;
	595
	596	clr = bgpio_map(pdev, "clr", sz, &err);
	597	if (err)
	598	return err;
	599
	600	dirout = bgpio_map(pdev, "dirout", sz, &err);
	601	if (err)
	602	return err;
	603
	604	dirin = bgpio_map(pdev, "dirin", sz, &err);
	605	if (err)
	606	return err;
	607
280df6b3 JI	608	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
	609	if (!bgc)
	610	return -ENOMEM;
	611
3e11f7b8	612	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
280df6b3 JI	613	if (err)
	614	return err;
	615
	616	if (pdata) {
781f6d71 PM	617	if (pdata->label)
781f6d71 PM	618	bgc->gc.label = pdata->label;
280df6b3 JI	619	bgc->gc.base = pdata->base;
	620	if (pdata->ngpio > 0)
	621	bgc->gc.ngpio = pdata->ngpio;
	622	}
	623
	624	platform_set_drvdata(pdev, bgc);
	625
	626	return gpiochip_add(&bgc->gc);
	627	}
	628
206210ce	629	static int bgpio_pdev_remove(struct platform_device *pdev)
aeec56e3	630	{
4ddb8ae2	631	struct bgpio_chip *bgc = platform_get_drvdata(pdev);
aeec56e3	632
280df6b3	633	return bgpio_remove(bgc);
aeec56e3 AV	634	}
	635
	636	static const struct platform_device_id bgpio_id_table[] = {
19338530 AS	637	{
	638	.name = "basic-mmio-gpio",
	639	.driver_data = 0,
	640	}, {
	641	.name = "basic-mmio-gpio-be",
	642	.driver_data = BGPIOF_BIG_ENDIAN,
	643	},
	644	{ }
aeec56e3 AV	645	};
	646	MODULE_DEVICE_TABLE(platform, bgpio_id_table);
	647
	648	static struct platform_driver bgpio_driver = {
	649	.driver = {
	650	.name = "basic-mmio-gpio",
	651	},
	652	.id_table = bgpio_id_table,
280df6b3	653	.probe = bgpio_pdev_probe,
8283c4ff	654	.remove = bgpio_pdev_remove,
aeec56e3 AV	655	};
aeec56e3 AV	656
6f61415e	657	module_platform_driver(bgpio_driver);
280df6b3	658
c103de24	659	#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
aeec56e3 AV	660
	661	MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
	662	MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
	663	MODULE_LICENSE("GPL");