[deliverable/linux.git] / drivers / gpio / gpio-intel-mid.c

/*
 * Intel MID GPIO driver
 *
 * Copyright (c) 2008-2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Clovertrail platform Cloverview chip.
 * Merrifield platform Tangier chip.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/irqdomain.h>

#define INTEL_MID_IRQ_TYPE_EDGE		(1 << 0)
#define INTEL_MID_IRQ_TYPE_LEVEL	(1 << 1)

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

/* intel_mid gpio driver data */
struct intel_mid_gpio_ddata {
	u16 ngpio;		/* number of gpio pins */
	u32 gplr_offset;	/* offset of first GPLR register from base */
	u32 flis_base;		/* base address of FLIS registers */
	u32 flis_len;		/* length of FLIS registers */
	u32 (*get_flis_offset)(int gpio);
	u32 chip_irq_type;	/* chip interrupt type */
};

struct intel_mid_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
	struct irq_domain		*domain;
};

#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	intel_gpio_set(chip, offset, value);

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	return irq_create_mapping(priv->domain, offset);
}

static int intel_mid_irq_type(struct irq_data *d, unsigned type)
{
	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);

	if (gpio >= priv->chip.ngpio)
		return -EINVAL;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static void intel_mid_irq_unmask(struct irq_data *d)
{
}

static void intel_mid_irq_mask(struct irq_data *d)
{
}

static int intel_mid_irq_reqres(struct irq_data *d)
{
	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);

	if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) {
		dev_err(priv->chip.dev,
			"unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void intel_mid_irq_relres(struct irq_data *d)
{
	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);

	gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
}

static struct irq_chip intel_mid_irqchip = {
	.name		= "INTEL_MID-GPIO",
	.irq_mask	= intel_mid_irq_mask,
	.irq_unmask	= intel_mid_irq_unmask,
	.irq_set_type	= intel_mid_irq_type,
	.irq_request_resources = intel_mid_irq_reqres,
	.irq_release_resources = intel_mid_irq_relres,
};

static const struct intel_mid_gpio_ddata gpio_lincroft = {
	.ngpio = 64,
};

static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_penwell_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_tangier = {
	.ngpio = 192,
	.gplr_offset = 4,
	.flis_base = 0xff0c0000,
	.flis_len = 0x8000,
	.get_flis_offset = NULL,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct pci_device_id intel_gpio_ids[] = {
	{
		/* Lincroft */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
		.driver_data = (kernel_ulong_t)&gpio_lincroft,
	},
	{
		/* Penwell AON */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
		.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	},
	{
		/* Penwell Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
		.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	},
	{
		/* Cloverview Aon */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	},
	{
		/* Cloverview Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	},
	{
		/* Tangier */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
		.driver_data = (kernel_ulong_t)&gpio_tangier,
	},
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, intel_gpio_ids);

static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < priv->chip.ngpio; base += 32) {
		gedr = gpio_reg(&priv->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(priv->domain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < priv->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&priv->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&priv->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&priv->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
			    irq_hw_number_t hwirq)
{
	struct intel_mid_gpio *priv = d->host_data;

	irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
	irq_set_chip_data(irq, priv);
	irq_set_irq_type(irq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops intel_gpio_irq_ops = {
	.map = intel_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int intel_gpio_runtime_idle(struct device *dev)
{
	int err = pm_schedule_suspend(dev, 500);
	return err ?: -EBUSY;
}

static const struct dev_pm_ops intel_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
};

static int intel_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct intel_mid_gpio *priv;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	struct intel_mid_gpio_ddata *ddata =
				(struct intel_mid_gpio_ddata *)id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "can't allocate chip data\n");
		return -ENOMEM;
	}

	priv->reg_base = pcim_iomap_table(pdev)[0];
	priv->chip.label = dev_name(&pdev->dev);
	priv->chip.dev = &pdev->dev;
	priv->chip.request = intel_gpio_request;
	priv->chip.direction_input = intel_gpio_direction_input;
	priv->chip.direction_output = intel_gpio_direction_output;
	priv->chip.get = intel_gpio_get;
	priv->chip.set = intel_gpio_set;
	priv->chip.to_irq = intel_gpio_to_irq;
	priv->chip.base = gpio_base;
	priv->chip.ngpio = ddata->ngpio;
	priv->chip.can_sleep = false;
	priv->pdev = pdev;

	spin_lock_init(&priv->lock);

	priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
					irq_base, &intel_gpio_irq_ops, priv);
	if (!priv->domain)
		return -ENOMEM;

	pci_set_drvdata(pdev, priv);
	retval = gpiochip_add(&priv->chip);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	intel_mid_irq_init_hw(priv);

	irq_set_handler_data(pdev->irq, priv);
	irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver intel_gpio_driver = {
	.name		= "intel_mid_gpio",
	.id_table	= intel_gpio_ids,
	.probe		= intel_gpio_probe,
	.driver		= {
		.pm	= &intel_gpio_pm_ops,
	},
};

static int __init intel_gpio_init(void)
{
	return pci_register_driver(&intel_gpio_driver);
}

device_initcall(intel_gpio_init);
Commit	Line	Data
c103de24	1	/*
a0bbf032	2	* Intel MID GPIO driver
c103de24	3	*
a0bbf032	4	* Copyright (c) 2008-2014 Intel Corporation.
8bf02617 AD	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
8bf02617 AD	14	*/
	15
	16	/* Supports:
	17	* Moorestown platform Langwell chip.
8081c84c	18	* Medfield platform Penwell chip.
f89a768f DC	19	* Clovertrail platform Cloverview chip.
f89a768f DC	20	* Merrifield platform Tangier chip.
8bf02617 AD	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/pci.h>
72b4379e	25	#include <linux/platform_device.h>
8bf02617 AD	26	#include <linux/kernel.h>
	27	#include <linux/delay.h>
	28	#include <linux/stddef.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/init.h>
	31	#include <linux/irq.h>
	32	#include <linux/io.h>
	33	#include <linux/gpio.h>
5a0e3ad6	34	#include <linux/slab.h>
7812803a	35	#include <linux/pm_runtime.h>
465f2bd4	36	#include <linux/irqdomain.h>
8bf02617	37
f89a768f DC	38	#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
f89a768f DC	39	#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
d56d6b3d	40
8081c84c AD	41	/*
	42	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	43	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	44	* registers to control them, so we only define the order here instead of a
	45	* structure, to get a bit offset for a pin (use GPDR as an example):
	46	*
	47	* nreg = ngpio / 32;
	48	* reg = offset / 32;
	49	* bit = offset % 32;
	50	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	51	*
	52	* so the bit of reg_addr is to control pin offset's GPDR feature
	53	*/
	54
	55	enum GPIO_REG {
	56	GPLR = 0, /* pin level read-only */
	57	GPDR, /* pin direction */
	58	GPSR, /* pin set */
	59	GPCR, /* pin clear */
	60	GRER, /* rising edge detect */
	61	GFER, /* falling edge detect */
	62	GEDR, /* edge detect result */
8c0f7b10	63	GAFR, /* alt function */
8bf02617 AD	64	};
8bf02617 AD	65
f89a768f DC	66	/* intel_mid gpio driver data */
f89a768f DC	67	struct intel_mid_gpio_ddata {
d56d6b3d DC	68	u16 ngpio; /* number of gpio pins */
	69	u32 gplr_offset; /* offset of first GPLR register from base */
	70	u32 flis_base; /* base address of FLIS registers */
	71	u32 flis_len; /* length of FLIS registers */
	72	u32 (*get_flis_offset)(int gpio);
	73	u32 chip_irq_type; /* chip interrupt type */
	74	};
	75
f89a768f	76	struct intel_mid_gpio {
8bf02617	77	struct gpio_chip chip;
64c8cbc1	78	void __iomem *reg_base;
8bf02617	79	spinlock_t lock;
7812803a	80	struct pci_dev *pdev;
465f2bd4	81	struct irq_domain *domain;
8bf02617 AD	82	};
8bf02617 AD	83
f89a768f	84	#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
46ebfbc3	85
8081c84c	86	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	87	enum GPIO_REG reg_type)
8bf02617	88	{
f89a768f	89	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	90	unsigned nreg = chip->ngpio / 32;
8bf02617	91	u8 reg = offset / 32;
8081c84c	92
f89a768f	93	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	94	}
8081c84c AD	95
8c0f7b10 AH	96	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	97	enum GPIO_REG reg_type)
	98	{
f89a768f	99	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8c0f7b10 AH	100	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	101	u8 reg = offset / 16;
8c0f7b10	102
f89a768f	103	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	104	}
8c0f7b10 AH	105
f89a768f	106	static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
8c0f7b10 AH	107	{
	108	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	109	u32 value = readl(gafr);
	110	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	111
	112	if (af) {
	113	value &= ~(3 << shift);
	114	writel(value, gafr);
	115	}
	116	return 0;
	117	}
	118
f89a768f	119	static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
8081c84c AD	120	{
8081c84c AD	121	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	122
8bf02617 AD	123	return readl(gplr) & BIT(offset % 32);
	124	}
	125
f89a768f	126	static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
8bf02617	127	{
8bf02617 AD	128	void __iomem gpsr, gpcr;
	129
	130	if (value) {
8081c84c	131	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	132	writel(BIT(offset % 32), gpsr);
8bf02617 AD	133	} else {
8081c84c	134	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	135	writel(BIT(offset % 32), gpcr);
	136	}
	137	}
	138
f89a768f	139	static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
8bf02617	140	{
f89a768f	141	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	142	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	143	u32 value;
8bf02617 AD	144	unsigned long flags;
8bf02617	145
f89a768f DC	146	if (priv->pdev)
f89a768f DC	147	pm_runtime_get(&priv->pdev->dev);
7812803a	148
f89a768f	149	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	150	value = readl(gpdr);
	151	value &= ~BIT(offset % 32);
	152	writel(value, gpdr);
f89a768f	153	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	154
f89a768f DC	155	if (priv->pdev)
f89a768f DC	156	pm_runtime_put(&priv->pdev->dev);
7812803a	157
8bf02617 AD	158	return 0;
	159	}
	160
f89a768f	161	static int intel_gpio_direction_output(struct gpio_chip *chip,
8bf02617 AD	162	unsigned offset, int value)
8bf02617 AD	163	{
f89a768f	164	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	165	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	166	unsigned long flags;
8bf02617	167
f89a768f	168	intel_gpio_set(chip, offset, value);
7812803a	169
f89a768f DC	170	if (priv->pdev)
f89a768f DC	171	pm_runtime_get(&priv->pdev->dev);
7812803a	172
f89a768f	173	spin_lock_irqsave(&priv->lock, flags);
8bf02617	174	value = readl(gpdr);
6eab04a8	175	value \|= BIT(offset % 32);
8bf02617	176	writel(value, gpdr);
f89a768f	177	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	178
f89a768f DC	179	if (priv->pdev)
f89a768f DC	180	pm_runtime_put(&priv->pdev->dev);
7812803a	181
8bf02617 AD	182	return 0;
	183	}
	184
f89a768f	185	static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
8bf02617	186	{
f89a768f DC	187	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
f89a768f DC	188	return irq_create_mapping(priv->domain, offset);
8bf02617 AD	189	}
8bf02617 AD	190
f89a768f	191	static int intel_mid_irq_type(struct irq_data *d, unsigned type)
8bf02617	192	{
f89a768f	193	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
465f2bd4	194	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	195	unsigned long flags;
8bf02617 AD	196	u32 value;
f89a768f DC	197	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
f89a768f DC	198	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
8bf02617	199
f89a768f	200	if (gpio >= priv->chip.ngpio)
8bf02617	201	return -EINVAL;
7812803a	202
f89a768f DC	203	if (priv->pdev)
f89a768f DC	204	pm_runtime_get(&priv->pdev->dev);
7812803a	205
f89a768f	206	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	207	if (type & IRQ_TYPE_EDGE_RISING)
	208	value = readl(grer) \| BIT(gpio % 32);
	209	else
	210	value = readl(grer) & (~BIT(gpio % 32));
	211	writel(value, grer);
	212
	213	if (type & IRQ_TYPE_EDGE_FALLING)
	214	value = readl(gfer) \| BIT(gpio % 32);
	215	else
	216	value = readl(gfer) & (~BIT(gpio % 32));
	217	writel(value, gfer);
f89a768f	218	spin_unlock_irqrestore(&priv->lock, flags);
8bf02617	219
f89a768f DC	220	if (priv->pdev)
f89a768f DC	221	pm_runtime_put(&priv->pdev->dev);
7812803a	222
8bf02617	223	return 0;
fd0574cb	224	}
8bf02617	225
f89a768f	226	static void intel_mid_irq_unmask(struct irq_data *d)
8bf02617	227	{
fd0574cb	228	}
8bf02617	229
f89a768f	230	static void intel_mid_irq_mask(struct irq_data *d)
8bf02617	231	{
fd0574cb	232	}
8bf02617	233
57ef0428	234	static int intel_mid_irq_reqres(struct irq_data *d)
aa6baa7e LW	235	{
	236	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
	237
57ef0428	238	if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) {
aa6baa7e LW	239	dev_err(priv->chip.dev,
	240	"unable to lock HW IRQ %lu for IRQ\n",
	241	irqd_to_hwirq(d));
57ef0428 LW	242	return -EINVAL;
57ef0428 LW	243	}
aa6baa7e LW	244	return 0;
	245	}
	246
57ef0428	247	static void intel_mid_irq_relres(struct irq_data *d)
aa6baa7e LW	248	{
	249	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
	250
aa6baa7e LW	251	gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
	252	}
	253
f89a768f DC	254	static struct irq_chip intel_mid_irqchip = {
	255	.name = "INTEL_MID-GPIO",
	256	.irq_mask = intel_mid_irq_mask,
	257	.irq_unmask = intel_mid_irq_unmask,
	258	.irq_set_type = intel_mid_irq_type,
57ef0428 LW	259	.irq_request_resources = intel_mid_irq_reqres,
57ef0428 LW	260	.irq_release_resources = intel_mid_irq_relres,
8bf02617 AD	261	};
8bf02617 AD	262
f89a768f	263	static const struct intel_mid_gpio_ddata gpio_lincroft = {
d56d6b3d DC	264	.ngpio = 64,
	265	};
	266
f89a768f	267	static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
d56d6b3d	268	.ngpio = 96,
f89a768f	269	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	270	};
d56d6b3d DC	271
f89a768f	272	static const struct intel_mid_gpio_ddata gpio_penwell_core = {
d56d6b3d	273	.ngpio = 96,
f89a768f	274	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	275	};
d56d6b3d DC	276
f89a768f	277	static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
d56d6b3d	278	.ngpio = 96,
f89a768f	279	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE \| INTEL_MID_IRQ_TYPE_LEVEL,
d56d6b3d DC	280	};
d56d6b3d DC	281
f89a768f	282	static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
d56d6b3d	283	.ngpio = 96,
f89a768f	284	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	285	};
d56d6b3d DC	286
f89a768f	287	static const struct intel_mid_gpio_ddata gpio_tangier = {
d56d6b3d DC	288	.ngpio = 192,
	289	.gplr_offset = 4,
	290	.flis_base = 0xff0c0000,
	291	.flis_len = 0x8000,
	292	.get_flis_offset = NULL,
f89a768f	293	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	294	};
d56d6b3d DC	295
14f4a883	296	static const struct pci_device_id intel_gpio_ids[] = {
d56d6b3d DC	297	{
	298	/* Lincroft */
	299	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
	300	.driver_data = (kernel_ulong_t)&gpio_lincroft,
	301	},
	302	{
	303	/* Penwell AON */
	304	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
	305	.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	306	},
	307	{
	308	/* Penwell Core */
	309	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
	310	.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	311	},
	312	{
	313	/* Cloverview Aon */
	314	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
	315	.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	316	},
	317	{
	318	/* Cloverview Core */
	319	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
	320	.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	321	},
	322	{
	323	/* Tangier */
	324	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
	325	.driver_data = (kernel_ulong_t)&gpio_tangier,
	326	},
	327	{ 0 }
8bf02617	328	};
f89a768f	329	MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
8bf02617	330
f89a768f	331	static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
8bf02617	332	{
20e2aa91	333	struct irq_data *data = irq_desc_get_irq_data(desc);
f89a768f	334	struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
20e2aa91	335	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	336	u32 base, gpio, mask;
732063b9	337	unsigned long pending;
8bf02617	338	void __iomem *gedr;
8bf02617 AD	339
8bf02617 AD	340	/* check GPIO controller to check which pin triggered the interrupt */
f89a768f DC	341	for (base = 0; base < priv->chip.ngpio; base += 32) {
f89a768f DC	342	gedr = gpio_reg(&priv->chip, base, GEDR);
c8f925b6	343	while ((pending = readl(gedr))) {
2345b20f	344	gpio = __ffs(pending);
84bead6c	345	mask = BIT(gpio);
84bead6c TG	346	/* Clear before handling so we can't lose an edge */
84bead6c TG	347	writel(mask, gedr);
f89a768f	348	generic_handle_irq(irq_find_mapping(priv->domain,
465f2bd4	349	base + gpio));
732063b9	350	}
8bf02617	351	}
0766d20f	352
20e2aa91	353	chip->irq_eoi(data);
8bf02617 AD	354	}
8bf02617 AD	355
f89a768f	356	static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
f5f93117 MW	357	{
	358	void __iomem *reg;
	359	unsigned base;
	360
f89a768f	361	for (base = 0; base < priv->chip.ngpio; base += 32) {
f5f93117	362	/* Clear the rising-edge detect register */
f89a768f	363	reg = gpio_reg(&priv->chip, base, GRER);
f5f93117 MW	364	writel(0, reg);
f5f93117 MW	365	/* Clear the falling-edge detect register */
f89a768f	366	reg = gpio_reg(&priv->chip, base, GFER);
f5f93117 MW	367	writel(0, reg);
f5f93117 MW	368	/* Clear the edge detect status register */
f89a768f	369	reg = gpio_reg(&priv->chip, base, GEDR);
f5f93117 MW	370	writel(~0, reg);
	371	}
	372	}
	373
ba519dd4 LW	374	static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
ba519dd4 LW	375	irq_hw_number_t hwirq)
465f2bd4	376	{
f89a768f	377	struct intel_mid_gpio *priv = d->host_data;
465f2bd4	378
e5428a68	379	irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
ba519dd4 LW	380	irq_set_chip_data(irq, priv);
ba519dd4 LW	381	irq_set_irq_type(irq, IRQ_TYPE_NONE);
465f2bd4 MW	382
	383	return 0;
	384	}
	385
f89a768f DC	386	static const struct irq_domain_ops intel_gpio_irq_ops = {
f89a768f DC	387	.map = intel_gpio_irq_map,
465f2bd4 MW	388	.xlate = irq_domain_xlate_twocell,
	389	};
	390
f89a768f	391	static int intel_gpio_runtime_idle(struct device *dev)
7812803a	392	{
84a34575	393	int err = pm_schedule_suspend(dev, 500);
84a34575	394	return err ?: -EBUSY;
7812803a KCA	395	}
7812803a KCA	396
f89a768f DC	397	static const struct dev_pm_ops intel_gpio_pm_ops = {
f89a768f DC	398	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
7812803a KCA	399	};
7812803a KCA	400
f89a768f	401	static int intel_gpio_probe(struct pci_dev *pdev,
64c8cbc1	402	const struct pci_device_id *id)
8bf02617	403	{
64c8cbc1	404	void __iomem *base;
f89a768f	405	struct intel_mid_gpio *priv;
8bf02617	406	u32 gpio_base;
2519f9ab	407	u32 irq_base;
d6a2b7ba	408	int retval;
f89a768f DC	409	struct intel_mid_gpio_ddata *ddata =
f89a768f DC	410	(struct intel_mid_gpio_ddata *)id->driver_data;
8bf02617	411
786e07ec	412	retval = pcim_enable_device(pdev);
8bf02617	413	if (retval)
8302c741	414	return retval;
8bf02617	415
786e07ec	416	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	417	if (retval) {
786e07ec AS	418	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	419	return retval;
8bf02617	420	}
64c8cbc1	421
786e07ec AS	422	base = pcim_iomap_table(pdev)[1];
786e07ec AS	423
64c8cbc1 AS	424	irq_base = readl(base);
	425	gpio_base = readl(sizeof(u32) + base);
	426
8bf02617	427	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	428	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	429
f89a768f DC	430	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
f89a768f DC	431	if (!priv) {
8aca119f	432	dev_err(&pdev->dev, "can't allocate chip data\n");
786e07ec	433	return -ENOMEM;
8bf02617	434	}
b3e35af2	435
f89a768f DC	436	priv->reg_base = pcim_iomap_table(pdev)[0];
f89a768f DC	437	priv->chip.label = dev_name(&pdev->dev);
aa6baa7e	438	priv->chip.dev = &pdev->dev;
f89a768f DC	439	priv->chip.request = intel_gpio_request;
	440	priv->chip.direction_input = intel_gpio_direction_input;
	441	priv->chip.direction_output = intel_gpio_direction_output;
	442	priv->chip.get = intel_gpio_get;
	443	priv->chip.set = intel_gpio_set;
	444	priv->chip.to_irq = intel_gpio_to_irq;
	445	priv->chip.base = gpio_base;
	446	priv->chip.ngpio = ddata->ngpio;
9fb1f39e	447	priv->chip.can_sleep = false;
f89a768f DC	448	priv->pdev = pdev;
	449
	450	spin_lock_init(&priv->lock);
	451
	452	priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
	453	irq_base, &intel_gpio_irq_ops, priv);
	454	if (!priv->domain)
786e07ec	455	return -ENOMEM;
2519f9ab	456
f89a768f DC	457	pci_set_drvdata(pdev, priv);
f89a768f DC	458	retval = gpiochip_add(&priv->chip);
8bf02617	459	if (retval) {
8aca119f	460	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	461	return retval;
8bf02617	462	}
f5f93117	463
f89a768f	464	intel_mid_irq_init_hw(priv);
f5f93117	465
f89a768f DC	466	irq_set_handler_data(pdev->irq, priv);
f89a768f DC	467	irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
8bf02617	468
7812803a KCA	469	pm_runtime_put_noidle(&pdev->dev);
	470	pm_runtime_allow(&pdev->dev);
	471
8302c741	472	return 0;
8bf02617 AD	473	}
8bf02617 AD	474
f89a768f DC	475	static struct pci_driver intel_gpio_driver = {
	476	.name = "intel_mid_gpio",
	477	.id_table = intel_gpio_ids,
	478	.probe = intel_gpio_probe,
7812803a	479	.driver = {
f89a768f	480	.pm = &intel_gpio_pm_ops,
7812803a	481	},
8bf02617 AD	482	};
8bf02617 AD	483
f89a768f	484	static int __init intel_gpio_init(void)
8bf02617	485	{
f89a768f	486	return pci_register_driver(&intel_gpio_driver);
8bf02617 AD	487	}
8bf02617 AD	488
f89a768f	489	device_initcall(intel_gpio_init);