Commit | Line | Data |
---|---|---|
c103de24 | 1 | /* |
a0bbf032 | 2 | * Intel MID GPIO driver |
c103de24 | 3 | * |
a0bbf032 | 4 | * Copyright (c) 2008-2014 Intel Corporation. |
8bf02617 AD |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
8bf02617 AD |
14 | */ |
15 | ||
16 | /* Supports: | |
17 | * Moorestown platform Langwell chip. | |
8081c84c | 18 | * Medfield platform Penwell chip. |
f89a768f DC |
19 | * Clovertrail platform Cloverview chip. |
20 | * Merrifield platform Tangier chip. | |
8bf02617 AD |
21 | */ |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/pci.h> | |
72b4379e | 25 | #include <linux/platform_device.h> |
8bf02617 AD |
26 | #include <linux/kernel.h> |
27 | #include <linux/delay.h> | |
28 | #include <linux/stddef.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/init.h> | |
8bf02617 | 31 | #include <linux/io.h> |
3f7dbfd8 | 32 | #include <linux/gpio/driver.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7812803a | 34 | #include <linux/pm_runtime.h> |
8bf02617 | 35 | |
f89a768f DC |
36 | #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0) |
37 | #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1) | |
d56d6b3d | 38 | |
8081c84c AD |
39 | /* |
40 | * Langwell chip has 64 pins and thus there are 2 32bit registers to control | |
41 | * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit | |
42 | * registers to control them, so we only define the order here instead of a | |
43 | * structure, to get a bit offset for a pin (use GPDR as an example): | |
44 | * | |
45 | * nreg = ngpio / 32; | |
46 | * reg = offset / 32; | |
47 | * bit = offset % 32; | |
48 | * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4; | |
49 | * | |
50 | * so the bit of reg_addr is to control pin offset's GPDR feature | |
51 | */ | |
52 | ||
53 | enum GPIO_REG { | |
54 | GPLR = 0, /* pin level read-only */ | |
55 | GPDR, /* pin direction */ | |
56 | GPSR, /* pin set */ | |
57 | GPCR, /* pin clear */ | |
58 | GRER, /* rising edge detect */ | |
59 | GFER, /* falling edge detect */ | |
60 | GEDR, /* edge detect result */ | |
8c0f7b10 | 61 | GAFR, /* alt function */ |
8bf02617 AD |
62 | }; |
63 | ||
f89a768f DC |
64 | /* intel_mid gpio driver data */ |
65 | struct intel_mid_gpio_ddata { | |
d56d6b3d DC |
66 | u16 ngpio; /* number of gpio pins */ |
67 | u32 gplr_offset; /* offset of first GPLR register from base */ | |
68 | u32 flis_base; /* base address of FLIS registers */ | |
69 | u32 flis_len; /* length of FLIS registers */ | |
70 | u32 (*get_flis_offset)(int gpio); | |
71 | u32 chip_irq_type; /* chip interrupt type */ | |
72 | }; | |
73 | ||
f89a768f | 74 | struct intel_mid_gpio { |
8bf02617 | 75 | struct gpio_chip chip; |
64c8cbc1 | 76 | void __iomem *reg_base; |
8bf02617 | 77 | spinlock_t lock; |
7812803a | 78 | struct pci_dev *pdev; |
8bf02617 AD |
79 | }; |
80 | ||
3f7dbfd8 LW |
81 | static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc) |
82 | { | |
83 | return container_of(gc, struct intel_mid_gpio, chip); | |
84 | } | |
46ebfbc3 | 85 | |
8081c84c | 86 | static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, |
611a485b | 87 | enum GPIO_REG reg_type) |
8bf02617 | 88 | { |
f89a768f | 89 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8081c84c | 90 | unsigned nreg = chip->ngpio / 32; |
8bf02617 | 91 | u8 reg = offset / 32; |
8081c84c | 92 | |
f89a768f | 93 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
8081c84c AD |
94 | } |
95 | ||
8c0f7b10 AH |
96 | static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, |
97 | enum GPIO_REG reg_type) | |
98 | { | |
f89a768f | 99 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8c0f7b10 AH |
100 | unsigned nreg = chip->ngpio / 32; |
101 | u8 reg = offset / 16; | |
8c0f7b10 | 102 | |
f89a768f | 103 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
8c0f7b10 AH |
104 | } |
105 | ||
f89a768f | 106 | static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) |
8c0f7b10 AH |
107 | { |
108 | void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR); | |
109 | u32 value = readl(gafr); | |
110 | int shift = (offset % 16) << 1, af = (value >> shift) & 3; | |
111 | ||
112 | if (af) { | |
113 | value &= ~(3 << shift); | |
114 | writel(value, gafr); | |
115 | } | |
116 | return 0; | |
117 | } | |
118 | ||
f89a768f | 119 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
8081c84c AD |
120 | { |
121 | void __iomem *gplr = gpio_reg(chip, offset, GPLR); | |
8bf02617 | 122 | |
8bf02617 AD |
123 | return readl(gplr) & BIT(offset % 32); |
124 | } | |
125 | ||
f89a768f | 126 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
8bf02617 | 127 | { |
8bf02617 AD |
128 | void __iomem *gpsr, *gpcr; |
129 | ||
130 | if (value) { | |
8081c84c | 131 | gpsr = gpio_reg(chip, offset, GPSR); |
8bf02617 AD |
132 | writel(BIT(offset % 32), gpsr); |
133 | } else { | |
8081c84c | 134 | gpcr = gpio_reg(chip, offset, GPCR); |
8bf02617 AD |
135 | writel(BIT(offset % 32), gpcr); |
136 | } | |
137 | } | |
138 | ||
f89a768f | 139 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
8bf02617 | 140 | { |
f89a768f | 141 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8081c84c | 142 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
8bf02617 AD |
143 | u32 value; |
144 | unsigned long flags; | |
8bf02617 | 145 | |
f89a768f DC |
146 | if (priv->pdev) |
147 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 148 | |
f89a768f | 149 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 AD |
150 | value = readl(gpdr); |
151 | value &= ~BIT(offset % 32); | |
152 | writel(value, gpdr); | |
f89a768f | 153 | spin_unlock_irqrestore(&priv->lock, flags); |
7812803a | 154 | |
f89a768f DC |
155 | if (priv->pdev) |
156 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 157 | |
8bf02617 AD |
158 | return 0; |
159 | } | |
160 | ||
f89a768f | 161 | static int intel_gpio_direction_output(struct gpio_chip *chip, |
8bf02617 AD |
162 | unsigned offset, int value) |
163 | { | |
f89a768f | 164 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8081c84c | 165 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
8bf02617 | 166 | unsigned long flags; |
8bf02617 | 167 | |
f89a768f | 168 | intel_gpio_set(chip, offset, value); |
7812803a | 169 | |
f89a768f DC |
170 | if (priv->pdev) |
171 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 172 | |
f89a768f | 173 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 | 174 | value = readl(gpdr); |
6eab04a8 | 175 | value |= BIT(offset % 32); |
8bf02617 | 176 | writel(value, gpdr); |
f89a768f | 177 | spin_unlock_irqrestore(&priv->lock, flags); |
7812803a | 178 | |
f89a768f DC |
179 | if (priv->pdev) |
180 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 181 | |
8bf02617 AD |
182 | return 0; |
183 | } | |
184 | ||
f89a768f | 185 | static int intel_mid_irq_type(struct irq_data *d, unsigned type) |
8bf02617 | 186 | { |
3f7dbfd8 LW |
187 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
188 | struct intel_mid_gpio *priv = to_intel_gpio_priv(gc); | |
465f2bd4 | 189 | u32 gpio = irqd_to_hwirq(d); |
8bf02617 AD |
190 | unsigned long flags; |
191 | u32 value; | |
f89a768f DC |
192 | void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); |
193 | void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); | |
8bf02617 | 194 | |
f89a768f | 195 | if (gpio >= priv->chip.ngpio) |
8bf02617 | 196 | return -EINVAL; |
7812803a | 197 | |
f89a768f DC |
198 | if (priv->pdev) |
199 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 200 | |
f89a768f | 201 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 AD |
202 | if (type & IRQ_TYPE_EDGE_RISING) |
203 | value = readl(grer) | BIT(gpio % 32); | |
204 | else | |
205 | value = readl(grer) & (~BIT(gpio % 32)); | |
206 | writel(value, grer); | |
207 | ||
208 | if (type & IRQ_TYPE_EDGE_FALLING) | |
209 | value = readl(gfer) | BIT(gpio % 32); | |
210 | else | |
211 | value = readl(gfer) & (~BIT(gpio % 32)); | |
212 | writel(value, gfer); | |
f89a768f | 213 | spin_unlock_irqrestore(&priv->lock, flags); |
8bf02617 | 214 | |
f89a768f DC |
215 | if (priv->pdev) |
216 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 217 | |
8bf02617 | 218 | return 0; |
fd0574cb | 219 | } |
8bf02617 | 220 | |
f89a768f | 221 | static void intel_mid_irq_unmask(struct irq_data *d) |
8bf02617 | 222 | { |
fd0574cb | 223 | } |
8bf02617 | 224 | |
f89a768f | 225 | static void intel_mid_irq_mask(struct irq_data *d) |
8bf02617 | 226 | { |
fd0574cb | 227 | } |
8bf02617 | 228 | |
f89a768f DC |
229 | static struct irq_chip intel_mid_irqchip = { |
230 | .name = "INTEL_MID-GPIO", | |
231 | .irq_mask = intel_mid_irq_mask, | |
232 | .irq_unmask = intel_mid_irq_unmask, | |
233 | .irq_set_type = intel_mid_irq_type, | |
8bf02617 AD |
234 | }; |
235 | ||
f89a768f | 236 | static const struct intel_mid_gpio_ddata gpio_lincroft = { |
d56d6b3d DC |
237 | .ngpio = 64, |
238 | }; | |
239 | ||
f89a768f | 240 | static const struct intel_mid_gpio_ddata gpio_penwell_aon = { |
d56d6b3d | 241 | .ngpio = 96, |
f89a768f | 242 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
243 | }; |
244 | ||
f89a768f | 245 | static const struct intel_mid_gpio_ddata gpio_penwell_core = { |
d56d6b3d | 246 | .ngpio = 96, |
f89a768f | 247 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
248 | }; |
249 | ||
f89a768f | 250 | static const struct intel_mid_gpio_ddata gpio_cloverview_aon = { |
d56d6b3d | 251 | .ngpio = 96, |
f89a768f | 252 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL, |
d56d6b3d DC |
253 | }; |
254 | ||
f89a768f | 255 | static const struct intel_mid_gpio_ddata gpio_cloverview_core = { |
d56d6b3d | 256 | .ngpio = 96, |
f89a768f | 257 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
258 | }; |
259 | ||
f89a768f | 260 | static const struct intel_mid_gpio_ddata gpio_tangier = { |
d56d6b3d DC |
261 | .ngpio = 192, |
262 | .gplr_offset = 4, | |
263 | .flis_base = 0xff0c0000, | |
264 | .flis_len = 0x8000, | |
265 | .get_flis_offset = NULL, | |
f89a768f | 266 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
267 | }; |
268 | ||
14f4a883 | 269 | static const struct pci_device_id intel_gpio_ids[] = { |
d56d6b3d DC |
270 | { |
271 | /* Lincroft */ | |
272 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), | |
273 | .driver_data = (kernel_ulong_t)&gpio_lincroft, | |
274 | }, | |
275 | { | |
276 | /* Penwell AON */ | |
277 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), | |
278 | .driver_data = (kernel_ulong_t)&gpio_penwell_aon, | |
279 | }, | |
280 | { | |
281 | /* Penwell Core */ | |
282 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), | |
283 | .driver_data = (kernel_ulong_t)&gpio_penwell_core, | |
284 | }, | |
285 | { | |
286 | /* Cloverview Aon */ | |
287 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), | |
288 | .driver_data = (kernel_ulong_t)&gpio_cloverview_aon, | |
289 | }, | |
290 | { | |
291 | /* Cloverview Core */ | |
292 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), | |
293 | .driver_data = (kernel_ulong_t)&gpio_cloverview_core, | |
294 | }, | |
295 | { | |
296 | /* Tangier */ | |
297 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199), | |
298 | .driver_data = (kernel_ulong_t)&gpio_tangier, | |
299 | }, | |
300 | { 0 } | |
8bf02617 | 301 | }; |
f89a768f | 302 | MODULE_DEVICE_TABLE(pci, intel_gpio_ids); |
8bf02617 | 303 | |
bd0b9ac4 | 304 | static void intel_mid_irq_handler(struct irq_desc *desc) |
8bf02617 | 305 | { |
3f7dbfd8 LW |
306 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
307 | struct intel_mid_gpio *priv = to_intel_gpio_priv(gc); | |
20e2aa91 | 308 | struct irq_data *data = irq_desc_get_irq_data(desc); |
20e2aa91 | 309 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
84bead6c | 310 | u32 base, gpio, mask; |
732063b9 | 311 | unsigned long pending; |
8bf02617 | 312 | void __iomem *gedr; |
8bf02617 AD |
313 | |
314 | /* check GPIO controller to check which pin triggered the interrupt */ | |
f89a768f DC |
315 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
316 | gedr = gpio_reg(&priv->chip, base, GEDR); | |
c8f925b6 | 317 | while ((pending = readl(gedr))) { |
2345b20f | 318 | gpio = __ffs(pending); |
84bead6c | 319 | mask = BIT(gpio); |
84bead6c TG |
320 | /* Clear before handling so we can't lose an edge */ |
321 | writel(mask, gedr); | |
3f7dbfd8 | 322 | generic_handle_irq(irq_find_mapping(gc->irqdomain, |
465f2bd4 | 323 | base + gpio)); |
732063b9 | 324 | } |
8bf02617 | 325 | } |
0766d20f | 326 | |
20e2aa91 | 327 | chip->irq_eoi(data); |
8bf02617 AD |
328 | } |
329 | ||
f89a768f | 330 | static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) |
f5f93117 MW |
331 | { |
332 | void __iomem *reg; | |
333 | unsigned base; | |
334 | ||
f89a768f | 335 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
f5f93117 | 336 | /* Clear the rising-edge detect register */ |
f89a768f | 337 | reg = gpio_reg(&priv->chip, base, GRER); |
f5f93117 MW |
338 | writel(0, reg); |
339 | /* Clear the falling-edge detect register */ | |
f89a768f | 340 | reg = gpio_reg(&priv->chip, base, GFER); |
f5f93117 MW |
341 | writel(0, reg); |
342 | /* Clear the edge detect status register */ | |
f89a768f | 343 | reg = gpio_reg(&priv->chip, base, GEDR); |
f5f93117 MW |
344 | writel(~0, reg); |
345 | } | |
346 | } | |
347 | ||
f89a768f | 348 | static int intel_gpio_runtime_idle(struct device *dev) |
7812803a | 349 | { |
84a34575 | 350 | int err = pm_schedule_suspend(dev, 500); |
351 | return err ?: -EBUSY; | |
7812803a KCA |
352 | } |
353 | ||
f89a768f DC |
354 | static const struct dev_pm_ops intel_gpio_pm_ops = { |
355 | SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle) | |
7812803a KCA |
356 | }; |
357 | ||
f89a768f | 358 | static int intel_gpio_probe(struct pci_dev *pdev, |
64c8cbc1 | 359 | const struct pci_device_id *id) |
8bf02617 | 360 | { |
64c8cbc1 | 361 | void __iomem *base; |
f89a768f | 362 | struct intel_mid_gpio *priv; |
8bf02617 | 363 | u32 gpio_base; |
2519f9ab | 364 | u32 irq_base; |
d6a2b7ba | 365 | int retval; |
f89a768f DC |
366 | struct intel_mid_gpio_ddata *ddata = |
367 | (struct intel_mid_gpio_ddata *)id->driver_data; | |
8bf02617 | 368 | |
786e07ec | 369 | retval = pcim_enable_device(pdev); |
8bf02617 | 370 | if (retval) |
8302c741 | 371 | return retval; |
8bf02617 | 372 | |
786e07ec | 373 | retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev)); |
8bf02617 | 374 | if (retval) { |
786e07ec AS |
375 | dev_err(&pdev->dev, "I/O memory mapping error\n"); |
376 | return retval; | |
8bf02617 | 377 | } |
64c8cbc1 | 378 | |
786e07ec AS |
379 | base = pcim_iomap_table(pdev)[1]; |
380 | ||
64c8cbc1 AS |
381 | irq_base = readl(base); |
382 | gpio_base = readl(sizeof(u32) + base); | |
383 | ||
8bf02617 | 384 | /* release the IO mapping, since we already get the info from bar1 */ |
786e07ec | 385 | pcim_iounmap_regions(pdev, 1 << 1); |
8bf02617 | 386 | |
f89a768f DC |
387 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
388 | if (!priv) { | |
8aca119f | 389 | dev_err(&pdev->dev, "can't allocate chip data\n"); |
786e07ec | 390 | return -ENOMEM; |
8bf02617 | 391 | } |
b3e35af2 | 392 | |
f89a768f DC |
393 | priv->reg_base = pcim_iomap_table(pdev)[0]; |
394 | priv->chip.label = dev_name(&pdev->dev); | |
aa6baa7e | 395 | priv->chip.dev = &pdev->dev; |
f89a768f DC |
396 | priv->chip.request = intel_gpio_request; |
397 | priv->chip.direction_input = intel_gpio_direction_input; | |
398 | priv->chip.direction_output = intel_gpio_direction_output; | |
399 | priv->chip.get = intel_gpio_get; | |
400 | priv->chip.set = intel_gpio_set; | |
f89a768f DC |
401 | priv->chip.base = gpio_base; |
402 | priv->chip.ngpio = ddata->ngpio; | |
9fb1f39e | 403 | priv->chip.can_sleep = false; |
f89a768f DC |
404 | priv->pdev = pdev; |
405 | ||
406 | spin_lock_init(&priv->lock); | |
407 | ||
f89a768f DC |
408 | pci_set_drvdata(pdev, priv); |
409 | retval = gpiochip_add(&priv->chip); | |
8bf02617 | 410 | if (retval) { |
8aca119f | 411 | dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
786e07ec | 412 | return retval; |
8bf02617 | 413 | } |
f5f93117 | 414 | |
3f7dbfd8 LW |
415 | retval = gpiochip_irqchip_add(&priv->chip, |
416 | &intel_mid_irqchip, | |
417 | irq_base, | |
418 | handle_simple_irq, | |
419 | IRQ_TYPE_NONE); | |
420 | if (retval) { | |
421 | dev_err(&pdev->dev, | |
422 | "could not connect irqchip to gpiochip\n"); | |
423 | return retval; | |
424 | } | |
425 | ||
f89a768f | 426 | intel_mid_irq_init_hw(priv); |
f5f93117 | 427 | |
3f7dbfd8 LW |
428 | gpiochip_set_chained_irqchip(&priv->chip, |
429 | &intel_mid_irqchip, | |
430 | pdev->irq, | |
431 | intel_mid_irq_handler); | |
8bf02617 | 432 | |
7812803a KCA |
433 | pm_runtime_put_noidle(&pdev->dev); |
434 | pm_runtime_allow(&pdev->dev); | |
435 | ||
8302c741 | 436 | return 0; |
8bf02617 AD |
437 | } |
438 | ||
f89a768f DC |
439 | static struct pci_driver intel_gpio_driver = { |
440 | .name = "intel_mid_gpio", | |
441 | .id_table = intel_gpio_ids, | |
442 | .probe = intel_gpio_probe, | |
7812803a | 443 | .driver = { |
f89a768f | 444 | .pm = &intel_gpio_pm_ops, |
7812803a | 445 | }, |
8bf02617 AD |
446 | }; |
447 | ||
f89a768f | 448 | static int __init intel_gpio_init(void) |
8bf02617 | 449 | { |
f89a768f | 450 | return pci_register_driver(&intel_gpio_driver); |
8bf02617 AD |
451 | } |
452 | ||
f89a768f | 453 | device_initcall(intel_gpio_init); |