[deliverable/linux.git] / drivers / gpio / gpio-intel-mid.c

/*
 * Moorestown platform Langwell chip GPIO driver
 *
 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/irqdomain.h>

#define LNW_IRQ_TYPE_EDGE	(1 << 0)
#define LNW_IRQ_TYPE_LEVEL	(1 << 1)

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

/* langwell gpio driver data */
struct lnw_gpio_ddata {
	u16 ngpio;		/* number of gpio pins */
	u32 gplr_offset;	/* offset of first GPLR register from base */
	u32 flis_base;		/* base address of FLIS registers */
	u32 flis_len;		/* length of FLIS registers */
	u32 (*get_flis_offset)(int gpio);
	u32 chip_irq_type;	/* chip interrupt type */
};

struct lnw_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
	struct irq_domain		*domain;
};

#define to_lnw_priv(chip)	container_of(chip, struct lnw_gpio, chip)

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	lnw_gpio_set(chip, offset, value);

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	return irq_create_mapping(lnw->domain, offset);
}

static int lnw_irq_type(struct irq_data *d, unsigned type)
{
	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);

	if (gpio >= lnw->chip.ngpio)
		return -EINVAL;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static void lnw_irq_unmask(struct irq_data *d)
{
}

static void lnw_irq_mask(struct irq_data *d)
{
}

static struct irq_chip lnw_irqchip = {
	.name		= "LNW-GPIO",
	.irq_mask	= lnw_irq_mask,
	.irq_unmask	= lnw_irq_unmask,
	.irq_set_type	= lnw_irq_type,
};

static const struct lnw_gpio_ddata gpio_lincroft = {
	.ngpio = 64,
};

static const struct lnw_gpio_ddata gpio_penwell_aon = {
	.ngpio = 96,
	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
};

static const struct lnw_gpio_ddata gpio_penwell_core = {
	.ngpio = 96,
	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
};

static const struct lnw_gpio_ddata gpio_cloverview_aon = {
	.ngpio = 96,
	.chip_irq_type = LNW_IRQ_TYPE_EDGE | LNW_IRQ_TYPE_LEVEL,
};

static const struct lnw_gpio_ddata gpio_cloverview_core = {
	.ngpio = 96,
	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
};

static const struct lnw_gpio_ddata gpio_tangier = {
	.ngpio = 192,
	.gplr_offset = 4,
	.flis_base = 0xff0c0000,
	.flis_len = 0x8000,
	.get_flis_offset = NULL,
	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
};

static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {
	{
		/* Lincroft */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
		.driver_data = (kernel_ulong_t)&gpio_lincroft,
	},
	{
		/* Penwell AON */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
		.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	},
	{
		/* Penwell Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
		.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	},
	{
		/* Cloverview Aon */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	},
	{
		/* Cloverview Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	},
	{
		/* Tangier */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
		.driver_data = (kernel_ulong_t)&gpio_tangier,
	},
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);

static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		gedr = gpio_reg(&lnw->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(lnw->domain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void lnw_irq_init_hw(struct lnw_gpio *lnw)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&lnw->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&lnw->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&lnw->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
			    irq_hw_number_t hw)
{
	struct lnw_gpio *lnw = d->host_data;

	irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
				      "demux");
	irq_set_chip_data(virq, lnw);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops lnw_gpio_irq_ops = {
	.map = lnw_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int lnw_gpio_runtime_idle(struct device *dev)
{
	pm_schedule_suspend(dev, 500);
	return -EBUSY;
}

static const struct dev_pm_ops lnw_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
};

static int lnw_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct lnw_gpio *lnw;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	struct lnw_gpio_ddata *ddata = (struct lnw_gpio_ddata *)id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
	if (!lnw) {
		dev_err(&pdev->dev, "can't allocate chip data\n");
		return -ENOMEM;
	}

	lnw->reg_base = pcim_iomap_table(pdev)[0];
	lnw->chip.label = dev_name(&pdev->dev);
	lnw->chip.request = lnw_gpio_request;
	lnw->chip.direction_input = lnw_gpio_direction_input;
	lnw->chip.direction_output = lnw_gpio_direction_output;
	lnw->chip.get = lnw_gpio_get;
	lnw->chip.set = lnw_gpio_set;
	lnw->chip.to_irq = lnw_gpio_to_irq;
	lnw->chip.base = gpio_base;
	lnw->chip.ngpio = ddata->ngpio;
	lnw->chip.can_sleep = 0;
	lnw->pdev = pdev;

	spin_lock_init(&lnw->lock);

	lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
					    irq_base, &lnw_gpio_irq_ops, lnw);
	if (!lnw->domain)
		return -ENOMEM;

	pci_set_drvdata(pdev, lnw);
	retval = gpiochip_add(&lnw->chip);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	lnw_irq_init_hw(lnw);

	irq_set_handler_data(pdev->irq, lnw);
	irq_set_chained_handler(pdev->irq, lnw_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver lnw_gpio_driver = {
	.name		= "langwell_gpio",
	.id_table	= lnw_gpio_ids,
	.probe		= lnw_gpio_probe,
	.driver		= {
		.pm	= &lnw_gpio_pm_ops,
	},
};

static int __init lnw_gpio_init(void)
{
	return pci_register_driver(&lnw_gpio_driver);
}

device_initcall(lnw_gpio_init);
Commit	Line	Data
c103de24 GL	1	/*
	2	* Moorestown platform Langwell chip GPIO driver
	3	*
611a485b	4	* Copyright (c) 2008, 2009, 2013, Intel Corporation.
8bf02617 AD	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/* Supports:
	21	* Moorestown platform Langwell chip.
8081c84c	22	* Medfield platform Penwell chip.
8bf02617 AD	23	*/
	24
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
72b4379e	27	#include <linux/platform_device.h>
8bf02617 AD	28	#include <linux/kernel.h>
	29	#include <linux/delay.h>
	30	#include <linux/stddef.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/init.h>
	33	#include <linux/irq.h>
	34	#include <linux/io.h>
	35	#include <linux/gpio.h>
5a0e3ad6	36	#include <linux/slab.h>
7812803a	37	#include <linux/pm_runtime.h>
465f2bd4	38	#include <linux/irqdomain.h>
8bf02617	39
d56d6b3d DC	40	#define LNW_IRQ_TYPE_EDGE (1 << 0)
	41	#define LNW_IRQ_TYPE_LEVEL (1 << 1)
	42
8081c84c AD	43	/*
	44	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	45	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	46	* registers to control them, so we only define the order here instead of a
	47	* structure, to get a bit offset for a pin (use GPDR as an example):
	48	*
	49	* nreg = ngpio / 32;
	50	* reg = offset / 32;
	51	* bit = offset % 32;
	52	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	53	*
	54	* so the bit of reg_addr is to control pin offset's GPDR feature
	55	*/
	56
	57	enum GPIO_REG {
	58	GPLR = 0, /* pin level read-only */
	59	GPDR, /* pin direction */
	60	GPSR, /* pin set */
	61	GPCR, /* pin clear */
	62	GRER, /* rising edge detect */
	63	GFER, /* falling edge detect */
	64	GEDR, /* edge detect result */
8c0f7b10	65	GAFR, /* alt function */
8bf02617 AD	66	};
8bf02617 AD	67
d56d6b3d DC	68	/* langwell gpio driver data */
	69	struct lnw_gpio_ddata {
	70	u16 ngpio; /* number of gpio pins */
	71	u32 gplr_offset; /* offset of first GPLR register from base */
	72	u32 flis_base; /* base address of FLIS registers */
	73	u32 flis_len; /* length of FLIS registers */
	74	u32 (*get_flis_offset)(int gpio);
	75	u32 chip_irq_type; /* chip interrupt type */
	76	};
	77
8bf02617 AD	78	struct lnw_gpio {
8bf02617 AD	79	struct gpio_chip chip;
64c8cbc1	80	void __iomem *reg_base;
8bf02617	81	spinlock_t lock;
7812803a	82	struct pci_dev *pdev;
465f2bd4	83	struct irq_domain *domain;
8bf02617 AD	84	};
8bf02617 AD	85
46ebfbc3 DC	86	#define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
46ebfbc3 DC	87
8081c84c	88	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	89	enum GPIO_REG reg_type)
8bf02617	90	{
46ebfbc3	91	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	92	unsigned nreg = chip->ngpio / 32;
8bf02617	93	u8 reg = offset / 32;
8081c84c	94
611a485b	95	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	96	}
8081c84c AD	97
8c0f7b10 AH	98	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	99	enum GPIO_REG reg_type)
	100	{
46ebfbc3	101	struct lnw_gpio *lnw = to_lnw_priv(chip);
8c0f7b10 AH	102	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	103	u8 reg = offset / 16;
8c0f7b10	104
611a485b	105	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	106	}
	107
	108	static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
	109	{
	110	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	111	u32 value = readl(gafr);
	112	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	113
	114	if (af) {
	115	value &= ~(3 << shift);
	116	writel(value, gafr);
	117	}
	118	return 0;
	119	}
	120
8081c84c AD	121	static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
	122	{
	123	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	124
8bf02617 AD	125	return readl(gplr) & BIT(offset % 32);
	126	}
	127
	128	static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	129	{
8bf02617 AD	130	void __iomem gpsr, gpcr;
	131
	132	if (value) {
8081c84c	133	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	134	writel(BIT(offset % 32), gpsr);
8bf02617 AD	135	} else {
8081c84c	136	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	137	writel(BIT(offset % 32), gpcr);
	138	}
	139	}
	140
	141	static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	142	{
46ebfbc3	143	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	144	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	145	u32 value;
8bf02617 AD	146	unsigned long flags;
8bf02617	147
7812803a KCA	148	if (lnw->pdev)
	149	pm_runtime_get(&lnw->pdev->dev);
	150
8bf02617 AD	151	spin_lock_irqsave(&lnw->lock, flags);
	152	value = readl(gpdr);
	153	value &= ~BIT(offset % 32);
	154	writel(value, gpdr);
	155	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	156
	157	if (lnw->pdev)
	158	pm_runtime_put(&lnw->pdev->dev);
	159
8bf02617 AD	160	return 0;
	161	}
	162
	163	static int lnw_gpio_direction_output(struct gpio_chip *chip,
	164	unsigned offset, int value)
	165	{
46ebfbc3	166	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	167	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	168	unsigned long flags;
8bf02617 AD	169
8bf02617 AD	170	lnw_gpio_set(chip, offset, value);
7812803a KCA	171
	172	if (lnw->pdev)
	173	pm_runtime_get(&lnw->pdev->dev);
	174
8bf02617 AD	175	spin_lock_irqsave(&lnw->lock, flags);
8bf02617 AD	176	value = readl(gpdr);
6eab04a8	177	value \|= BIT(offset % 32);
8bf02617 AD	178	writel(value, gpdr);
8bf02617 AD	179	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	180
	181	if (lnw->pdev)
	182	pm_runtime_put(&lnw->pdev->dev);
	183
8bf02617 AD	184	return 0;
	185	}
	186
	187	static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	188	{
46ebfbc3	189	struct lnw_gpio *lnw = to_lnw_priv(chip);
465f2bd4	190	return irq_create_mapping(lnw->domain, offset);
8bf02617 AD	191	}
8bf02617 AD	192
5ffd72c6	193	static int lnw_irq_type(struct irq_data *d, unsigned type)
8bf02617	194	{
5ffd72c6	195	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
465f2bd4	196	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	197	unsigned long flags;
8bf02617 AD	198	u32 value;
8081c84c AD	199	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
8081c84c AD	200	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
8bf02617	201
4efec627	202	if (gpio >= lnw->chip.ngpio)
8bf02617	203	return -EINVAL;
7812803a KCA	204
	205	if (lnw->pdev)
	206	pm_runtime_get(&lnw->pdev->dev);
	207
8bf02617 AD	208	spin_lock_irqsave(&lnw->lock, flags);
	209	if (type & IRQ_TYPE_EDGE_RISING)
	210	value = readl(grer) \| BIT(gpio % 32);
	211	else
	212	value = readl(grer) & (~BIT(gpio % 32));
	213	writel(value, grer);
	214
	215	if (type & IRQ_TYPE_EDGE_FALLING)
	216	value = readl(gfer) \| BIT(gpio % 32);
	217	else
	218	value = readl(gfer) & (~BIT(gpio % 32));
	219	writel(value, gfer);
	220	spin_unlock_irqrestore(&lnw->lock, flags);
	221
7812803a KCA	222	if (lnw->pdev)
	223	pm_runtime_put(&lnw->pdev->dev);
	224
8bf02617	225	return 0;
fd0574cb	226	}
8bf02617	227
5ffd72c6	228	static void lnw_irq_unmask(struct irq_data *d)
8bf02617	229	{
fd0574cb	230	}
8bf02617	231
5ffd72c6	232	static void lnw_irq_mask(struct irq_data *d)
8bf02617	233	{
fd0574cb	234	}
8bf02617 AD	235
	236	static struct irq_chip lnw_irqchip = {
	237	.name = "LNW-GPIO",
5ffd72c6 LB	238	.irq_mask = lnw_irq_mask,
	239	.irq_unmask = lnw_irq_unmask,
	240	.irq_set_type = lnw_irq_type,
8bf02617 AD	241	};
8bf02617 AD	242
d56d6b3d DC	243	static const struct lnw_gpio_ddata gpio_lincroft = {
	244	.ngpio = 64,
	245	};
	246
	247	static const struct lnw_gpio_ddata gpio_penwell_aon = {
	248	.ngpio = 96,
	249	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
	250	};
	251
	252	static const struct lnw_gpio_ddata gpio_penwell_core = {
	253	.ngpio = 96,
	254	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
	255	};
	256
	257	static const struct lnw_gpio_ddata gpio_cloverview_aon = {
	258	.ngpio = 96,
	259	.chip_irq_type = LNW_IRQ_TYPE_EDGE \| LNW_IRQ_TYPE_LEVEL,
	260	};
	261
	262	static const struct lnw_gpio_ddata gpio_cloverview_core = {
	263	.ngpio = 96,
	264	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
	265	};
	266
	267	static const struct lnw_gpio_ddata gpio_tangier = {
	268	.ngpio = 192,
	269	.gplr_offset = 4,
	270	.flis_base = 0xff0c0000,
	271	.flis_len = 0x8000,
	272	.get_flis_offset = NULL,
	273	.chip_irq_type = LNW_IRQ_TYPE_EDGE,
	274	};
	275
	276	static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {
	277	{
	278	/* Lincroft */
	279	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
	280	.driver_data = (kernel_ulong_t)&gpio_lincroft,
	281	},
	282	{
	283	/* Penwell AON */
	284	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
	285	.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	286	},
	287	{
	288	/* Penwell Core */
	289	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
	290	.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	291	},
	292	{
	293	/* Cloverview Aon */
	294	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
	295	.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	296	},
	297	{
	298	/* Cloverview Core */
	299	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
	300	.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	301	},
	302	{
	303	/* Tangier */
	304	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
	305	.driver_data = (kernel_ulong_t)&gpio_tangier,
	306	},
307	{ 0 }
8bf02617 AD	308	};
	309	MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
	310
	311	static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
	312	{
20e2aa91 TG	313	struct irq_data *data = irq_desc_get_irq_data(desc);
	314	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	315	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	316	u32 base, gpio, mask;
732063b9	317	unsigned long pending;
8bf02617	318	void __iomem *gedr;
8bf02617 AD	319
8bf02617 AD	320	/* check GPIO controller to check which pin triggered the interrupt */
8081c84c AD	321	for (base = 0; base < lnw->chip.ngpio; base += 32) {
8081c84c AD	322	gedr = gpio_reg(&lnw->chip, base, GEDR);
c8f925b6	323	while ((pending = readl(gedr))) {
2345b20f	324	gpio = __ffs(pending);
84bead6c	325	mask = BIT(gpio);
84bead6c TG	326	/* Clear before handling so we can't lose an edge */
84bead6c TG	327	writel(mask, gedr);
465f2bd4 MW	328	generic_handle_irq(irq_find_mapping(lnw->domain,
465f2bd4 MW	329	base + gpio));
732063b9	330	}
8bf02617	331	}
0766d20f	332
20e2aa91	333	chip->irq_eoi(data);
8bf02617 AD	334	}
8bf02617 AD	335
f5f93117 MW	336	static void lnw_irq_init_hw(struct lnw_gpio *lnw)
	337	{
	338	void __iomem *reg;
	339	unsigned base;
	340
	341	for (base = 0; base < lnw->chip.ngpio; base += 32) {
	342	/* Clear the rising-edge detect register */
	343	reg = gpio_reg(&lnw->chip, base, GRER);
	344	writel(0, reg);
	345	/* Clear the falling-edge detect register */
	346	reg = gpio_reg(&lnw->chip, base, GFER);
	347	writel(0, reg);
	348	/* Clear the edge detect status register */
	349	reg = gpio_reg(&lnw->chip, base, GEDR);
	350	writel(~0, reg);
	351	}
	352	}
	353
465f2bd4 MW	354	static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
	355	irq_hw_number_t hw)
	356	{
	357	struct lnw_gpio *lnw = d->host_data;
	358
	359	irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
	360	"demux");
	361	irq_set_chip_data(virq, lnw);
	362	irq_set_irq_type(virq, IRQ_TYPE_NONE);
	363
	364	return 0;
	365	}
	366
	367	static const struct irq_domain_ops lnw_gpio_irq_ops = {
	368	.map = lnw_gpio_irq_map,
	369	.xlate = irq_domain_xlate_twocell,
	370	};
	371
7812803a KCA	372	static int lnw_gpio_runtime_idle(struct device *dev)
7812803a KCA	373	{
45f0a85c	374	pm_schedule_suspend(dev, 500);
7812803a KCA	375	return -EBUSY;
	376	}
	377
7812803a	378	static const struct dev_pm_ops lnw_gpio_pm_ops = {
46ebfbc3	379	SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
7812803a KCA	380	};
7812803a KCA	381
3836309d	382	static int lnw_gpio_probe(struct pci_dev *pdev,
64c8cbc1	383	const struct pci_device_id *id)
8bf02617	384	{
64c8cbc1	385	void __iomem *base;
8bf02617	386	struct lnw_gpio *lnw;
8bf02617	387	u32 gpio_base;
2519f9ab	388	u32 irq_base;
d6a2b7ba	389	int retval;
d56d6b3d	390	struct lnw_gpio_ddata ddata = (struct lnw_gpio_ddata )id->driver_data;
8bf02617	391
786e07ec	392	retval = pcim_enable_device(pdev);
8bf02617	393	if (retval)
8302c741	394	return retval;
8bf02617	395
786e07ec	396	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	397	if (retval) {
786e07ec AS	398	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	399	return retval;
8bf02617	400	}
64c8cbc1	401
786e07ec AS	402	base = pcim_iomap_table(pdev)[1];
786e07ec AS	403
64c8cbc1 AS	404	irq_base = readl(base);
	405	gpio_base = readl(sizeof(u32) + base);
	406
8bf02617	407	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	408	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	409
46ebfbc3	410	lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
8bf02617	411	if (!lnw) {
8aca119f	412	dev_err(&pdev->dev, "can't allocate chip data\n");
786e07ec	413	return -ENOMEM;
8bf02617	414	}
b3e35af2	415
786e07ec	416	lnw->reg_base = pcim_iomap_table(pdev)[0];
8bf02617	417	lnw->chip.label = dev_name(&pdev->dev);
8c0f7b10	418	lnw->chip.request = lnw_gpio_request;
8bf02617 AD	419	lnw->chip.direction_input = lnw_gpio_direction_input;
	420	lnw->chip.direction_output = lnw_gpio_direction_output;
	421	lnw->chip.get = lnw_gpio_get;
	422	lnw->chip.set = lnw_gpio_set;
	423	lnw->chip.to_irq = lnw_gpio_to_irq;
	424	lnw->chip.base = gpio_base;
d56d6b3d	425	lnw->chip.ngpio = ddata->ngpio;
8bf02617	426	lnw->chip.can_sleep = 0;
7812803a	427	lnw->pdev = pdev;
2519f9ab	428
aeb168f7 AS	429	spin_lock_init(&lnw->lock);
aeb168f7 AS	430
d56d6b3d DC	431	lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
d56d6b3d DC	432	irq_base, &lnw_gpio_irq_ops, lnw);
786e07ec AS	433	if (!lnw->domain)
786e07ec AS	434	return -ENOMEM;
2519f9ab	435
8bf02617 AD	436	pci_set_drvdata(pdev, lnw);
	437	retval = gpiochip_add(&lnw->chip);
	438	if (retval) {
8aca119f	439	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	440	return retval;
8bf02617	441	}
f5f93117 MW	442
	443	lnw_irq_init_hw(lnw);
	444
674db906 TG	445	irq_set_handler_data(pdev->irq, lnw);
674db906 TG	446	irq_set_chained_handler(pdev->irq, lnw_irq_handler);
8bf02617	447
7812803a KCA	448	pm_runtime_put_noidle(&pdev->dev);
	449	pm_runtime_allow(&pdev->dev);
	450
8302c741	451	return 0;
8bf02617 AD	452	}
	453
	454	static struct pci_driver lnw_gpio_driver = {
	455	.name = "langwell_gpio",
	456	.id_table = lnw_gpio_ids,
	457	.probe = lnw_gpio_probe,
7812803a KCA	458	.driver = {
	459	.pm = &lnw_gpio_pm_ops,
	460	},
8bf02617 AD	461	};
	462
	463	static int __init lnw_gpio_init(void)
	464	{
10b20a93	465	return pci_register_driver(&lnw_gpio_driver);
8bf02617 AD	466	}
	467
	468	device_initcall(lnw_gpio_init);