Commit | Line | Data |
---|---|---|
e58b9e27 | 1 | /* |
4e47f91b LP |
2 | * MCP23S08 SPI/I2C GPIO gpio expander driver |
3 | * | |
4 | * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are | |
5 | * supported. | |
6 | * For the I2C versions of the chips (mcp23008 and mcp23017) generation of | |
7 | * interrupts is also supported. | |
8 | * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is | |
9 | * also capable of generating interrupts, but the linux driver does not | |
10 | * support that yet. | |
e58b9e27 DB |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/device.h> | |
e58b9e27 | 15 | #include <linux/mutex.h> |
bb207ef1 | 16 | #include <linux/module.h> |
d120c17f | 17 | #include <linux/gpio.h> |
752ad5e8 | 18 | #include <linux/i2c.h> |
e58b9e27 DB |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0b7bb77f | 22 | #include <asm/byteorder.h> |
4e47f91b LP |
23 | #include <linux/interrupt.h> |
24 | #include <linux/of_irq.h> | |
97ddb1c8 | 25 | #include <linux/of_device.h> |
e58b9e27 | 26 | |
0b7bb77f PK |
27 | /** |
28 | * MCP types supported by driver | |
29 | */ | |
30 | #define MCP_TYPE_S08 0 | |
31 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
32 | #define MCP_TYPE_008 2 |
33 | #define MCP_TYPE_017 3 | |
e58b9e27 DB |
34 | |
35 | /* Registers are all 8 bits wide. | |
36 | * | |
37 | * The mcp23s17 has twice as many bits, and can be configured to work | |
38 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
39 | */ |
40 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
41 | #define MCP_IPOL 0x01 | |
42 | #define MCP_GPINTEN 0x02 | |
43 | #define MCP_DEFVAL 0x03 | |
44 | #define MCP_INTCON 0x04 | |
45 | #define MCP_IOCON 0x05 | |
4e47f91b | 46 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
47 | # define IOCON_SEQOP (1 << 5) |
48 | # define IOCON_HAEN (1 << 3) | |
49 | # define IOCON_ODR (1 << 2) | |
50 | # define IOCON_INTPOL (1 << 1) | |
51 | #define MCP_GPPU 0x06 | |
52 | #define MCP_INTF 0x07 | |
53 | #define MCP_INTCAP 0x08 | |
54 | #define MCP_GPIO 0x09 | |
55 | #define MCP_OLAT 0x0a | |
56 | ||
0b7bb77f PK |
57 | struct mcp23s08; |
58 | ||
59 | struct mcp23s08_ops { | |
60 | int (*read)(struct mcp23s08 *mcp, unsigned reg); | |
61 | int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val); | |
62 | int (*read_regs)(struct mcp23s08 *mcp, unsigned reg, | |
63 | u16 *vals, unsigned n); | |
64 | }; | |
65 | ||
e58b9e27 | 66 | struct mcp23s08 { |
e58b9e27 | 67 | u8 addr; |
a4e63554 | 68 | bool irq_active_high; |
e58b9e27 | 69 | |
0b7bb77f | 70 | u16 cache[11]; |
4e47f91b LP |
71 | u16 irq_rise; |
72 | u16 irq_fall; | |
73 | int irq; | |
74 | bool irq_controller; | |
e58b9e27 DB |
75 | /* lock protects the cached values */ |
76 | struct mutex lock; | |
4e47f91b LP |
77 | struct mutex irq_lock; |
78 | struct irq_domain *irq_domain; | |
e58b9e27 DB |
79 | |
80 | struct gpio_chip chip; | |
81 | ||
0b7bb77f | 82 | const struct mcp23s08_ops *ops; |
d62b98f3 | 83 | void *data; /* ops specific data */ |
e58b9e27 DB |
84 | }; |
85 | ||
0b7bb77f | 86 | /* A given spi_device can represent up to eight mcp23sxx chips |
8f1cc3b1 DB |
87 | * sharing the same chipselect but using different addresses |
88 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
89 | * Driver data holds all the per-chip data. | |
90 | */ | |
91 | struct mcp23s08_driver_data { | |
92 | unsigned ngpio; | |
0b7bb77f | 93 | struct mcp23s08 *mcp[8]; |
8f1cc3b1 DB |
94 | struct mcp23s08 chip[]; |
95 | }; | |
96 | ||
4e47f91b LP |
97 | /* This lock class tells lockdep that GPIO irqs are in a different |
98 | * category than their parents, so it won't report false recursion. | |
99 | */ | |
100 | static struct lock_class_key gpio_lock_class; | |
101 | ||
752ad5e8 PK |
102 | /*----------------------------------------------------------------------*/ |
103 | ||
cbf24fad | 104 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 PK |
105 | |
106 | static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg) | |
107 | { | |
108 | return i2c_smbus_read_byte_data(mcp->data, reg); | |
109 | } | |
110 | ||
111 | static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
112 | { | |
113 | return i2c_smbus_write_byte_data(mcp->data, reg, val); | |
114 | } | |
115 | ||
116 | static int | |
117 | mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
118 | { | |
119 | while (n--) { | |
120 | int ret = mcp23008_read(mcp, reg++); | |
121 | if (ret < 0) | |
122 | return ret; | |
123 | *vals++ = ret; | |
124 | } | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
129 | static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg) | |
130 | { | |
131 | return i2c_smbus_read_word_data(mcp->data, reg << 1); | |
132 | } | |
133 | ||
134 | static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
135 | { | |
136 | return i2c_smbus_write_word_data(mcp->data, reg << 1, val); | |
137 | } | |
138 | ||
139 | static int | |
140 | mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
141 | { | |
142 | while (n--) { | |
143 | int ret = mcp23017_read(mcp, reg++); | |
144 | if (ret < 0) | |
145 | return ret; | |
146 | *vals++ = ret; | |
147 | } | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | static const struct mcp23s08_ops mcp23008_ops = { | |
153 | .read = mcp23008_read, | |
154 | .write = mcp23008_write, | |
155 | .read_regs = mcp23008_read_regs, | |
156 | }; | |
157 | ||
158 | static const struct mcp23s08_ops mcp23017_ops = { | |
159 | .read = mcp23017_read, | |
160 | .write = mcp23017_write, | |
161 | .read_regs = mcp23017_read_regs, | |
162 | }; | |
163 | ||
164 | #endif /* CONFIG_I2C */ | |
165 | ||
166 | /*----------------------------------------------------------------------*/ | |
167 | ||
d62b98f3 PK |
168 | #ifdef CONFIG_SPI_MASTER |
169 | ||
e58b9e27 DB |
170 | static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg) |
171 | { | |
172 | u8 tx[2], rx[1]; | |
173 | int status; | |
174 | ||
175 | tx[0] = mcp->addr | 0x01; | |
176 | tx[1] = reg; | |
33bc8411 | 177 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx)); |
e58b9e27 DB |
178 | return (status < 0) ? status : rx[0]; |
179 | } | |
180 | ||
0b7bb77f | 181 | static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) |
e58b9e27 DB |
182 | { |
183 | u8 tx[3]; | |
184 | ||
185 | tx[0] = mcp->addr; | |
186 | tx[1] = reg; | |
187 | tx[2] = val; | |
33bc8411 | 188 | return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0); |
e58b9e27 DB |
189 | } |
190 | ||
191 | static int | |
0b7bb77f | 192 | mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) |
e58b9e27 | 193 | { |
0b7bb77f PK |
194 | u8 tx[2], *tmp; |
195 | int status; | |
e58b9e27 | 196 | |
33bc8411 | 197 | if ((n + reg) > sizeof(mcp->cache)) |
e58b9e27 DB |
198 | return -EINVAL; |
199 | tx[0] = mcp->addr | 0x01; | |
200 | tx[1] = reg; | |
0b7bb77f PK |
201 | |
202 | tmp = (u8 *)vals; | |
33bc8411 | 203 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n); |
0b7bb77f PK |
204 | if (status >= 0) { |
205 | while (n--) | |
206 | vals[n] = tmp[n]; /* expand to 16bit */ | |
207 | } | |
208 | return status; | |
209 | } | |
210 | ||
211 | static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg) | |
212 | { | |
213 | u8 tx[2], rx[2]; | |
214 | int status; | |
215 | ||
216 | tx[0] = mcp->addr | 0x01; | |
217 | tx[1] = reg << 1; | |
33bc8411 | 218 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx)); |
0b7bb77f PK |
219 | return (status < 0) ? status : (rx[0] | (rx[1] << 8)); |
220 | } | |
221 | ||
222 | static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
223 | { | |
224 | u8 tx[4]; | |
225 | ||
226 | tx[0] = mcp->addr; | |
227 | tx[1] = reg << 1; | |
228 | tx[2] = val; | |
229 | tx[3] = val >> 8; | |
33bc8411 | 230 | return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0); |
0b7bb77f PK |
231 | } |
232 | ||
233 | static int | |
234 | mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
235 | { | |
236 | u8 tx[2]; | |
237 | int status; | |
238 | ||
33bc8411 | 239 | if ((n + reg) > sizeof(mcp->cache)) |
0b7bb77f PK |
240 | return -EINVAL; |
241 | tx[0] = mcp->addr | 0x01; | |
242 | tx[1] = reg << 1; | |
243 | ||
33bc8411 | 244 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), |
0b7bb77f PK |
245 | (u8 *)vals, n * 2); |
246 | if (status >= 0) { | |
247 | while (n--) | |
248 | vals[n] = __le16_to_cpu((__le16)vals[n]); | |
249 | } | |
250 | ||
251 | return status; | |
e58b9e27 DB |
252 | } |
253 | ||
0b7bb77f PK |
254 | static const struct mcp23s08_ops mcp23s08_ops = { |
255 | .read = mcp23s08_read, | |
256 | .write = mcp23s08_write, | |
257 | .read_regs = mcp23s08_read_regs, | |
258 | }; | |
259 | ||
260 | static const struct mcp23s08_ops mcp23s17_ops = { | |
261 | .read = mcp23s17_read, | |
262 | .write = mcp23s17_write, | |
263 | .read_regs = mcp23s17_read_regs, | |
264 | }; | |
265 | ||
d62b98f3 | 266 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 267 | |
e58b9e27 DB |
268 | /*----------------------------------------------------------------------*/ |
269 | ||
270 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
271 | { | |
272 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
273 | int status; | |
274 | ||
275 | mutex_lock(&mcp->lock); | |
276 | mcp->cache[MCP_IODIR] |= (1 << offset); | |
0b7bb77f | 277 | status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
278 | mutex_unlock(&mcp->lock); |
279 | return status; | |
280 | } | |
281 | ||
282 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
283 | { | |
284 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
285 | int status; | |
286 | ||
287 | mutex_lock(&mcp->lock); | |
288 | ||
289 | /* REVISIT reading this clears any IRQ ... */ | |
0b7bb77f | 290 | status = mcp->ops->read(mcp, MCP_GPIO); |
e58b9e27 DB |
291 | if (status < 0) |
292 | status = 0; | |
293 | else { | |
294 | mcp->cache[MCP_GPIO] = status; | |
295 | status = !!(status & (1 << offset)); | |
296 | } | |
297 | mutex_unlock(&mcp->lock); | |
298 | return status; | |
299 | } | |
300 | ||
301 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value) | |
302 | { | |
0b7bb77f | 303 | unsigned olat = mcp->cache[MCP_OLAT]; |
e58b9e27 DB |
304 | |
305 | if (value) | |
306 | olat |= mask; | |
307 | else | |
308 | olat &= ~mask; | |
309 | mcp->cache[MCP_OLAT] = olat; | |
0b7bb77f | 310 | return mcp->ops->write(mcp, MCP_OLAT, olat); |
e58b9e27 DB |
311 | } |
312 | ||
313 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
314 | { | |
315 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
0b7bb77f | 316 | unsigned mask = 1 << offset; |
e58b9e27 DB |
317 | |
318 | mutex_lock(&mcp->lock); | |
319 | __mcp23s08_set(mcp, mask, value); | |
320 | mutex_unlock(&mcp->lock); | |
321 | } | |
322 | ||
323 | static int | |
324 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
325 | { | |
326 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
0b7bb77f | 327 | unsigned mask = 1 << offset; |
e58b9e27 DB |
328 | int status; |
329 | ||
330 | mutex_lock(&mcp->lock); | |
331 | status = __mcp23s08_set(mcp, mask, value); | |
332 | if (status == 0) { | |
333 | mcp->cache[MCP_IODIR] &= ~mask; | |
0b7bb77f | 334 | status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
335 | } |
336 | mutex_unlock(&mcp->lock); | |
337 | return status; | |
338 | } | |
339 | ||
4e47f91b LP |
340 | /*----------------------------------------------------------------------*/ |
341 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
342 | { | |
343 | struct mcp23s08 *mcp = data; | |
344 | int intcap, intf, i; | |
345 | unsigned int child_irq; | |
346 | ||
347 | mutex_lock(&mcp->lock); | |
348 | intf = mcp->ops->read(mcp, MCP_INTF); | |
349 | if (intf < 0) { | |
350 | mutex_unlock(&mcp->lock); | |
351 | return IRQ_HANDLED; | |
352 | } | |
353 | ||
354 | mcp->cache[MCP_INTF] = intf; | |
355 | ||
356 | intcap = mcp->ops->read(mcp, MCP_INTCAP); | |
357 | if (intcap < 0) { | |
358 | mutex_unlock(&mcp->lock); | |
359 | return IRQ_HANDLED; | |
360 | } | |
361 | ||
362 | mcp->cache[MCP_INTCAP] = intcap; | |
363 | mutex_unlock(&mcp->lock); | |
364 | ||
365 | ||
366 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
367 | if ((BIT(i) & mcp->cache[MCP_INTF]) && | |
368 | ((BIT(i) & intcap & mcp->irq_rise) || | |
369 | (mcp->irq_fall & ~intcap & BIT(i)))) { | |
370 | child_irq = irq_find_mapping(mcp->irq_domain, i); | |
371 | handle_nested_irq(child_irq); | |
372 | } | |
373 | } | |
374 | ||
375 | return IRQ_HANDLED; | |
376 | } | |
377 | ||
378 | static int mcp23s08_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
379 | { | |
380 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
381 | ||
382 | return irq_find_mapping(mcp->irq_domain, offset); | |
383 | } | |
384 | ||
385 | static void mcp23s08_irq_mask(struct irq_data *data) | |
386 | { | |
387 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
388 | unsigned int pos = data->hwirq; | |
389 | ||
390 | mcp->cache[MCP_GPINTEN] &= ~BIT(pos); | |
391 | } | |
392 | ||
393 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
394 | { | |
395 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
396 | unsigned int pos = data->hwirq; | |
397 | ||
398 | mcp->cache[MCP_GPINTEN] |= BIT(pos); | |
399 | } | |
400 | ||
401 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
402 | { | |
403 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
404 | unsigned int pos = data->hwirq; | |
405 | int status = 0; | |
406 | ||
407 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
408 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
409 | mcp->irq_rise |= BIT(pos); | |
410 | mcp->irq_fall |= BIT(pos); | |
411 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
412 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
413 | mcp->irq_rise |= BIT(pos); | |
414 | mcp->irq_fall &= ~BIT(pos); | |
415 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
416 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
417 | mcp->irq_rise &= ~BIT(pos); | |
418 | mcp->irq_fall |= BIT(pos); | |
419 | } else | |
420 | return -EINVAL; | |
421 | ||
422 | return status; | |
423 | } | |
424 | ||
425 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
426 | { | |
427 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
428 | ||
429 | mutex_lock(&mcp->irq_lock); | |
430 | } | |
431 | ||
432 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
433 | { | |
434 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
435 | ||
436 | mutex_lock(&mcp->lock); | |
437 | mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]); | |
438 | mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]); | |
439 | mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]); | |
440 | mutex_unlock(&mcp->lock); | |
441 | mutex_unlock(&mcp->irq_lock); | |
442 | } | |
443 | ||
57ef0428 | 444 | static int mcp23s08_irq_reqres(struct irq_data *data) |
4e47f91b LP |
445 | { |
446 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
447 | ||
e3a2e878 | 448 | if (gpiochip_lock_as_irq(&mcp->chip, data->hwirq)) { |
4e47f91b LP |
449 | dev_err(mcp->chip.dev, |
450 | "unable to lock HW IRQ %lu for IRQ usage\n", | |
451 | data->hwirq); | |
57ef0428 LW |
452 | return -EINVAL; |
453 | } | |
4e47f91b | 454 | |
4e47f91b LP |
455 | return 0; |
456 | } | |
457 | ||
57ef0428 | 458 | static void mcp23s08_irq_relres(struct irq_data *data) |
4e47f91b LP |
459 | { |
460 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
461 | ||
e3a2e878 | 462 | gpiochip_unlock_as_irq(&mcp->chip, data->hwirq); |
4e47f91b LP |
463 | } |
464 | ||
465 | static struct irq_chip mcp23s08_irq_chip = { | |
466 | .name = "gpio-mcp23xxx", | |
467 | .irq_mask = mcp23s08_irq_mask, | |
468 | .irq_unmask = mcp23s08_irq_unmask, | |
469 | .irq_set_type = mcp23s08_irq_set_type, | |
470 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
471 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
57ef0428 LW |
472 | .irq_request_resources = mcp23s08_irq_reqres, |
473 | .irq_release_resources = mcp23s08_irq_relres, | |
4e47f91b LP |
474 | }; |
475 | ||
476 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
477 | { | |
478 | struct gpio_chip *chip = &mcp->chip; | |
479 | int err, irq, j; | |
a4e63554 | 480 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b LP |
481 | |
482 | mutex_init(&mcp->irq_lock); | |
483 | ||
3af0dbd5 | 484 | mcp->irq_domain = irq_domain_add_linear(chip->dev->of_node, chip->ngpio, |
4e47f91b LP |
485 | &irq_domain_simple_ops, mcp); |
486 | if (!mcp->irq_domain) | |
487 | return -ENODEV; | |
488 | ||
a4e63554 AS |
489 | if (mcp->irq_active_high) |
490 | irqflags |= IRQF_TRIGGER_HIGH; | |
491 | else | |
492 | irqflags |= IRQF_TRIGGER_LOW; | |
493 | ||
4e47f91b | 494 | err = devm_request_threaded_irq(chip->dev, mcp->irq, NULL, mcp23s08_irq, |
a4e63554 | 495 | irqflags, dev_name(chip->dev), mcp); |
4e47f91b LP |
496 | if (err != 0) { |
497 | dev_err(chip->dev, "unable to request IRQ#%d: %d\n", | |
498 | mcp->irq, err); | |
499 | return err; | |
500 | } | |
501 | ||
502 | chip->to_irq = mcp23s08_gpio_to_irq; | |
503 | ||
504 | for (j = 0; j < mcp->chip.ngpio; j++) { | |
505 | irq = irq_create_mapping(mcp->irq_domain, j); | |
506 | irq_set_lockdep_class(irq, &gpio_lock_class); | |
507 | irq_set_chip_data(irq, mcp); | |
508 | irq_set_chip(irq, &mcp23s08_irq_chip); | |
509 | irq_set_nested_thread(irq, true); | |
4e47f91b | 510 | irq_set_noprobe(irq); |
4e47f91b LP |
511 | } |
512 | return 0; | |
513 | } | |
514 | ||
515 | static void mcp23s08_irq_teardown(struct mcp23s08 *mcp) | |
516 | { | |
517 | unsigned int irq, i; | |
518 | ||
4e47f91b LP |
519 | for (i = 0; i < mcp->chip.ngpio; i++) { |
520 | irq = irq_find_mapping(mcp->irq_domain, i); | |
521 | if (irq > 0) | |
522 | irq_dispose_mapping(irq); | |
523 | } | |
524 | ||
525 | irq_domain_remove(mcp->irq_domain); | |
526 | } | |
527 | ||
e58b9e27 DB |
528 | /*----------------------------------------------------------------------*/ |
529 | ||
530 | #ifdef CONFIG_DEBUG_FS | |
531 | ||
532 | #include <linux/seq_file.h> | |
533 | ||
534 | /* | |
535 | * This shows more info than the generic gpio dump code: | |
536 | * pullups, deglitching, open drain drive. | |
537 | */ | |
538 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
539 | { | |
540 | struct mcp23s08 *mcp; | |
541 | char bank; | |
1d1c1d9b | 542 | int t; |
e58b9e27 DB |
543 | unsigned mask; |
544 | ||
545 | mcp = container_of(chip, struct mcp23s08, chip); | |
546 | ||
547 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 548 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
549 | |
550 | mutex_lock(&mcp->lock); | |
0b7bb77f | 551 | t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache)); |
e58b9e27 DB |
552 | if (t < 0) { |
553 | seq_printf(s, " I/O ERROR %d\n", t); | |
554 | goto done; | |
555 | } | |
556 | ||
0b7bb77f | 557 | for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) { |
e58b9e27 DB |
558 | const char *label; |
559 | ||
560 | label = gpiochip_is_requested(chip, t); | |
561 | if (!label) | |
562 | continue; | |
563 | ||
564 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
565 | chip->base + t, bank, t, label, | |
566 | (mcp->cache[MCP_IODIR] & mask) ? "in " : "out", | |
567 | (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", | |
eb1567f7 | 568 | (mcp->cache[MCP_GPPU] & mask) ? "up" : " "); |
e58b9e27 | 569 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 570 | seq_puts(s, "\n"); |
e58b9e27 DB |
571 | } |
572 | done: | |
573 | mutex_unlock(&mcp->lock); | |
574 | } | |
575 | ||
576 | #else | |
577 | #define mcp23s08_dbg_show NULL | |
578 | #endif | |
579 | ||
580 | /*----------------------------------------------------------------------*/ | |
581 | ||
d62b98f3 | 582 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 583 | void *data, unsigned addr, unsigned type, |
3af0dbd5 | 584 | struct mcp23s08_platform_data *pdata, int cs) |
e58b9e27 | 585 | { |
d62b98f3 | 586 | int status; |
4e47f91b | 587 | bool mirror = false; |
e58b9e27 | 588 | |
e58b9e27 DB |
589 | mutex_init(&mcp->lock); |
590 | ||
d62b98f3 PK |
591 | mcp->data = data; |
592 | mcp->addr = addr; | |
a4e63554 | 593 | mcp->irq_active_high = false; |
e58b9e27 | 594 | |
e58b9e27 DB |
595 | mcp->chip.direction_input = mcp23s08_direction_input; |
596 | mcp->chip.get = mcp23s08_get; | |
597 | mcp->chip.direction_output = mcp23s08_direction_output; | |
598 | mcp->chip.set = mcp23s08_set; | |
599 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
97ddb1c8 LP |
600 | #ifdef CONFIG_OF |
601 | mcp->chip.of_gpio_n_cells = 2; | |
602 | mcp->chip.of_node = dev->of_node; | |
603 | #endif | |
e58b9e27 | 604 | |
d62b98f3 PK |
605 | switch (type) { |
606 | #ifdef CONFIG_SPI_MASTER | |
607 | case MCP_TYPE_S08: | |
0b7bb77f PK |
608 | mcp->ops = &mcp23s08_ops; |
609 | mcp->chip.ngpio = 8; | |
610 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
611 | break; |
612 | ||
613 | case MCP_TYPE_S17: | |
614 | mcp->ops = &mcp23s17_ops; | |
615 | mcp->chip.ngpio = 16; | |
616 | mcp->chip.label = "mcp23s17"; | |
617 | break; | |
618 | #endif /* CONFIG_SPI_MASTER */ | |
619 | ||
cbf24fad | 620 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 PK |
621 | case MCP_TYPE_008: |
622 | mcp->ops = &mcp23008_ops; | |
623 | mcp->chip.ngpio = 8; | |
624 | mcp->chip.label = "mcp23008"; | |
625 | break; | |
626 | ||
627 | case MCP_TYPE_017: | |
628 | mcp->ops = &mcp23017_ops; | |
629 | mcp->chip.ngpio = 16; | |
630 | mcp->chip.label = "mcp23017"; | |
631 | break; | |
632 | #endif /* CONFIG_I2C */ | |
633 | ||
d62b98f3 PK |
634 | default: |
635 | dev_err(dev, "invalid device type (%d)\n", type); | |
636 | return -EINVAL; | |
0b7bb77f | 637 | } |
d62b98f3 | 638 | |
3af0dbd5 | 639 | mcp->chip.base = pdata->base; |
9fb1f39e | 640 | mcp->chip.can_sleep = true; |
d62b98f3 | 641 | mcp->chip.dev = dev; |
d72cbed0 | 642 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 643 | |
8f1cc3b1 DB |
644 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
645 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
646 | */ | |
4e47f91b | 647 | |
0b7bb77f | 648 | status = mcp->ops->read(mcp, MCP_IOCON); |
e58b9e27 DB |
649 | if (status < 0) |
650 | goto fail; | |
4e47f91b | 651 | |
3af0dbd5 | 652 | mcp->irq_controller = pdata->irq_controller; |
a4e63554 | 653 | if (mcp->irq && mcp->irq_controller) { |
170680ab LW |
654 | mcp->irq_active_high = |
655 | of_property_read_bool(mcp->chip.dev->of_node, | |
656 | "microchip,irq-active-high"); | |
4e47f91b | 657 | |
a4e63554 AS |
658 | if (type == MCP_TYPE_017) |
659 | mirror = pdata->mirror; | |
660 | } | |
661 | ||
662 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
663 | mcp->irq_active_high) { | |
0b7bb77f PK |
664 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
665 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
666 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
667 | if (mcp->irq_active_high) |
668 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
669 | else | |
670 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
671 | ||
4e47f91b LP |
672 | if (mirror) |
673 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
674 | ||
0b7bb77f | 675 | status = mcp->ops->write(mcp, MCP_IOCON, status); |
e58b9e27 DB |
676 | if (status < 0) |
677 | goto fail; | |
678 | } | |
679 | ||
680 | /* configure ~100K pullups */ | |
3af0dbd5 | 681 | status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups); |
e58b9e27 DB |
682 | if (status < 0) |
683 | goto fail; | |
684 | ||
0b7bb77f | 685 | status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache)); |
e58b9e27 DB |
686 | if (status < 0) |
687 | goto fail; | |
688 | ||
689 | /* disable inverter on input */ | |
690 | if (mcp->cache[MCP_IPOL] != 0) { | |
691 | mcp->cache[MCP_IPOL] = 0; | |
0b7bb77f PK |
692 | status = mcp->ops->write(mcp, MCP_IPOL, 0); |
693 | if (status < 0) | |
694 | goto fail; | |
e58b9e27 DB |
695 | } |
696 | ||
697 | /* disable irqs */ | |
698 | if (mcp->cache[MCP_GPINTEN] != 0) { | |
699 | mcp->cache[MCP_GPINTEN] = 0; | |
0b7bb77f | 700 | status = mcp->ops->write(mcp, MCP_GPINTEN, 0); |
8f1cc3b1 DB |
701 | if (status < 0) |
702 | goto fail; | |
e58b9e27 DB |
703 | } |
704 | ||
705 | status = gpiochip_add(&mcp->chip); | |
4e47f91b LP |
706 | if (status < 0) |
707 | goto fail; | |
708 | ||
709 | if (mcp->irq && mcp->irq_controller) { | |
710 | status = mcp23s08_irq_setup(mcp); | |
711 | if (status) { | |
712 | mcp23s08_irq_teardown(mcp); | |
713 | goto fail; | |
714 | } | |
715 | } | |
8f1cc3b1 DB |
716 | fail: |
717 | if (status < 0) | |
d62b98f3 PK |
718 | dev_dbg(dev, "can't setup chip %d, --> %d\n", |
719 | addr, status); | |
8f1cc3b1 DB |
720 | return status; |
721 | } | |
722 | ||
752ad5e8 PK |
723 | /*----------------------------------------------------------------------*/ |
724 | ||
97ddb1c8 LP |
725 | #ifdef CONFIG_OF |
726 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 727 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 728 | { |
45971686 LP |
729 | .compatible = "microchip,mcp23s08", |
730 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
731 | }, |
732 | { | |
45971686 LP |
733 | .compatible = "microchip,mcp23s17", |
734 | .data = (void *) MCP_TYPE_S17, | |
735 | }, | |
736 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
737 | { | |
738 | .compatible = "mcp,mcp23s08", | |
739 | .data = (void *) MCP_TYPE_S08, | |
740 | }, | |
741 | { | |
742 | .compatible = "mcp,mcp23s17", | |
743 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
744 | }, |
745 | { }, | |
746 | }; | |
747 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
748 | #endif | |
749 | ||
750 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 751 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 752 | { |
45971686 LP |
753 | .compatible = "microchip,mcp23008", |
754 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
755 | }, |
756 | { | |
45971686 LP |
757 | .compatible = "microchip,mcp23017", |
758 | .data = (void *) MCP_TYPE_017, | |
759 | }, | |
760 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
761 | { | |
762 | .compatible = "mcp,mcp23008", | |
763 | .data = (void *) MCP_TYPE_008, | |
764 | }, | |
765 | { | |
766 | .compatible = "mcp,mcp23017", | |
767 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
768 | }, |
769 | { }, | |
770 | }; | |
771 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
772 | #endif | |
773 | #endif /* CONFIG_OF */ | |
774 | ||
775 | ||
cbf24fad | 776 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 777 | |
3836309d | 778 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
779 | const struct i2c_device_id *id) |
780 | { | |
3af0dbd5 | 781 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 782 | struct mcp23s08 *mcp; |
3af0dbd5 | 783 | int status; |
97ddb1c8 LP |
784 | const struct of_device_id *match; |
785 | ||
786 | match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match), | |
787 | &client->dev); | |
3af0dbd5 SZ |
788 | if (match) { |
789 | pdata = &local_pdata; | |
790 | pdata->base = -1; | |
791 | pdata->chip[0].pullups = 0; | |
792 | pdata->irq_controller = of_property_read_bool( | |
793 | client->dev.of_node, | |
794 | "interrupt-controller"); | |
795 | pdata->mirror = of_property_read_bool(client->dev.of_node, | |
796 | "microchip,irq-mirror"); | |
4e47f91b | 797 | client->irq = irq_of_parse_and_map(client->dev.of_node, 0); |
97ddb1c8 | 798 | } else { |
3af0dbd5 | 799 | pdata = dev_get_platdata(&client->dev); |
b184c388 SZ |
800 | if (!pdata) { |
801 | pdata = devm_kzalloc(&client->dev, | |
802 | sizeof(struct mcp23s08_platform_data), | |
803 | GFP_KERNEL); | |
804 | pdata->base = -1; | |
97ddb1c8 | 805 | } |
752ad5e8 PK |
806 | } |
807 | ||
33bc8411 | 808 | mcp = kzalloc(sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
809 | if (!mcp) |
810 | return -ENOMEM; | |
811 | ||
4e47f91b | 812 | mcp->irq = client->irq; |
752ad5e8 | 813 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
3af0dbd5 | 814 | id->driver_data, pdata, 0); |
752ad5e8 PK |
815 | if (status) |
816 | goto fail; | |
817 | ||
818 | i2c_set_clientdata(client, mcp); | |
819 | ||
820 | return 0; | |
821 | ||
822 | fail: | |
823 | kfree(mcp); | |
824 | ||
825 | return status; | |
826 | } | |
827 | ||
206210ce | 828 | static int mcp230xx_remove(struct i2c_client *client) |
752ad5e8 PK |
829 | { |
830 | struct mcp23s08 *mcp = i2c_get_clientdata(client); | |
752ad5e8 | 831 | |
4e47f91b LP |
832 | if (client->irq && mcp->irq_controller) |
833 | mcp23s08_irq_teardown(mcp); | |
834 | ||
9f5132ae | 835 | gpiochip_remove(&mcp->chip); |
836 | kfree(mcp); | |
752ad5e8 | 837 | |
9f5132ae | 838 | return 0; |
752ad5e8 PK |
839 | } |
840 | ||
841 | static const struct i2c_device_id mcp230xx_id[] = { | |
842 | { "mcp23008", MCP_TYPE_008 }, | |
843 | { "mcp23017", MCP_TYPE_017 }, | |
844 | { }, | |
845 | }; | |
846 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
847 | ||
848 | static struct i2c_driver mcp230xx_driver = { | |
849 | .driver = { | |
850 | .name = "mcp230xx", | |
851 | .owner = THIS_MODULE, | |
97ddb1c8 | 852 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
853 | }, |
854 | .probe = mcp230xx_probe, | |
8283c4ff | 855 | .remove = mcp230xx_remove, |
752ad5e8 PK |
856 | .id_table = mcp230xx_id, |
857 | }; | |
858 | ||
859 | static int __init mcp23s08_i2c_init(void) | |
860 | { | |
861 | return i2c_add_driver(&mcp230xx_driver); | |
862 | } | |
863 | ||
864 | static void mcp23s08_i2c_exit(void) | |
865 | { | |
866 | i2c_del_driver(&mcp230xx_driver); | |
867 | } | |
868 | ||
869 | #else | |
870 | ||
871 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
872 | static void mcp23s08_i2c_exit(void) { } | |
873 | ||
874 | #endif /* CONFIG_I2C */ | |
875 | ||
876 | /*----------------------------------------------------------------------*/ | |
877 | ||
d62b98f3 PK |
878 | #ifdef CONFIG_SPI_MASTER |
879 | ||
8f1cc3b1 DB |
880 | static int mcp23s08_probe(struct spi_device *spi) |
881 | { | |
3af0dbd5 | 882 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 883 | unsigned addr; |
596a1c5f | 884 | int chips = 0; |
8f1cc3b1 | 885 | struct mcp23s08_driver_data *data; |
0b7bb77f | 886 | int status, type; |
3af0dbd5 | 887 | unsigned ngpio = 0; |
97ddb1c8 LP |
888 | const struct of_device_id *match; |
889 | u32 spi_present_mask = 0; | |
890 | ||
891 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
892 | if (match) { | |
de755c33 | 893 | type = (int)(uintptr_t)match->data; |
97ddb1c8 | 894 | status = of_property_read_u32(spi->dev.of_node, |
45971686 | 895 | "microchip,spi-present-mask", &spi_present_mask); |
97ddb1c8 | 896 | if (status) { |
45971686 LP |
897 | status = of_property_read_u32(spi->dev.of_node, |
898 | "mcp,spi-present-mask", &spi_present_mask); | |
899 | if (status) { | |
900 | dev_err(&spi->dev, | |
901 | "DT has no spi-present-mask\n"); | |
902 | return -ENODEV; | |
903 | } | |
97ddb1c8 LP |
904 | } |
905 | if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) { | |
906 | dev_err(&spi->dev, "invalid spi-present-mask\n"); | |
907 | return -ENODEV; | |
908 | } | |
8f1cc3b1 | 909 | |
3af0dbd5 SZ |
910 | pdata = &local_pdata; |
911 | pdata->base = -1; | |
99e4b98d | 912 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
3af0dbd5 | 913 | pdata->chip[addr].pullups = 0; |
3e3bed91 MS |
914 | if (spi_present_mask & (1 << addr)) |
915 | chips++; | |
99e4b98d | 916 | } |
3af0dbd5 SZ |
917 | pdata->irq_controller = of_property_read_bool( |
918 | spi->dev.of_node, | |
919 | "interrupt-controller"); | |
920 | pdata->mirror = of_property_read_bool(spi->dev.of_node, | |
921 | "microchip,irq-mirror"); | |
97ddb1c8 LP |
922 | } else { |
923 | type = spi_get_device_id(spi)->driver_data; | |
e56aee18 | 924 | pdata = dev_get_platdata(&spi->dev); |
b184c388 SZ |
925 | if (!pdata) { |
926 | pdata = devm_kzalloc(&spi->dev, | |
927 | sizeof(struct mcp23s08_platform_data), | |
928 | GFP_KERNEL); | |
929 | pdata->base = -1; | |
0b7bb77f | 930 | } |
97ddb1c8 LP |
931 | |
932 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { | |
933 | if (!pdata->chip[addr].is_present) | |
934 | continue; | |
935 | chips++; | |
936 | if ((type == MCP_TYPE_S08) && (addr > 3)) { | |
937 | dev_err(&spi->dev, | |
938 | "mcp23s08 only supports address 0..3\n"); | |
939 | return -EINVAL; | |
940 | } | |
941 | spi_present_mask |= 1 << addr; | |
97ddb1c8 | 942 | } |
8f1cc3b1 | 943 | } |
8f1cc3b1 | 944 | |
99e4b98d MW |
945 | if (!chips) |
946 | return -ENODEV; | |
947 | ||
7898b31e VB |
948 | data = devm_kzalloc(&spi->dev, |
949 | sizeof(*data) + chips * sizeof(struct mcp23s08), | |
950 | GFP_KERNEL); | |
8f1cc3b1 DB |
951 | if (!data) |
952 | return -ENOMEM; | |
7898b31e | 953 | |
8f1cc3b1 DB |
954 | spi_set_drvdata(spi, data); |
955 | ||
a231b88c AS |
956 | spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0); |
957 | ||
0b7bb77f | 958 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
97ddb1c8 | 959 | if (!(spi_present_mask & (1 << addr))) |
8f1cc3b1 DB |
960 | continue; |
961 | chips--; | |
962 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 963 | data->mcp[addr]->irq = spi->irq; |
d62b98f3 | 964 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
3af0dbd5 SZ |
965 | 0x40 | (addr << 1), type, pdata, |
966 | addr); | |
8f1cc3b1 DB |
967 | if (status < 0) |
968 | goto fail; | |
0b7bb77f | 969 | |
3af0dbd5 SZ |
970 | if (pdata->base != -1) |
971 | pdata->base += (type == MCP_TYPE_S17) ? 16 : 8; | |
97ddb1c8 | 972 | ngpio += (type == MCP_TYPE_S17) ? 16 : 8; |
8f1cc3b1 | 973 | } |
97ddb1c8 | 974 | data->ngpio = ngpio; |
e58b9e27 DB |
975 | |
976 | /* NOTE: these chips have a relatively sane IRQ framework, with | |
977 | * per-signal masking and level/edge triggering. It's not yet | |
978 | * handled here... | |
979 | */ | |
980 | ||
e58b9e27 DB |
981 | return 0; |
982 | ||
983 | fail: | |
0b7bb77f | 984 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
985 | |
986 | if (!data->mcp[addr]) | |
987 | continue; | |
9f5132ae | 988 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 989 | } |
e58b9e27 DB |
990 | return status; |
991 | } | |
992 | ||
993 | static int mcp23s08_remove(struct spi_device *spi) | |
994 | { | |
8f1cc3b1 | 995 | struct mcp23s08_driver_data *data = spi_get_drvdata(spi); |
8f1cc3b1 | 996 | unsigned addr; |
e58b9e27 | 997 | |
0b7bb77f | 998 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
999 | |
1000 | if (!data->mcp[addr]) | |
1001 | continue; | |
1002 | ||
a231b88c AS |
1003 | if (spi->irq && data->mcp[addr]->irq_controller) |
1004 | mcp23s08_irq_teardown(data->mcp[addr]); | |
9f5132ae | 1005 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 1006 | } |
c4941e07 | 1007 | |
9f5132ae | 1008 | return 0; |
e58b9e27 DB |
1009 | } |
1010 | ||
0b7bb77f PK |
1011 | static const struct spi_device_id mcp23s08_ids[] = { |
1012 | { "mcp23s08", MCP_TYPE_S08 }, | |
1013 | { "mcp23s17", MCP_TYPE_S17 }, | |
1014 | { }, | |
1015 | }; | |
1016 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
1017 | ||
e58b9e27 DB |
1018 | static struct spi_driver mcp23s08_driver = { |
1019 | .probe = mcp23s08_probe, | |
1020 | .remove = mcp23s08_remove, | |
0b7bb77f | 1021 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1022 | .driver = { |
1023 | .name = "mcp23s08", | |
1024 | .owner = THIS_MODULE, | |
97ddb1c8 | 1025 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
1026 | }, |
1027 | }; | |
1028 | ||
d62b98f3 PK |
1029 | static int __init mcp23s08_spi_init(void) |
1030 | { | |
1031 | return spi_register_driver(&mcp23s08_driver); | |
1032 | } | |
1033 | ||
1034 | static void mcp23s08_spi_exit(void) | |
1035 | { | |
1036 | spi_unregister_driver(&mcp23s08_driver); | |
1037 | } | |
1038 | ||
1039 | #else | |
1040 | ||
1041 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1042 | static void mcp23s08_spi_exit(void) { } | |
1043 | ||
1044 | #endif /* CONFIG_SPI_MASTER */ | |
1045 | ||
e58b9e27 DB |
1046 | /*----------------------------------------------------------------------*/ |
1047 | ||
1048 | static int __init mcp23s08_init(void) | |
1049 | { | |
752ad5e8 PK |
1050 | int ret; |
1051 | ||
1052 | ret = mcp23s08_spi_init(); | |
1053 | if (ret) | |
1054 | goto spi_fail; | |
1055 | ||
1056 | ret = mcp23s08_i2c_init(); | |
1057 | if (ret) | |
1058 | goto i2c_fail; | |
1059 | ||
1060 | return 0; | |
1061 | ||
1062 | i2c_fail: | |
1063 | mcp23s08_spi_exit(); | |
1064 | spi_fail: | |
1065 | return ret; | |
e58b9e27 | 1066 | } |
752ad5e8 | 1067 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1068 | * subsys initcalls that may rely on these GPIOs |
1069 | */ | |
1070 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1071 | |
1072 | static void __exit mcp23s08_exit(void) | |
1073 | { | |
d62b98f3 | 1074 | mcp23s08_spi_exit(); |
752ad5e8 | 1075 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1076 | } |
1077 | module_exit(mcp23s08_exit); | |
1078 | ||
1079 | MODULE_LICENSE("GPL"); |