Commit | Line | Data |
---|---|---|
1e16dfc1 | 1 | /* |
e39d5ef6 | 2 | * GPIOs on MPC512x/8349/8572/8610 and compatible |
1e16dfc1 PK |
3 | * |
4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_gpio.h> | |
17 | #include <linux/gpio.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
345e5c8a | 19 | #include <linux/irq.h> |
1e16dfc1 PK |
20 | |
21 | #define MPC8XXX_GPIO_PINS 32 | |
22 | ||
23 | #define GPIO_DIR 0x00 | |
24 | #define GPIO_ODR 0x04 | |
25 | #define GPIO_DAT 0x08 | |
26 | #define GPIO_IER 0x0c | |
27 | #define GPIO_IMR 0x10 | |
28 | #define GPIO_ICR 0x14 | |
e39d5ef6 | 29 | #define GPIO_ICR2 0x18 |
1e16dfc1 PK |
30 | |
31 | struct mpc8xxx_gpio_chip { | |
32 | struct of_mm_gpio_chip mm_gc; | |
33 | spinlock_t lock; | |
34 | ||
35 | /* | |
36 | * shadowed data register to be able to clear/set output pins in | |
37 | * open drain mode safely | |
38 | */ | |
39 | u32 data; | |
bae1d8f1 | 40 | struct irq_domain *irq; |
01a04ddc | 41 | const void *of_dev_id_data; |
1e16dfc1 PK |
42 | }; |
43 | ||
44 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) | |
45 | { | |
46 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); | |
47 | } | |
48 | ||
49 | static inline struct mpc8xxx_gpio_chip * | |
50 | to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) | |
51 | { | |
52 | return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); | |
53 | } | |
54 | ||
55 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) | |
56 | { | |
57 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
58 | ||
59 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); | |
60 | } | |
61 | ||
c1a676df FR |
62 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
63 | * defined as output cannot be determined by reading GPDAT register, | |
64 | * so we use shadow data register instead. The status of input pins | |
65 | * is determined by reading GPDAT register. | |
66 | */ | |
67 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) | |
68 | { | |
69 | u32 val; | |
70 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
71 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
72 | ||
73 | val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); | |
74 | ||
75 | return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); | |
76 | } | |
77 | ||
1e16dfc1 PK |
78 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
79 | { | |
80 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
81 | ||
82 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); | |
83 | } | |
84 | ||
85 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
86 | { | |
87 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
88 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
89 | unsigned long flags; | |
90 | ||
91 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
92 | ||
93 | if (val) | |
94 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); | |
95 | else | |
96 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); | |
97 | ||
98 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); | |
99 | ||
100 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
101 | } | |
102 | ||
103 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
104 | { | |
105 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
106 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
107 | unsigned long flags; | |
108 | ||
109 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
110 | ||
111 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
112 | ||
113 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
119 | { | |
120 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
121 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
122 | unsigned long flags; | |
123 | ||
124 | mpc8xxx_gpio_set(gc, gpio, val); | |
125 | ||
126 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
127 | ||
128 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
129 | ||
130 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
28538df0 WS |
135 | static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
136 | { | |
137 | /* GPIO 28..31 are input only on MPC5121 */ | |
138 | if (gpio >= 28) | |
139 | return -EINVAL; | |
140 | ||
141 | return mpc8xxx_gpio_dir_out(gc, gpio, val); | |
142 | } | |
143 | ||
345e5c8a PK |
144 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
145 | { | |
146 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
147 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
148 | ||
149 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) | |
150 | return irq_create_mapping(mpc8xxx_gc->irq, offset); | |
151 | else | |
152 | return -ENXIO; | |
153 | } | |
154 | ||
155 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | |
156 | { | |
ec775d0e | 157 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
cfadd838 | 158 | struct irq_chip *chip = irq_desc_get_chip(desc); |
345e5c8a PK |
159 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
160 | unsigned int mask; | |
161 | ||
162 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); | |
163 | if (mask) | |
164 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, | |
165 | 32 - ffs(mask))); | |
d6de85e8 TG |
166 | if (chip->irq_eoi) |
167 | chip->irq_eoi(&desc->irq_data); | |
345e5c8a PK |
168 | } |
169 | ||
94347cb3 | 170 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
345e5c8a | 171 | { |
94347cb3 | 172 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
173 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
174 | unsigned long flags; | |
175 | ||
176 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
177 | ||
476eb491 | 178 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
179 | |
180 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
181 | } | |
182 | ||
94347cb3 | 183 | static void mpc8xxx_irq_mask(struct irq_data *d) |
345e5c8a | 184 | { |
94347cb3 | 185 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
186 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
187 | unsigned long flags; | |
188 | ||
189 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
190 | ||
476eb491 | 191 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
192 | |
193 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
194 | } | |
195 | ||
94347cb3 | 196 | static void mpc8xxx_irq_ack(struct irq_data *d) |
345e5c8a | 197 | { |
94347cb3 | 198 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
199 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
200 | ||
476eb491 | 201 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
202 | } |
203 | ||
94347cb3 | 204 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
345e5c8a | 205 | { |
94347cb3 | 206 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
207 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
208 | unsigned long flags; | |
209 | ||
210 | switch (flow_type) { | |
211 | case IRQ_TYPE_EDGE_FALLING: | |
212 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
213 | setbits32(mm->regs + GPIO_ICR, | |
476eb491 | 214 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
215 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
216 | break; | |
217 | ||
218 | case IRQ_TYPE_EDGE_BOTH: | |
219 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
220 | clrbits32(mm->regs + GPIO_ICR, | |
476eb491 | 221 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
222 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
223 | break; | |
224 | ||
225 | default: | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
94347cb3 | 232 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
e39d5ef6 | 233 | { |
94347cb3 | 234 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
e39d5ef6 | 235 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
476eb491 | 236 | unsigned long gpio = irqd_to_hwirq(d); |
e39d5ef6 AG |
237 | void __iomem *reg; |
238 | unsigned int shift; | |
239 | unsigned long flags; | |
240 | ||
241 | if (gpio < 16) { | |
242 | reg = mm->regs + GPIO_ICR; | |
243 | shift = (15 - gpio) * 2; | |
244 | } else { | |
245 | reg = mm->regs + GPIO_ICR2; | |
246 | shift = (15 - (gpio % 16)) * 2; | |
247 | } | |
248 | ||
249 | switch (flow_type) { | |
250 | case IRQ_TYPE_EDGE_FALLING: | |
251 | case IRQ_TYPE_LEVEL_LOW: | |
252 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
253 | clrsetbits_be32(reg, 3 << shift, 2 << shift); | |
254 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
255 | break; | |
256 | ||
257 | case IRQ_TYPE_EDGE_RISING: | |
258 | case IRQ_TYPE_LEVEL_HIGH: | |
259 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
260 | clrsetbits_be32(reg, 3 << shift, 1 << shift); | |
261 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
262 | break; | |
263 | ||
264 | case IRQ_TYPE_EDGE_BOTH: | |
265 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
266 | clrbits32(reg, 3 << shift); | |
267 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
268 | break; | |
269 | ||
270 | default: | |
271 | return -EINVAL; | |
272 | } | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
345e5c8a PK |
277 | static struct irq_chip mpc8xxx_irq_chip = { |
278 | .name = "mpc8xxx-gpio", | |
94347cb3 LB |
279 | .irq_unmask = mpc8xxx_irq_unmask, |
280 | .irq_mask = mpc8xxx_irq_mask, | |
281 | .irq_ack = mpc8xxx_irq_ack, | |
282 | .irq_set_type = mpc8xxx_irq_set_type, | |
345e5c8a PK |
283 | }; |
284 | ||
bae1d8f1 | 285 | static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
345e5c8a PK |
286 | irq_hw_number_t hw) |
287 | { | |
e39d5ef6 AG |
288 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; |
289 | ||
290 | if (mpc8xxx_gc->of_dev_id_data) | |
94347cb3 | 291 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
e39d5ef6 | 292 | |
ec775d0e TG |
293 | irq_set_chip_data(virq, h->host_data); |
294 | irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); | |
345e5c8a PK |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
bae1d8f1 | 299 | static struct irq_domain_ops mpc8xxx_gpio_irq_ops = { |
345e5c8a | 300 | .map = mpc8xxx_gpio_irq_map, |
ff8c3ab8 | 301 | .xlate = irq_domain_xlate_twocell, |
345e5c8a PK |
302 | }; |
303 | ||
e39d5ef6 AG |
304 | static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { |
305 | { .compatible = "fsl,mpc8349-gpio", }, | |
306 | { .compatible = "fsl,mpc8572-gpio", }, | |
307 | { .compatible = "fsl,mpc8610-gpio", }, | |
308 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, | |
15a5148c | 309 | { .compatible = "fsl,pq3-gpio", }, |
d1dcfbbb | 310 | { .compatible = "fsl,qoriq-gpio", }, |
e39d5ef6 AG |
311 | {} |
312 | }; | |
313 | ||
1e16dfc1 PK |
314 | static void __init mpc8xxx_add_controller(struct device_node *np) |
315 | { | |
316 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; | |
317 | struct of_mm_gpio_chip *mm_gc; | |
1e16dfc1 | 318 | struct gpio_chip *gc; |
e39d5ef6 | 319 | const struct of_device_id *id; |
345e5c8a | 320 | unsigned hwirq; |
1e16dfc1 PK |
321 | int ret; |
322 | ||
323 | mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); | |
324 | if (!mpc8xxx_gc) { | |
325 | ret = -ENOMEM; | |
326 | goto err; | |
327 | } | |
328 | ||
329 | spin_lock_init(&mpc8xxx_gc->lock); | |
330 | ||
331 | mm_gc = &mpc8xxx_gc->mm_gc; | |
a19e3da5 | 332 | gc = &mm_gc->gc; |
1e16dfc1 PK |
333 | |
334 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; | |
1e16dfc1 PK |
335 | gc->ngpio = MPC8XXX_GPIO_PINS; |
336 | gc->direction_input = mpc8xxx_gpio_dir_in; | |
28538df0 WS |
337 | gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ? |
338 | mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out; | |
339 | gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ? | |
340 | mpc8572_gpio_get : mpc8xxx_gpio_get; | |
1e16dfc1 | 341 | gc->set = mpc8xxx_gpio_set; |
345e5c8a | 342 | gc->to_irq = mpc8xxx_gpio_to_irq; |
1e16dfc1 PK |
343 | |
344 | ret = of_mm_gpiochip_add(np, mm_gc); | |
345 | if (ret) | |
346 | goto err; | |
347 | ||
345e5c8a PK |
348 | hwirq = irq_of_parse_and_map(np, 0); |
349 | if (hwirq == NO_IRQ) | |
350 | goto skip_irq; | |
351 | ||
a8db8cf0 GL |
352 | mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, |
353 | &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); | |
345e5c8a PK |
354 | if (!mpc8xxx_gc->irq) |
355 | goto skip_irq; | |
356 | ||
e39d5ef6 AG |
357 | id = of_match_node(mpc8xxx_gpio_ids, np); |
358 | if (id) | |
359 | mpc8xxx_gc->of_dev_id_data = id->data; | |
360 | ||
345e5c8a PK |
361 | /* ack and mask all irqs */ |
362 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); | |
363 | out_be32(mm_gc->regs + GPIO_IMR, 0); | |
364 | ||
ec775d0e TG |
365 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
366 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); | |
345e5c8a PK |
367 | |
368 | skip_irq: | |
1e16dfc1 PK |
369 | return; |
370 | ||
371 | err: | |
372 | pr_err("%s: registration failed with status %d\n", | |
373 | np->full_name, ret); | |
374 | kfree(mpc8xxx_gc); | |
375 | ||
376 | return; | |
377 | } | |
378 | ||
379 | static int __init mpc8xxx_add_gpiochips(void) | |
380 | { | |
381 | struct device_node *np; | |
382 | ||
e39d5ef6 | 383 | for_each_matching_node(np, mpc8xxx_gpio_ids) |
1e16dfc1 PK |
384 | mpc8xxx_add_controller(np); |
385 | ||
386 | return 0; | |
387 | } | |
388 | arch_initcall(mpc8xxx_add_gpiochips); |