Commit | Line | Data |
---|---|---|
1e16dfc1 | 1 | /* |
e39d5ef6 | 2 | * GPIOs on MPC512x/8349/8572/8610 and compatible |
1e16dfc1 PK |
3 | * |
4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_gpio.h> | |
5af50730 | 17 | #include <linux/of_irq.h> |
98686d9a | 18 | #include <linux/of_platform.h> |
1e16dfc1 | 19 | #include <linux/gpio.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
345e5c8a | 21 | #include <linux/irq.h> |
1e16dfc1 PK |
22 | |
23 | #define MPC8XXX_GPIO_PINS 32 | |
24 | ||
25 | #define GPIO_DIR 0x00 | |
26 | #define GPIO_ODR 0x04 | |
27 | #define GPIO_DAT 0x08 | |
28 | #define GPIO_IER 0x0c | |
29 | #define GPIO_IMR 0x10 | |
30 | #define GPIO_ICR 0x14 | |
e39d5ef6 | 31 | #define GPIO_ICR2 0x18 |
1e16dfc1 PK |
32 | |
33 | struct mpc8xxx_gpio_chip { | |
34 | struct of_mm_gpio_chip mm_gc; | |
35 | spinlock_t lock; | |
36 | ||
37 | /* | |
38 | * shadowed data register to be able to clear/set output pins in | |
39 | * open drain mode safely | |
40 | */ | |
41 | u32 data; | |
bae1d8f1 | 42 | struct irq_domain *irq; |
01a04ddc | 43 | const void *of_dev_id_data; |
1e16dfc1 PK |
44 | }; |
45 | ||
46 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) | |
47 | { | |
48 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); | |
49 | } | |
50 | ||
51 | static inline struct mpc8xxx_gpio_chip * | |
52 | to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) | |
53 | { | |
54 | return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); | |
55 | } | |
56 | ||
57 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) | |
58 | { | |
59 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
60 | ||
61 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); | |
62 | } | |
63 | ||
c1a676df FR |
64 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
65 | * defined as output cannot be determined by reading GPDAT register, | |
66 | * so we use shadow data register instead. The status of input pins | |
67 | * is determined by reading GPDAT register. | |
68 | */ | |
69 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) | |
70 | { | |
71 | u32 val; | |
72 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
73 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
1aeef303 | 74 | u32 out_mask, out_shadow; |
c1a676df | 75 | |
1aeef303 | 76 | out_mask = in_be32(mm->regs + GPIO_DIR); |
c1a676df | 77 | |
1aeef303 LG |
78 | val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; |
79 | out_shadow = mpc8xxx_gc->data & out_mask; | |
80 | ||
81 | return (val | out_shadow) & mpc8xxx_gpio2mask(gpio); | |
c1a676df FR |
82 | } |
83 | ||
1e16dfc1 PK |
84 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
85 | { | |
86 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
87 | ||
88 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); | |
89 | } | |
90 | ||
91 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
92 | { | |
93 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
94 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
95 | unsigned long flags; | |
96 | ||
97 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
98 | ||
99 | if (val) | |
100 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); | |
101 | else | |
102 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); | |
103 | ||
104 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); | |
105 | ||
106 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
107 | } | |
108 | ||
e5db3b33 RI |
109 | static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc, |
110 | unsigned long *mask, unsigned long *bits) | |
111 | { | |
112 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
113 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
114 | unsigned long flags; | |
115 | int i; | |
116 | ||
117 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
118 | ||
119 | for (i = 0; i < gc->ngpio; i++) { | |
120 | if (*mask == 0) | |
121 | break; | |
122 | if (__test_and_clear_bit(i, mask)) { | |
123 | if (test_bit(i, bits)) | |
124 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i); | |
125 | else | |
126 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i); | |
127 | } | |
128 | } | |
129 | ||
130 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); | |
131 | ||
132 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
133 | } | |
134 | ||
1e16dfc1 PK |
135 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
136 | { | |
137 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
138 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
139 | unsigned long flags; | |
140 | ||
141 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
142 | ||
143 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
144 | ||
145 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
151 | { | |
152 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
153 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
154 | unsigned long flags; | |
155 | ||
156 | mpc8xxx_gpio_set(gc, gpio, val); | |
157 | ||
158 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
159 | ||
160 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
161 | ||
162 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
28538df0 WS |
167 | static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
168 | { | |
169 | /* GPIO 28..31 are input only on MPC5121 */ | |
170 | if (gpio >= 28) | |
171 | return -EINVAL; | |
172 | ||
173 | return mpc8xxx_gpio_dir_out(gc, gpio, val); | |
174 | } | |
175 | ||
345e5c8a PK |
176 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
177 | { | |
178 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
179 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
180 | ||
181 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) | |
182 | return irq_create_mapping(mpc8xxx_gc->irq, offset); | |
183 | else | |
184 | return -ENXIO; | |
185 | } | |
186 | ||
187 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | |
188 | { | |
ec775d0e | 189 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
cfadd838 | 190 | struct irq_chip *chip = irq_desc_get_chip(desc); |
345e5c8a PK |
191 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
192 | unsigned int mask; | |
193 | ||
194 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); | |
195 | if (mask) | |
196 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, | |
197 | 32 - ffs(mask))); | |
d6de85e8 TG |
198 | if (chip->irq_eoi) |
199 | chip->irq_eoi(&desc->irq_data); | |
345e5c8a PK |
200 | } |
201 | ||
94347cb3 | 202 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
345e5c8a | 203 | { |
94347cb3 | 204 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
205 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
206 | unsigned long flags; | |
207 | ||
208 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
209 | ||
476eb491 | 210 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
211 | |
212 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
213 | } | |
214 | ||
94347cb3 | 215 | static void mpc8xxx_irq_mask(struct irq_data *d) |
345e5c8a | 216 | { |
94347cb3 | 217 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
218 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
219 | unsigned long flags; | |
220 | ||
221 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
222 | ||
476eb491 | 223 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
224 | |
225 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
226 | } | |
227 | ||
94347cb3 | 228 | static void mpc8xxx_irq_ack(struct irq_data *d) |
345e5c8a | 229 | { |
94347cb3 | 230 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
231 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
232 | ||
476eb491 | 233 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
234 | } |
235 | ||
94347cb3 | 236 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
345e5c8a | 237 | { |
94347cb3 | 238 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
239 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
240 | unsigned long flags; | |
241 | ||
242 | switch (flow_type) { | |
243 | case IRQ_TYPE_EDGE_FALLING: | |
244 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
245 | setbits32(mm->regs + GPIO_ICR, | |
476eb491 | 246 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
247 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
248 | break; | |
249 | ||
250 | case IRQ_TYPE_EDGE_BOTH: | |
251 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
252 | clrbits32(mm->regs + GPIO_ICR, | |
476eb491 | 253 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
254 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
255 | break; | |
256 | ||
257 | default: | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
94347cb3 | 264 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
e39d5ef6 | 265 | { |
94347cb3 | 266 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
e39d5ef6 | 267 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
476eb491 | 268 | unsigned long gpio = irqd_to_hwirq(d); |
e39d5ef6 AG |
269 | void __iomem *reg; |
270 | unsigned int shift; | |
271 | unsigned long flags; | |
272 | ||
273 | if (gpio < 16) { | |
274 | reg = mm->regs + GPIO_ICR; | |
275 | shift = (15 - gpio) * 2; | |
276 | } else { | |
277 | reg = mm->regs + GPIO_ICR2; | |
278 | shift = (15 - (gpio % 16)) * 2; | |
279 | } | |
280 | ||
281 | switch (flow_type) { | |
282 | case IRQ_TYPE_EDGE_FALLING: | |
283 | case IRQ_TYPE_LEVEL_LOW: | |
284 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
285 | clrsetbits_be32(reg, 3 << shift, 2 << shift); | |
286 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
287 | break; | |
288 | ||
289 | case IRQ_TYPE_EDGE_RISING: | |
290 | case IRQ_TYPE_LEVEL_HIGH: | |
291 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
292 | clrsetbits_be32(reg, 3 << shift, 1 << shift); | |
293 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
294 | break; | |
295 | ||
296 | case IRQ_TYPE_EDGE_BOTH: | |
297 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
298 | clrbits32(reg, 3 << shift); | |
299 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
300 | break; | |
301 | ||
302 | default: | |
303 | return -EINVAL; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
345e5c8a PK |
309 | static struct irq_chip mpc8xxx_irq_chip = { |
310 | .name = "mpc8xxx-gpio", | |
94347cb3 LB |
311 | .irq_unmask = mpc8xxx_irq_unmask, |
312 | .irq_mask = mpc8xxx_irq_mask, | |
313 | .irq_ack = mpc8xxx_irq_ack, | |
314 | .irq_set_type = mpc8xxx_irq_set_type, | |
345e5c8a PK |
315 | }; |
316 | ||
5ba17ae9 LW |
317 | static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, |
318 | irq_hw_number_t hwirq) | |
345e5c8a | 319 | { |
e39d5ef6 AG |
320 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; |
321 | ||
322 | if (mpc8xxx_gc->of_dev_id_data) | |
94347cb3 | 323 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
e39d5ef6 | 324 | |
5ba17ae9 LW |
325 | irq_set_chip_data(irq, h->host_data); |
326 | irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq); | |
345e5c8a PK |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
bae1d8f1 | 331 | static struct irq_domain_ops mpc8xxx_gpio_irq_ops = { |
345e5c8a | 332 | .map = mpc8xxx_gpio_irq_map, |
ff8c3ab8 | 333 | .xlate = irq_domain_xlate_twocell, |
345e5c8a PK |
334 | }; |
335 | ||
e39d5ef6 AG |
336 | static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { |
337 | { .compatible = "fsl,mpc8349-gpio", }, | |
338 | { .compatible = "fsl,mpc8572-gpio", }, | |
339 | { .compatible = "fsl,mpc8610-gpio", }, | |
340 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, | |
15a5148c | 341 | { .compatible = "fsl,pq3-gpio", }, |
d1dcfbbb | 342 | { .compatible = "fsl,qoriq-gpio", }, |
e39d5ef6 AG |
343 | {} |
344 | }; | |
345 | ||
98686d9a | 346 | static int mpc8xxx_probe(struct platform_device *pdev) |
1e16dfc1 | 347 | { |
98686d9a | 348 | struct device_node *np = pdev->dev.of_node; |
1e16dfc1 PK |
349 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; |
350 | struct of_mm_gpio_chip *mm_gc; | |
1e16dfc1 | 351 | struct gpio_chip *gc; |
e39d5ef6 | 352 | const struct of_device_id *id; |
345e5c8a | 353 | unsigned hwirq; |
1e16dfc1 PK |
354 | int ret; |
355 | ||
98686d9a RRD |
356 | mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); |
357 | if (!mpc8xxx_gc) | |
358 | return -ENOMEM; | |
1e16dfc1 PK |
359 | |
360 | spin_lock_init(&mpc8xxx_gc->lock); | |
361 | ||
362 | mm_gc = &mpc8xxx_gc->mm_gc; | |
a19e3da5 | 363 | gc = &mm_gc->gc; |
1e16dfc1 PK |
364 | |
365 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; | |
1e16dfc1 PK |
366 | gc->ngpio = MPC8XXX_GPIO_PINS; |
367 | gc->direction_input = mpc8xxx_gpio_dir_in; | |
28538df0 WS |
368 | gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ? |
369 | mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out; | |
370 | gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ? | |
371 | mpc8572_gpio_get : mpc8xxx_gpio_get; | |
1e16dfc1 | 372 | gc->set = mpc8xxx_gpio_set; |
e5db3b33 | 373 | gc->set_multiple = mpc8xxx_gpio_set_multiple; |
345e5c8a | 374 | gc->to_irq = mpc8xxx_gpio_to_irq; |
1e16dfc1 PK |
375 | |
376 | ret = of_mm_gpiochip_add(np, mm_gc); | |
377 | if (ret) | |
98686d9a | 378 | return ret; |
1e16dfc1 | 379 | |
345e5c8a PK |
380 | hwirq = irq_of_parse_and_map(np, 0); |
381 | if (hwirq == NO_IRQ) | |
98686d9a | 382 | return 0; |
345e5c8a | 383 | |
a8db8cf0 GL |
384 | mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, |
385 | &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); | |
345e5c8a | 386 | if (!mpc8xxx_gc->irq) |
98686d9a | 387 | return 0; |
345e5c8a | 388 | |
e39d5ef6 AG |
389 | id = of_match_node(mpc8xxx_gpio_ids, np); |
390 | if (id) | |
391 | mpc8xxx_gc->of_dev_id_data = id->data; | |
392 | ||
345e5c8a PK |
393 | /* ack and mask all irqs */ |
394 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); | |
395 | out_be32(mm_gc->regs + GPIO_IMR, 0); | |
396 | ||
ec775d0e TG |
397 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
398 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); | |
345e5c8a | 399 | |
98686d9a | 400 | return 0; |
1e16dfc1 PK |
401 | } |
402 | ||
98686d9a RRD |
403 | static struct platform_driver mpc8xxx_plat_driver = { |
404 | .probe = mpc8xxx_probe, | |
405 | .driver = { | |
406 | .name = "gpio-mpc8xxx", | |
407 | .of_match_table = mpc8xxx_gpio_ids, | |
408 | }, | |
409 | }; | |
1e16dfc1 | 410 | |
98686d9a RRD |
411 | static int __init mpc8xxx_init(void) |
412 | { | |
413 | return platform_driver_register(&mpc8xxx_plat_driver); | |
1e16dfc1 | 414 | } |
98686d9a RRD |
415 | |
416 | arch_initcall(mpc8xxx_init); |