Commit | Line | Data |
---|---|---|
1e16dfc1 | 1 | /* |
e39d5ef6 | 2 | * GPIOs on MPC512x/8349/8572/8610 and compatible |
1e16dfc1 PK |
3 | * |
4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_gpio.h> | |
17 | #include <linux/gpio.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
345e5c8a | 19 | #include <linux/irq.h> |
1e16dfc1 PK |
20 | |
21 | #define MPC8XXX_GPIO_PINS 32 | |
22 | ||
23 | #define GPIO_DIR 0x00 | |
24 | #define GPIO_ODR 0x04 | |
25 | #define GPIO_DAT 0x08 | |
26 | #define GPIO_IER 0x0c | |
27 | #define GPIO_IMR 0x10 | |
28 | #define GPIO_ICR 0x14 | |
e39d5ef6 | 29 | #define GPIO_ICR2 0x18 |
1e16dfc1 PK |
30 | |
31 | struct mpc8xxx_gpio_chip { | |
32 | struct of_mm_gpio_chip mm_gc; | |
33 | spinlock_t lock; | |
34 | ||
35 | /* | |
36 | * shadowed data register to be able to clear/set output pins in | |
37 | * open drain mode safely | |
38 | */ | |
39 | u32 data; | |
345e5c8a | 40 | struct irq_host *irq; |
e39d5ef6 | 41 | void *of_dev_id_data; |
1e16dfc1 PK |
42 | }; |
43 | ||
44 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) | |
45 | { | |
46 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); | |
47 | } | |
48 | ||
49 | static inline struct mpc8xxx_gpio_chip * | |
50 | to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) | |
51 | { | |
52 | return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); | |
53 | } | |
54 | ||
55 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) | |
56 | { | |
57 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
58 | ||
59 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); | |
60 | } | |
61 | ||
c1a676df FR |
62 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
63 | * defined as output cannot be determined by reading GPDAT register, | |
64 | * so we use shadow data register instead. The status of input pins | |
65 | * is determined by reading GPDAT register. | |
66 | */ | |
67 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) | |
68 | { | |
69 | u32 val; | |
70 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
71 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
72 | ||
73 | val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); | |
74 | ||
75 | return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); | |
76 | } | |
77 | ||
1e16dfc1 PK |
78 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
79 | { | |
80 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
81 | ||
82 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); | |
83 | } | |
84 | ||
85 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
86 | { | |
87 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
88 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
89 | unsigned long flags; | |
90 | ||
91 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
92 | ||
93 | if (val) | |
94 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); | |
95 | else | |
96 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); | |
97 | ||
98 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); | |
99 | ||
100 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
101 | } | |
102 | ||
103 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
104 | { | |
105 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
106 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
107 | unsigned long flags; | |
108 | ||
109 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
110 | ||
111 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
112 | ||
113 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
119 | { | |
120 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
121 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
122 | unsigned long flags; | |
123 | ||
124 | mpc8xxx_gpio_set(gc, gpio, val); | |
125 | ||
126 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
127 | ||
128 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); | |
129 | ||
130 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
345e5c8a PK |
135 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
136 | { | |
137 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); | |
138 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); | |
139 | ||
140 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) | |
141 | return irq_create_mapping(mpc8xxx_gc->irq, offset); | |
142 | else | |
143 | return -ENXIO; | |
144 | } | |
145 | ||
146 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | |
147 | { | |
ec775d0e | 148 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
cfadd838 | 149 | struct irq_chip *chip = irq_desc_get_chip(desc); |
345e5c8a PK |
150 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
151 | unsigned int mask; | |
152 | ||
153 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); | |
154 | if (mask) | |
155 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, | |
156 | 32 - ffs(mask))); | |
cfadd838 | 157 | chip->irq_eoi(&desc->irq_data); |
345e5c8a PK |
158 | } |
159 | ||
94347cb3 | 160 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
345e5c8a | 161 | { |
94347cb3 | 162 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
163 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
164 | unsigned long flags; | |
165 | ||
166 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
167 | ||
476eb491 | 168 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
169 | |
170 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
171 | } | |
172 | ||
94347cb3 | 173 | static void mpc8xxx_irq_mask(struct irq_data *d) |
345e5c8a | 174 | { |
94347cb3 | 175 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
176 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
177 | unsigned long flags; | |
178 | ||
179 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
180 | ||
476eb491 | 181 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
182 | |
183 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
184 | } | |
185 | ||
94347cb3 | 186 | static void mpc8xxx_irq_ack(struct irq_data *d) |
345e5c8a | 187 | { |
94347cb3 | 188 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
189 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
190 | ||
476eb491 | 191 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
192 | } |
193 | ||
94347cb3 | 194 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
345e5c8a | 195 | { |
94347cb3 | 196 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
345e5c8a PK |
197 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
198 | unsigned long flags; | |
199 | ||
200 | switch (flow_type) { | |
201 | case IRQ_TYPE_EDGE_FALLING: | |
202 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
203 | setbits32(mm->regs + GPIO_ICR, | |
476eb491 | 204 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
205 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
206 | break; | |
207 | ||
208 | case IRQ_TYPE_EDGE_BOTH: | |
209 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
210 | clrbits32(mm->regs + GPIO_ICR, | |
476eb491 | 211 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
345e5c8a PK |
212 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
213 | break; | |
214 | ||
215 | default: | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
94347cb3 | 222 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
e39d5ef6 | 223 | { |
94347cb3 | 224 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
e39d5ef6 | 225 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
476eb491 | 226 | unsigned long gpio = irqd_to_hwirq(d); |
e39d5ef6 AG |
227 | void __iomem *reg; |
228 | unsigned int shift; | |
229 | unsigned long flags; | |
230 | ||
231 | if (gpio < 16) { | |
232 | reg = mm->regs + GPIO_ICR; | |
233 | shift = (15 - gpio) * 2; | |
234 | } else { | |
235 | reg = mm->regs + GPIO_ICR2; | |
236 | shift = (15 - (gpio % 16)) * 2; | |
237 | } | |
238 | ||
239 | switch (flow_type) { | |
240 | case IRQ_TYPE_EDGE_FALLING: | |
241 | case IRQ_TYPE_LEVEL_LOW: | |
242 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
243 | clrsetbits_be32(reg, 3 << shift, 2 << shift); | |
244 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
245 | break; | |
246 | ||
247 | case IRQ_TYPE_EDGE_RISING: | |
248 | case IRQ_TYPE_LEVEL_HIGH: | |
249 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
250 | clrsetbits_be32(reg, 3 << shift, 1 << shift); | |
251 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
252 | break; | |
253 | ||
254 | case IRQ_TYPE_EDGE_BOTH: | |
255 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
256 | clrbits32(reg, 3 << shift); | |
257 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
258 | break; | |
259 | ||
260 | default: | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
345e5c8a PK |
267 | static struct irq_chip mpc8xxx_irq_chip = { |
268 | .name = "mpc8xxx-gpio", | |
94347cb3 LB |
269 | .irq_unmask = mpc8xxx_irq_unmask, |
270 | .irq_mask = mpc8xxx_irq_mask, | |
271 | .irq_ack = mpc8xxx_irq_ack, | |
272 | .irq_set_type = mpc8xxx_irq_set_type, | |
345e5c8a PK |
273 | }; |
274 | ||
275 | static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, | |
276 | irq_hw_number_t hw) | |
277 | { | |
e39d5ef6 AG |
278 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; |
279 | ||
280 | if (mpc8xxx_gc->of_dev_id_data) | |
94347cb3 | 281 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
e39d5ef6 | 282 | |
ec775d0e TG |
283 | irq_set_chip_data(virq, h->host_data); |
284 | irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); | |
285 | irq_set_irq_type(virq, IRQ_TYPE_NONE); | |
345e5c8a PK |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct, | |
291 | const u32 *intspec, unsigned int intsize, | |
292 | irq_hw_number_t *out_hwirq, | |
293 | unsigned int *out_flags) | |
294 | ||
295 | { | |
296 | /* interrupt sense values coming from the device tree equal either | |
297 | * EDGE_FALLING or EDGE_BOTH | |
298 | */ | |
299 | *out_hwirq = intspec[0]; | |
300 | *out_flags = intspec[1]; | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | static struct irq_host_ops mpc8xxx_gpio_irq_ops = { | |
306 | .map = mpc8xxx_gpio_irq_map, | |
307 | .xlate = mpc8xxx_gpio_irq_xlate, | |
308 | }; | |
309 | ||
e39d5ef6 AG |
310 | static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { |
311 | { .compatible = "fsl,mpc8349-gpio", }, | |
312 | { .compatible = "fsl,mpc8572-gpio", }, | |
313 | { .compatible = "fsl,mpc8610-gpio", }, | |
314 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, | |
15a5148c | 315 | { .compatible = "fsl,pq3-gpio", }, |
d1dcfbbb | 316 | { .compatible = "fsl,qoriq-gpio", }, |
e39d5ef6 AG |
317 | {} |
318 | }; | |
319 | ||
1e16dfc1 PK |
320 | static void __init mpc8xxx_add_controller(struct device_node *np) |
321 | { | |
322 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; | |
323 | struct of_mm_gpio_chip *mm_gc; | |
1e16dfc1 | 324 | struct gpio_chip *gc; |
e39d5ef6 | 325 | const struct of_device_id *id; |
345e5c8a | 326 | unsigned hwirq; |
1e16dfc1 PK |
327 | int ret; |
328 | ||
329 | mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); | |
330 | if (!mpc8xxx_gc) { | |
331 | ret = -ENOMEM; | |
332 | goto err; | |
333 | } | |
334 | ||
335 | spin_lock_init(&mpc8xxx_gc->lock); | |
336 | ||
337 | mm_gc = &mpc8xxx_gc->mm_gc; | |
a19e3da5 | 338 | gc = &mm_gc->gc; |
1e16dfc1 PK |
339 | |
340 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; | |
1e16dfc1 PK |
341 | gc->ngpio = MPC8XXX_GPIO_PINS; |
342 | gc->direction_input = mpc8xxx_gpio_dir_in; | |
343 | gc->direction_output = mpc8xxx_gpio_dir_out; | |
c1a676df FR |
344 | if (of_device_is_compatible(np, "fsl,mpc8572-gpio")) |
345 | gc->get = mpc8572_gpio_get; | |
346 | else | |
347 | gc->get = mpc8xxx_gpio_get; | |
1e16dfc1 | 348 | gc->set = mpc8xxx_gpio_set; |
345e5c8a | 349 | gc->to_irq = mpc8xxx_gpio_to_irq; |
1e16dfc1 PK |
350 | |
351 | ret = of_mm_gpiochip_add(np, mm_gc); | |
352 | if (ret) | |
353 | goto err; | |
354 | ||
345e5c8a PK |
355 | hwirq = irq_of_parse_and_map(np, 0); |
356 | if (hwirq == NO_IRQ) | |
357 | goto skip_irq; | |
358 | ||
359 | mpc8xxx_gc->irq = | |
360 | irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS, | |
361 | &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS); | |
362 | if (!mpc8xxx_gc->irq) | |
363 | goto skip_irq; | |
364 | ||
e39d5ef6 AG |
365 | id = of_match_node(mpc8xxx_gpio_ids, np); |
366 | if (id) | |
367 | mpc8xxx_gc->of_dev_id_data = id->data; | |
368 | ||
345e5c8a PK |
369 | mpc8xxx_gc->irq->host_data = mpc8xxx_gc; |
370 | ||
371 | /* ack and mask all irqs */ | |
372 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); | |
373 | out_be32(mm_gc->regs + GPIO_IMR, 0); | |
374 | ||
ec775d0e TG |
375 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
376 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); | |
345e5c8a PK |
377 | |
378 | skip_irq: | |
1e16dfc1 PK |
379 | return; |
380 | ||
381 | err: | |
382 | pr_err("%s: registration failed with status %d\n", | |
383 | np->full_name, ret); | |
384 | kfree(mpc8xxx_gc); | |
385 | ||
386 | return; | |
387 | } | |
388 | ||
389 | static int __init mpc8xxx_add_gpiochips(void) | |
390 | { | |
391 | struct device_node *np; | |
392 | ||
e39d5ef6 | 393 | for_each_matching_node(np, mpc8xxx_gpio_ids) |
1e16dfc1 PK |
394 | mpc8xxx_add_controller(np); |
395 | ||
396 | return 0; | |
397 | } | |
398 | arch_initcall(mpc8xxx_add_gpiochips); |