[deliverable/linux.git] / drivers / gpio / gpio-msm-v2.c

/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 *
 */
#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>

#include <mach/msm_iomap.h>

/* Bits of interest in the GPIO_IN_OUT register.
 */
enum {
	GPIO_IN  = 0,
	GPIO_OUT = 1
};

/* Bits of interest in the GPIO_INTR_STATUS register.
 */
enum {
	INTR_STATUS = 0,
};

/* Bits of interest in the GPIO_CFG register.
 */
enum {
	GPIO_OE = 9,
};

/* Bits of interest in the GPIO_INTR_CFG register.
 * When a GPIO triggers, two separate decisions are made, controlled
 * by two separate flags.
 *
 * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
 * register for that GPIO will be updated to reflect the triggering of that
 * gpio.  If this bit is 0, this register will not be updated.
 * - Second, INTR_ENABLE controls whether an interrupt is triggered.
 *
 * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
 * can be triggered but the status register will not reflect it.
 */
enum {
	INTR_ENABLE        = 0,
	INTR_POL_CTL       = 1,
	INTR_DECT_CTL      = 2,
	INTR_RAW_STATUS_EN = 3,
};

/* Codes of interest in GPIO_INTR_CFG_SU.
 */
enum {
	TARGET_PROC_SCORPION = 4,
	TARGET_PROC_NONE     = 7,
};


#define GPIO_INTR_CFG_SU(gpio)    (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
#define GPIO_CONFIG(gpio)         (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
#define GPIO_IN_OUT(gpio)         (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
#define GPIO_INTR_CFG(gpio)       (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
#define GPIO_INTR_STATUS(gpio)    (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))

/**
 * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
 *
 * @enabled_irqs: a bitmap used to optimize the summary-irq handler.  By
 * keeping track of which gpios are unmasked as irq sources, we avoid
 * having to do readl calls on hundreds of iomapped registers each time
 * the summary interrupt fires in order to locate the active interrupts.
 *
 * @wake_irqs: a bitmap for tracking which interrupt lines are enabled
 * as wakeup sources.  When the device is suspended, interrupts which are
 * not wakeup sources are disabled.
 *
 * @dual_edge_irqs: a bitmap used to track which irqs are configured
 * as dual-edge, as this is not supported by the hardware and requires
 * some special handling in the driver.
 */
struct msm_gpio_dev {
	struct gpio_chip gpio_chip;
	DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
	DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
	DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
};

static DEFINE_SPINLOCK(tlmm_lock);

static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
{
	return container_of(chip, struct msm_gpio_dev, gpio_chip);
}

static inline void set_gpio_bits(unsigned n, void __iomem *reg)
{
	writel(readl(reg) | n, reg);
}

static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
{
	writel(readl(reg) & ~n, reg);
}

static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
}

static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
}

static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	return 0;
}

static int msm_gpio_direction_output(struct gpio_chip *chip,
				unsigned offset,
				int val)
{
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	msm_gpio_set(chip, offset, val);
	set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	return 0;
}

static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return 0;
}

static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	return;
}

static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return MSM_GPIO_TO_INT(chip->base + offset);
}

static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
{
	return irq - MSM_GPIO_TO_INT(chip->base);
}

static struct msm_gpio_dev msm_gpio = {
	.gpio_chip = {
		.base             = 0,
		.ngpio            = NR_GPIO_IRQS,
		.direction_input  = msm_gpio_direction_input,
		.direction_output = msm_gpio_direction_output,
		.get              = msm_gpio_get,
		.set              = msm_gpio_set,
		.to_irq           = msm_gpio_to_irq,
		.request          = msm_gpio_request,
		.free             = msm_gpio_free,
	},
};

/* For dual-edge interrupts in software, since the hardware has no
 * such support:
 *
 * At appropriate moments, this function may be called to flip the polarity
 * settings of both-edge irq lines to try and catch the next edge.
 *
 * The attempt is considered successful if:
 * - the status bit goes high, indicating that an edge was caught, or
 * - the input value of the gpio doesn't change during the attempt.
 * If the value changes twice during the process, that would cause the first
 * test to fail but would force the second, as two opposite
 * transitions would cause a detection no matter the polarity setting.
 *
 * The do-loop tries to sledge-hammer closed the timing hole between
 * the initial value-read and the polarity-write - if the line value changes
 * during that window, an interrupt is lost, the new polarity setting is
 * incorrect, and the first success test will fail, causing a retry.
 *
 * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
 */
static void msm_gpio_update_dual_edge_pos(unsigned gpio)
{
	int loop_limit = 100;
	unsigned val, val2, intstat;

	do {
		val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
		if (val)
			clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
		else
			set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
		val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
		intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
		if (intstat || val == val2)
			return;
	} while (loop_limit-- > 0);
	pr_err("dual-edge irq failed to stabilize, "
	       "interrupts dropped. %#08x != %#08x\n",
	       val, val2);
}

static void msm_gpio_irq_ack(struct irq_data *d)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);

	writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
	if (test_bit(gpio, msm_gpio.dual_edge_irqs))
		msm_gpio_update_dual_edge_pos(gpio);
}

static void msm_gpio_irq_mask(struct irq_data *d)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
	clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
	__clear_bit(gpio, msm_gpio.enabled_irqs);
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
}

static void msm_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	__set_bit(gpio, msm_gpio.enabled_irqs);
	set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
	writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
}

static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
	unsigned long irq_flags;
	uint32_t bits;

	spin_lock_irqsave(&tlmm_lock, irq_flags);

	bits = readl(GPIO_INTR_CFG(gpio));

	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
		bits |= BIT(INTR_DECT_CTL);
		__irq_set_handler_locked(d->irq, handle_edge_irq);
		if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
			__set_bit(gpio, msm_gpio.dual_edge_irqs);
		else
			__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	} else {
		bits &= ~BIT(INTR_DECT_CTL);
		__irq_set_handler_locked(d->irq, handle_level_irq);
		__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	}

	if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
		bits |= BIT(INTR_POL_CTL);
	else
		bits &= ~BIT(INTR_POL_CTL);

	writel(bits, GPIO_INTR_CFG(gpio));

	if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		msm_gpio_update_dual_edge_pos(gpio);

	spin_unlock_irqrestore(&tlmm_lock, irq_flags);

	return 0;
}

/*
 * When the summary IRQ is raised, any number of GPIO lines may be high.
 * It is the job of the summary handler to find all those GPIO lines
 * which have been set as summary IRQ lines and which are triggered,
 * and to call their interrupt handlers.
 */
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long i;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) {
		if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
			generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
							   i));
	}

	chained_irq_exit(chip, desc);
}

static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);

	if (on) {
		if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
			irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
		set_bit(gpio, msm_gpio.wake_irqs);
	} else {
		clear_bit(gpio, msm_gpio.wake_irqs);
		if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
			irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
	}

	return 0;
}

static struct irq_chip msm_gpio_irq_chip = {
	.name		= "msmgpio",
	.irq_mask	= msm_gpio_irq_mask,
	.irq_unmask	= msm_gpio_irq_unmask,
	.irq_ack	= msm_gpio_irq_ack,
	.irq_set_type	= msm_gpio_irq_set_type,
	.irq_set_wake	= msm_gpio_irq_set_wake,
};

static int msm_gpio_probe(struct platform_device *dev)
{
	int i, irq, ret;

	bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
	bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
	bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
	msm_gpio.gpio_chip.label = dev->name;
	ret = gpiochip_add(&msm_gpio.gpio_chip);
	if (ret < 0)
		return ret;

	for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
		irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
		irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
				msm_summary_irq_handler);
	return 0;
}

static int msm_gpio_remove(struct platform_device *dev)
{
	int ret = gpiochip_remove(&msm_gpio.gpio_chip);

	if (ret < 0)
		return ret;

	irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);

	return 0;
}

static struct platform_driver msm_gpio_driver = {
	.probe = msm_gpio_probe,
	.remove = msm_gpio_remove,
	.driver = {
		.name = "msmgpio",
		.owner = THIS_MODULE,
	},
};

static struct platform_device msm_device_gpio = {
	.name = "msmgpio",
	.id   = -1,
};

static int __init msm_gpio_init(void)
{
	int rc;

	rc = platform_driver_register(&msm_gpio_driver);
	if (!rc) {
		rc = platform_device_register(&msm_device_gpio);
		if (rc)
			platform_driver_unregister(&msm_gpio_driver);
	}

	return rc;
}

static void __exit msm_gpio_exit(void)
{
	platform_device_unregister(&msm_device_gpio);
	platform_driver_unregister(&msm_gpio_driver);
}

postcore_initcall(msm_gpio_init);
module_exit(msm_gpio_exit);

MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:msmgpio");
Commit	Line	Data
1a5ab4b3	1	/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
0cc2fc1f GB	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	* 02110-1301, USA.
	16	*
	17	*/
70cc2c00 GB	18	#define pr_fmt(fmt) "%s: " fmt, __func__
	19
	20	#include <linux/bitmap.h>
	21	#include <linux/bitops.h>
0cc2fc1f	22	#include <linux/gpio.h>
70cc2c00 GB	23	#include <linux/init.h>
70cc2c00 GB	24	#include <linux/interrupt.h>
0cc2fc1f	25	#include <linux/io.h>
de88cbb7	26	#include <linux/irqchip/chained_irq.h>
0cc2fc1f GB	27	#include <linux/irq.h>
	28	#include <linux/module.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/spinlock.h>
03dd765f	31
0cc2fc1f	32	#include <mach/msm_iomap.h>
0cc2fc1f GB	33
	34	/* Bits of interest in the GPIO_IN_OUT register.
	35	*/
	36	enum {
70cc2c00 GB	37	GPIO_IN = 0,
	38	GPIO_OUT = 1
	39	};
	40
	41	/* Bits of interest in the GPIO_INTR_STATUS register.
	42	*/
	43	enum {
	44	INTR_STATUS = 0,
0cc2fc1f GB	45	};
	46
	47	/* Bits of interest in the GPIO_CFG register.
	48	*/
	49	enum {
70cc2c00 GB	50	GPIO_OE = 9,
	51	};
	52
	53	/* Bits of interest in the GPIO_INTR_CFG register.
	54	* When a GPIO triggers, two separate decisions are made, controlled
	55	* by two separate flags.
	56	*
	57	* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
	58	* register for that GPIO will be updated to reflect the triggering of that
	59	* gpio. If this bit is 0, this register will not be updated.
	60	* - Second, INTR_ENABLE controls whether an interrupt is triggered.
	61	*
	62	* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
	63	* can be triggered but the status register will not reflect it.
	64	*/
	65	enum {
	66	INTR_ENABLE = 0,
	67	INTR_POL_CTL = 1,
	68	INTR_DECT_CTL = 2,
	69	INTR_RAW_STATUS_EN = 3,
	70	};
	71
	72	/* Codes of interest in GPIO_INTR_CFG_SU.
	73	*/
	74	enum {
	75	TARGET_PROC_SCORPION = 4,
	76	TARGET_PROC_NONE = 7,
0cc2fc1f GB	77	};
0cc2fc1f GB	78
70cc2c00 GB	79
70cc2c00 GB	80	#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
0cc2fc1f GB	81	#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
0cc2fc1f GB	82	#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
70cc2c00 GB	83	#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
	84	#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
	85
	86	/**
	87	* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
	88	*
	89	* @enabled_irqs: a bitmap used to optimize the summary-irq handler. By
	90	* keeping track of which gpios are unmasked as irq sources, we avoid
	91	* having to do readl calls on hundreds of iomapped registers each time
	92	* the summary interrupt fires in order to locate the active interrupts.
	93	*
	94	* @wake_irqs: a bitmap for tracking which interrupt lines are enabled
	95	* as wakeup sources. When the device is suspended, interrupts which are
	96	* not wakeup sources are disabled.
	97	*
	98	* @dual_edge_irqs: a bitmap used to track which irqs are configured
	99	* as dual-edge, as this is not supported by the hardware and requires
	100	* some special handling in the driver.
	101	*/
	102	struct msm_gpio_dev {
	103	struct gpio_chip gpio_chip;
	104	DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
	105	DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
	106	DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
	107	};
0cc2fc1f GB	108
	109	static DEFINE_SPINLOCK(tlmm_lock);
	110
70cc2c00 GB	111	static inline struct msm_gpio_dev to_msm_gpio_dev(struct gpio_chip chip)
	112	{
	113	return container_of(chip, struct msm_gpio_dev, gpio_chip);
	114	}
	115
	116	static inline void set_gpio_bits(unsigned n, void __iomem *reg)
	117	{
	118	writel(readl(reg) \| n, reg);
	119	}
	120
	121	static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
	122	{
	123	writel(readl(reg) & ~n, reg);
	124	}
	125
0cc2fc1f GB	126	static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
0cc2fc1f GB	127	{
70cc2c00	128	return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
0cc2fc1f GB	129	}
	130
	131	static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	132	{
70cc2c00	133	writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
0cc2fc1f GB	134	}
	135
	136	static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	137	{
	138	unsigned long irq_flags;
	139
	140	spin_lock_irqsave(&tlmm_lock, irq_flags);
70cc2c00	141	clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
0cc2fc1f GB	142	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	143	return 0;
	144	}
	145
	146	static int msm_gpio_direction_output(struct gpio_chip *chip,
	147	unsigned offset,
	148	int val)
	149	{
	150	unsigned long irq_flags;
	151
	152	spin_lock_irqsave(&tlmm_lock, irq_flags);
	153	msm_gpio_set(chip, offset, val);
70cc2c00	154	set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
0cc2fc1f GB	155	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	156	return 0;
	157	}
	158
	159	static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
	160	{
eda9dcfa	161	return 0;
0cc2fc1f GB	162	}
	163
	164	static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
	165	{
eda9dcfa	166	return;
0cc2fc1f GB	167	}
0cc2fc1f GB	168
70cc2c00 GB	169	static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	170	{
	171	return MSM_GPIO_TO_INT(chip->base + offset);
	172	}
	173
	174	static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
	175	{
	176	return irq - MSM_GPIO_TO_INT(chip->base);
	177	}
	178
	179	static struct msm_gpio_dev msm_gpio = {
	180	.gpio_chip = {
	181	.base = 0,
	182	.ngpio = NR_GPIO_IRQS,
	183	.direction_input = msm_gpio_direction_input,
	184	.direction_output = msm_gpio_direction_output,
	185	.get = msm_gpio_get,
	186	.set = msm_gpio_set,
	187	.to_irq = msm_gpio_to_irq,
	188	.request = msm_gpio_request,
	189	.free = msm_gpio_free,
	190	},
	191	};
	192
	193	/* For dual-edge interrupts in software, since the hardware has no
	194	* such support:
	195	*
	196	* At appropriate moments, this function may be called to flip the polarity
	197	* settings of both-edge irq lines to try and catch the next edge.
	198	*
	199	* The attempt is considered successful if:
	200	* - the status bit goes high, indicating that an edge was caught, or
	201	* - the input value of the gpio doesn't change during the attempt.
	202	* If the value changes twice during the process, that would cause the first
	203	* test to fail but would force the second, as two opposite
	204	* transitions would cause a detection no matter the polarity setting.
	205	*
	206	* The do-loop tries to sledge-hammer closed the timing hole between
	207	* the initial value-read and the polarity-write - if the line value changes
	208	* during that window, an interrupt is lost, the new polarity setting is
	209	* incorrect, and the first success test will fail, causing a retry.
	210	*
	211	* Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
	212	*/
	213	static void msm_gpio_update_dual_edge_pos(unsigned gpio)
	214	{
	215	int loop_limit = 100;
	216	unsigned val, val2, intstat;
	217
	218	do {
	219	val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
	220	if (val)
	221	clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
	222	else
	223	set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
	224	val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
	225	intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
	226	if (intstat \|\| val == val2)
	227	return;
	228	} while (loop_limit-- > 0);
	229	pr_err("dual-edge irq failed to stabilize, "
	230	"interrupts dropped. %#08x != %#08x\n",
	231	val, val2);
	232	}
233
cf8d1581	234	static void msm_gpio_irq_ack(struct irq_data *d)
70cc2c00	235	{
cf8d1581	236	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	237
	238	writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
	239	if (test_bit(gpio, msm_gpio.dual_edge_irqs))
	240	msm_gpio_update_dual_edge_pos(gpio);
	241	}
	242
cf8d1581	243	static void msm_gpio_irq_mask(struct irq_data *d)
70cc2c00	244	{
cf8d1581	245	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	246	unsigned long irq_flags;
	247
	248	spin_lock_irqsave(&tlmm_lock, irq_flags);
	249	writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
	250	clear_gpio_bits(INTR_RAW_STATUS_EN \| INTR_ENABLE, GPIO_INTR_CFG(gpio));
	251	__clear_bit(gpio, msm_gpio.enabled_irqs);
	252	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	253	}
	254
cf8d1581	255	static void msm_gpio_irq_unmask(struct irq_data *d)
70cc2c00	256	{
cf8d1581	257	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	258	unsigned long irq_flags;
	259
	260	spin_lock_irqsave(&tlmm_lock, irq_flags);
	261	__set_bit(gpio, msm_gpio.enabled_irqs);
	262	set_gpio_bits(INTR_RAW_STATUS_EN \| INTR_ENABLE, GPIO_INTR_CFG(gpio));
	263	writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
	264	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	265	}
	266
cf8d1581	267	static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
70cc2c00	268	{
cf8d1581	269	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	270	unsigned long irq_flags;
	271	uint32_t bits;
	272
	273	spin_lock_irqsave(&tlmm_lock, irq_flags);
	274
	275	bits = readl(GPIO_INTR_CFG(gpio));
	276
	277	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
	278	bits \|= BIT(INTR_DECT_CTL);
70c4fa22	279	__irq_set_handler_locked(d->irq, handle_edge_irq);
70cc2c00 GB	280	if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	281	__set_bit(gpio, msm_gpio.dual_edge_irqs);
	282	else
	283	__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	284	} else {
	285	bits &= ~BIT(INTR_DECT_CTL);
70c4fa22	286	__irq_set_handler_locked(d->irq, handle_level_irq);
70cc2c00 GB	287	__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	288	}
	289
	290	if (flow_type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_LEVEL_HIGH))
	291	bits \|= BIT(INTR_POL_CTL);
	292	else
	293	bits &= ~BIT(INTR_POL_CTL);
	294
	295	writel(bits, GPIO_INTR_CFG(gpio));
	296
	297	if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	298	msm_gpio_update_dual_edge_pos(gpio);
	299
	300	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	301
	302	return 0;
	303	}
	304
	305	/*
	306	* When the summary IRQ is raised, any number of GPIO lines may be high.
	307	* It is the job of the summary handler to find all those GPIO lines
	308	* which have been set as summary IRQ lines and which are triggered,
	309	* and to call their interrupt handlers.
	310	*/
	311	static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
	312	{
	313	unsigned long i;
03dd765f WD	314	struct irq_chip *chip = irq_desc_get_chip(desc);
	315
	316	chained_irq_enter(chip, desc);
70cc2c00	317
939d902d	318	for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) {
70cc2c00 GB	319	if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
	320	generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
	321	i));
	322	}
03dd765f WD	323
03dd765f WD	324	chained_irq_exit(chip, desc);
70cc2c00 GB	325	}
70cc2c00 GB	326
cf8d1581	327	static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
70cc2c00	328	{
cf8d1581	329	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	330
	331	if (on) {
	332	if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
6845664a	333	irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
70cc2c00 GB	334	set_bit(gpio, msm_gpio.wake_irqs);
	335	} else {
	336	clear_bit(gpio, msm_gpio.wake_irqs);
	337	if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
6845664a	338	irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
70cc2c00 GB	339	}
	340
	341	return 0;
	342	}
	343
	344	static struct irq_chip msm_gpio_irq_chip = {
	345	.name = "msmgpio",
cf8d1581 TG	346	.irq_mask = msm_gpio_irq_mask,
	347	.irq_unmask = msm_gpio_irq_unmask,
	348	.irq_ack = msm_gpio_irq_ack,
	349	.irq_set_type = msm_gpio_irq_set_type,
	350	.irq_set_wake = msm_gpio_irq_set_wake,
0cc2fc1f GB	351	};
0cc2fc1f GB	352
3836309d	353	static int msm_gpio_probe(struct platform_device *dev)
0cc2fc1f	354	{
70cc2c00 GB	355	int i, irq, ret;
	356
	357	bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
	358	bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
	359	bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
	360	msm_gpio.gpio_chip.label = dev->name;
	361	ret = gpiochip_add(&msm_gpio.gpio_chip);
	362	if (ret < 0)
	363	return ret;
0cc2fc1f	364
70cc2c00 GB	365	for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
70cc2c00 GB	366	irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
f38c02f3 TG	367	irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
f38c02f3 TG	368	handle_level_irq);
70cc2c00 GB	369	set_irq_flags(irq, IRQF_VALID);
70cc2c00 GB	370	}
0cc2fc1f	371
6845664a	372	irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
70cc2c00 GB	373	msm_summary_irq_handler);
70cc2c00 GB	374	return 0;
0cc2fc1f GB	375	}
0cc2fc1f GB	376
206210ce	377	static int msm_gpio_remove(struct platform_device *dev)
0cc2fc1f	378	{
70cc2c00	379	int ret = gpiochip_remove(&msm_gpio.gpio_chip);
0cc2fc1f GB	380
	381	if (ret < 0)
	382	return ret;
	383
6845664a	384	irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
0cc2fc1f GB	385
	386	return 0;
	387	}
	388
	389	static struct platform_driver msm_gpio_driver = {
	390	.probe = msm_gpio_probe,
8283c4ff	391	.remove = msm_gpio_remove,
0cc2fc1f GB	392	.driver = {
	393	.name = "msmgpio",
	394	.owner = THIS_MODULE,
	395	},
	396	};
	397
	398	static struct platform_device msm_device_gpio = {
	399	.name = "msmgpio",
	400	.id = -1,
	401	};
	402
	403	static int __init msm_gpio_init(void)
	404	{
	405	int rc;
	406
	407	rc = platform_driver_register(&msm_gpio_driver);
	408	if (!rc) {
	409	rc = platform_device_register(&msm_device_gpio);
	410	if (rc)
	411	platform_driver_unregister(&msm_gpio_driver);
	412	}
	413
	414	return rc;
	415	}
	416
	417	static void __exit msm_gpio_exit(void)
	418	{
	419	platform_device_unregister(&msm_device_gpio);
	420	platform_driver_unregister(&msm_gpio_driver);
	421	}
	422
	423	postcore_initcall(msm_gpio_init);
	424	module_exit(msm_gpio_exit);
	425
	426	MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
	427	MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
	428	MODULE_LICENSE("GPL v2");
	429	MODULE_ALIAS("platform:msmgpio");