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fefe7b09 TP |
1 | /* |
2 | * GPIO driver for Marvell SoCs | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * Andrew Lunn <andrew@lunn.ch> | |
8 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * This driver is a fairly straightforward GPIO driver for the | |
15 | * complete family of Marvell EBU SoC platforms (Orion, Dove, | |
16 | * Kirkwood, Discovery, Armada 370/XP). The only complexity of this | |
17 | * driver is the different register layout that exists between the | |
18 | * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP | |
19 | * platforms (MV78200 from the Discovery family and the Armada | |
20 | * XP). Therefore, this driver handles three variants of the GPIO | |
21 | * block: | |
22 | * - the basic variant, called "orion-gpio", with the simplest | |
23 | * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and | |
24 | * non-SMP Discovery systems | |
25 | * - the mv78200 variant for MV78200 Discovery systems. This variant | |
26 | * turns the edge mask and level mask registers into CPU0 edge | |
27 | * mask/level mask registers, and adds CPU1 edge mask/level mask | |
28 | * registers. | |
29 | * - the armadaxp variant for Armada XP systems. This variant keeps | |
30 | * the normal cause/edge mask/level mask registers when the global | |
31 | * interrupts are used, but adds per-CPU cause/edge mask/level mask | |
32 | * registers n a separate memory area for the per-CPU GPIO | |
33 | * interrupts. | |
34 | */ | |
35 | ||
641d0342 | 36 | #include <linux/err.h> |
fefe7b09 TP |
37 | #include <linux/module.h> |
38 | #include <linux/gpio.h> | |
39 | #include <linux/irq.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/irqdomain.h> | |
42 | #include <linux/io.h> | |
43 | #include <linux/of_irq.h> | |
44 | #include <linux/of_device.h> | |
de88747f | 45 | #include <linux/clk.h> |
fefe7b09 | 46 | #include <linux/pinctrl/consumer.h> |
01ca59f1 | 47 | #include <linux/irqchip/chained_irq.h> |
fefe7b09 TP |
48 | |
49 | /* | |
50 | * GPIO unit register offsets. | |
51 | */ | |
52 | #define GPIO_OUT_OFF 0x0000 | |
53 | #define GPIO_IO_CONF_OFF 0x0004 | |
54 | #define GPIO_BLINK_EN_OFF 0x0008 | |
55 | #define GPIO_IN_POL_OFF 0x000c | |
56 | #define GPIO_DATA_IN_OFF 0x0010 | |
57 | #define GPIO_EDGE_CAUSE_OFF 0x0014 | |
58 | #define GPIO_EDGE_MASK_OFF 0x0018 | |
59 | #define GPIO_LEVEL_MASK_OFF 0x001c | |
60 | ||
61 | /* The MV78200 has per-CPU registers for edge mask and level mask */ | |
62 | #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) | |
63 | #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) | |
64 | ||
65 | /* The Armada XP has per-CPU registers for interrupt cause, interrupt | |
66 | * mask and interrupt level mask. Those are relative to the | |
67 | * percpu_membase. */ | |
68 | #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) | |
69 | #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) | |
70 | #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) | |
71 | ||
72 | #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 | |
73 | #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 | |
74 | #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 | |
75 | ||
76 | #define MVEBU_MAX_GPIO_PER_BANK 32 | |
77 | ||
78 | struct mvebu_gpio_chip { | |
79 | struct gpio_chip chip; | |
80 | spinlock_t lock; | |
81 | void __iomem *membase; | |
82 | void __iomem *percpu_membase; | |
d5359226 | 83 | int irqbase; |
fefe7b09 TP |
84 | struct irq_domain *domain; |
85 | int soc_variant; | |
b5b7b487 TP |
86 | |
87 | /* Used to preserve GPIO registers accross suspend/resume */ | |
88 | u32 out_reg; | |
89 | u32 io_conf_reg; | |
90 | u32 blink_en_reg; | |
91 | u32 in_pol_reg; | |
92 | u32 edge_mask_regs[4]; | |
93 | u32 level_mask_regs[4]; | |
fefe7b09 TP |
94 | }; |
95 | ||
96 | /* | |
97 | * Functions returning addresses of individual registers for a given | |
98 | * GPIO controller. | |
99 | */ | |
100 | static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) | |
101 | { | |
102 | return mvchip->membase + GPIO_OUT_OFF; | |
103 | } | |
104 | ||
e9133760 JL |
105 | static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) |
106 | { | |
107 | return mvchip->membase + GPIO_BLINK_EN_OFF; | |
108 | } | |
109 | ||
fefe7b09 TP |
110 | static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) |
111 | { | |
112 | return mvchip->membase + GPIO_IO_CONF_OFF; | |
113 | } | |
114 | ||
115 | static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) | |
116 | { | |
117 | return mvchip->membase + GPIO_IN_POL_OFF; | |
118 | } | |
119 | ||
120 | static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) | |
121 | { | |
122 | return mvchip->membase + GPIO_DATA_IN_OFF; | |
123 | } | |
124 | ||
125 | static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) | |
126 | { | |
127 | int cpu; | |
128 | ||
f4dcd2d9 | 129 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
130 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
131 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
132 | return mvchip->membase + GPIO_EDGE_CAUSE_OFF; | |
133 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
134 | cpu = smp_processor_id(); | |
135 | return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); | |
136 | default: | |
137 | BUG(); | |
138 | } | |
139 | } | |
140 | ||
141 | static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) | |
142 | { | |
143 | int cpu; | |
144 | ||
f4dcd2d9 | 145 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
146 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
147 | return mvchip->membase + GPIO_EDGE_MASK_OFF; | |
148 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
149 | cpu = smp_processor_id(); | |
150 | return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); | |
151 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
152 | cpu = smp_processor_id(); | |
153 | return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); | |
154 | default: | |
155 | BUG(); | |
156 | } | |
157 | } | |
158 | ||
159 | static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) | |
160 | { | |
161 | int cpu; | |
162 | ||
f4dcd2d9 | 163 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
164 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
165 | return mvchip->membase + GPIO_LEVEL_MASK_OFF; | |
166 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
167 | cpu = smp_processor_id(); | |
168 | return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); | |
169 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
170 | cpu = smp_processor_id(); | |
171 | return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); | |
172 | default: | |
173 | BUG(); | |
174 | } | |
175 | } | |
176 | ||
177 | /* | |
178 | * Functions implementing the gpio_chip methods | |
179 | */ | |
180 | ||
3764bdde | 181 | static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin) |
fefe7b09 TP |
182 | { |
183 | return pinctrl_request_gpio(chip->base + pin); | |
184 | } | |
185 | ||
3764bdde | 186 | static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin) |
fefe7b09 TP |
187 | { |
188 | pinctrl_free_gpio(chip->base + pin); | |
189 | } | |
190 | ||
191 | static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) | |
192 | { | |
193 | struct mvebu_gpio_chip *mvchip = | |
194 | container_of(chip, struct mvebu_gpio_chip, chip); | |
195 | unsigned long flags; | |
196 | u32 u; | |
197 | ||
198 | spin_lock_irqsave(&mvchip->lock, flags); | |
199 | u = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
200 | if (value) | |
201 | u |= 1 << pin; | |
202 | else | |
203 | u &= ~(1 << pin); | |
204 | writel_relaxed(u, mvebu_gpioreg_out(mvchip)); | |
205 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
206 | } | |
207 | ||
208 | static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) | |
209 | { | |
210 | struct mvebu_gpio_chip *mvchip = | |
211 | container_of(chip, struct mvebu_gpio_chip, chip); | |
212 | u32 u; | |
213 | ||
214 | if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { | |
215 | u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ | |
216 | readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
217 | } else { | |
218 | u = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
219 | } | |
220 | ||
221 | return (u >> pin) & 1; | |
222 | } | |
223 | ||
e9133760 JL |
224 | static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) |
225 | { | |
226 | struct mvebu_gpio_chip *mvchip = | |
227 | container_of(chip, struct mvebu_gpio_chip, chip); | |
228 | unsigned long flags; | |
229 | u32 u; | |
230 | ||
231 | spin_lock_irqsave(&mvchip->lock, flags); | |
232 | u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); | |
233 | if (value) | |
234 | u |= 1 << pin; | |
235 | else | |
236 | u &= ~(1 << pin); | |
237 | writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); | |
238 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
239 | } | |
240 | ||
fefe7b09 TP |
241 | static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) |
242 | { | |
243 | struct mvebu_gpio_chip *mvchip = | |
244 | container_of(chip, struct mvebu_gpio_chip, chip); | |
245 | unsigned long flags; | |
246 | int ret; | |
247 | u32 u; | |
248 | ||
249 | /* Check with the pinctrl driver whether this pin is usable as | |
250 | * an input GPIO */ | |
251 | ret = pinctrl_gpio_direction_input(chip->base + pin); | |
252 | if (ret) | |
253 | return ret; | |
254 | ||
255 | spin_lock_irqsave(&mvchip->lock, flags); | |
256 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
257 | u |= 1 << pin; | |
258 | writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); | |
259 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, | |
265 | int value) | |
266 | { | |
267 | struct mvebu_gpio_chip *mvchip = | |
268 | container_of(chip, struct mvebu_gpio_chip, chip); | |
269 | unsigned long flags; | |
270 | int ret; | |
271 | u32 u; | |
272 | ||
273 | /* Check with the pinctrl driver whether this pin is usable as | |
274 | * an output GPIO */ | |
275 | ret = pinctrl_gpio_direction_output(chip->base + pin); | |
276 | if (ret) | |
277 | return ret; | |
278 | ||
e9133760 | 279 | mvebu_gpio_blink(chip, pin, 0); |
c57d75c0 TP |
280 | mvebu_gpio_set(chip, pin, value); |
281 | ||
fefe7b09 TP |
282 | spin_lock_irqsave(&mvchip->lock, flags); |
283 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
284 | u &= ~(1 << pin); | |
285 | writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); | |
286 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) | |
292 | { | |
293 | struct mvebu_gpio_chip *mvchip = | |
294 | container_of(chip, struct mvebu_gpio_chip, chip); | |
295 | return irq_create_mapping(mvchip->domain, pin); | |
296 | } | |
297 | ||
298 | /* | |
299 | * Functions implementing the irq_chip methods | |
300 | */ | |
301 | static void mvebu_gpio_irq_ack(struct irq_data *d) | |
302 | { | |
303 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
304 | struct mvebu_gpio_chip *mvchip = gc->private; | |
305 | u32 mask = ~(1 << (d->irq - gc->irq_base)); | |
306 | ||
307 | irq_gc_lock(gc); | |
308 | writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); | |
309 | irq_gc_unlock(gc); | |
310 | } | |
311 | ||
312 | static void mvebu_gpio_edge_irq_mask(struct irq_data *d) | |
313 | { | |
314 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
315 | struct mvebu_gpio_chip *mvchip = gc->private; | |
316 | u32 mask = 1 << (d->irq - gc->irq_base); | |
317 | ||
318 | irq_gc_lock(gc); | |
319 | gc->mask_cache &= ~mask; | |
320 | writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); | |
321 | irq_gc_unlock(gc); | |
322 | } | |
323 | ||
324 | static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) | |
325 | { | |
326 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
327 | struct mvebu_gpio_chip *mvchip = gc->private; | |
328 | u32 mask = 1 << (d->irq - gc->irq_base); | |
329 | ||
330 | irq_gc_lock(gc); | |
331 | gc->mask_cache |= mask; | |
332 | writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); | |
333 | irq_gc_unlock(gc); | |
334 | } | |
335 | ||
336 | static void mvebu_gpio_level_irq_mask(struct irq_data *d) | |
337 | { | |
338 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
339 | struct mvebu_gpio_chip *mvchip = gc->private; | |
340 | u32 mask = 1 << (d->irq - gc->irq_base); | |
341 | ||
342 | irq_gc_lock(gc); | |
343 | gc->mask_cache &= ~mask; | |
344 | writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); | |
345 | irq_gc_unlock(gc); | |
346 | } | |
347 | ||
348 | static void mvebu_gpio_level_irq_unmask(struct irq_data *d) | |
349 | { | |
350 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
351 | struct mvebu_gpio_chip *mvchip = gc->private; | |
352 | u32 mask = 1 << (d->irq - gc->irq_base); | |
353 | ||
354 | irq_gc_lock(gc); | |
355 | gc->mask_cache |= mask; | |
356 | writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); | |
357 | irq_gc_unlock(gc); | |
358 | } | |
359 | ||
360 | /***************************************************************************** | |
361 | * MVEBU GPIO IRQ | |
362 | * | |
363 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same | |
364 | * value of the line or the opposite value. | |
365 | * | |
366 | * Level IRQ handlers: DATA_IN is used directly as cause register. | |
367 | * Interrupt are masked by LEVEL_MASK registers. | |
368 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. | |
369 | * Interrupt are masked by EDGE_MASK registers. | |
370 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps | |
371 | * the polarity to catch the next line transaction. | |
372 | * This is a race condition that might not perfectly | |
373 | * work on some use cases. | |
374 | * | |
375 | * Every eight GPIO lines are grouped (OR'ed) before going up to main | |
376 | * cause register. | |
377 | * | |
378 | * EDGE cause mask | |
379 | * data-in /--------| |-----| |----\ | |
380 | * -----| |----- ---- to main cause reg | |
381 | * X \----------------| |----/ | |
382 | * polarity LEVEL mask | |
383 | * | |
384 | ****************************************************************************/ | |
385 | ||
386 | static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
387 | { | |
388 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
389 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
390 | struct mvebu_gpio_chip *mvchip = gc->private; | |
391 | int pin; | |
392 | u32 u; | |
393 | ||
394 | pin = d->hwirq; | |
395 | ||
396 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); | |
397 | if (!u) { | |
398 | return -EINVAL; | |
399 | } | |
400 | ||
401 | type &= IRQ_TYPE_SENSE_MASK; | |
402 | if (type == IRQ_TYPE_NONE) | |
403 | return -EINVAL; | |
404 | ||
405 | /* Check if we need to change chip and handler */ | |
406 | if (!(ct->type & type)) | |
407 | if (irq_setup_alt_chip(d, type)) | |
408 | return -EINVAL; | |
409 | ||
410 | /* | |
411 | * Configure interrupt polarity. | |
412 | */ | |
f4dcd2d9 | 413 | switch (type) { |
fefe7b09 TP |
414 | case IRQ_TYPE_EDGE_RISING: |
415 | case IRQ_TYPE_LEVEL_HIGH: | |
416 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
417 | u &= ~(1 << pin); | |
418 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); | |
7cf8c9f7 | 419 | break; |
fefe7b09 TP |
420 | case IRQ_TYPE_EDGE_FALLING: |
421 | case IRQ_TYPE_LEVEL_LOW: | |
422 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
423 | u |= 1 << pin; | |
424 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); | |
7cf8c9f7 | 425 | break; |
fefe7b09 TP |
426 | case IRQ_TYPE_EDGE_BOTH: { |
427 | u32 v; | |
428 | ||
429 | v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ | |
430 | readl_relaxed(mvebu_gpioreg_data_in(mvchip)); | |
431 | ||
432 | /* | |
433 | * set initial polarity based on current input level | |
434 | */ | |
435 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
436 | if (v & (1 << pin)) | |
437 | u |= 1 << pin; /* falling */ | |
438 | else | |
439 | u &= ~(1 << pin); /* rising */ | |
440 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); | |
7cf8c9f7 | 441 | break; |
fefe7b09 TP |
442 | } |
443 | } | |
444 | return 0; | |
445 | } | |
446 | ||
447 | static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
448 | { | |
449 | struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq); | |
01ca59f1 | 450 | struct irq_chip *chip = irq_desc_get_chip(desc); |
fefe7b09 TP |
451 | u32 cause, type; |
452 | int i; | |
453 | ||
454 | if (mvchip == NULL) | |
455 | return; | |
456 | ||
01ca59f1 TP |
457 | chained_irq_enter(chip, desc); |
458 | ||
fefe7b09 TP |
459 | cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & |
460 | readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); | |
461 | cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & | |
462 | readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); | |
463 | ||
464 | for (i = 0; i < mvchip->chip.ngpio; i++) { | |
465 | int irq; | |
466 | ||
467 | irq = mvchip->irqbase + i; | |
468 | ||
469 | if (!(cause & (1 << i))) | |
470 | continue; | |
471 | ||
fb90c22a | 472 | type = irq_get_trigger_type(irq); |
fefe7b09 TP |
473 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
474 | /* Swap polarity (race with GPIO line) */ | |
475 | u32 polarity; | |
476 | ||
477 | polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
478 | polarity ^= 1 << i; | |
479 | writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); | |
480 | } | |
01ca59f1 | 481 | |
fefe7b09 TP |
482 | generic_handle_irq(irq); |
483 | } | |
01ca59f1 TP |
484 | |
485 | chained_irq_exit(chip, desc); | |
fefe7b09 TP |
486 | } |
487 | ||
a4ba5e1b SG |
488 | #ifdef CONFIG_DEBUG_FS |
489 | #include <linux/seq_file.h> | |
490 | ||
491 | static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
492 | { | |
493 | struct mvebu_gpio_chip *mvchip = | |
494 | container_of(chip, struct mvebu_gpio_chip, chip); | |
495 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; | |
496 | int i; | |
497 | ||
498 | out = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
499 | io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
500 | blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); | |
501 | in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
502 | data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); | |
503 | cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); | |
504 | edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); | |
505 | lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); | |
506 | ||
507 | for (i = 0; i < chip->ngpio; i++) { | |
508 | const char *label; | |
509 | u32 msk; | |
510 | bool is_out; | |
511 | ||
512 | label = gpiochip_is_requested(chip, i); | |
513 | if (!label) | |
514 | continue; | |
515 | ||
516 | msk = 1 << i; | |
517 | is_out = !(io_conf & msk); | |
518 | ||
519 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); | |
520 | ||
521 | if (is_out) { | |
522 | seq_printf(s, " out %s %s\n", | |
523 | out & msk ? "hi" : "lo", | |
524 | blink & msk ? "(blink )" : ""); | |
525 | continue; | |
526 | } | |
527 | ||
528 | seq_printf(s, " in %s (act %s) - IRQ", | |
529 | (data_in ^ in_pol) & msk ? "hi" : "lo", | |
530 | in_pol & msk ? "lo" : "hi"); | |
531 | if (!((edg_msk | lvl_msk) & msk)) { | |
532 | seq_printf(s, " disabled\n"); | |
533 | continue; | |
534 | } | |
535 | if (edg_msk & msk) | |
536 | seq_printf(s, " edge "); | |
537 | if (lvl_msk & msk) | |
538 | seq_printf(s, " level"); | |
539 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); | |
540 | } | |
541 | } | |
542 | #else | |
543 | #define mvebu_gpio_dbg_show NULL | |
544 | #endif | |
545 | ||
271b17b6 | 546 | static const struct of_device_id mvebu_gpio_of_match[] = { |
fefe7b09 TP |
547 | { |
548 | .compatible = "marvell,orion-gpio", | |
f4dcd2d9 | 549 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
fefe7b09 TP |
550 | }, |
551 | { | |
552 | .compatible = "marvell,mv78200-gpio", | |
f4dcd2d9 | 553 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, |
fefe7b09 TP |
554 | }, |
555 | { | |
556 | .compatible = "marvell,armadaxp-gpio", | |
f4dcd2d9 | 557 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, |
fefe7b09 TP |
558 | }, |
559 | { | |
560 | /* sentinel */ | |
561 | }, | |
562 | }; | |
563 | MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); | |
564 | ||
b5b7b487 TP |
565 | static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) |
566 | { | |
567 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
568 | int i; | |
569 | ||
570 | mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); | |
571 | mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); | |
572 | mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); | |
573 | mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); | |
574 | ||
575 | switch (mvchip->soc_variant) { | |
576 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
577 | mvchip->edge_mask_regs[0] = | |
578 | readl(mvchip->membase + GPIO_EDGE_MASK_OFF); | |
579 | mvchip->level_mask_regs[0] = | |
580 | readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
581 | break; | |
582 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
583 | for (i = 0; i < 2; i++) { | |
584 | mvchip->edge_mask_regs[i] = | |
585 | readl(mvchip->membase + | |
586 | GPIO_EDGE_MASK_MV78200_OFF(i)); | |
587 | mvchip->level_mask_regs[i] = | |
588 | readl(mvchip->membase + | |
589 | GPIO_LEVEL_MASK_MV78200_OFF(i)); | |
590 | } | |
591 | break; | |
592 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
593 | for (i = 0; i < 4; i++) { | |
594 | mvchip->edge_mask_regs[i] = | |
595 | readl(mvchip->membase + | |
596 | GPIO_EDGE_MASK_ARMADAXP_OFF(i)); | |
597 | mvchip->level_mask_regs[i] = | |
598 | readl(mvchip->membase + | |
599 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); | |
600 | } | |
601 | break; | |
602 | default: | |
603 | BUG(); | |
604 | } | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static int mvebu_gpio_resume(struct platform_device *pdev) | |
610 | { | |
611 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
612 | int i; | |
613 | ||
614 | writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); | |
615 | writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); | |
616 | writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); | |
617 | writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); | |
618 | ||
619 | switch (mvchip->soc_variant) { | |
620 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
621 | writel(mvchip->edge_mask_regs[0], | |
622 | mvchip->membase + GPIO_EDGE_MASK_OFF); | |
623 | writel(mvchip->level_mask_regs[0], | |
624 | mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
625 | break; | |
626 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
627 | for (i = 0; i < 2; i++) { | |
628 | writel(mvchip->edge_mask_regs[i], | |
629 | mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); | |
630 | writel(mvchip->level_mask_regs[i], | |
631 | mvchip->membase + | |
632 | GPIO_LEVEL_MASK_MV78200_OFF(i)); | |
633 | } | |
634 | break; | |
635 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
636 | for (i = 0; i < 4; i++) { | |
637 | writel(mvchip->edge_mask_regs[i], | |
638 | mvchip->membase + | |
639 | GPIO_EDGE_MASK_ARMADAXP_OFF(i)); | |
640 | writel(mvchip->level_mask_regs[i], | |
641 | mvchip->membase + | |
642 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); | |
643 | } | |
644 | break; | |
645 | default: | |
646 | BUG(); | |
647 | } | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
3836309d | 652 | static int mvebu_gpio_probe(struct platform_device *pdev) |
fefe7b09 TP |
653 | { |
654 | struct mvebu_gpio_chip *mvchip; | |
655 | const struct of_device_id *match; | |
656 | struct device_node *np = pdev->dev.of_node; | |
657 | struct resource *res; | |
658 | struct irq_chip_generic *gc; | |
659 | struct irq_chip_type *ct; | |
de88747f | 660 | struct clk *clk; |
fefe7b09 TP |
661 | unsigned int ngpios; |
662 | int soc_variant; | |
663 | int i, cpu, id; | |
664 | ||
665 | match = of_match_device(mvebu_gpio_of_match, &pdev->dev); | |
666 | if (match) | |
667 | soc_variant = (int) match->data; | |
668 | else | |
669 | soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; | |
670 | ||
fefe7b09 | 671 | mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); |
6c8365f6 | 672 | if (!mvchip) |
fefe7b09 | 673 | return -ENOMEM; |
fefe7b09 | 674 | |
b5b7b487 TP |
675 | platform_set_drvdata(pdev, mvchip); |
676 | ||
fefe7b09 TP |
677 | if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { |
678 | dev_err(&pdev->dev, "Missing ngpios OF property\n"); | |
679 | return -ENODEV; | |
680 | } | |
681 | ||
682 | id = of_alias_get_id(pdev->dev.of_node, "gpio"); | |
683 | if (id < 0) { | |
684 | dev_err(&pdev->dev, "Couldn't get OF id\n"); | |
685 | return id; | |
686 | } | |
687 | ||
de88747f AL |
688 | clk = devm_clk_get(&pdev->dev, NULL); |
689 | /* Not all SoCs require a clock.*/ | |
690 | if (!IS_ERR(clk)) | |
691 | clk_prepare_enable(clk); | |
692 | ||
fefe7b09 TP |
693 | mvchip->soc_variant = soc_variant; |
694 | mvchip->chip.label = dev_name(&pdev->dev); | |
695 | mvchip->chip.dev = &pdev->dev; | |
696 | mvchip->chip.request = mvebu_gpio_request; | |
3764bdde | 697 | mvchip->chip.free = mvebu_gpio_free; |
fefe7b09 TP |
698 | mvchip->chip.direction_input = mvebu_gpio_direction_input; |
699 | mvchip->chip.get = mvebu_gpio_get; | |
700 | mvchip->chip.direction_output = mvebu_gpio_direction_output; | |
701 | mvchip->chip.set = mvebu_gpio_set; | |
702 | mvchip->chip.to_irq = mvebu_gpio_to_irq; | |
703 | mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; | |
704 | mvchip->chip.ngpio = ngpios; | |
9fb1f39e | 705 | mvchip->chip.can_sleep = false; |
fefe7b09 | 706 | mvchip->chip.of_node = np; |
a4ba5e1b | 707 | mvchip->chip.dbg_show = mvebu_gpio_dbg_show; |
fefe7b09 TP |
708 | |
709 | spin_lock_init(&mvchip->lock); | |
08a67a58 | 710 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
641d0342 | 711 | mvchip->membase = devm_ioremap_resource(&pdev->dev, res); |
422d26b6 | 712 | if (IS_ERR(mvchip->membase)) |
641d0342 | 713 | return PTR_ERR(mvchip->membase); |
fefe7b09 TP |
714 | |
715 | /* The Armada XP has a second range of registers for the | |
716 | * per-CPU registers */ | |
717 | if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { | |
718 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
641d0342 TR |
719 | mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, |
720 | res); | |
f4dcd2d9 | 721 | if (IS_ERR(mvchip->percpu_membase)) |
641d0342 | 722 | return PTR_ERR(mvchip->percpu_membase); |
fefe7b09 TP |
723 | } |
724 | ||
725 | /* | |
726 | * Mask and clear GPIO interrupts. | |
727 | */ | |
f4dcd2d9 | 728 | switch (soc_variant) { |
fefe7b09 TP |
729 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
730 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
731 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); | |
732 | writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
733 | break; | |
734 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
735 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
736 | for (cpu = 0; cpu < 2; cpu++) { | |
737 | writel_relaxed(0, mvchip->membase + | |
738 | GPIO_EDGE_MASK_MV78200_OFF(cpu)); | |
739 | writel_relaxed(0, mvchip->membase + | |
740 | GPIO_LEVEL_MASK_MV78200_OFF(cpu)); | |
741 | } | |
742 | break; | |
743 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
744 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
745 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); | |
746 | writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
747 | for (cpu = 0; cpu < 4; cpu++) { | |
748 | writel_relaxed(0, mvchip->percpu_membase + | |
749 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); | |
750 | writel_relaxed(0, mvchip->percpu_membase + | |
751 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); | |
752 | writel_relaxed(0, mvchip->percpu_membase + | |
753 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); | |
754 | } | |
755 | break; | |
756 | default: | |
757 | BUG(); | |
758 | } | |
759 | ||
760 | gpiochip_add(&mvchip->chip); | |
761 | ||
762 | /* Some gpio controllers do not provide irq support */ | |
763 | if (!of_irq_count(np)) | |
764 | return 0; | |
765 | ||
766 | /* Setup the interrupt handlers. Each chip can have up to 4 | |
767 | * interrupt handlers, with each handler dealing with 8 GPIO | |
768 | * pins. */ | |
769 | for (i = 0; i < 4; i++) { | |
770 | int irq; | |
771 | irq = platform_get_irq(pdev, i); | |
772 | if (irq < 0) | |
773 | continue; | |
774 | irq_set_handler_data(irq, mvchip); | |
775 | irq_set_chained_handler(irq, mvebu_gpio_irq_handler); | |
776 | } | |
777 | ||
778 | mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); | |
779 | if (mvchip->irqbase < 0) { | |
780 | dev_err(&pdev->dev, "no irqs\n"); | |
3509c6fa | 781 | return mvchip->irqbase; |
fefe7b09 TP |
782 | } |
783 | ||
784 | gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, | |
785 | mvchip->membase, handle_level_irq); | |
f4dcd2d9 | 786 | if (!gc) { |
fefe7b09 | 787 | dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); |
fefe7b09 TP |
788 | return -ENOMEM; |
789 | } | |
790 | ||
791 | gc->private = mvchip; | |
792 | ct = &gc->chip_types[0]; | |
793 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
794 | ct->chip.irq_mask = mvebu_gpio_level_irq_mask; | |
795 | ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; | |
796 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
797 | ct->chip.name = mvchip->chip.label; | |
798 | ||
799 | ct = &gc->chip_types[1]; | |
800 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
801 | ct->chip.irq_ack = mvebu_gpio_irq_ack; | |
802 | ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; | |
803 | ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; | |
804 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
805 | ct->handler = handle_edge_irq; | |
806 | ct->chip.name = mvchip->chip.label; | |
807 | ||
8fcff5f1 | 808 | irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, |
fefe7b09 TP |
809 | IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); |
810 | ||
811 | /* Setup irq domain on top of the generic chip. */ | |
ce931f57 LW |
812 | mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio, |
813 | mvchip->irqbase, | |
fefe7b09 TP |
814 | &irq_domain_simple_ops, |
815 | mvchip); | |
816 | if (!mvchip->domain) { | |
817 | dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", | |
818 | mvchip->chip.label); | |
819 | irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, | |
820 | IRQ_LEVEL | IRQ_NOPROBE); | |
821 | kfree(gc); | |
fefe7b09 TP |
822 | return -ENODEV; |
823 | } | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
828 | static struct platform_driver mvebu_gpio_driver = { | |
829 | .driver = { | |
830 | .name = "mvebu-gpio", | |
fefe7b09 TP |
831 | .of_match_table = mvebu_gpio_of_match, |
832 | }, | |
833 | .probe = mvebu_gpio_probe, | |
b5b7b487 TP |
834 | .suspend = mvebu_gpio_suspend, |
835 | .resume = mvebu_gpio_resume, | |
fefe7b09 | 836 | }; |
dd640039 | 837 | module_platform_driver(mvebu_gpio_driver); |