Commit | Line | Data |
---|---|---|
07bd1a6c JB |
1 | /* |
2 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * Based on code from Freescale, | |
e24798e6 | 6 | * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
07bd1a6c JB |
7 | * |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | */ | |
21 | ||
18f92b19 | 22 | #include <linux/err.h> |
07bd1a6c | 23 | #include <linux/init.h> |
a3484ffd | 24 | #include <linux/interrupt.h> |
07bd1a6c JB |
25 | #include <linux/io.h> |
26 | #include <linux/irq.h> | |
1ab7ef15 | 27 | #include <linux/irqdomain.h> |
de88cbb7 | 28 | #include <linux/irqchip/chained_irq.h> |
07bd1a6c | 29 | #include <linux/gpio.h> |
b78d8e59 SG |
30 | #include <linux/platform_device.h> |
31 | #include <linux/slab.h> | |
2ce420da | 32 | #include <linux/basic_mmio_gpio.h> |
8937cb60 SG |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
bb207ef1 | 35 | #include <linux/module.h> |
07bd1a6c JB |
36 | #include <asm-generic/bug.h> |
37 | ||
e7fc6ae7 SG |
38 | enum mxc_gpio_hwtype { |
39 | IMX1_GPIO, /* runs on i.mx1 */ | |
40 | IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ | |
aeb27748 BT |
41 | IMX31_GPIO, /* runs on i.mx31 */ |
42 | IMX35_GPIO, /* runs on all other i.mx */ | |
e7fc6ae7 SG |
43 | }; |
44 | ||
45 | /* device type dependent stuff */ | |
46 | struct mxc_gpio_hwdata { | |
47 | unsigned dr_reg; | |
48 | unsigned gdir_reg; | |
49 | unsigned psr_reg; | |
50 | unsigned icr1_reg; | |
51 | unsigned icr2_reg; | |
52 | unsigned imr_reg; | |
53 | unsigned isr_reg; | |
aeb27748 | 54 | int edge_sel_reg; |
e7fc6ae7 SG |
55 | unsigned low_level; |
56 | unsigned high_level; | |
57 | unsigned rise_edge; | |
58 | unsigned fall_edge; | |
59 | }; | |
60 | ||
b78d8e59 SG |
61 | struct mxc_gpio_port { |
62 | struct list_head node; | |
63 | void __iomem *base; | |
64 | int irq; | |
65 | int irq_high; | |
1ab7ef15 | 66 | struct irq_domain *domain; |
2ce420da | 67 | struct bgpio_chip bgc; |
b78d8e59 | 68 | u32 both_edges; |
b78d8e59 SG |
69 | }; |
70 | ||
e7fc6ae7 SG |
71 | static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { |
72 | .dr_reg = 0x1c, | |
73 | .gdir_reg = 0x00, | |
74 | .psr_reg = 0x24, | |
75 | .icr1_reg = 0x28, | |
76 | .icr2_reg = 0x2c, | |
77 | .imr_reg = 0x30, | |
78 | .isr_reg = 0x34, | |
aeb27748 | 79 | .edge_sel_reg = -EINVAL, |
e7fc6ae7 SG |
80 | .low_level = 0x03, |
81 | .high_level = 0x02, | |
82 | .rise_edge = 0x00, | |
83 | .fall_edge = 0x01, | |
84 | }; | |
85 | ||
86 | static struct mxc_gpio_hwdata imx31_gpio_hwdata = { | |
87 | .dr_reg = 0x00, | |
88 | .gdir_reg = 0x04, | |
89 | .psr_reg = 0x08, | |
90 | .icr1_reg = 0x0c, | |
91 | .icr2_reg = 0x10, | |
92 | .imr_reg = 0x14, | |
93 | .isr_reg = 0x18, | |
aeb27748 BT |
94 | .edge_sel_reg = -EINVAL, |
95 | .low_level = 0x00, | |
96 | .high_level = 0x01, | |
97 | .rise_edge = 0x02, | |
98 | .fall_edge = 0x03, | |
99 | }; | |
100 | ||
101 | static struct mxc_gpio_hwdata imx35_gpio_hwdata = { | |
102 | .dr_reg = 0x00, | |
103 | .gdir_reg = 0x04, | |
104 | .psr_reg = 0x08, | |
105 | .icr1_reg = 0x0c, | |
106 | .icr2_reg = 0x10, | |
107 | .imr_reg = 0x14, | |
108 | .isr_reg = 0x18, | |
109 | .edge_sel_reg = 0x1c, | |
e7fc6ae7 SG |
110 | .low_level = 0x00, |
111 | .high_level = 0x01, | |
112 | .rise_edge = 0x02, | |
113 | .fall_edge = 0x03, | |
114 | }; | |
115 | ||
116 | static enum mxc_gpio_hwtype mxc_gpio_hwtype; | |
117 | static struct mxc_gpio_hwdata *mxc_gpio_hwdata; | |
118 | ||
119 | #define GPIO_DR (mxc_gpio_hwdata->dr_reg) | |
120 | #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) | |
121 | #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) | |
122 | #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) | |
123 | #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) | |
124 | #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) | |
125 | #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) | |
aeb27748 | 126 | #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) |
e7fc6ae7 SG |
127 | |
128 | #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) | |
129 | #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) | |
130 | #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) | |
131 | #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) | |
aeb27748 | 132 | #define GPIO_INT_BOTH_EDGES 0x4 |
e7fc6ae7 | 133 | |
f4f79d40 | 134 | static const struct platform_device_id mxc_gpio_devtype[] = { |
e7fc6ae7 SG |
135 | { |
136 | .name = "imx1-gpio", | |
137 | .driver_data = IMX1_GPIO, | |
138 | }, { | |
139 | .name = "imx21-gpio", | |
140 | .driver_data = IMX21_GPIO, | |
141 | }, { | |
142 | .name = "imx31-gpio", | |
143 | .driver_data = IMX31_GPIO, | |
aeb27748 BT |
144 | }, { |
145 | .name = "imx35-gpio", | |
146 | .driver_data = IMX35_GPIO, | |
e7fc6ae7 SG |
147 | }, { |
148 | /* sentinel */ | |
149 | } | |
150 | }; | |
151 | ||
8937cb60 SG |
152 | static const struct of_device_id mxc_gpio_dt_ids[] = { |
153 | { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, | |
154 | { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, | |
155 | { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, | |
aeb27748 | 156 | { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, |
8937cb60 SG |
157 | { /* sentinel */ } |
158 | }; | |
159 | ||
b78d8e59 SG |
160 | /* |
161 | * MX2 has one interrupt *for all* gpio ports. The list is used | |
162 | * to save the references to all ports, so that mx2_gpio_irq_handler | |
163 | * can walk through all interrupt status registers. | |
164 | */ | |
165 | static LIST_HEAD(mxc_gpio_ports); | |
07bd1a6c JB |
166 | |
167 | /* Note: This driver assumes 32 GPIOs are handled in one register */ | |
168 | ||
4d93579f | 169 | static int gpio_set_irq_type(struct irq_data *d, u32 type) |
07bd1a6c | 170 | { |
e4ea9333 SG |
171 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
172 | struct mxc_gpio_port *port = gc->private; | |
07bd1a6c | 173 | u32 bit, val; |
1ab7ef15 SG |
174 | u32 gpio_idx = d->hwirq; |
175 | u32 gpio = port->bgc.gc.base + gpio_idx; | |
07bd1a6c JB |
176 | int edge; |
177 | void __iomem *reg = port->base; | |
178 | ||
1ab7ef15 | 179 | port->both_edges &= ~(1 << gpio_idx); |
07bd1a6c | 180 | switch (type) { |
6cab4860 | 181 | case IRQ_TYPE_EDGE_RISING: |
07bd1a6c JB |
182 | edge = GPIO_INT_RISE_EDGE; |
183 | break; | |
6cab4860 | 184 | case IRQ_TYPE_EDGE_FALLING: |
07bd1a6c JB |
185 | edge = GPIO_INT_FALL_EDGE; |
186 | break; | |
910862ec | 187 | case IRQ_TYPE_EDGE_BOTH: |
aeb27748 BT |
188 | if (GPIO_EDGE_SEL >= 0) { |
189 | edge = GPIO_INT_BOTH_EDGES; | |
910862ec | 190 | } else { |
aeb27748 BT |
191 | val = gpio_get_value(gpio); |
192 | if (val) { | |
193 | edge = GPIO_INT_LOW_LEV; | |
194 | pr_debug("mxc: set GPIO %d to low trigger\n", gpio); | |
195 | } else { | |
196 | edge = GPIO_INT_HIGH_LEV; | |
197 | pr_debug("mxc: set GPIO %d to high trigger\n", gpio); | |
198 | } | |
f948ad07 | 199 | port->both_edges |= 1 << gpio_idx; |
910862ec | 200 | } |
910862ec | 201 | break; |
6cab4860 | 202 | case IRQ_TYPE_LEVEL_LOW: |
07bd1a6c JB |
203 | edge = GPIO_INT_LOW_LEV; |
204 | break; | |
6cab4860 | 205 | case IRQ_TYPE_LEVEL_HIGH: |
07bd1a6c JB |
206 | edge = GPIO_INT_HIGH_LEV; |
207 | break; | |
910862ec | 208 | default: |
07bd1a6c JB |
209 | return -EINVAL; |
210 | } | |
211 | ||
aeb27748 BT |
212 | if (GPIO_EDGE_SEL >= 0) { |
213 | val = readl(port->base + GPIO_EDGE_SEL); | |
214 | if (edge == GPIO_INT_BOTH_EDGES) | |
f948ad07 | 215 | writel(val | (1 << gpio_idx), |
aeb27748 BT |
216 | port->base + GPIO_EDGE_SEL); |
217 | else | |
f948ad07 | 218 | writel(val & ~(1 << gpio_idx), |
aeb27748 BT |
219 | port->base + GPIO_EDGE_SEL); |
220 | } | |
221 | ||
222 | if (edge != GPIO_INT_BOTH_EDGES) { | |
f948ad07 LT |
223 | reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ |
224 | bit = gpio_idx & 0xf; | |
aeb27748 BT |
225 | val = readl(reg) & ~(0x3 << (bit << 1)); |
226 | writel(val | (edge << (bit << 1)), reg); | |
227 | } | |
228 | ||
1ab7ef15 | 229 | writel(1 << gpio_idx, port->base + GPIO_ISR); |
07bd1a6c JB |
230 | |
231 | return 0; | |
232 | } | |
233 | ||
910862ec GL |
234 | static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) |
235 | { | |
236 | void __iomem *reg = port->base; | |
237 | u32 bit, val; | |
238 | int edge; | |
239 | ||
240 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ | |
241 | bit = gpio & 0xf; | |
b78d8e59 | 242 | val = readl(reg); |
910862ec GL |
243 | edge = (val >> (bit << 1)) & 3; |
244 | val &= ~(0x3 << (bit << 1)); | |
3d40f7fe | 245 | if (edge == GPIO_INT_HIGH_LEV) { |
910862ec GL |
246 | edge = GPIO_INT_LOW_LEV; |
247 | pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); | |
3d40f7fe | 248 | } else if (edge == GPIO_INT_LOW_LEV) { |
910862ec GL |
249 | edge = GPIO_INT_HIGH_LEV; |
250 | pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); | |
3d40f7fe | 251 | } else { |
910862ec GL |
252 | pr_err("mxc: invalid configuration for GPIO %d: %x\n", |
253 | gpio, edge); | |
254 | return; | |
255 | } | |
b78d8e59 | 256 | writel(val | (edge << (bit << 1)), reg); |
910862ec GL |
257 | } |
258 | ||
3621f188 | 259 | /* handle 32 interrupts in one status register */ |
07bd1a6c JB |
260 | static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) |
261 | { | |
3621f188 UKK |
262 | while (irq_stat != 0) { |
263 | int irqoffset = fls(irq_stat) - 1; | |
07bd1a6c | 264 | |
3621f188 UKK |
265 | if (port->both_edges & (1 << irqoffset)) |
266 | mxc_flip_edge(port, irqoffset); | |
910862ec | 267 | |
1ab7ef15 | 268 | generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); |
910862ec | 269 | |
3621f188 | 270 | irq_stat &= ~(1 << irqoffset); |
07bd1a6c JB |
271 | } |
272 | } | |
273 | ||
cfca8b53 | 274 | /* MX1 and MX3 has one interrupt *per* gpio port */ |
07bd1a6c JB |
275 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
276 | { | |
277 | u32 irq_stat; | |
476f8b4c JL |
278 | struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); |
279 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0e44b6ec SG |
280 | |
281 | chained_irq_enter(chip, desc); | |
07bd1a6c | 282 | |
b78d8e59 | 283 | irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); |
e2c97e7f | 284 | |
07bd1a6c | 285 | mxc_gpio_irq_handler(port, irq_stat); |
0e44b6ec SG |
286 | |
287 | chained_irq_exit(chip, desc); | |
07bd1a6c | 288 | } |
07bd1a6c | 289 | |
07bd1a6c JB |
290 | /* MX2 has one interrupt *for all* gpio ports */ |
291 | static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |
292 | { | |
07bd1a6c | 293 | u32 irq_msk, irq_stat; |
b78d8e59 | 294 | struct mxc_gpio_port *port; |
476f8b4c | 295 | struct irq_chip *chip = irq_desc_get_chip(desc); |
c0e811d9 UKK |
296 | |
297 | chained_irq_enter(chip, desc); | |
07bd1a6c JB |
298 | |
299 | /* walk through all interrupt status registers */ | |
b78d8e59 SG |
300 | list_for_each_entry(port, &mxc_gpio_ports, node) { |
301 | irq_msk = readl(port->base + GPIO_IMR); | |
07bd1a6c JB |
302 | if (!irq_msk) |
303 | continue; | |
304 | ||
b78d8e59 | 305 | irq_stat = readl(port->base + GPIO_ISR) & irq_msk; |
07bd1a6c | 306 | if (irq_stat) |
b78d8e59 | 307 | mxc_gpio_irq_handler(port, irq_stat); |
07bd1a6c | 308 | } |
c0e811d9 | 309 | chained_irq_exit(chip, desc); |
07bd1a6c | 310 | } |
07bd1a6c | 311 | |
a3484ffd DN |
312 | /* |
313 | * Set interrupt number "irq" in the GPIO as a wake-up source. | |
314 | * While system is running, all registered GPIO interrupts need to have | |
315 | * wake-up enabled. When system is suspended, only selected GPIO interrupts | |
316 | * need to have wake-up enabled. | |
317 | * @param irq interrupt source number | |
318 | * @param enable enable as wake-up if equal to non-zero | |
319 | * @return This function returns 0 on success. | |
320 | */ | |
4d93579f | 321 | static int gpio_set_wake_irq(struct irq_data *d, u32 enable) |
a3484ffd | 322 | { |
e4ea9333 SG |
323 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
324 | struct mxc_gpio_port *port = gc->private; | |
1ab7ef15 | 325 | u32 gpio_idx = d->hwirq; |
a3484ffd DN |
326 | |
327 | if (enable) { | |
328 | if (port->irq_high && (gpio_idx >= 16)) | |
329 | enable_irq_wake(port->irq_high); | |
330 | else | |
331 | enable_irq_wake(port->irq); | |
332 | } else { | |
333 | if (port->irq_high && (gpio_idx >= 16)) | |
334 | disable_irq_wake(port->irq_high); | |
335 | else | |
336 | disable_irq_wake(port->irq); | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
9e26b0b1 | 342 | static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) |
e4ea9333 SG |
343 | { |
344 | struct irq_chip_generic *gc; | |
345 | struct irq_chip_type *ct; | |
346 | ||
1ab7ef15 | 347 | gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base, |
e4ea9333 | 348 | port->base, handle_level_irq); |
9e26b0b1 PF |
349 | if (!gc) |
350 | return -ENOMEM; | |
e4ea9333 SG |
351 | gc->private = port; |
352 | ||
353 | ct = gc->chip_types; | |
591567a5 | 354 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
e4ea9333 SG |
355 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
356 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
357 | ct->chip.irq_set_type = gpio_set_irq_type; | |
591567a5 | 358 | ct->chip.irq_set_wake = gpio_set_wake_irq; |
952cfbd3 | 359 | ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; |
e4ea9333 SG |
360 | ct->regs.ack = GPIO_ISR; |
361 | ct->regs.mask = GPIO_IMR; | |
362 | ||
363 | irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, | |
364 | IRQ_NOREQUEST, 0); | |
9e26b0b1 PF |
365 | |
366 | return 0; | |
e4ea9333 | 367 | } |
b5eee2fd | 368 | |
3836309d | 369 | static void mxc_gpio_get_hw(struct platform_device *pdev) |
e7fc6ae7 | 370 | { |
8937cb60 SG |
371 | const struct of_device_id *of_id = |
372 | of_match_device(mxc_gpio_dt_ids, &pdev->dev); | |
373 | enum mxc_gpio_hwtype hwtype; | |
374 | ||
375 | if (of_id) | |
376 | pdev->id_entry = of_id->data; | |
377 | hwtype = pdev->id_entry->driver_data; | |
e7fc6ae7 SG |
378 | |
379 | if (mxc_gpio_hwtype) { | |
380 | /* | |
381 | * The driver works with a reasonable presupposition, | |
382 | * that is all gpio ports must be the same type when | |
383 | * running on one soc. | |
384 | */ | |
385 | BUG_ON(mxc_gpio_hwtype != hwtype); | |
386 | return; | |
387 | } | |
388 | ||
aeb27748 BT |
389 | if (hwtype == IMX35_GPIO) |
390 | mxc_gpio_hwdata = &imx35_gpio_hwdata; | |
391 | else if (hwtype == IMX31_GPIO) | |
e7fc6ae7 SG |
392 | mxc_gpio_hwdata = &imx31_gpio_hwdata; |
393 | else | |
394 | mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; | |
395 | ||
396 | mxc_gpio_hwtype = hwtype; | |
397 | } | |
398 | ||
09ad8039 SG |
399 | static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
400 | { | |
401 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
402 | struct mxc_gpio_port *port = | |
403 | container_of(bgc, struct mxc_gpio_port, bgc); | |
404 | ||
1ab7ef15 | 405 | return irq_find_mapping(port->domain, offset); |
09ad8039 SG |
406 | } |
407 | ||
3836309d | 408 | static int mxc_gpio_probe(struct platform_device *pdev) |
07bd1a6c | 409 | { |
8937cb60 | 410 | struct device_node *np = pdev->dev.of_node; |
b78d8e59 SG |
411 | struct mxc_gpio_port *port; |
412 | struct resource *iores; | |
1ab7ef15 | 413 | int irq_base; |
e4ea9333 | 414 | int err; |
b78d8e59 | 415 | |
e7fc6ae7 SG |
416 | mxc_gpio_get_hw(pdev); |
417 | ||
8cd73e4e | 418 | port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); |
b78d8e59 SG |
419 | if (!port) |
420 | return -ENOMEM; | |
07bd1a6c | 421 | |
b78d8e59 | 422 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8cd73e4e FE |
423 | port->base = devm_ioremap_resource(&pdev->dev, iores); |
424 | if (IS_ERR(port->base)) | |
425 | return PTR_ERR(port->base); | |
b78d8e59 SG |
426 | |
427 | port->irq_high = platform_get_irq(pdev, 1); | |
428 | port->irq = platform_get_irq(pdev, 0); | |
8cd73e4e | 429 | if (port->irq < 0) |
5ea80e49 | 430 | return port->irq; |
b78d8e59 SG |
431 | |
432 | /* disable the interrupt and clear the status */ | |
433 | writel(0, port->base + GPIO_IMR); | |
434 | writel(~0, port->base + GPIO_ISR); | |
435 | ||
e7fc6ae7 | 436 | if (mxc_gpio_hwtype == IMX21_GPIO) { |
33a4e985 UKK |
437 | /* |
438 | * Setup one handler for all GPIO interrupts. Actually setting | |
439 | * the handler is needed only once, but doing it for every port | |
440 | * is more robust and easier. | |
441 | */ | |
442 | irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); | |
b78d8e59 SG |
443 | } else { |
444 | /* setup one handler for each entry */ | |
e65eea54 RK |
445 | irq_set_chained_handler_and_data(port->irq, |
446 | mx3_gpio_irq_handler, port); | |
447 | if (port->irq_high > 0) | |
b78d8e59 | 448 | /* setup handler for GPIO 16 to 31 */ |
e65eea54 RK |
449 | irq_set_chained_handler_and_data(port->irq_high, |
450 | mx3_gpio_irq_handler, | |
451 | port); | |
07bd1a6c JB |
452 | } |
453 | ||
2ce420da SG |
454 | err = bgpio_init(&port->bgc, &pdev->dev, 4, |
455 | port->base + GPIO_PSR, | |
456 | port->base + GPIO_DR, NULL, | |
442b2494 VZ |
457 | port->base + GPIO_GDIR, NULL, |
458 | BGPIOF_READ_OUTPUT_REG_SET); | |
2ce420da | 459 | if (err) |
8cd73e4e | 460 | goto out_bgio; |
b78d8e59 | 461 | |
09ad8039 | 462 | port->bgc.gc.to_irq = mxc_gpio_to_irq; |
7e6086d9 SG |
463 | port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : |
464 | pdev->id * 32; | |
b78d8e59 | 465 | |
2ce420da | 466 | err = gpiochip_add(&port->bgc.gc); |
b78d8e59 | 467 | if (err) |
2ce420da | 468 | goto out_bgpio_remove; |
b78d8e59 | 469 | |
1ab7ef15 SG |
470 | irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id()); |
471 | if (irq_base < 0) { | |
472 | err = irq_base; | |
473 | goto out_gpiochip_remove; | |
474 | } | |
475 | ||
476 | port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, | |
477 | &irq_domain_simple_ops, NULL); | |
478 | if (!port->domain) { | |
479 | err = -ENODEV; | |
480 | goto out_irqdesc_free; | |
481 | } | |
8937cb60 SG |
482 | |
483 | /* gpio-mxc can be a generic irq chip */ | |
9e26b0b1 PF |
484 | err = mxc_gpio_init_gc(port, irq_base); |
485 | if (err < 0) | |
486 | goto out_irqdomain_remove; | |
8937cb60 | 487 | |
b78d8e59 SG |
488 | list_add_tail(&port->node, &mxc_gpio_ports); |
489 | ||
07bd1a6c | 490 | return 0; |
b78d8e59 | 491 | |
9e26b0b1 PF |
492 | out_irqdomain_remove: |
493 | irq_domain_remove(port->domain); | |
1ab7ef15 SG |
494 | out_irqdesc_free: |
495 | irq_free_descs(irq_base, 32); | |
496 | out_gpiochip_remove: | |
9f5132ae | 497 | gpiochip_remove(&port->bgc.gc); |
2ce420da SG |
498 | out_bgpio_remove: |
499 | bgpio_remove(&port->bgc); | |
8cd73e4e | 500 | out_bgio: |
b78d8e59 SG |
501 | dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); |
502 | return err; | |
07bd1a6c | 503 | } |
b78d8e59 SG |
504 | |
505 | static struct platform_driver mxc_gpio_driver = { | |
506 | .driver = { | |
507 | .name = "gpio-mxc", | |
8937cb60 | 508 | .of_match_table = mxc_gpio_dt_ids, |
b78d8e59 SG |
509 | }, |
510 | .probe = mxc_gpio_probe, | |
e7fc6ae7 | 511 | .id_table = mxc_gpio_devtype, |
b78d8e59 SG |
512 | }; |
513 | ||
514 | static int __init gpio_mxc_init(void) | |
515 | { | |
516 | return platform_driver_register(&mxc_gpio_driver); | |
517 | } | |
518 | postcore_initcall(gpio_mxc_init); | |
519 | ||
520 | MODULE_AUTHOR("Freescale Semiconductor, " | |
521 | "Daniel Mack <danielncaiaq.de>, " | |
522 | "Juergen Beisert <kernel@pengutronix.de>"); | |
523 | MODULE_DESCRIPTION("Freescale MXC GPIO"); | |
524 | MODULE_LICENSE("GPL"); |