Commit | Line | Data |
---|---|---|
07bd1a6c JB |
1 | /* |
2 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * Based on code from Freescale, | |
e24798e6 | 6 | * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
07bd1a6c JB |
7 | * |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
a3484ffd | 23 | #include <linux/interrupt.h> |
07bd1a6c JB |
24 | #include <linux/io.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/gpio.h> | |
b78d8e59 SG |
27 | #include <linux/platform_device.h> |
28 | #include <linux/slab.h> | |
2ce420da | 29 | #include <linux/basic_mmio_gpio.h> |
8937cb60 SG |
30 | #include <linux/of.h> |
31 | #include <linux/of_device.h> | |
07bd1a6c JB |
32 | #include <asm-generic/bug.h> |
33 | ||
e7fc6ae7 SG |
34 | enum mxc_gpio_hwtype { |
35 | IMX1_GPIO, /* runs on i.mx1 */ | |
36 | IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ | |
37 | IMX31_GPIO, /* runs on all other i.mx */ | |
38 | }; | |
39 | ||
40 | /* device type dependent stuff */ | |
41 | struct mxc_gpio_hwdata { | |
42 | unsigned dr_reg; | |
43 | unsigned gdir_reg; | |
44 | unsigned psr_reg; | |
45 | unsigned icr1_reg; | |
46 | unsigned icr2_reg; | |
47 | unsigned imr_reg; | |
48 | unsigned isr_reg; | |
49 | unsigned low_level; | |
50 | unsigned high_level; | |
51 | unsigned rise_edge; | |
52 | unsigned fall_edge; | |
53 | }; | |
54 | ||
b78d8e59 SG |
55 | struct mxc_gpio_port { |
56 | struct list_head node; | |
57 | void __iomem *base; | |
58 | int irq; | |
59 | int irq_high; | |
60 | int virtual_irq_start; | |
2ce420da | 61 | struct bgpio_chip bgc; |
b78d8e59 | 62 | u32 both_edges; |
b78d8e59 SG |
63 | }; |
64 | ||
e7fc6ae7 SG |
65 | static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { |
66 | .dr_reg = 0x1c, | |
67 | .gdir_reg = 0x00, | |
68 | .psr_reg = 0x24, | |
69 | .icr1_reg = 0x28, | |
70 | .icr2_reg = 0x2c, | |
71 | .imr_reg = 0x30, | |
72 | .isr_reg = 0x34, | |
73 | .low_level = 0x03, | |
74 | .high_level = 0x02, | |
75 | .rise_edge = 0x00, | |
76 | .fall_edge = 0x01, | |
77 | }; | |
78 | ||
79 | static struct mxc_gpio_hwdata imx31_gpio_hwdata = { | |
80 | .dr_reg = 0x00, | |
81 | .gdir_reg = 0x04, | |
82 | .psr_reg = 0x08, | |
83 | .icr1_reg = 0x0c, | |
84 | .icr2_reg = 0x10, | |
85 | .imr_reg = 0x14, | |
86 | .isr_reg = 0x18, | |
87 | .low_level = 0x00, | |
88 | .high_level = 0x01, | |
89 | .rise_edge = 0x02, | |
90 | .fall_edge = 0x03, | |
91 | }; | |
92 | ||
93 | static enum mxc_gpio_hwtype mxc_gpio_hwtype; | |
94 | static struct mxc_gpio_hwdata *mxc_gpio_hwdata; | |
95 | ||
96 | #define GPIO_DR (mxc_gpio_hwdata->dr_reg) | |
97 | #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) | |
98 | #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) | |
99 | #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) | |
100 | #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) | |
101 | #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) | |
102 | #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) | |
103 | ||
104 | #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) | |
105 | #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) | |
106 | #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) | |
107 | #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) | |
108 | #define GPIO_INT_NONE 0x4 | |
109 | ||
110 | static struct platform_device_id mxc_gpio_devtype[] = { | |
111 | { | |
112 | .name = "imx1-gpio", | |
113 | .driver_data = IMX1_GPIO, | |
114 | }, { | |
115 | .name = "imx21-gpio", | |
116 | .driver_data = IMX21_GPIO, | |
117 | }, { | |
118 | .name = "imx31-gpio", | |
119 | .driver_data = IMX31_GPIO, | |
120 | }, { | |
121 | /* sentinel */ | |
122 | } | |
123 | }; | |
124 | ||
8937cb60 SG |
125 | static const struct of_device_id mxc_gpio_dt_ids[] = { |
126 | { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, | |
127 | { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, | |
128 | { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, | |
129 | { /* sentinel */ } | |
130 | }; | |
131 | ||
b78d8e59 SG |
132 | /* |
133 | * MX2 has one interrupt *for all* gpio ports. The list is used | |
134 | * to save the references to all ports, so that mx2_gpio_irq_handler | |
135 | * can walk through all interrupt status registers. | |
136 | */ | |
137 | static LIST_HEAD(mxc_gpio_ports); | |
07bd1a6c JB |
138 | |
139 | /* Note: This driver assumes 32 GPIOs are handled in one register */ | |
140 | ||
4d93579f | 141 | static int gpio_set_irq_type(struct irq_data *d, u32 type) |
07bd1a6c | 142 | { |
4d93579f | 143 | u32 gpio = irq_to_gpio(d->irq); |
e4ea9333 SG |
144 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
145 | struct mxc_gpio_port *port = gc->private; | |
07bd1a6c JB |
146 | u32 bit, val; |
147 | int edge; | |
148 | void __iomem *reg = port->base; | |
149 | ||
910862ec | 150 | port->both_edges &= ~(1 << (gpio & 31)); |
07bd1a6c | 151 | switch (type) { |
6cab4860 | 152 | case IRQ_TYPE_EDGE_RISING: |
07bd1a6c JB |
153 | edge = GPIO_INT_RISE_EDGE; |
154 | break; | |
6cab4860 | 155 | case IRQ_TYPE_EDGE_FALLING: |
07bd1a6c JB |
156 | edge = GPIO_INT_FALL_EDGE; |
157 | break; | |
910862ec | 158 | case IRQ_TYPE_EDGE_BOTH: |
5523f86b | 159 | val = gpio_get_value(gpio); |
910862ec GL |
160 | if (val) { |
161 | edge = GPIO_INT_LOW_LEV; | |
162 | pr_debug("mxc: set GPIO %d to low trigger\n", gpio); | |
163 | } else { | |
164 | edge = GPIO_INT_HIGH_LEV; | |
165 | pr_debug("mxc: set GPIO %d to high trigger\n", gpio); | |
166 | } | |
167 | port->both_edges |= 1 << (gpio & 31); | |
168 | break; | |
6cab4860 | 169 | case IRQ_TYPE_LEVEL_LOW: |
07bd1a6c JB |
170 | edge = GPIO_INT_LOW_LEV; |
171 | break; | |
6cab4860 | 172 | case IRQ_TYPE_LEVEL_HIGH: |
07bd1a6c JB |
173 | edge = GPIO_INT_HIGH_LEV; |
174 | break; | |
910862ec | 175 | default: |
07bd1a6c JB |
176 | return -EINVAL; |
177 | } | |
178 | ||
179 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ | |
180 | bit = gpio & 0xf; | |
b78d8e59 SG |
181 | val = readl(reg) & ~(0x3 << (bit << 1)); |
182 | writel(val | (edge << (bit << 1)), reg); | |
e4ea9333 | 183 | writel(1 << (gpio & 0x1f), port->base + GPIO_ISR); |
07bd1a6c JB |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
910862ec GL |
188 | static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) |
189 | { | |
190 | void __iomem *reg = port->base; | |
191 | u32 bit, val; | |
192 | int edge; | |
193 | ||
194 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ | |
195 | bit = gpio & 0xf; | |
b78d8e59 | 196 | val = readl(reg); |
910862ec GL |
197 | edge = (val >> (bit << 1)) & 3; |
198 | val &= ~(0x3 << (bit << 1)); | |
3d40f7fe | 199 | if (edge == GPIO_INT_HIGH_LEV) { |
910862ec GL |
200 | edge = GPIO_INT_LOW_LEV; |
201 | pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); | |
3d40f7fe | 202 | } else if (edge == GPIO_INT_LOW_LEV) { |
910862ec GL |
203 | edge = GPIO_INT_HIGH_LEV; |
204 | pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); | |
3d40f7fe | 205 | } else { |
910862ec GL |
206 | pr_err("mxc: invalid configuration for GPIO %d: %x\n", |
207 | gpio, edge); | |
208 | return; | |
209 | } | |
b78d8e59 | 210 | writel(val | (edge << (bit << 1)), reg); |
910862ec GL |
211 | } |
212 | ||
3621f188 | 213 | /* handle 32 interrupts in one status register */ |
07bd1a6c JB |
214 | static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) |
215 | { | |
3621f188 | 216 | u32 gpio_irq_no_base = port->virtual_irq_start; |
07bd1a6c | 217 | |
3621f188 UKK |
218 | while (irq_stat != 0) { |
219 | int irqoffset = fls(irq_stat) - 1; | |
07bd1a6c | 220 | |
3621f188 UKK |
221 | if (port->both_edges & (1 << irqoffset)) |
222 | mxc_flip_edge(port, irqoffset); | |
910862ec | 223 | |
3621f188 | 224 | generic_handle_irq(gpio_irq_no_base + irqoffset); |
910862ec | 225 | |
3621f188 | 226 | irq_stat &= ~(1 << irqoffset); |
07bd1a6c JB |
227 | } |
228 | } | |
229 | ||
cfca8b53 | 230 | /* MX1 and MX3 has one interrupt *per* gpio port */ |
07bd1a6c JB |
231 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
232 | { | |
233 | u32 irq_stat; | |
6845664a | 234 | struct mxc_gpio_port *port = irq_get_handler_data(irq); |
07bd1a6c | 235 | |
b78d8e59 | 236 | irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); |
e2c97e7f | 237 | |
07bd1a6c JB |
238 | mxc_gpio_irq_handler(port, irq_stat); |
239 | } | |
07bd1a6c | 240 | |
07bd1a6c JB |
241 | /* MX2 has one interrupt *for all* gpio ports */ |
242 | static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |
243 | { | |
07bd1a6c | 244 | u32 irq_msk, irq_stat; |
b78d8e59 | 245 | struct mxc_gpio_port *port; |
07bd1a6c JB |
246 | |
247 | /* walk through all interrupt status registers */ | |
b78d8e59 SG |
248 | list_for_each_entry(port, &mxc_gpio_ports, node) { |
249 | irq_msk = readl(port->base + GPIO_IMR); | |
07bd1a6c JB |
250 | if (!irq_msk) |
251 | continue; | |
252 | ||
b78d8e59 | 253 | irq_stat = readl(port->base + GPIO_ISR) & irq_msk; |
07bd1a6c | 254 | if (irq_stat) |
b78d8e59 | 255 | mxc_gpio_irq_handler(port, irq_stat); |
07bd1a6c JB |
256 | } |
257 | } | |
07bd1a6c | 258 | |
a3484ffd DN |
259 | /* |
260 | * Set interrupt number "irq" in the GPIO as a wake-up source. | |
261 | * While system is running, all registered GPIO interrupts need to have | |
262 | * wake-up enabled. When system is suspended, only selected GPIO interrupts | |
263 | * need to have wake-up enabled. | |
264 | * @param irq interrupt source number | |
265 | * @param enable enable as wake-up if equal to non-zero | |
266 | * @return This function returns 0 on success. | |
267 | */ | |
4d93579f | 268 | static int gpio_set_wake_irq(struct irq_data *d, u32 enable) |
a3484ffd | 269 | { |
4d93579f | 270 | u32 gpio = irq_to_gpio(d->irq); |
a3484ffd | 271 | u32 gpio_idx = gpio & 0x1F; |
e4ea9333 SG |
272 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
273 | struct mxc_gpio_port *port = gc->private; | |
a3484ffd DN |
274 | |
275 | if (enable) { | |
276 | if (port->irq_high && (gpio_idx >= 16)) | |
277 | enable_irq_wake(port->irq_high); | |
278 | else | |
279 | enable_irq_wake(port->irq); | |
280 | } else { | |
281 | if (port->irq_high && (gpio_idx >= 16)) | |
282 | disable_irq_wake(port->irq_high); | |
283 | else | |
284 | disable_irq_wake(port->irq); | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
e4ea9333 SG |
290 | static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port) |
291 | { | |
292 | struct irq_chip_generic *gc; | |
293 | struct irq_chip_type *ct; | |
294 | ||
295 | gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start, | |
296 | port->base, handle_level_irq); | |
297 | gc->private = port; | |
298 | ||
299 | ct = gc->chip_types; | |
591567a5 | 300 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
e4ea9333 SG |
301 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
302 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
303 | ct->chip.irq_set_type = gpio_set_irq_type; | |
591567a5 | 304 | ct->chip.irq_set_wake = gpio_set_wake_irq; |
e4ea9333 SG |
305 | ct->regs.ack = GPIO_ISR; |
306 | ct->regs.mask = GPIO_IMR; | |
307 | ||
308 | irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, | |
309 | IRQ_NOREQUEST, 0); | |
310 | } | |
b5eee2fd | 311 | |
e7fc6ae7 SG |
312 | static void __devinit mxc_gpio_get_hw(struct platform_device *pdev) |
313 | { | |
8937cb60 SG |
314 | const struct of_device_id *of_id = |
315 | of_match_device(mxc_gpio_dt_ids, &pdev->dev); | |
316 | enum mxc_gpio_hwtype hwtype; | |
317 | ||
318 | if (of_id) | |
319 | pdev->id_entry = of_id->data; | |
320 | hwtype = pdev->id_entry->driver_data; | |
e7fc6ae7 SG |
321 | |
322 | if (mxc_gpio_hwtype) { | |
323 | /* | |
324 | * The driver works with a reasonable presupposition, | |
325 | * that is all gpio ports must be the same type when | |
326 | * running on one soc. | |
327 | */ | |
328 | BUG_ON(mxc_gpio_hwtype != hwtype); | |
329 | return; | |
330 | } | |
331 | ||
332 | if (hwtype == IMX31_GPIO) | |
333 | mxc_gpio_hwdata = &imx31_gpio_hwdata; | |
334 | else | |
335 | mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; | |
336 | ||
337 | mxc_gpio_hwtype = hwtype; | |
338 | } | |
339 | ||
b78d8e59 | 340 | static int __devinit mxc_gpio_probe(struct platform_device *pdev) |
07bd1a6c | 341 | { |
8937cb60 | 342 | struct device_node *np = pdev->dev.of_node; |
b78d8e59 SG |
343 | struct mxc_gpio_port *port; |
344 | struct resource *iores; | |
e4ea9333 | 345 | int err; |
b78d8e59 | 346 | |
e7fc6ae7 SG |
347 | mxc_gpio_get_hw(pdev); |
348 | ||
b78d8e59 SG |
349 | port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL); |
350 | if (!port) | |
351 | return -ENOMEM; | |
07bd1a6c | 352 | |
b78d8e59 SG |
353 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
354 | if (!iores) { | |
355 | err = -ENODEV; | |
356 | goto out_kfree; | |
357 | } | |
14cb0deb | 358 | |
b78d8e59 SG |
359 | if (!request_mem_region(iores->start, resource_size(iores), |
360 | pdev->name)) { | |
361 | err = -EBUSY; | |
362 | goto out_kfree; | |
363 | } | |
07bd1a6c | 364 | |
b78d8e59 SG |
365 | port->base = ioremap(iores->start, resource_size(iores)); |
366 | if (!port->base) { | |
367 | err = -ENOMEM; | |
368 | goto out_release_mem; | |
369 | } | |
370 | ||
371 | port->irq_high = platform_get_irq(pdev, 1); | |
372 | port->irq = platform_get_irq(pdev, 0); | |
373 | if (port->irq < 0) { | |
374 | err = -EINVAL; | |
375 | goto out_iounmap; | |
376 | } | |
377 | ||
378 | /* disable the interrupt and clear the status */ | |
379 | writel(0, port->base + GPIO_IMR); | |
380 | writel(~0, port->base + GPIO_ISR); | |
381 | ||
e7fc6ae7 | 382 | if (mxc_gpio_hwtype == IMX21_GPIO) { |
8afaada2 | 383 | /* setup one handler for all GPIO interrupts */ |
b78d8e59 SG |
384 | if (pdev->id == 0) |
385 | irq_set_chained_handler(port->irq, | |
386 | mx2_gpio_irq_handler); | |
387 | } else { | |
388 | /* setup one handler for each entry */ | |
389 | irq_set_chained_handler(port->irq, mx3_gpio_irq_handler); | |
390 | irq_set_handler_data(port->irq, port); | |
391 | if (port->irq_high > 0) { | |
392 | /* setup handler for GPIO 16 to 31 */ | |
393 | irq_set_chained_handler(port->irq_high, | |
394 | mx3_gpio_irq_handler); | |
395 | irq_set_handler_data(port->irq_high, port); | |
396 | } | |
07bd1a6c JB |
397 | } |
398 | ||
2ce420da SG |
399 | err = bgpio_init(&port->bgc, &pdev->dev, 4, |
400 | port->base + GPIO_PSR, | |
401 | port->base + GPIO_DR, NULL, | |
402 | port->base + GPIO_GDIR, NULL, false); | |
403 | if (err) | |
404 | goto out_iounmap; | |
b78d8e59 | 405 | |
2ce420da | 406 | port->bgc.gc.base = pdev->id * 32; |
fb149218 LW |
407 | port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir); |
408 | port->bgc.data = port->bgc.read_reg(port->bgc.reg_set); | |
b78d8e59 | 409 | |
2ce420da | 410 | err = gpiochip_add(&port->bgc.gc); |
b78d8e59 | 411 | if (err) |
2ce420da | 412 | goto out_bgpio_remove; |
b78d8e59 | 413 | |
8937cb60 SG |
414 | /* |
415 | * In dt case, we use gpio number range dynamically | |
416 | * allocated by gpio core. | |
417 | */ | |
418 | port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base : | |
419 | pdev->id * 32); | |
420 | ||
421 | /* gpio-mxc can be a generic irq chip */ | |
422 | mxc_gpio_init_gc(port); | |
423 | ||
b78d8e59 SG |
424 | list_add_tail(&port->node, &mxc_gpio_ports); |
425 | ||
07bd1a6c | 426 | return 0; |
b78d8e59 | 427 | |
2ce420da SG |
428 | out_bgpio_remove: |
429 | bgpio_remove(&port->bgc); | |
b78d8e59 SG |
430 | out_iounmap: |
431 | iounmap(port->base); | |
432 | out_release_mem: | |
433 | release_mem_region(iores->start, resource_size(iores)); | |
434 | out_kfree: | |
435 | kfree(port); | |
436 | dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); | |
437 | return err; | |
07bd1a6c | 438 | } |
b78d8e59 SG |
439 | |
440 | static struct platform_driver mxc_gpio_driver = { | |
441 | .driver = { | |
442 | .name = "gpio-mxc", | |
443 | .owner = THIS_MODULE, | |
8937cb60 | 444 | .of_match_table = mxc_gpio_dt_ids, |
b78d8e59 SG |
445 | }, |
446 | .probe = mxc_gpio_probe, | |
e7fc6ae7 | 447 | .id_table = mxc_gpio_devtype, |
b78d8e59 SG |
448 | }; |
449 | ||
450 | static int __init gpio_mxc_init(void) | |
451 | { | |
452 | return platform_driver_register(&mxc_gpio_driver); | |
453 | } | |
454 | postcore_initcall(gpio_mxc_init); | |
455 | ||
456 | MODULE_AUTHOR("Freescale Semiconductor, " | |
457 | "Daniel Mack <danielncaiaq.de>, " | |
458 | "Juergen Beisert <kernel@pengutronix.de>"); | |
459 | MODULE_DESCRIPTION("Freescale MXC GPIO"); | |
460 | MODULE_LICENSE("GPL"); |