[deliverable/linux.git] / drivers / gpio / gpio-mxc.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <asm-generic/bug.h>
#include <asm/mach/irq.h>

enum mxc_gpio_hwtype {
	IMX1_GPIO,	/* runs on i.mx1 */
	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
	IMX31_GPIO,	/* runs on all other i.mx */
};

/* device type dependent stuff */
struct mxc_gpio_hwdata {
	unsigned dr_reg;
	unsigned gdir_reg;
	unsigned psr_reg;
	unsigned icr1_reg;
	unsigned icr2_reg;
	unsigned imr_reg;
	unsigned isr_reg;
	unsigned low_level;
	unsigned high_level;
	unsigned rise_edge;
	unsigned fall_edge;
};

struct mxc_gpio_port {
	struct list_head node;
	void __iomem *base;
	int irq;
	int irq_high;
	struct irq_domain *domain;
	struct bgpio_chip bgc;
	u32 both_edges;
};

static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	.dr_reg		= 0x1c,
	.gdir_reg	= 0x00,
	.psr_reg	= 0x24,
	.icr1_reg	= 0x28,
	.icr2_reg	= 0x2c,
	.imr_reg	= 0x30,
	.isr_reg	= 0x34,
	.low_level	= 0x03,
	.high_level	= 0x02,
	.rise_edge	= 0x00,
	.fall_edge	= 0x01,
};

static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	.dr_reg		= 0x00,
	.gdir_reg	= 0x04,
	.psr_reg	= 0x08,
	.icr1_reg	= 0x0c,
	.icr2_reg	= 0x10,
	.imr_reg	= 0x14,
	.isr_reg	= 0x18,
	.low_level	= 0x00,
	.high_level	= 0x01,
	.rise_edge	= 0x02,
	.fall_edge	= 0x03,
};

static enum mxc_gpio_hwtype mxc_gpio_hwtype;
static struct mxc_gpio_hwdata *mxc_gpio_hwdata;

#define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
#define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
#define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
#define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
#define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
#define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
#define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)

#define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
#define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
#define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
#define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
#define GPIO_INT_NONE		0x4

static struct platform_device_id mxc_gpio_devtype[] = {
	{
		.name = "imx1-gpio",
		.driver_data = IMX1_GPIO,
	}, {
		.name = "imx21-gpio",
		.driver_data = IMX21_GPIO,
	}, {
		.name = "imx31-gpio",
		.driver_data = IMX31_GPIO,
	}, {
		/* sentinel */
	}
};

static const struct of_device_id mxc_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
	{ /* sentinel */ }
};

/*
 * MX2 has one interrupt *for all* gpio ports. The list is used
 * to save the references to all ports, so that mx2_gpio_irq_handler
 * can walk through all interrupt status registers.
 */
static LIST_HEAD(mxc_gpio_ports);

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 bit, val;
	u32 gpio_idx = d->hwirq;
	u32 gpio = port->bgc.gc.base + gpio_idx;
	int edge;
	void __iomem *reg = port->base;

	port->both_edges &= ~(1 << gpio_idx);
	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = gpio_get_value(gpio);
		if (val) {
			edge = GPIO_INT_LOW_LEV;
			pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
		} else {
			edge = GPIO_INT_HIGH_LEV;
			pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
		}
		port->both_edges |= 1 << gpio_idx;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* ICR1 or ICR2 */
	bit = gpio_idx & 0xf;
	val = readl(reg) & ~(0x3 << (bit << 1));
	writel(val | (edge << (bit << 1)), reg);
	writel(1 << gpio_idx, port->base + GPIO_ISR);

	return 0;
}

static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
{
	void __iomem *reg = port->base;
	u32 bit, val;
	int edge;

	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	bit = gpio & 0xf;
	val = readl(reg);
	edge = (val >> (bit << 1)) & 3;
	val &= ~(0x3 << (bit << 1));
	if (edge == GPIO_INT_HIGH_LEV) {
		edge = GPIO_INT_LOW_LEV;
		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
	} else if (edge == GPIO_INT_LOW_LEV) {
		edge = GPIO_INT_HIGH_LEV;
		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
	} else {
		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
		       gpio, edge);
		return;
	}
	writel(val | (edge << (bit << 1)), reg);
}

/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;

		if (port->both_edges & (1 << irqoffset))
			mxc_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));

		irq_stat &= ~(1 << irqoffset);
	}
}

/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxc_gpio_port *port = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);

	chained_irq_enter(chip, desc);

	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);

	mxc_gpio_irq_handler(port, irq_stat);

	chained_irq_exit(chip, desc);
}

/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_msk, irq_stat;
	struct mxc_gpio_port *port;

	/* walk through all interrupt status registers */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		irq_msk = readl(port->base + GPIO_IMR);
		if (!irq_msk)
			continue;

		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
		if (irq_stat)
			mxc_gpio_irq_handler(port, irq_stat);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 gpio_idx = d->hwirq;

	if (enable) {
		if (port->irq_high && (gpio_idx >= 16))
			enable_irq_wake(port->irq_high);
		else
			enable_irq_wake(port->irq);
	} else {
		if (port->irq_high && (gpio_idx >= 16))
			disable_irq_wake(port->irq_high);
		else
			disable_irq_wake(port->irq);
	}

	return 0;
}

static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
				    port->base, handle_level_irq);
	gc->private = port;

	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = gpio_set_irq_type;
	ct->chip.irq_set_wake = gpio_set_wake_irq;
	ct->regs.ack = GPIO_ISR;
	ct->regs.mask = GPIO_IMR;

	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
			       IRQ_NOREQUEST, 0);
}

static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
	enum mxc_gpio_hwtype hwtype;

	if (of_id)
		pdev->id_entry = of_id->data;
	hwtype = pdev->id_entry->driver_data;

	if (mxc_gpio_hwtype) {
		/*
		 * The driver works with a reasonable presupposition,
		 * that is all gpio ports must be the same type when
		 * running on one soc.
		 */
		BUG_ON(mxc_gpio_hwtype != hwtype);
		return;
	}

	if (hwtype == IMX31_GPIO)
		mxc_gpio_hwdata = &imx31_gpio_hwdata;
	else
		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;

	mxc_gpio_hwtype = hwtype;
}

static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct mxc_gpio_port *port =
		container_of(bgc, struct mxc_gpio_port, bgc);

	return irq_find_mapping(port->domain, offset);
}

static int __devinit mxc_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxc_gpio_port *port;
	struct resource *iores;
	int irq_base;
	int err;

	mxc_gpio_get_hw(pdev);

	port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores) {
		err = -ENODEV;
		goto out_kfree;
	}

	if (!request_mem_region(iores->start, resource_size(iores),
				pdev->name)) {
		err = -EBUSY;
		goto out_kfree;
	}

	port->base = ioremap(iores->start, resource_size(iores));
	if (!port->base) {
		err = -ENOMEM;
		goto out_release_mem;
	}

	port->irq_high = platform_get_irq(pdev, 1);
	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0) {
		err = -EINVAL;
		goto out_iounmap;
	}

	/* disable the interrupt and clear the status */
	writel(0, port->base + GPIO_IMR);
	writel(~0, port->base + GPIO_ISR);

	if (mxc_gpio_hwtype == IMX21_GPIO) {
		/*
		 * Setup one handler for all GPIO interrupts. Actually setting
		 * the handler is needed only once, but doing it for every port
		 * is more robust and easier.
		 */
		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
	} else {
		/* setup one handler for each entry */
		irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
		irq_set_handler_data(port->irq, port);
		if (port->irq_high > 0) {
			/* setup handler for GPIO 16 to 31 */
			irq_set_chained_handler(port->irq_high,
						mx3_gpio_irq_handler);
			irq_set_handler_data(port->irq_high, port);
		}
	}

	err = bgpio_init(&port->bgc, &pdev->dev, 4,
			 port->base + GPIO_PSR,
			 port->base + GPIO_DR, NULL,
			 port->base + GPIO_GDIR, NULL, 0);
	if (err)
		goto out_iounmap;

	port->bgc.gc.to_irq = mxc_gpio_to_irq;
	port->bgc.gc.base = pdev->id * 32;
	port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
	port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		goto out_bgpio_remove;

	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	if (irq_base < 0) {
		err = irq_base;
		goto out_gpiochip_remove;
	}

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_irqdesc_free;
	}

	/* gpio-mxc can be a generic irq chip */
	mxc_gpio_init_gc(port, irq_base);

	list_add_tail(&port->node, &mxc_gpio_ports);

	return 0;

out_irqdesc_free:
	irq_free_descs(irq_base, 32);
out_gpiochip_remove:
	WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
out_bgpio_remove:
	bgpio_remove(&port->bgc);
out_iounmap:
	iounmap(port->base);
out_release_mem:
	release_mem_region(iores->start, resource_size(iores));
out_kfree:
	kfree(port);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	return err;
}

static struct platform_driver mxc_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxc",
		.owner	= THIS_MODULE,
		.of_match_table = mxc_gpio_dt_ids,
	},
	.probe		= mxc_gpio_probe,
	.id_table	= mxc_gpio_devtype,
};

static int __init gpio_mxc_init(void)
{
	return platform_driver_register(&mxc_gpio_driver);
}
postcore_initcall(gpio_mxc_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXC GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
07bd1a6c JB	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* Based on code from Freescale,
e24798e6	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
07bd1a6c JB	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*/
	21
	22	#include <linux/init.h>
a3484ffd	23	#include <linux/interrupt.h>
07bd1a6c JB	24	#include <linux/io.h>
07bd1a6c JB	25	#include <linux/irq.h>
1ab7ef15	26	#include <linux/irqdomain.h>
07bd1a6c	27	#include <linux/gpio.h>
b78d8e59 SG	28	#include <linux/platform_device.h>
b78d8e59 SG	29	#include <linux/slab.h>
2ce420da	30	#include <linux/basic_mmio_gpio.h>
8937cb60 SG	31	#include <linux/of.h>
8937cb60 SG	32	#include <linux/of_device.h>
bb207ef1	33	#include <linux/module.h>
07bd1a6c	34	#include <asm-generic/bug.h>
0e44b6ec	35	#include <asm/mach/irq.h>
07bd1a6c	36
e7fc6ae7 SG	37	enum mxc_gpio_hwtype {
	38	IMX1_GPIO, /* runs on i.mx1 */
	39	IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
	40	IMX31_GPIO, /* runs on all other i.mx */
	41	};
	42
	43	/* device type dependent stuff */
	44	struct mxc_gpio_hwdata {
	45	unsigned dr_reg;
	46	unsigned gdir_reg;
	47	unsigned psr_reg;
	48	unsigned icr1_reg;
	49	unsigned icr2_reg;
	50	unsigned imr_reg;
	51	unsigned isr_reg;
	52	unsigned low_level;
	53	unsigned high_level;
	54	unsigned rise_edge;
	55	unsigned fall_edge;
	56	};
	57
b78d8e59 SG	58	struct mxc_gpio_port {
	59	struct list_head node;
	60	void __iomem *base;
	61	int irq;
	62	int irq_high;
1ab7ef15	63	struct irq_domain *domain;
2ce420da	64	struct bgpio_chip bgc;
b78d8e59	65	u32 both_edges;
b78d8e59 SG	66	};
b78d8e59 SG	67
e7fc6ae7 SG	68	static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	69	.dr_reg = 0x1c,
	70	.gdir_reg = 0x00,
	71	.psr_reg = 0x24,
	72	.icr1_reg = 0x28,
	73	.icr2_reg = 0x2c,
	74	.imr_reg = 0x30,
	75	.isr_reg = 0x34,
	76	.low_level = 0x03,
	77	.high_level = 0x02,
	78	.rise_edge = 0x00,
	79	.fall_edge = 0x01,
	80	};
	81
	82	static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	83	.dr_reg = 0x00,
	84	.gdir_reg = 0x04,
	85	.psr_reg = 0x08,
	86	.icr1_reg = 0x0c,
	87	.icr2_reg = 0x10,
	88	.imr_reg = 0x14,
	89	.isr_reg = 0x18,
	90	.low_level = 0x00,
	91	.high_level = 0x01,
	92	.rise_edge = 0x02,
	93	.fall_edge = 0x03,
	94	};
	95
	96	static enum mxc_gpio_hwtype mxc_gpio_hwtype;
	97	static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
	98
	99	#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
	100	#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
	101	#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
	102	#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
	103	#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
	104	#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
	105	#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
	106
	107	#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
	108	#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
	109	#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
	110	#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
	111	#define GPIO_INT_NONE 0x4
	112
	113	static struct platform_device_id mxc_gpio_devtype[] = {
	114	{
	115	.name = "imx1-gpio",
	116	.driver_data = IMX1_GPIO,
	117	}, {
	118	.name = "imx21-gpio",
	119	.driver_data = IMX21_GPIO,
	120	}, {
	121	.name = "imx31-gpio",
	122	.driver_data = IMX31_GPIO,
	123	}, {
	124	/* sentinel */
	125	}
	126	};
	127
8937cb60 SG	128	static const struct of_device_id mxc_gpio_dt_ids[] = {
	129	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
	130	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
	131	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
	132	{ /* sentinel */ }
	133	};
	134
b78d8e59 SG	135	/*
	136	* MX2 has one interrupt for all gpio ports. The list is used
	137	* to save the references to all ports, so that mx2_gpio_irq_handler
	138	* can walk through all interrupt status registers.
	139	*/
	140	static LIST_HEAD(mxc_gpio_ports);
07bd1a6c JB	141
	142	/* Note: This driver assumes 32 GPIOs are handled in one register */
	143
4d93579f	144	static int gpio_set_irq_type(struct irq_data *d, u32 type)
07bd1a6c	145	{
e4ea9333 SG	146	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	147	struct mxc_gpio_port *port = gc->private;
07bd1a6c	148	u32 bit, val;
1ab7ef15 SG	149	u32 gpio_idx = d->hwirq;
1ab7ef15 SG	150	u32 gpio = port->bgc.gc.base + gpio_idx;
07bd1a6c JB	151	int edge;
	152	void __iomem *reg = port->base;
	153
1ab7ef15	154	port->both_edges &= ~(1 << gpio_idx);
07bd1a6c	155	switch (type) {
6cab4860	156	case IRQ_TYPE_EDGE_RISING:
07bd1a6c JB	157	edge = GPIO_INT_RISE_EDGE;
07bd1a6c JB	158	break;
6cab4860	159	case IRQ_TYPE_EDGE_FALLING:
07bd1a6c JB	160	edge = GPIO_INT_FALL_EDGE;
07bd1a6c JB	161	break;
910862ec	162	case IRQ_TYPE_EDGE_BOTH:
5523f86b	163	val = gpio_get_value(gpio);
910862ec GL	164	if (val) {
	165	edge = GPIO_INT_LOW_LEV;
	166	pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
	167	} else {
	168	edge = GPIO_INT_HIGH_LEV;
	169	pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
	170	}
1ab7ef15	171	port->both_edges \|= 1 << gpio_idx;
910862ec	172	break;
6cab4860	173	case IRQ_TYPE_LEVEL_LOW:
07bd1a6c JB	174	edge = GPIO_INT_LOW_LEV;
07bd1a6c JB	175	break;
6cab4860	176	case IRQ_TYPE_LEVEL_HIGH:
07bd1a6c JB	177	edge = GPIO_INT_HIGH_LEV;
07bd1a6c JB	178	break;
910862ec	179	default:
07bd1a6c JB	180	return -EINVAL;
	181	}
	182
1ab7ef15 SG	183	reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* ICR1 or ICR2 */
1ab7ef15 SG	184	bit = gpio_idx & 0xf;
b78d8e59 SG	185	val = readl(reg) & ~(0x3 << (bit << 1));
b78d8e59 SG	186	writel(val \| (edge << (bit << 1)), reg);
1ab7ef15	187	writel(1 << gpio_idx, port->base + GPIO_ISR);
07bd1a6c JB	188
	189	return 0;
	190	}
	191
910862ec GL	192	static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
	193	{
	194	void __iomem *reg = port->base;
	195	u32 bit, val;
	196	int edge;
	197
	198	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	199	bit = gpio & 0xf;
b78d8e59	200	val = readl(reg);
910862ec GL	201	edge = (val >> (bit << 1)) & 3;
910862ec GL	202	val &= ~(0x3 << (bit << 1));
3d40f7fe	203	if (edge == GPIO_INT_HIGH_LEV) {
910862ec GL	204	edge = GPIO_INT_LOW_LEV;
910862ec GL	205	pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
3d40f7fe	206	} else if (edge == GPIO_INT_LOW_LEV) {
910862ec GL	207	edge = GPIO_INT_HIGH_LEV;
910862ec GL	208	pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
3d40f7fe	209	} else {
910862ec GL	210	pr_err("mxc: invalid configuration for GPIO %d: %x\n",
	211	gpio, edge);
	212	return;
	213	}
b78d8e59	214	writel(val \| (edge << (bit << 1)), reg);
910862ec GL	215	}
910862ec GL	216
3621f188	217	/* handle 32 interrupts in one status register */
07bd1a6c JB	218	static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
07bd1a6c JB	219	{
3621f188 UKK	220	while (irq_stat != 0) {
3621f188 UKK	221	int irqoffset = fls(irq_stat) - 1;
07bd1a6c	222
3621f188 UKK	223	if (port->both_edges & (1 << irqoffset))
3621f188 UKK	224	mxc_flip_edge(port, irqoffset);
910862ec	225
1ab7ef15	226	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
910862ec	227
3621f188	228	irq_stat &= ~(1 << irqoffset);
07bd1a6c JB	229	}
	230	}
	231
cfca8b53	232	/* MX1 and MX3 has one interrupt per gpio port */
07bd1a6c JB	233	static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	234	{
	235	u32 irq_stat;
6845664a	236	struct mxc_gpio_port *port = irq_get_handler_data(irq);
0e44b6ec SG	237	struct irq_chip *chip = irq_get_chip(irq);
	238
	239	chained_irq_enter(chip, desc);
07bd1a6c	240
b78d8e59	241	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
e2c97e7f	242
07bd1a6c	243	mxc_gpio_irq_handler(port, irq_stat);
0e44b6ec SG	244
0e44b6ec SG	245	chained_irq_exit(chip, desc);
07bd1a6c	246	}
07bd1a6c	247
07bd1a6c JB	248	/* MX2 has one interrupt for all gpio ports */
	249	static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	250	{
07bd1a6c	251	u32 irq_msk, irq_stat;
b78d8e59	252	struct mxc_gpio_port *port;
07bd1a6c JB	253
07bd1a6c JB	254	/* walk through all interrupt status registers */
b78d8e59 SG	255	list_for_each_entry(port, &mxc_gpio_ports, node) {
b78d8e59 SG	256	irq_msk = readl(port->base + GPIO_IMR);
07bd1a6c JB	257	if (!irq_msk)
	258	continue;
	259
b78d8e59	260	irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
07bd1a6c	261	if (irq_stat)
b78d8e59	262	mxc_gpio_irq_handler(port, irq_stat);
07bd1a6c JB	263	}
07bd1a6c JB	264	}
07bd1a6c	265
a3484ffd DN	266	/*
	267	* Set interrupt number "irq" in the GPIO as a wake-up source.
	268	* While system is running, all registered GPIO interrupts need to have
	269	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	270	* need to have wake-up enabled.
	271	* @param irq interrupt source number
	272	* @param enable enable as wake-up if equal to non-zero
	273	* @return This function returns 0 on success.
	274	*/
4d93579f	275	static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
a3484ffd	276	{
e4ea9333 SG	277	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	278	struct mxc_gpio_port *port = gc->private;
1ab7ef15	279	u32 gpio_idx = d->hwirq;
a3484ffd DN	280
	281	if (enable) {
	282	if (port->irq_high && (gpio_idx >= 16))
	283	enable_irq_wake(port->irq_high);
	284	else
	285	enable_irq_wake(port->irq);
	286	} else {
	287	if (port->irq_high && (gpio_idx >= 16))
	288	disable_irq_wake(port->irq_high);
	289	else
	290	disable_irq_wake(port->irq);
	291	}
	292
	293	return 0;
	294	}
	295
1ab7ef15	296	static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
e4ea9333 SG	297	{
	298	struct irq_chip_generic *gc;
	299	struct irq_chip_type *ct;
	300
1ab7ef15	301	gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
e4ea9333 SG	302	port->base, handle_level_irq);
	303	gc->private = port;
	304
	305	ct = gc->chip_types;
591567a5	306	ct->chip.irq_ack = irq_gc_ack_set_bit;
e4ea9333 SG	307	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	308	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	309	ct->chip.irq_set_type = gpio_set_irq_type;
591567a5	310	ct->chip.irq_set_wake = gpio_set_wake_irq;
e4ea9333 SG	311	ct->regs.ack = GPIO_ISR;
	312	ct->regs.mask = GPIO_IMR;
	313
	314	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
	315	IRQ_NOREQUEST, 0);
	316	}
b5eee2fd	317
e7fc6ae7 SG	318	static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
e7fc6ae7 SG	319	{
8937cb60 SG	320	const struct of_device_id *of_id =
	321	of_match_device(mxc_gpio_dt_ids, &pdev->dev);
	322	enum mxc_gpio_hwtype hwtype;
	323
	324	if (of_id)
	325	pdev->id_entry = of_id->data;
	326	hwtype = pdev->id_entry->driver_data;
e7fc6ae7 SG	327
	328	if (mxc_gpio_hwtype) {
	329	/*
	330	* The driver works with a reasonable presupposition,
	331	* that is all gpio ports must be the same type when
	332	* running on one soc.
	333	*/
	334	BUG_ON(mxc_gpio_hwtype != hwtype);
	335	return;
	336	}
	337
	338	if (hwtype == IMX31_GPIO)
	339	mxc_gpio_hwdata = &imx31_gpio_hwdata;
	340	else
	341	mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
	342
	343	mxc_gpio_hwtype = hwtype;
	344	}
	345
09ad8039 SG	346	static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
	347	{
	348	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	349	struct mxc_gpio_port *port =
	350	container_of(bgc, struct mxc_gpio_port, bgc);
	351
1ab7ef15	352	return irq_find_mapping(port->domain, offset);
09ad8039 SG	353	}
09ad8039 SG	354
b78d8e59	355	static int __devinit mxc_gpio_probe(struct platform_device *pdev)
07bd1a6c	356	{
8937cb60	357	struct device_node *np = pdev->dev.of_node;
b78d8e59 SG	358	struct mxc_gpio_port *port;
b78d8e59 SG	359	struct resource *iores;
1ab7ef15	360	int irq_base;
e4ea9333	361	int err;
b78d8e59	362
e7fc6ae7 SG	363	mxc_gpio_get_hw(pdev);
e7fc6ae7 SG	364
b78d8e59 SG	365	port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
	366	if (!port)
	367	return -ENOMEM;
07bd1a6c	368
b78d8e59 SG	369	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	370	if (!iores) {
	371	err = -ENODEV;
	372	goto out_kfree;
	373	}
14cb0deb	374
b78d8e59 SG	375	if (!request_mem_region(iores->start, resource_size(iores),
	376	pdev->name)) {
	377	err = -EBUSY;
	378	goto out_kfree;
	379	}
07bd1a6c	380
b78d8e59 SG	381	port->base = ioremap(iores->start, resource_size(iores));
	382	if (!port->base) {
	383	err = -ENOMEM;
	384	goto out_release_mem;
	385	}
	386
	387	port->irq_high = platform_get_irq(pdev, 1);
	388	port->irq = platform_get_irq(pdev, 0);
	389	if (port->irq < 0) {
	390	err = -EINVAL;
	391	goto out_iounmap;
	392	}
	393
	394	/* disable the interrupt and clear the status */
	395	writel(0, port->base + GPIO_IMR);
	396	writel(~0, port->base + GPIO_ISR);
	397
e7fc6ae7	398	if (mxc_gpio_hwtype == IMX21_GPIO) {
33a4e985 UKK	399	/*
	400	* Setup one handler for all GPIO interrupts. Actually setting
	401	* the handler is needed only once, but doing it for every port
	402	* is more robust and easier.
	403	*/
	404	irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
b78d8e59 SG	405	} else {
	406	/* setup one handler for each entry */
	407	irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
	408	irq_set_handler_data(port->irq, port);
	409	if (port->irq_high > 0) {
	410	/* setup handler for GPIO 16 to 31 */
	411	irq_set_chained_handler(port->irq_high,
	412	mx3_gpio_irq_handler);
	413	irq_set_handler_data(port->irq_high, port);
	414	}
07bd1a6c JB	415	}
07bd1a6c JB	416
2ce420da SG	417	err = bgpio_init(&port->bgc, &pdev->dev, 4,
	418	port->base + GPIO_PSR,
	419	port->base + GPIO_DR, NULL,
3e11f7b8	420	port->base + GPIO_GDIR, NULL, 0);
2ce420da SG	421	if (err)
2ce420da SG	422	goto out_iounmap;
b78d8e59	423
09ad8039	424	port->bgc.gc.to_irq = mxc_gpio_to_irq;
2ce420da	425	port->bgc.gc.base = pdev->id * 32;
fb149218 LW	426	port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
fb149218 LW	427	port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
b78d8e59	428
2ce420da	429	err = gpiochip_add(&port->bgc.gc);
b78d8e59	430	if (err)
2ce420da	431	goto out_bgpio_remove;
b78d8e59	432
1ab7ef15 SG	433	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	434	if (irq_base < 0) {
	435	err = irq_base;
	436	goto out_gpiochip_remove;
	437	}
	438
	439	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	440	&irq_domain_simple_ops, NULL);
	441	if (!port->domain) {
	442	err = -ENODEV;
	443	goto out_irqdesc_free;
	444	}
8937cb60 SG	445
8937cb60 SG	446	/* gpio-mxc can be a generic irq chip */
1ab7ef15	447	mxc_gpio_init_gc(port, irq_base);
8937cb60	448
b78d8e59 SG	449	list_add_tail(&port->node, &mxc_gpio_ports);
b78d8e59 SG	450
07bd1a6c	451	return 0;
b78d8e59	452
1ab7ef15 SG	453	out_irqdesc_free:
	454	irq_free_descs(irq_base, 32);
	455	out_gpiochip_remove:
	456	WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
2ce420da SG	457	out_bgpio_remove:
2ce420da SG	458	bgpio_remove(&port->bgc);
b78d8e59 SG	459	out_iounmap:
	460	iounmap(port->base);
	461	out_release_mem:
	462	release_mem_region(iores->start, resource_size(iores));
	463	out_kfree:
	464	kfree(port);
	465	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	466	return err;
07bd1a6c	467	}
b78d8e59 SG	468
	469	static struct platform_driver mxc_gpio_driver = {
	470	.driver = {
	471	.name = "gpio-mxc",
	472	.owner = THIS_MODULE,
8937cb60	473	.of_match_table = mxc_gpio_dt_ids,
b78d8e59 SG	474	},
b78d8e59 SG	475	.probe = mxc_gpio_probe,
e7fc6ae7	476	.id_table = mxc_gpio_devtype,
b78d8e59 SG	477	};
	478
	479	static int __init gpio_mxc_init(void)
	480	{
	481	return platform_driver_register(&mxc_gpio_driver);
	482	}
	483	postcore_initcall(gpio_mxc_init);
	484
	485	MODULE_AUTHOR("Freescale Semiconductor, "
	486	"Daniel Mack <danielncaiaq.de>, "
	487	"Juergen Beisert <kernel@pengutronix.de>");
	488	MODULE_DESCRIPTION("Freescale MXC GPIO");
	489	MODULE_LICENSE("GPL");