[deliverable/linux.git] / drivers / gpio / gpio-mxc.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <asm-generic/bug.h>
#include <asm/mach/irq.h>

enum mxc_gpio_hwtype {
	IMX1_GPIO,	/* runs on i.mx1 */
	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
	IMX31_GPIO,	/* runs on all other i.mx */
};

/* device type dependent stuff */
struct mxc_gpio_hwdata {
	unsigned dr_reg;
	unsigned gdir_reg;
	unsigned psr_reg;
	unsigned icr1_reg;
	unsigned icr2_reg;
	unsigned imr_reg;
	unsigned isr_reg;
	unsigned low_level;
	unsigned high_level;
	unsigned rise_edge;
	unsigned fall_edge;
};

struct mxc_gpio_port {
	struct list_head node;
	void __iomem *base;
	int irq;
	int irq_high;
	int virtual_irq_start;
	struct bgpio_chip bgc;
	u32 both_edges;
};

static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	.dr_reg		= 0x1c,
	.gdir_reg	= 0x00,
	.psr_reg	= 0x24,
	.icr1_reg	= 0x28,
	.icr2_reg	= 0x2c,
	.imr_reg	= 0x30,
	.isr_reg	= 0x34,
	.low_level	= 0x03,
	.high_level	= 0x02,
	.rise_edge	= 0x00,
	.fall_edge	= 0x01,
};

static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	.dr_reg		= 0x00,
	.gdir_reg	= 0x04,
	.psr_reg	= 0x08,
	.icr1_reg	= 0x0c,
	.icr2_reg	= 0x10,
	.imr_reg	= 0x14,
	.isr_reg	= 0x18,
	.low_level	= 0x00,
	.high_level	= 0x01,
	.rise_edge	= 0x02,
	.fall_edge	= 0x03,
};

static enum mxc_gpio_hwtype mxc_gpio_hwtype;
static struct mxc_gpio_hwdata *mxc_gpio_hwdata;

#define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
#define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
#define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
#define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
#define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
#define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
#define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)

#define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
#define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
#define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
#define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
#define GPIO_INT_NONE		0x4

static struct platform_device_id mxc_gpio_devtype[] = {
	{
		.name = "imx1-gpio",
		.driver_data = IMX1_GPIO,
	}, {
		.name = "imx21-gpio",
		.driver_data = IMX21_GPIO,
	}, {
		.name = "imx31-gpio",
		.driver_data = IMX31_GPIO,
	}, {
		/* sentinel */
	}
};

static const struct of_device_id mxc_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
	{ /* sentinel */ }
};

/*
 * MX2 has one interrupt *for all* gpio ports. The list is used
 * to save the references to all ports, so that mx2_gpio_irq_handler
 * can walk through all interrupt status registers.
 */
static LIST_HEAD(mxc_gpio_ports);

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
	u32 gpio = irq_to_gpio(d->irq);
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 bit, val;
	int edge;
	void __iomem *reg = port->base;

	port->both_edges &= ~(1 << (gpio & 31));
	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = gpio_get_value(gpio);
		if (val) {
			edge = GPIO_INT_LOW_LEV;
			pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
		} else {
			edge = GPIO_INT_HIGH_LEV;
			pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
		}
		port->both_edges |= 1 << (gpio & 31);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	bit = gpio & 0xf;
	val = readl(reg) & ~(0x3 << (bit << 1));
	writel(val | (edge << (bit << 1)), reg);
	writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);

	return 0;
}

static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
{
	void __iomem *reg = port->base;
	u32 bit, val;
	int edge;

	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	bit = gpio & 0xf;
	val = readl(reg);
	edge = (val >> (bit << 1)) & 3;
	val &= ~(0x3 << (bit << 1));
	if (edge == GPIO_INT_HIGH_LEV) {
		edge = GPIO_INT_LOW_LEV;
		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
	} else if (edge == GPIO_INT_LOW_LEV) {
		edge = GPIO_INT_HIGH_LEV;
		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
	} else {
		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
		       gpio, edge);
		return;
	}
	writel(val | (edge << (bit << 1)), reg);
}

/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
	u32 gpio_irq_no_base = port->virtual_irq_start;

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;

		if (port->both_edges & (1 << irqoffset))
			mxc_flip_edge(port, irqoffset);

		generic_handle_irq(gpio_irq_no_base + irqoffset);

		irq_stat &= ~(1 << irqoffset);
	}
}

/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxc_gpio_port *port = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);

	chained_irq_enter(chip, desc);

	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);

	mxc_gpio_irq_handler(port, irq_stat);

	chained_irq_exit(chip, desc);
}

/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_msk, irq_stat;
	struct mxc_gpio_port *port;

	/* walk through all interrupt status registers */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		irq_msk = readl(port->base + GPIO_IMR);
		if (!irq_msk)
			continue;

		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
		if (irq_stat)
			mxc_gpio_irq_handler(port, irq_stat);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
	u32 gpio = irq_to_gpio(d->irq);
	u32 gpio_idx = gpio & 0x1F;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;

	if (enable) {
		if (port->irq_high && (gpio_idx >= 16))
			enable_irq_wake(port->irq_high);
		else
			enable_irq_wake(port->irq);
	} else {
		if (port->irq_high && (gpio_idx >= 16))
			disable_irq_wake(port->irq_high);
		else
			disable_irq_wake(port->irq);
	}

	return 0;
}

static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
				    port->base, handle_level_irq);
	gc->private = port;

	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = gpio_set_irq_type;
	ct->chip.irq_set_wake = gpio_set_wake_irq;
	ct->regs.ack = GPIO_ISR;
	ct->regs.mask = GPIO_IMR;

	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
			       IRQ_NOREQUEST, 0);
}

static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
	enum mxc_gpio_hwtype hwtype;

	if (of_id)
		pdev->id_entry = of_id->data;
	hwtype = pdev->id_entry->driver_data;

	if (mxc_gpio_hwtype) {
		/*
		 * The driver works with a reasonable presupposition,
		 * that is all gpio ports must be the same type when
		 * running on one soc.
		 */
		BUG_ON(mxc_gpio_hwtype != hwtype);
		return;
	}

	if (hwtype == IMX31_GPIO)
		mxc_gpio_hwdata = &imx31_gpio_hwdata;
	else
		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;

	mxc_gpio_hwtype = hwtype;
}

static int __devinit mxc_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxc_gpio_port *port;
	struct resource *iores;
	int err;

	mxc_gpio_get_hw(pdev);

	port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores) {
		err = -ENODEV;
		goto out_kfree;
	}

	if (!request_mem_region(iores->start, resource_size(iores),
				pdev->name)) {
		err = -EBUSY;
		goto out_kfree;
	}

	port->base = ioremap(iores->start, resource_size(iores));
	if (!port->base) {
		err = -ENOMEM;
		goto out_release_mem;
	}

	port->irq_high = platform_get_irq(pdev, 1);
	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0) {
		err = -EINVAL;
		goto out_iounmap;
	}

	/* disable the interrupt and clear the status */
	writel(0, port->base + GPIO_IMR);
	writel(~0, port->base + GPIO_ISR);

	if (mxc_gpio_hwtype == IMX21_GPIO) {
		/* setup one handler for all GPIO interrupts */
		if (pdev->id == 0)
			irq_set_chained_handler(port->irq,
						mx2_gpio_irq_handler);
	} else {
		/* setup one handler for each entry */
		irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
		irq_set_handler_data(port->irq, port);
		if (port->irq_high > 0) {
			/* setup handler for GPIO 16 to 31 */
			irq_set_chained_handler(port->irq_high,
						mx3_gpio_irq_handler);
			irq_set_handler_data(port->irq_high, port);
		}
	}

	err = bgpio_init(&port->bgc, &pdev->dev, 4,
			 port->base + GPIO_PSR,
			 port->base + GPIO_DR, NULL,
			 port->base + GPIO_GDIR, NULL, false);
	if (err)
		goto out_iounmap;

	port->bgc.gc.base = pdev->id * 32;
	port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
	port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		goto out_bgpio_remove;

	/*
	 * In dt case, we use gpio number range dynamically
	 * allocated by gpio core.
	 */
	port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
							     pdev->id * 32);

	/* gpio-mxc can be a generic irq chip */
	mxc_gpio_init_gc(port);

	list_add_tail(&port->node, &mxc_gpio_ports);

	return 0;

out_bgpio_remove:
	bgpio_remove(&port->bgc);
out_iounmap:
	iounmap(port->base);
out_release_mem:
	release_mem_region(iores->start, resource_size(iores));
out_kfree:
	kfree(port);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	return err;
}

static struct platform_driver mxc_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxc",
		.owner	= THIS_MODULE,
		.of_match_table = mxc_gpio_dt_ids,
	},
	.probe		= mxc_gpio_probe,
	.id_table	= mxc_gpio_devtype,
};

static int __init gpio_mxc_init(void)
{
	return platform_driver_register(&mxc_gpio_driver);
}
postcore_initcall(gpio_mxc_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXC GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
07bd1a6c JB	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* Based on code from Freescale,
e24798e6	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
07bd1a6c JB	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*/
	21
	22	#include <linux/init.h>
a3484ffd	23	#include <linux/interrupt.h>
07bd1a6c JB	24	#include <linux/io.h>
	25	#include <linux/irq.h>
	26	#include <linux/gpio.h>
b78d8e59 SG	27	#include <linux/platform_device.h>
b78d8e59 SG	28	#include <linux/slab.h>
2ce420da	29	#include <linux/basic_mmio_gpio.h>
8937cb60 SG	30	#include <linux/of.h>
8937cb60 SG	31	#include <linux/of_device.h>
07bd1a6c	32	#include <asm-generic/bug.h>
0e44b6ec	33	#include <asm/mach/irq.h>
07bd1a6c	34
e7fc6ae7 SG	35	enum mxc_gpio_hwtype {
	36	IMX1_GPIO, /* runs on i.mx1 */
	37	IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
	38	IMX31_GPIO, /* runs on all other i.mx */
	39	};
	40
	41	/* device type dependent stuff */
	42	struct mxc_gpio_hwdata {
	43	unsigned dr_reg;
	44	unsigned gdir_reg;
	45	unsigned psr_reg;
	46	unsigned icr1_reg;
	47	unsigned icr2_reg;
	48	unsigned imr_reg;
	49	unsigned isr_reg;
	50	unsigned low_level;
	51	unsigned high_level;
	52	unsigned rise_edge;
	53	unsigned fall_edge;
	54	};
	55
b78d8e59 SG	56	struct mxc_gpio_port {
	57	struct list_head node;
	58	void __iomem *base;
	59	int irq;
	60	int irq_high;
	61	int virtual_irq_start;
2ce420da	62	struct bgpio_chip bgc;
b78d8e59	63	u32 both_edges;
b78d8e59 SG	64	};
b78d8e59 SG	65
e7fc6ae7 SG	66	static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	67	.dr_reg = 0x1c,
	68	.gdir_reg = 0x00,
	69	.psr_reg = 0x24,
	70	.icr1_reg = 0x28,
	71	.icr2_reg = 0x2c,
	72	.imr_reg = 0x30,
	73	.isr_reg = 0x34,
	74	.low_level = 0x03,
	75	.high_level = 0x02,
	76	.rise_edge = 0x00,
	77	.fall_edge = 0x01,
	78	};
	79
	80	static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	81	.dr_reg = 0x00,
	82	.gdir_reg = 0x04,
	83	.psr_reg = 0x08,
	84	.icr1_reg = 0x0c,
	85	.icr2_reg = 0x10,
	86	.imr_reg = 0x14,
	87	.isr_reg = 0x18,
	88	.low_level = 0x00,
	89	.high_level = 0x01,
	90	.rise_edge = 0x02,
	91	.fall_edge = 0x03,
	92	};
	93
	94	static enum mxc_gpio_hwtype mxc_gpio_hwtype;
	95	static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
	96
	97	#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
	98	#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
	99	#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
	100	#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
	101	#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
	102	#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
	103	#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
	104
	105	#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
	106	#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
	107	#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
	108	#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
	109	#define GPIO_INT_NONE 0x4
	110
	111	static struct platform_device_id mxc_gpio_devtype[] = {
	112	{
	113	.name = "imx1-gpio",
	114	.driver_data = IMX1_GPIO,
	115	}, {
	116	.name = "imx21-gpio",
	117	.driver_data = IMX21_GPIO,
	118	}, {
	119	.name = "imx31-gpio",
	120	.driver_data = IMX31_GPIO,
	121	}, {
	122	/* sentinel */
	123	}
	124	};
	125
8937cb60 SG	126	static const struct of_device_id mxc_gpio_dt_ids[] = {
	127	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
	128	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
	129	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
	130	{ /* sentinel */ }
	131	};
	132
b78d8e59 SG	133	/*
	134	* MX2 has one interrupt for all gpio ports. The list is used
	135	* to save the references to all ports, so that mx2_gpio_irq_handler
	136	* can walk through all interrupt status registers.
	137	*/
	138	static LIST_HEAD(mxc_gpio_ports);
07bd1a6c JB	139
	140	/* Note: This driver assumes 32 GPIOs are handled in one register */
	141
4d93579f	142	static int gpio_set_irq_type(struct irq_data *d, u32 type)
07bd1a6c	143	{
4d93579f	144	u32 gpio = irq_to_gpio(d->irq);
e4ea9333 SG	145	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	146	struct mxc_gpio_port *port = gc->private;
07bd1a6c JB	147	u32 bit, val;
	148	int edge;
	149	void __iomem *reg = port->base;
	150
910862ec	151	port->both_edges &= ~(1 << (gpio & 31));
07bd1a6c	152	switch (type) {
6cab4860	153	case IRQ_TYPE_EDGE_RISING:
07bd1a6c JB	154	edge = GPIO_INT_RISE_EDGE;
07bd1a6c JB	155	break;
6cab4860	156	case IRQ_TYPE_EDGE_FALLING:
07bd1a6c JB	157	edge = GPIO_INT_FALL_EDGE;
07bd1a6c JB	158	break;
910862ec	159	case IRQ_TYPE_EDGE_BOTH:
5523f86b	160	val = gpio_get_value(gpio);
910862ec GL	161	if (val) {
	162	edge = GPIO_INT_LOW_LEV;
	163	pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
	164	} else {
	165	edge = GPIO_INT_HIGH_LEV;
	166	pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
	167	}
	168	port->both_edges \|= 1 << (gpio & 31);
	169	break;
6cab4860	170	case IRQ_TYPE_LEVEL_LOW:
07bd1a6c JB	171	edge = GPIO_INT_LOW_LEV;
07bd1a6c JB	172	break;
6cab4860	173	case IRQ_TYPE_LEVEL_HIGH:
07bd1a6c JB	174	edge = GPIO_INT_HIGH_LEV;
07bd1a6c JB	175	break;
910862ec	176	default:
07bd1a6c JB	177	return -EINVAL;
	178	}
	179
	180	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	181	bit = gpio & 0xf;
b78d8e59 SG	182	val = readl(reg) & ~(0x3 << (bit << 1));
b78d8e59 SG	183	writel(val \| (edge << (bit << 1)), reg);
e4ea9333	184	writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
07bd1a6c JB	185
	186	return 0;
	187	}
	188
910862ec GL	189	static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
	190	{
	191	void __iomem *reg = port->base;
	192	u32 bit, val;
	193	int edge;
	194
	195	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	196	bit = gpio & 0xf;
b78d8e59	197	val = readl(reg);
910862ec GL	198	edge = (val >> (bit << 1)) & 3;
910862ec GL	199	val &= ~(0x3 << (bit << 1));
3d40f7fe	200	if (edge == GPIO_INT_HIGH_LEV) {
910862ec GL	201	edge = GPIO_INT_LOW_LEV;
910862ec GL	202	pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
3d40f7fe	203	} else if (edge == GPIO_INT_LOW_LEV) {
910862ec GL	204	edge = GPIO_INT_HIGH_LEV;
910862ec GL	205	pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
3d40f7fe	206	} else {
910862ec GL	207	pr_err("mxc: invalid configuration for GPIO %d: %x\n",
	208	gpio, edge);
	209	return;
	210	}
b78d8e59	211	writel(val \| (edge << (bit << 1)), reg);
910862ec GL	212	}
910862ec GL	213
3621f188	214	/* handle 32 interrupts in one status register */
07bd1a6c JB	215	static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
07bd1a6c JB	216	{
3621f188	217	u32 gpio_irq_no_base = port->virtual_irq_start;
07bd1a6c	218
3621f188 UKK	219	while (irq_stat != 0) {
3621f188 UKK	220	int irqoffset = fls(irq_stat) - 1;
07bd1a6c	221
3621f188 UKK	222	if (port->both_edges & (1 << irqoffset))
3621f188 UKK	223	mxc_flip_edge(port, irqoffset);
910862ec	224
3621f188	225	generic_handle_irq(gpio_irq_no_base + irqoffset);
910862ec	226
3621f188	227	irq_stat &= ~(1 << irqoffset);
07bd1a6c JB	228	}
	229	}
	230
cfca8b53	231	/* MX1 and MX3 has one interrupt per gpio port */
07bd1a6c JB	232	static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	233	{
	234	u32 irq_stat;
6845664a	235	struct mxc_gpio_port *port = irq_get_handler_data(irq);
0e44b6ec SG	236	struct irq_chip *chip = irq_get_chip(irq);
	237
	238	chained_irq_enter(chip, desc);
07bd1a6c	239
b78d8e59	240	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
e2c97e7f	241
07bd1a6c	242	mxc_gpio_irq_handler(port, irq_stat);
0e44b6ec SG	243
0e44b6ec SG	244	chained_irq_exit(chip, desc);
07bd1a6c	245	}
07bd1a6c	246
07bd1a6c JB	247	/* MX2 has one interrupt for all gpio ports */
	248	static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	249	{
07bd1a6c	250	u32 irq_msk, irq_stat;
b78d8e59	251	struct mxc_gpio_port *port;
07bd1a6c JB	252
07bd1a6c JB	253	/* walk through all interrupt status registers */
b78d8e59 SG	254	list_for_each_entry(port, &mxc_gpio_ports, node) {
b78d8e59 SG	255	irq_msk = readl(port->base + GPIO_IMR);
07bd1a6c JB	256	if (!irq_msk)
	257	continue;
	258
b78d8e59	259	irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
07bd1a6c	260	if (irq_stat)
b78d8e59	261	mxc_gpio_irq_handler(port, irq_stat);
07bd1a6c JB	262	}
07bd1a6c JB	263	}
07bd1a6c	264
a3484ffd DN	265	/*
	266	* Set interrupt number "irq" in the GPIO as a wake-up source.
	267	* While system is running, all registered GPIO interrupts need to have
	268	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	269	* need to have wake-up enabled.
	270	* @param irq interrupt source number
	271	* @param enable enable as wake-up if equal to non-zero
	272	* @return This function returns 0 on success.
	273	*/
4d93579f	274	static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
a3484ffd	275	{
4d93579f	276	u32 gpio = irq_to_gpio(d->irq);
a3484ffd	277	u32 gpio_idx = gpio & 0x1F;
e4ea9333 SG	278	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	279	struct mxc_gpio_port *port = gc->private;
a3484ffd DN	280
	281	if (enable) {
	282	if (port->irq_high && (gpio_idx >= 16))
	283	enable_irq_wake(port->irq_high);
	284	else
	285	enable_irq_wake(port->irq);
	286	} else {
	287	if (port->irq_high && (gpio_idx >= 16))
	288	disable_irq_wake(port->irq_high);
	289	else
	290	disable_irq_wake(port->irq);
	291	}
	292
	293	return 0;
	294	}
	295
e4ea9333 SG	296	static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
	297	{
	298	struct irq_chip_generic *gc;
	299	struct irq_chip_type *ct;
	300
	301	gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
	302	port->base, handle_level_irq);
	303	gc->private = port;
	304
	305	ct = gc->chip_types;
591567a5	306	ct->chip.irq_ack = irq_gc_ack_set_bit;
e4ea9333 SG	307	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	308	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	309	ct->chip.irq_set_type = gpio_set_irq_type;
591567a5	310	ct->chip.irq_set_wake = gpio_set_wake_irq;
e4ea9333 SG	311	ct->regs.ack = GPIO_ISR;
	312	ct->regs.mask = GPIO_IMR;
	313
	314	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
	315	IRQ_NOREQUEST, 0);
	316	}
b5eee2fd	317
e7fc6ae7 SG	318	static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
e7fc6ae7 SG	319	{
8937cb60 SG	320	const struct of_device_id *of_id =
	321	of_match_device(mxc_gpio_dt_ids, &pdev->dev);
	322	enum mxc_gpio_hwtype hwtype;
	323
	324	if (of_id)
	325	pdev->id_entry = of_id->data;
	326	hwtype = pdev->id_entry->driver_data;
e7fc6ae7 SG	327
	328	if (mxc_gpio_hwtype) {
	329	/*
	330	* The driver works with a reasonable presupposition,
	331	* that is all gpio ports must be the same type when
	332	* running on one soc.
	333	*/
	334	BUG_ON(mxc_gpio_hwtype != hwtype);
	335	return;
	336	}
	337
	338	if (hwtype == IMX31_GPIO)
	339	mxc_gpio_hwdata = &imx31_gpio_hwdata;
	340	else
	341	mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
	342
	343	mxc_gpio_hwtype = hwtype;
	344	}
	345
b78d8e59	346	static int __devinit mxc_gpio_probe(struct platform_device *pdev)
07bd1a6c	347	{
8937cb60	348	struct device_node *np = pdev->dev.of_node;
b78d8e59 SG	349	struct mxc_gpio_port *port;
b78d8e59 SG	350	struct resource *iores;
e4ea9333	351	int err;
b78d8e59	352
e7fc6ae7 SG	353	mxc_gpio_get_hw(pdev);
e7fc6ae7 SG	354
b78d8e59 SG	355	port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
	356	if (!port)
	357	return -ENOMEM;
07bd1a6c	358
b78d8e59 SG	359	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	360	if (!iores) {
	361	err = -ENODEV;
	362	goto out_kfree;
	363	}
14cb0deb	364
b78d8e59 SG	365	if (!request_mem_region(iores->start, resource_size(iores),
	366	pdev->name)) {
	367	err = -EBUSY;
	368	goto out_kfree;
	369	}
07bd1a6c	370
b78d8e59 SG	371	port->base = ioremap(iores->start, resource_size(iores));
	372	if (!port->base) {
	373	err = -ENOMEM;
	374	goto out_release_mem;
	375	}
	376
	377	port->irq_high = platform_get_irq(pdev, 1);
	378	port->irq = platform_get_irq(pdev, 0);
	379	if (port->irq < 0) {
	380	err = -EINVAL;
	381	goto out_iounmap;
	382	}
	383
	384	/* disable the interrupt and clear the status */
	385	writel(0, port->base + GPIO_IMR);
	386	writel(~0, port->base + GPIO_ISR);
	387
e7fc6ae7	388	if (mxc_gpio_hwtype == IMX21_GPIO) {
8afaada2	389	/* setup one handler for all GPIO interrupts */
b78d8e59 SG	390	if (pdev->id == 0)
	391	irq_set_chained_handler(port->irq,
	392	mx2_gpio_irq_handler);
	393	} else {
	394	/* setup one handler for each entry */
	395	irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
	396	irq_set_handler_data(port->irq, port);
	397	if (port->irq_high > 0) {
	398	/* setup handler for GPIO 16 to 31 */
	399	irq_set_chained_handler(port->irq_high,
	400	mx3_gpio_irq_handler);
	401	irq_set_handler_data(port->irq_high, port);
	402	}
07bd1a6c JB	403	}
07bd1a6c JB	404
2ce420da SG	405	err = bgpio_init(&port->bgc, &pdev->dev, 4,
	406	port->base + GPIO_PSR,
	407	port->base + GPIO_DR, NULL,
	408	port->base + GPIO_GDIR, NULL, false);
	409	if (err)
	410	goto out_iounmap;
b78d8e59	411
2ce420da	412	port->bgc.gc.base = pdev->id * 32;
fb149218 LW	413	port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
fb149218 LW	414	port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
b78d8e59	415
2ce420da	416	err = gpiochip_add(&port->bgc.gc);
b78d8e59	417	if (err)
2ce420da	418	goto out_bgpio_remove;
b78d8e59	419
8937cb60 SG	420	/*
	421	* In dt case, we use gpio number range dynamically
	422	* allocated by gpio core.
	423	*/
	424	port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
	425	pdev->id * 32);
	426
	427	/* gpio-mxc can be a generic irq chip */
	428	mxc_gpio_init_gc(port);
	429
b78d8e59 SG	430	list_add_tail(&port->node, &mxc_gpio_ports);
b78d8e59 SG	431
07bd1a6c	432	return 0;
b78d8e59	433
2ce420da SG	434	out_bgpio_remove:
2ce420da SG	435	bgpio_remove(&port->bgc);
b78d8e59 SG	436	out_iounmap:
	437	iounmap(port->base);
	438	out_release_mem:
	439	release_mem_region(iores->start, resource_size(iores));
	440	out_kfree:
	441	kfree(port);
	442	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	443	return err;
07bd1a6c	444	}
b78d8e59 SG	445
	446	static struct platform_driver mxc_gpio_driver = {
	447	.driver = {
	448	.name = "gpio-mxc",
	449	.owner = THIS_MODULE,
8937cb60	450	.of_match_table = mxc_gpio_dt_ids,
b78d8e59 SG	451	},
b78d8e59 SG	452	.probe = mxc_gpio_probe,
e7fc6ae7	453	.id_table = mxc_gpio_devtype,
b78d8e59 SG	454	};
	455
	456	static int __init gpio_mxc_init(void)
	457	{
	458	return platform_driver_register(&mxc_gpio_driver);
	459	}
	460	postcore_initcall(gpio_mxc_init);
	461
	462	MODULE_AUTHOR("Freescale Semiconductor, "
	463	"Daniel Mack <danielncaiaq.de>, "
	464	"Juergen Beisert <kernel@pengutronix.de>");
	465	MODULE_DESCRIPTION("Freescale MXC GPIO");
	466	MODULE_LICENSE("GPL");