[deliverable/linux.git] / drivers / gpio / gpio-mxs.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>
#include <linux/module.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
#define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
#define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
#define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
#define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
#define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
#define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
#define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

#define irq_to_gpio(irq)	((irq) - MXS_GPIO_IRQ_START)

enum mxs_gpio_id {
	IMX23_GPIO,
	IMX28_GPIO,
};

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	int virtual_irq_start;
	struct bgpio_chip bgc;
	enum mxs_gpio_id devid;
};

static inline int is_imx23_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX23_GPIO;
}

static inline int is_imx28_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX28_GPIO;
}

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 gpio = irq_to_gpio(d->irq);
	u32 pin_mask = 1 << (gpio & 31);
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;
	void __iomem *pin_addr;
	int edge;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port);
	if (edge & GPIO_INT_LEV_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	writel(1 << (gpio & 0x1f),
	       port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	return 0;
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_get_handler_data(irq);
	u32 gpio_irq_no_base = port->virtual_irq_start;

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
			readl(port->base + PINCTRL_IRQEN(port));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		generic_handle_irq(gpio_irq_no_base + irqoffset);
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
				    port->base, handle_level_irq);
	gc->private = port;

	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.mask = PINCTRL_IRQEN(port);

	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}

static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct mxs_gpio_port *port =
		container_of(bgc, struct mxs_gpio_port, bgc);

	return port->virtual_irq_start + offset;
}

static struct platform_device_id mxs_gpio_ids[] = {
	{
		.name = "imx23-gpio",
		.driver_data = IMX23_GPIO,
	}, {
		.name = "imx28-gpio",
		.driver_data = IMX28_GPIO,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);

static const struct of_device_id mxs_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);

static int __devinit mxs_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_gpio_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct device_node *parent;
	static void __iomem *base;
	struct mxs_gpio_port *port;
	struct resource *iores = NULL;
	int err;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	if (np) {
		port->id = of_alias_get_id(np, "gpio");
		if (port->id < 0)
			return port->id;
		port->devid = (enum mxs_gpio_id) of_id->data;
	} else {
		port->id = pdev->id;
		port->devid = pdev->id_entry->driver_data;
	}
	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		if (np) {
			parent = of_get_parent(np);
			base = of_iomap(parent, 0);
			of_node_put(parent);
		} else {
			iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
			base = devm_request_and_ioremap(&pdev->dev, iores);
		}
		if (!base)
			return -EADDRNOTAVAIL;
	}
	port->base = base;

	/*
	 * select the pin interrupt functionality but initially
	 * disable the interrupts
	 */
	writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
	writel(0, port->base + PINCTRL_IRQEN(port));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	/* gpio-mxs can be a generic irq chip */
	mxs_gpio_init_gc(port);

	/* setup one handler for each entry */
	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
	irq_set_handler_data(port->irq, port);

	err = bgpio_init(&port->bgc, &pdev->dev, 4,
			 port->base + PINCTRL_DIN(port),
			 port->base + PINCTRL_DOUT(port), NULL,
			 port->base + PINCTRL_DOE(port), NULL, 0);
	if (err)
		return err;

	port->bgc.gc.to_irq = mxs_gpio_to_irq;
	port->bgc.gc.base = port->id * 32;

	err = gpiochip_add(&port->bgc.gc);
	if (err) {
		bgpio_remove(&port->bgc);
		return err;
	}

	return 0;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.owner	= THIS_MODULE,
		.of_match_table = mxs_gpio_dt_ids,
	},
	.probe		= mxs_gpio_probe,
	.id_table	= mxs_gpio_ids,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
fba311fc SG	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* Based on code from Freescale,
	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
	23	#include <linux/init.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/gpio.h>
4052d45e SG	28	#include <linux/of.h>
	29	#include <linux/of_address.h>
	30	#include <linux/of_device.h>
8d7cf837 SG	31	#include <linux/platform_device.h>
8d7cf837 SG	32	#include <linux/slab.h>
06f88a8a	33	#include <linux/basic_mmio_gpio.h>
bb207ef1	34	#include <linux/module.h>
fba311fc	35
8d7cf837 SG	36	#define MXS_SET 0x4
8d7cf837 SG	37	#define MXS_CLR 0x8
fba311fc	38
164387d2 SG	39	#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
	40	#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
	41	#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
	42	#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
	43	#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
	44	#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
	45	#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
	46	#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
fba311fc SG	47
	48	#define GPIO_INT_FALL_EDGE 0x0
	49	#define GPIO_INT_LOW_LEV 0x1
	50	#define GPIO_INT_RISE_EDGE 0x2
	51	#define GPIO_INT_HIGH_LEV 0x3
	52	#define GPIO_INT_LEV_MASK (1 << 0)
	53	#define GPIO_INT_POL_MASK (1 << 1)
	54
7e6c53aa SG	55	#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
7e6c53aa SG	56
164387d2 SG	57	enum mxs_gpio_id {
	58	IMX23_GPIO,
	59	IMX28_GPIO,
	60	};
	61
7b2fa570 GL	62	struct mxs_gpio_port {
	63	void __iomem *base;
	64	int id;
	65	int irq;
7b2fa570	66	int virtual_irq_start;
06f88a8a	67	struct bgpio_chip bgc;
164387d2	68	enum mxs_gpio_id devid;
7b2fa570 GL	69	};
7b2fa570 GL	70
164387d2 SG	71	static inline int is_imx23_gpio(struct mxs_gpio_port *port)
	72	{
	73	return port->devid == IMX23_GPIO;
	74	}
	75
	76	static inline int is_imx28_gpio(struct mxs_gpio_port *port)
	77	{
	78	return port->devid == IMX28_GPIO;
	79	}
	80
fba311fc SG	81	/* Note: This driver assumes 32 GPIOs are handled in one register */
fba311fc SG	82
bf0c1118	83	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	84	{
bf0c1118	85	u32 gpio = irq_to_gpio(d->irq);
fba311fc	86	u32 pin_mask = 1 << (gpio & 31);
498c17cf SG	87	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	88	struct mxs_gpio_port *port = gc->private;
fba311fc SG	89	void __iomem *pin_addr;
	90	int edge;
	91
	92	switch (type) {
	93	case IRQ_TYPE_EDGE_RISING:
	94	edge = GPIO_INT_RISE_EDGE;
	95	break;
	96	case IRQ_TYPE_EDGE_FALLING:
	97	edge = GPIO_INT_FALL_EDGE;
	98	break;
	99	case IRQ_TYPE_LEVEL_LOW:
	100	edge = GPIO_INT_LOW_LEV;
	101	break;
	102	case IRQ_TYPE_LEVEL_HIGH:
	103	edge = GPIO_INT_HIGH_LEV;
	104	break;
	105	default:
	106	return -EINVAL;
	107	}
	108
	109	/* set level or edge */
164387d2	110	pin_addr = port->base + PINCTRL_IRQLEV(port);
fba311fc	111	if (edge & GPIO_INT_LEV_MASK)
8d7cf837	112	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	113	else
8d7cf837	114	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc SG	115
fba311fc SG	116	/* set polarity */
164387d2	117	pin_addr = port->base + PINCTRL_IRQPOL(port);
fba311fc	118	if (edge & GPIO_INT_POL_MASK)
8d7cf837	119	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	120	else
8d7cf837	121	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc	122
498c17cf	123	writel(1 << (gpio & 0x1f),
164387d2	124	port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc SG	125
	126	return 0;
	127	}
	128
	129	/* MXS has one interrupt per gpio port */
	130	static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	131	{
	132	u32 irq_stat;
8d7cf837	133	struct mxs_gpio_port *port = irq_get_handler_data(irq);
fba311fc SG	134	u32 gpio_irq_no_base = port->virtual_irq_start;
fba311fc SG	135
1f6b5dd4 UKK	136	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	137
164387d2 SG	138	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
164387d2 SG	139	readl(port->base + PINCTRL_IRQEN(port));
fba311fc SG	140
	141	while (irq_stat != 0) {
	142	int irqoffset = fls(irq_stat) - 1;
	143	generic_handle_irq(gpio_irq_no_base + irqoffset);
	144	irq_stat &= ~(1 << irqoffset);
	145	}
	146	}
	147
	148	/*
	149	* Set interrupt number "irq" in the GPIO as a wake-up source.
	150	* While system is running, all registered GPIO interrupts need to have
	151	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	152	* need to have wake-up enabled.
	153	* @param irq interrupt source number
	154	* @param enable enable as wake-up if equal to non-zero
	155	* @return This function returns 0 on success.
	156	*/
bf0c1118	157	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	158	{
498c17cf SG	159	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	160	struct mxs_gpio_port *port = gc->private;
fba311fc	161
6161715e SG	162	if (enable)
	163	enable_irq_wake(port->irq);
	164	else
	165	disable_irq_wake(port->irq);
fba311fc SG	166
	167	return 0;
	168	}
	169
498c17cf SG	170	static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
	171	{
	172	struct irq_chip_generic *gc;
	173	struct irq_chip_type *ct;
	174
	175	gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
	176	port->base, handle_level_irq);
	177	gc->private = port;
	178
	179	ct = gc->chip_types;
591567a5	180	ct->chip.irq_ack = irq_gc_ack_set_bit;
498c17cf SG	181	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	182	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	183	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
591567a5	184	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
164387d2 SG	185	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
164387d2 SG	186	ct->regs.mask = PINCTRL_IRQEN(port);
498c17cf SG	187
	188	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
	189	}
fba311fc	190
06f88a8a	191	static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
fba311fc	192	{
06f88a8a	193	struct bgpio_chip *bgc = to_bgpio_chip(gc);
fba311fc	194	struct mxs_gpio_port *port =
06f88a8a	195	container_of(bgc, struct mxs_gpio_port, bgc);
fba311fc SG	196
	197	return port->virtual_irq_start + offset;
	198	}
	199
164387d2 SG	200	static struct platform_device_id mxs_gpio_ids[] = {
	201	{
	202	.name = "imx23-gpio",
	203	.driver_data = IMX23_GPIO,
	204	}, {
	205	.name = "imx28-gpio",
	206	.driver_data = IMX28_GPIO,
	207	}, {
	208	/* sentinel */
	209	}
	210	};
	211	MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
	212
4052d45e SG	213	static const struct of_device_id mxs_gpio_dt_ids[] = {
	214	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	215	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	216	{ /* sentinel */ }
	217	};
	218	MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
	219
8d7cf837	220	static int __devinit mxs_gpio_probe(struct platform_device *pdev)
fba311fc	221	{
4052d45e SG	222	const struct of_device_id *of_id =
	223	of_match_device(mxs_gpio_dt_ids, &pdev->dev);
	224	struct device_node *np = pdev->dev.of_node;
	225	struct device_node *parent;
8d7cf837 SG	226	static void __iomem *base;
	227	struct mxs_gpio_port *port;
	228	struct resource *iores = NULL;
498c17cf	229	int err;
8d7cf837	230
940a4f7b	231	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
8d7cf837 SG	232	if (!port)
	233	return -ENOMEM;
	234
4052d45e SG	235	if (np) {
	236	port->id = of_alias_get_id(np, "gpio");
	237	if (port->id < 0)
	238	return port->id;
	239	port->devid = (enum mxs_gpio_id) of_id->data;
	240	} else {
	241	port->id = pdev->id;
	242	port->devid = pdev->id_entry->driver_data;
	243	}
8d7cf837 SG	244	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
8d7cf837 SG	245
940a4f7b SG	246	port->irq = platform_get_irq(pdev, 0);
	247	if (port->irq < 0)
	248	return port->irq;
	249
8d7cf837 SG	250	/*
	251	* map memory region only once, as all the gpio ports
	252	* share the same one
	253	*/
	254	if (!base) {
4052d45e SG	255	if (np) {
	256	parent = of_get_parent(np);
	257	base = of_iomap(parent, 0);
	258	of_node_put(parent);
	259	} else {
	260	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	261	base = devm_request_and_ioremap(&pdev->dev, iores);
8d7cf837	262	}
940a4f7b SG	263	if (!base)
940a4f7b SG	264	return -EADDRNOTAVAIL;
8d7cf837 SG	265	}
8d7cf837 SG	266	port->base = base;
fba311fc	267
498c17cf SG	268	/*
	269	* select the pin interrupt functionality but initially
	270	* disable the interrupts
	271	*/
164387d2 SG	272	writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
164387d2 SG	273	writel(0, port->base + PINCTRL_IRQEN(port));
fba311fc	274
8d7cf837	275	/* clear address has to be used to clear IRQSTAT bits */
164387d2	276	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc	277
498c17cf SG	278	/* gpio-mxs can be a generic irq chip */
498c17cf SG	279	mxs_gpio_init_gc(port);
fba311fc	280
8d7cf837 SG	281	/* setup one handler for each entry */
	282	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
	283	irq_set_handler_data(port->irq, port);
fba311fc	284
06f88a8a	285	err = bgpio_init(&port->bgc, &pdev->dev, 4,
164387d2 SG	286	port->base + PINCTRL_DIN(port),
164387d2 SG	287	port->base + PINCTRL_DOUT(port), NULL,
84a442b9	288	port->base + PINCTRL_DOE(port), NULL, 0);
8d7cf837	289	if (err)
940a4f7b	290	return err;
fba311fc	291
06f88a8a SG	292	port->bgc.gc.to_irq = mxs_gpio_to_irq;
	293	port->bgc.gc.base = port->id * 32;
	294
	295	err = gpiochip_add(&port->bgc.gc);
940a4f7b SG	296	if (err) {
	297	bgpio_remove(&port->bgc);
	298	return err;
	299	}
06f88a8a	300
8d7cf837	301	return 0;
ef19660b	302	}
8d7cf837 SG	303
	304	static struct platform_driver mxs_gpio_driver = {
	305	.driver = {
	306	.name = "gpio-mxs",
	307	.owner = THIS_MODULE,
4052d45e	308	.of_match_table = mxs_gpio_dt_ids,
8d7cf837 SG	309	},
8d7cf837 SG	310	.probe = mxs_gpio_probe,
164387d2	311	.id_table = mxs_gpio_ids,
fba311fc	312	};
ef19660b	313
8d7cf837	314	static int __init mxs_gpio_init(void)
ef19660b	315	{
8d7cf837	316	return platform_driver_register(&mxs_gpio_driver);
ef19660b	317	}
8d7cf837 SG	318	postcore_initcall(mxs_gpio_init);
	319
	320	MODULE_AUTHOR("Freescale Semiconductor, "
	321	"Daniel Mack <danielncaiaq.de>, "
	322	"Juergen Beisert <kernel@pengutronix.de>");
	323	MODULE_DESCRIPTION("Freescale MXS GPIO");
	324	MODULE_LICENSE("GPL");