[deliverable/linux.git] / drivers / gpio / gpio-mxs.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>
#include <mach/mxs.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(n)		((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
#define PINCTRL_DIN(n)		((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
#define PINCTRL_DOE(n)		((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
#define PINCTRL_PIN2IRQ(n)	((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
#define PINCTRL_IRQEN(n)	((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
#define PINCTRL_IRQLEV(n)	((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
#define PINCTRL_IRQPOL(n)	((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
#define PINCTRL_IRQSTAT(n)	((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	int irq_high;
	int virtual_irq_start;
	struct bgpio_chip bgc;
};

/* Note: This driver assumes 32 GPIOs are handled in one register */

static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
{
	writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
}

static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
				int enable)
{
	if (enable) {
		writel(1 << index,
			port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
		writel(1 << index,
			port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
	} else {
		writel(1 << index,
			port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
	}
}

static void mxs_gpio_ack_irq(struct irq_data *d)
{
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	u32 gpio = irq_to_gpio(d->irq);
	clear_gpio_irqstatus(port, gpio & 0x1f);
}

static void mxs_gpio_mask_irq(struct irq_data *d)
{
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	u32 gpio = irq_to_gpio(d->irq);
	set_gpio_irqenable(port, gpio & 0x1f, 0);
}

static void mxs_gpio_unmask_irq(struct irq_data *d)
{
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	u32 gpio = irq_to_gpio(d->irq);
	set_gpio_irqenable(port, gpio & 0x1f, 1);
}

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 gpio = irq_to_gpio(d->irq);
	u32 pin_mask = 1 << (gpio & 31);
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	void __iomem *pin_addr;
	int edge;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port->id);
	if (edge & GPIO_INT_LEV_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port->id);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	clear_gpio_irqstatus(port, gpio & 0x1f);

	return 0;
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_get_handler_data(irq);
	u32 gpio_irq_no_base = port->virtual_irq_start;

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
			readl(port->base + PINCTRL_IRQEN(port->id));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		generic_handle_irq(gpio_irq_no_base + irqoffset);
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	u32 gpio = irq_to_gpio(d->irq);
	u32 gpio_idx = gpio & 0x1f;
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);

	if (enable) {
		if (port->irq_high && (gpio_idx >= 16))
			enable_irq_wake(port->irq_high);
		else
			enable_irq_wake(port->irq);
	} else {
		if (port->irq_high && (gpio_idx >= 16))
			disable_irq_wake(port->irq_high);
		else
			disable_irq_wake(port->irq);
	}

	return 0;
}

static struct irq_chip gpio_irq_chip = {
	.name = "mxs gpio",
	.irq_ack = mxs_gpio_ack_irq,
	.irq_mask = mxs_gpio_mask_irq,
	.irq_unmask = mxs_gpio_unmask_irq,
	.irq_set_type = mxs_gpio_set_irq_type,
	.irq_set_wake = mxs_gpio_set_wake_irq,
};

static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct mxs_gpio_port *port =
		container_of(bgc, struct mxs_gpio_port, bgc);

	return port->virtual_irq_start + offset;
}

static int __devinit mxs_gpio_probe(struct platform_device *pdev)
{
	static void __iomem *base;
	struct mxs_gpio_port *port;
	struct resource *iores = NULL;
	int err, i;

	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->id = pdev->id;
	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!iores) {
			err = -ENODEV;
			goto out_kfree;
		}

		if (!request_mem_region(iores->start, resource_size(iores),
					pdev->name)) {
			err = -EBUSY;
			goto out_kfree;
		}

		base = ioremap(iores->start, resource_size(iores));
		if (!base) {
			err = -ENOMEM;
			goto out_release_mem;
		}
	}
	port->base = base;

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0) {
		err = -EINVAL;
		goto out_iounmap;
	}

	/* disable the interrupt and clear the status */
	writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
	writel(0, port->base + PINCTRL_IRQEN(port->id));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);

	for (i = port->virtual_irq_start;
		i < port->virtual_irq_start + 32; i++) {
		irq_set_chip_and_handler(i, &gpio_irq_chip,
					 handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
		irq_set_chip_data(i, port);
	}

	/* setup one handler for each entry */
	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
	irq_set_handler_data(port->irq, port);

	err = bgpio_init(&port->bgc, &pdev->dev, 4,
			 port->base + PINCTRL_DIN(port->id),
			 port->base + PINCTRL_DOUT(port->id), NULL,
			 port->base + PINCTRL_DOE(port->id), NULL, false);
	if (err)
		goto out_iounmap;

	port->bgc.gc.to_irq = mxs_gpio_to_irq;
	port->bgc.gc.base = port->id * 32;

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		goto out_bgpio_remove;

	return 0;

out_bgpio_remove:
	bgpio_remove(&port->bgc);
out_iounmap:
	if (iores)
		iounmap(port->base);
out_release_mem:
	if (iores)
		release_mem_region(iores->start, resource_size(iores));
out_kfree:
	kfree(port);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	return err;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.owner	= THIS_MODULE,
	},
	.probe		= mxs_gpio_probe,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
fba311fc SG	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* Based on code from Freescale,
	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
	23	#include <linux/init.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/gpio.h>
8d7cf837 SG	28	#include <linux/platform_device.h>
8d7cf837 SG	29	#include <linux/slab.h>
06f88a8a	30	#include <linux/basic_mmio_gpio.h>
8d7cf837	31	#include <mach/mxs.h>
fba311fc	32
8d7cf837 SG	33	#define MXS_SET 0x4
8d7cf837 SG	34	#define MXS_CLR 0x8
fba311fc SG	35
	36	#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
	37	#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
	38	#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
	39	#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
	40	#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
	41	#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
	42	#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
	43	#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
	44
	45	#define GPIO_INT_FALL_EDGE 0x0
	46	#define GPIO_INT_LOW_LEV 0x1
	47	#define GPIO_INT_RISE_EDGE 0x2
	48	#define GPIO_INT_HIGH_LEV 0x3
	49	#define GPIO_INT_LEV_MASK (1 << 0)
	50	#define GPIO_INT_POL_MASK (1 << 1)
	51
7b2fa570 GL	52	struct mxs_gpio_port {
	53	void __iomem *base;
	54	int id;
	55	int irq;
	56	int irq_high;
	57	int virtual_irq_start;
06f88a8a	58	struct bgpio_chip bgc;
7b2fa570 GL	59	};
7b2fa570 GL	60
fba311fc SG	61	/* Note: This driver assumes 32 GPIOs are handled in one register */
	62
	63	static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
	64	{
8d7cf837	65	writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
fba311fc SG	66	}
	67
	68	static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
	69	int enable)
	70	{
	71	if (enable) {
8d7cf837 SG	72	writel(1 << index,
	73	port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
	74	writel(1 << index,
	75	port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
fba311fc	76	} else {
8d7cf837 SG	77	writel(1 << index,
8d7cf837 SG	78	port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
fba311fc SG	79	}
	80	}
	81
bf0c1118	82	static void mxs_gpio_ack_irq(struct irq_data *d)
fba311fc	83	{
8d7cf837	84	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
bf0c1118	85	u32 gpio = irq_to_gpio(d->irq);
8d7cf837	86	clear_gpio_irqstatus(port, gpio & 0x1f);
fba311fc SG	87	}
fba311fc SG	88
bf0c1118	89	static void mxs_gpio_mask_irq(struct irq_data *d)
fba311fc	90	{
8d7cf837	91	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
bf0c1118	92	u32 gpio = irq_to_gpio(d->irq);
8d7cf837	93	set_gpio_irqenable(port, gpio & 0x1f, 0);
fba311fc SG	94	}
fba311fc SG	95
bf0c1118	96	static void mxs_gpio_unmask_irq(struct irq_data *d)
fba311fc	97	{
8d7cf837	98	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
bf0c1118	99	u32 gpio = irq_to_gpio(d->irq);
8d7cf837	100	set_gpio_irqenable(port, gpio & 0x1f, 1);
fba311fc SG	101	}
fba311fc SG	102
bf0c1118	103	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	104	{
bf0c1118	105	u32 gpio = irq_to_gpio(d->irq);
fba311fc	106	u32 pin_mask = 1 << (gpio & 31);
8d7cf837	107	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
fba311fc SG	108	void __iomem *pin_addr;
	109	int edge;
	110
	111	switch (type) {
	112	case IRQ_TYPE_EDGE_RISING:
	113	edge = GPIO_INT_RISE_EDGE;
	114	break;
	115	case IRQ_TYPE_EDGE_FALLING:
	116	edge = GPIO_INT_FALL_EDGE;
	117	break;
	118	case IRQ_TYPE_LEVEL_LOW:
	119	edge = GPIO_INT_LOW_LEV;
	120	break;
	121	case IRQ_TYPE_LEVEL_HIGH:
	122	edge = GPIO_INT_HIGH_LEV;
	123	break;
	124	default:
	125	return -EINVAL;
	126	}
	127
	128	/* set level or edge */
	129	pin_addr = port->base + PINCTRL_IRQLEV(port->id);
	130	if (edge & GPIO_INT_LEV_MASK)
8d7cf837	131	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	132	else
8d7cf837	133	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc SG	134
	135	/* set polarity */
	136	pin_addr = port->base + PINCTRL_IRQPOL(port->id);
	137	if (edge & GPIO_INT_POL_MASK)
8d7cf837	138	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	139	else
8d7cf837	140	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc SG	141
	142	clear_gpio_irqstatus(port, gpio & 0x1f);
	143
	144	return 0;
	145	}
	146
	147	/* MXS has one interrupt per gpio port */
	148	static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	149	{
	150	u32 irq_stat;
8d7cf837	151	struct mxs_gpio_port *port = irq_get_handler_data(irq);
fba311fc SG	152	u32 gpio_irq_no_base = port->virtual_irq_start;
fba311fc SG	153
1f6b5dd4 UKK	154	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	155
8d7cf837 SG	156	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
8d7cf837 SG	157	readl(port->base + PINCTRL_IRQEN(port->id));
fba311fc SG	158
	159	while (irq_stat != 0) {
	160	int irqoffset = fls(irq_stat) - 1;
	161	generic_handle_irq(gpio_irq_no_base + irqoffset);
	162	irq_stat &= ~(1 << irqoffset);
	163	}
	164	}
	165
	166	/*
	167	* Set interrupt number "irq" in the GPIO as a wake-up source.
	168	* While system is running, all registered GPIO interrupts need to have
	169	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	170	* need to have wake-up enabled.
	171	* @param irq interrupt source number
	172	* @param enable enable as wake-up if equal to non-zero
	173	* @return This function returns 0 on success.
	174	*/
bf0c1118	175	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	176	{
bf0c1118	177	u32 gpio = irq_to_gpio(d->irq);
fba311fc	178	u32 gpio_idx = gpio & 0x1f;
8d7cf837	179	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
fba311fc SG	180
	181	if (enable) {
	182	if (port->irq_high && (gpio_idx >= 16))
	183	enable_irq_wake(port->irq_high);
	184	else
	185	enable_irq_wake(port->irq);
	186	} else {
	187	if (port->irq_high && (gpio_idx >= 16))
	188	disable_irq_wake(port->irq_high);
	189	else
	190	disable_irq_wake(port->irq);
	191	}
	192
	193	return 0;
	194	}
	195
	196	static struct irq_chip gpio_irq_chip = {
761b6d1a	197	.name = "mxs gpio",
bf0c1118 UKK	198	.irq_ack = mxs_gpio_ack_irq,
	199	.irq_mask = mxs_gpio_mask_irq,
	200	.irq_unmask = mxs_gpio_unmask_irq,
	201	.irq_set_type = mxs_gpio_set_irq_type,
	202	.irq_set_wake = mxs_gpio_set_wake_irq,
fba311fc SG	203	};
fba311fc SG	204
06f88a8a	205	static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
fba311fc	206	{
06f88a8a	207	struct bgpio_chip *bgc = to_bgpio_chip(gc);
fba311fc	208	struct mxs_gpio_port *port =
06f88a8a	209	container_of(bgc, struct mxs_gpio_port, bgc);
fba311fc SG	210
	211	return port->virtual_irq_start + offset;
	212	}
	213
8d7cf837	214	static int __devinit mxs_gpio_probe(struct platform_device *pdev)
fba311fc	215	{
8d7cf837 SG	216	static void __iomem *base;
	217	struct mxs_gpio_port *port;
	218	struct resource *iores = NULL;
	219	int err, i;
	220
	221	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
	222	if (!port)
	223	return -ENOMEM;
	224
	225	port->id = pdev->id;
	226	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
	227
	228	/*
	229	* map memory region only once, as all the gpio ports
	230	* share the same one
	231	*/
	232	if (!base) {
	233	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	234	if (!iores) {
	235	err = -ENODEV;
	236	goto out_kfree;
	237	}
fba311fc	238
8d7cf837 SG	239	if (!request_mem_region(iores->start, resource_size(iores),
	240	pdev->name)) {
	241	err = -EBUSY;
	242	goto out_kfree;
	243	}
fba311fc	244
8d7cf837 SG	245	base = ioremap(iores->start, resource_size(iores));
	246	if (!base) {
	247	err = -ENOMEM;
	248	goto out_release_mem;
	249	}
	250	}
	251	port->base = base;
fba311fc	252
8d7cf837 SG	253	port->irq = platform_get_irq(pdev, 0);
	254	if (port->irq < 0) {
	255	err = -EINVAL;
	256	goto out_iounmap;
	257	}
fba311fc	258
8d7cf837 SG	259	/* disable the interrupt and clear the status */
	260	writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
	261	writel(0, port->base + PINCTRL_IRQEN(port->id));
fba311fc	262
8d7cf837 SG	263	/* clear address has to be used to clear IRQSTAT bits */
8d7cf837 SG	264	writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
fba311fc	265
8d7cf837 SG	266	for (i = port->virtual_irq_start;
	267	i < port->virtual_irq_start + 32; i++) {
	268	irq_set_chip_and_handler(i, &gpio_irq_chip,
	269	handle_level_irq);
	270	set_irq_flags(i, IRQF_VALID);
	271	irq_set_chip_data(i, port);
fba311fc SG	272	}
fba311fc SG	273
8d7cf837 SG	274	/* setup one handler for each entry */
	275	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
	276	irq_set_handler_data(port->irq, port);
fba311fc	277
06f88a8a SG	278	err = bgpio_init(&port->bgc, &pdev->dev, 4,
	279	port->base + PINCTRL_DIN(port->id),
	280	port->base + PINCTRL_DOUT(port->id), NULL,
	281	port->base + PINCTRL_DOE(port->id), NULL, false);
8d7cf837 SG	282	if (err)
8d7cf837 SG	283	goto out_iounmap;
fba311fc	284
06f88a8a SG	285	port->bgc.gc.to_irq = mxs_gpio_to_irq;
	286	port->bgc.gc.base = port->id * 32;
	287
	288	err = gpiochip_add(&port->bgc.gc);
	289	if (err)
	290	goto out_bgpio_remove;
	291
8d7cf837	292	return 0;
ef19660b	293
06f88a8a SG	294	out_bgpio_remove:
06f88a8a SG	295	bgpio_remove(&port->bgc);
8d7cf837 SG	296	out_iounmap:
	297	if (iores)
	298	iounmap(port->base);
	299	out_release_mem:
	300	if (iores)
	301	release_mem_region(iores->start, resource_size(iores));
	302	out_kfree:
	303	kfree(port);
	304	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	305	return err;
ef19660b	306	}
8d7cf837 SG	307
	308	static struct platform_driver mxs_gpio_driver = {
	309	.driver = {
	310	.name = "gpio-mxs",
	311	.owner = THIS_MODULE,
	312	},
	313	.probe = mxs_gpio_probe,
fba311fc	314	};
ef19660b	315
8d7cf837	316	static int __init mxs_gpio_init(void)
ef19660b	317	{
8d7cf837	318	return platform_driver_register(&mxs_gpio_driver);
ef19660b	319	}
8d7cf837 SG	320	postcore_initcall(mxs_gpio_init);
	321
	322	MODULE_AUTHOR("Freescale Semiconductor, "
	323	"Daniel Mack <danielncaiaq.de>, "
	324	"Juergen Beisert <kernel@pengutronix.de>");
	325	MODULE_DESCRIPTION("Freescale MXS GPIO");
	326	MODULE_LICENSE("GPL");