Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
2ec1d359 | 26 | |
adfed159 WD |
27 | #include <asm/mach/irq.h> |
28 | ||
378be066 | 29 | #include <plat/pincfg.h> |
0f332861 | 30 | #include <plat/gpio-nomadik.h> |
2ec1d359 AR |
31 | |
32 | /* | |
33 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
34 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 35 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
36 | * |
37 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
38 | */ | |
39 | ||
01727e61 RV |
40 | #define NMK_GPIO_PER_CHIP 32 |
41 | ||
2ec1d359 AR |
42 | struct nmk_gpio_chip { |
43 | struct gpio_chip chip; | |
44 | void __iomem *addr; | |
af7dc228 | 45 | struct clk *clk; |
33b744b3 | 46 | unsigned int bank; |
2ec1d359 | 47 | unsigned int parent_irq; |
2c8bb0eb | 48 | int secondary_parent_irq; |
33b744b3 | 49 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 50 | void (*set_ioforce)(bool enable); |
c0fcb8db | 51 | spinlock_t lock; |
33d78647 | 52 | bool sleepmode; |
2ec1d359 AR |
53 | /* Keep track of configured edges */ |
54 | u32 edge_rising; | |
55 | u32 edge_falling; | |
b9df468d RV |
56 | u32 real_wake; |
57 | u32 rwimsc; | |
58 | u32 fwimsc; | |
6c12fe88 RV |
59 | u32 rimsc; |
60 | u32 fimsc; | |
bc6f5cf6 | 61 | u32 pull_up; |
ebc6178d | 62 | u32 lowemi; |
2ec1d359 AR |
63 | }; |
64 | ||
01727e61 RV |
65 | static struct nmk_gpio_chip * |
66 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
67 | ||
68 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
69 | ||
70 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
71 | ||
6f9a974c RV |
72 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
73 | unsigned offset, int gpio_mode) | |
74 | { | |
75 | u32 bit = 1 << offset; | |
76 | u32 afunc, bfunc; | |
77 | ||
78 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
79 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
80 | if (gpio_mode & NMK_GPIO_ALT_A) | |
81 | afunc |= bit; | |
82 | if (gpio_mode & NMK_GPIO_ALT_B) | |
83 | bfunc |= bit; | |
84 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
85 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
86 | } | |
87 | ||
81a3c298 RV |
88 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
89 | unsigned offset, enum nmk_gpio_slpm mode) | |
90 | { | |
91 | u32 bit = 1 << offset; | |
92 | u32 slpm; | |
93 | ||
94 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
95 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
96 | slpm |= bit; | |
97 | else | |
98 | slpm &= ~bit; | |
99 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
100 | } | |
101 | ||
5b327edf RV |
102 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
103 | unsigned offset, enum nmk_gpio_pull pull) | |
104 | { | |
105 | u32 bit = 1 << offset; | |
106 | u32 pdis; | |
107 | ||
108 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 109 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 110 | pdis |= bit; |
bc6f5cf6 RA |
111 | nmk_chip->pull_up &= ~bit; |
112 | } else { | |
5b327edf | 113 | pdis &= ~bit; |
bc6f5cf6 RA |
114 | } |
115 | ||
5b327edf RV |
116 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
117 | ||
bc6f5cf6 RA |
118 | if (pull == NMK_GPIO_PULL_UP) { |
119 | nmk_chip->pull_up |= bit; | |
5b327edf | 120 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
121 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
122 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 123 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 124 | } |
5b327edf RV |
125 | } |
126 | ||
ebc6178d RV |
127 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
128 | unsigned offset, bool lowemi) | |
129 | { | |
130 | u32 bit = BIT(offset); | |
131 | bool enabled = nmk_chip->lowemi & bit; | |
132 | ||
133 | if (lowemi == enabled) | |
134 | return; | |
135 | ||
136 | if (lowemi) | |
137 | nmk_chip->lowemi |= bit; | |
138 | else | |
139 | nmk_chip->lowemi &= ~bit; | |
140 | ||
141 | writel_relaxed(nmk_chip->lowemi, | |
142 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
143 | } | |
144 | ||
378be066 RV |
145 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
146 | unsigned offset) | |
147 | { | |
148 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
149 | } | |
150 | ||
6720db7c RV |
151 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
152 | unsigned offset, int val) | |
153 | { | |
154 | if (val) | |
155 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
156 | else | |
157 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
158 | } | |
159 | ||
160 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
161 | unsigned offset, int val) | |
162 | { | |
163 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
164 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
165 | } | |
166 | ||
01727e61 RV |
167 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
168 | unsigned offset, int gpio_mode, | |
169 | bool glitch) | |
170 | { | |
6c12fe88 RV |
171 | u32 rwimsc = nmk_chip->rwimsc; |
172 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
173 | |
174 | if (glitch && nmk_chip->set_ioforce) { | |
175 | u32 bit = BIT(offset); | |
176 | ||
01727e61 RV |
177 | /* Prevent spurious wakeups */ |
178 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
179 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
180 | ||
181 | nmk_chip->set_ioforce(true); | |
182 | } | |
183 | ||
184 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
185 | ||
186 | if (glitch && nmk_chip->set_ioforce) { | |
187 | nmk_chip->set_ioforce(false); | |
188 | ||
189 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
190 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
191 | } | |
192 | } | |
193 | ||
6c42ad1c RV |
194 | static void |
195 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
196 | { | |
197 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
198 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
199 | int gpio = nmk_chip->chip.base + offset; | |
200 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | |
201 | struct irq_data *d = irq_get_irq_data(irq); | |
202 | ||
203 | if (!rising && !falling) | |
204 | return; | |
205 | ||
206 | if (!d || !irqd_irq_disabled(d)) | |
207 | return; | |
208 | ||
209 | if (rising) { | |
210 | nmk_chip->rimsc &= ~BIT(offset); | |
211 | writel_relaxed(nmk_chip->rimsc, | |
212 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
213 | } | |
214 | ||
215 | if (falling) { | |
216 | nmk_chip->fimsc &= ~BIT(offset); | |
217 | writel_relaxed(nmk_chip->fimsc, | |
218 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
219 | } | |
220 | ||
221 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
222 | } | |
223 | ||
378be066 | 224 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 225 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
226 | { |
227 | static const char *afnames[] = { | |
228 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
229 | [NMK_GPIO_ALT_A] = "A", | |
230 | [NMK_GPIO_ALT_B] = "B", | |
231 | [NMK_GPIO_ALT_C] = "C" | |
232 | }; | |
233 | static const char *pullnames[] = { | |
234 | [NMK_GPIO_PULL_NONE] = "none", | |
235 | [NMK_GPIO_PULL_UP] = "up", | |
236 | [NMK_GPIO_PULL_DOWN] = "down", | |
237 | [3] /* illegal */ = "??" | |
238 | }; | |
239 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
240 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
241 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
242 | }; |
243 | ||
244 | int pin = PIN_NUM(cfg); | |
245 | int pull = PIN_PULL(cfg); | |
246 | int af = PIN_ALT(cfg); | |
247 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
248 | int output = PIN_DIR(cfg); |
249 | int val = PIN_VAL(cfg); | |
01727e61 | 250 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 251 | |
dacdc96c RV |
252 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
253 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
254 | output ? "output " : "input", |
255 | output ? (val ? "high" : "low") : ""); | |
256 | ||
dacdc96c RV |
257 | if (sleep) { |
258 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
259 | int slpm_output = PIN_SLPM_DIR(cfg); | |
260 | int slpm_val = PIN_SLPM_VAL(cfg); | |
261 | ||
3546d15c RV |
262 | af = NMK_GPIO_ALT_GPIO; |
263 | ||
dacdc96c RV |
264 | /* |
265 | * The SLPM_* values are normal values + 1 to allow zero to | |
266 | * mean "same as normal". | |
267 | */ | |
268 | if (slpm_pull) | |
269 | pull = slpm_pull - 1; | |
270 | if (slpm_output) | |
271 | output = slpm_output - 1; | |
272 | if (slpm_val) | |
273 | val = slpm_val - 1; | |
274 | ||
275 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
276 | pin, | |
277 | slpm_pull ? pullnames[pull] : "same", | |
278 | slpm_output ? (output ? "output" : "input") : "same", | |
279 | slpm_val ? (val ? "high" : "low") : "same"); | |
280 | } | |
281 | ||
6720db7c RV |
282 | if (output) |
283 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
284 | else { | |
285 | __nmk_gpio_make_input(nmk_chip, offset); | |
286 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
287 | } | |
378be066 | 288 | |
ebc6178d RV |
289 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
290 | ||
6c42ad1c RV |
291 | /* |
292 | * If the pin is switching to altfunc, and there was an interrupt | |
293 | * installed on it which has been lazy disabled, actually mask the | |
294 | * interrupt to prevent spurious interrupts that would occur while the | |
295 | * pin is under control of the peripheral. Only SKE does this. | |
296 | */ | |
297 | if (af != NMK_GPIO_ALT_GPIO) | |
298 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
299 | ||
01727e61 RV |
300 | /* |
301 | * If we've backed up the SLPM registers (glitch workaround), modify | |
302 | * the backups since they will be restored. | |
303 | */ | |
304 | if (slpmregs) { | |
305 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
306 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
307 | else | |
308 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
309 | } else | |
310 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
311 | ||
312 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
313 | } | |
314 | ||
315 | /* | |
316 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
317 | * - Save SLPM registers | |
318 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
319 | * - Configure the GPIO registers for the IOs that are being switched | |
320 | * - Set IOFORCE=1 | |
321 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
322 | * - Set IOFORCE=0 | |
323 | * - Restore SLPM registers | |
324 | * - Any spurious wake up event during switch sequence to be ignored and | |
325 | * cleared | |
326 | */ | |
327 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
328 | { | |
329 | int i; | |
330 | ||
331 | for (i = 0; i < NUM_BANKS; i++) { | |
332 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
333 | unsigned int temp = slpm[i]; | |
334 | ||
335 | if (!chip) | |
336 | break; | |
337 | ||
3c0227d2 RV |
338 | clk_enable(chip->clk); |
339 | ||
01727e61 RV |
340 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
341 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
342 | } | |
343 | } | |
344 | ||
345 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
346 | { | |
347 | int i; | |
348 | ||
349 | for (i = 0; i < NUM_BANKS; i++) { | |
350 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
351 | ||
352 | if (!chip) | |
353 | break; | |
354 | ||
355 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
356 | |
357 | clk_disable(chip->clk); | |
01727e61 RV |
358 | } |
359 | } | |
360 | ||
361 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
362 | { | |
363 | static unsigned int slpm[NUM_BANKS]; | |
364 | unsigned long flags; | |
365 | bool glitch = false; | |
366 | int ret = 0; | |
367 | int i; | |
368 | ||
369 | for (i = 0; i < num; i++) { | |
370 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
371 | glitch = true; | |
372 | break; | |
373 | } | |
374 | } | |
375 | ||
376 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
377 | ||
378 | if (glitch) { | |
379 | memset(slpm, 0xff, sizeof(slpm)); | |
380 | ||
381 | for (i = 0; i < num; i++) { | |
382 | int pin = PIN_NUM(cfgs[i]); | |
383 | int offset = pin % NMK_GPIO_PER_CHIP; | |
384 | ||
385 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
386 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
387 | } | |
388 | ||
389 | nmk_gpio_glitch_slpm_init(slpm); | |
390 | } | |
391 | ||
392 | for (i = 0; i < num; i++) { | |
393 | struct nmk_gpio_chip *nmk_chip; | |
394 | int pin = PIN_NUM(cfgs[i]); | |
395 | ||
6845664a | 396 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
01727e61 RV |
397 | if (!nmk_chip) { |
398 | ret = -EINVAL; | |
399 | break; | |
400 | } | |
401 | ||
3c0227d2 | 402 | clk_enable(nmk_chip->clk); |
01727e61 RV |
403 | spin_lock(&nmk_chip->lock); |
404 | __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, | |
405 | cfgs[i], sleep, glitch ? slpm : NULL); | |
406 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 407 | clk_disable(nmk_chip->clk); |
01727e61 RV |
408 | } |
409 | ||
410 | if (glitch) | |
411 | nmk_gpio_glitch_slpm_restore(slpm); | |
412 | ||
413 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
414 | ||
415 | return ret; | |
378be066 RV |
416 | } |
417 | ||
418 | /** | |
419 | * nmk_config_pin - configure a pin's mux attributes | |
420 | * @cfg: pin confguration | |
421 | * | |
422 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
423 | * and its sleep mode based on the specified configuration. The @cfg is | |
424 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
425 | * are constructed using, and can be further enhanced with, the macros in | |
426 | * plat/pincfg.h. | |
427 | * | |
428 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
429 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
430 | * calls. | |
431 | */ | |
dacdc96c | 432 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 433 | { |
01727e61 | 434 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
435 | } |
436 | EXPORT_SYMBOL(nmk_config_pin); | |
437 | ||
438 | /** | |
439 | * nmk_config_pins - configure several pins at once | |
440 | * @cfgs: array of pin configurations | |
441 | * @num: number of elments in the array | |
442 | * | |
443 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
444 | * further information. | |
445 | */ | |
446 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
447 | { | |
01727e61 | 448 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
449 | } |
450 | EXPORT_SYMBOL(nmk_config_pins); | |
451 | ||
dacdc96c RV |
452 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
453 | { | |
01727e61 | 454 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
455 | } |
456 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
457 | ||
81a3c298 RV |
458 | /** |
459 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
460 | * @gpio: pin number | |
461 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
462 | * | |
33d78647 LW |
463 | * This register is actually in the pinmux layer, not the GPIO block itself. |
464 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
465 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
466 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
467 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
468 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
469 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 470 | * |
33d78647 LW |
471 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
472 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
473 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
474 | * ENABLED. | |
475 | * | |
476 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
477 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
478 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
479 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
480 | * | |
481 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
482 | */ |
483 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
484 | { | |
485 | struct nmk_gpio_chip *nmk_chip; | |
486 | unsigned long flags; | |
487 | ||
6845664a | 488 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
81a3c298 RV |
489 | if (!nmk_chip) |
490 | return -EINVAL; | |
491 | ||
3c0227d2 | 492 | clk_enable(nmk_chip->clk); |
01727e61 RV |
493 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
494 | spin_lock(&nmk_chip->lock); | |
495 | ||
81a3c298 | 496 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); |
01727e61 RV |
497 | |
498 | spin_unlock(&nmk_chip->lock); | |
499 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 500 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
501 | |
502 | return 0; | |
503 | } | |
504 | ||
5b327edf RV |
505 | /** |
506 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
507 | * @gpio: pin number | |
508 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
509 | * | |
510 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
511 | * the pin is configured as an input (either explicitly or by the alternate | |
512 | * function). | |
513 | * | |
514 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
515 | * configured as an input. Otherwise, due to the way the controller registers | |
516 | * work, this function will change the value output on the pin. | |
517 | */ | |
518 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
519 | { | |
520 | struct nmk_gpio_chip *nmk_chip; | |
521 | unsigned long flags; | |
522 | ||
6845664a | 523 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
5b327edf RV |
524 | if (!nmk_chip) |
525 | return -EINVAL; | |
526 | ||
3c0227d2 | 527 | clk_enable(nmk_chip->clk); |
5b327edf RV |
528 | spin_lock_irqsave(&nmk_chip->lock, flags); |
529 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
530 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
3c0227d2 | 531 | clk_disable(nmk_chip->clk); |
5b327edf RV |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
2ec1d359 | 536 | /* Mode functions */ |
9c66ee6f JA |
537 | /** |
538 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
539 | * @gpio: pin number | |
540 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
541 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
542 | * | |
543 | * Sets the mode of the specified pin to one of the alternate functions or | |
544 | * plain GPIO. | |
545 | */ | |
2ec1d359 AR |
546 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
547 | { | |
548 | struct nmk_gpio_chip *nmk_chip; | |
549 | unsigned long flags; | |
2ec1d359 | 550 | |
6845664a | 551 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
552 | if (!nmk_chip) |
553 | return -EINVAL; | |
554 | ||
3c0227d2 | 555 | clk_enable(nmk_chip->clk); |
2ec1d359 | 556 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 557 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 | 558 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 559 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
560 | |
561 | return 0; | |
562 | } | |
563 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
564 | ||
565 | int nmk_gpio_get_mode(int gpio) | |
566 | { | |
567 | struct nmk_gpio_chip *nmk_chip; | |
568 | u32 afunc, bfunc, bit; | |
569 | ||
6845664a | 570 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
571 | if (!nmk_chip) |
572 | return -EINVAL; | |
573 | ||
574 | bit = 1 << (gpio - nmk_chip->chip.base); | |
575 | ||
3c0227d2 RV |
576 | clk_enable(nmk_chip->clk); |
577 | ||
2ec1d359 AR |
578 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
579 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
580 | ||
3c0227d2 RV |
581 | clk_disable(nmk_chip->clk); |
582 | ||
2ec1d359 AR |
583 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
584 | } | |
585 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
586 | ||
587 | ||
588 | /* IRQ functions */ | |
589 | static inline int nmk_gpio_get_bitmask(int gpio) | |
590 | { | |
591 | return 1 << (gpio % 32); | |
592 | } | |
593 | ||
f272c00e | 594 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 AR |
595 | { |
596 | int gpio; | |
597 | struct nmk_gpio_chip *nmk_chip; | |
598 | ||
f272c00e LB |
599 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
600 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
601 | if (!nmk_chip) |
602 | return; | |
3c0227d2 RV |
603 | |
604 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 605 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 606 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
607 | } |
608 | ||
4d4e20f7 RV |
609 | enum nmk_gpio_irq_type { |
610 | NORMAL, | |
611 | WAKE, | |
612 | }; | |
613 | ||
040e5ecd | 614 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
615 | int gpio, enum nmk_gpio_irq_type which, |
616 | bool enable) | |
2ec1d359 | 617 | { |
040e5ecd | 618 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
619 | u32 *rimscval; |
620 | u32 *fimscval; | |
621 | u32 rimscreg; | |
622 | u32 fimscreg; | |
623 | ||
624 | if (which == NORMAL) { | |
625 | rimscreg = NMK_GPIO_RIMSC; | |
626 | fimscreg = NMK_GPIO_FIMSC; | |
627 | rimscval = &nmk_chip->rimsc; | |
628 | fimscval = &nmk_chip->fimsc; | |
629 | } else { | |
630 | rimscreg = NMK_GPIO_RWIMSC; | |
631 | fimscreg = NMK_GPIO_FWIMSC; | |
632 | rimscval = &nmk_chip->rwimsc; | |
633 | fimscval = &nmk_chip->fwimsc; | |
634 | } | |
2ec1d359 | 635 | |
040e5ecd | 636 | /* we must individually set/clear the two edges */ |
2ec1d359 | 637 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 638 | if (enable) |
6c12fe88 | 639 | *rimscval |= bitmask; |
040e5ecd | 640 | else |
6c12fe88 RV |
641 | *rimscval &= ~bitmask; |
642 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
643 | } |
644 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 645 | if (enable) |
6c12fe88 | 646 | *fimscval |= bitmask; |
040e5ecd | 647 | else |
6c12fe88 RV |
648 | *fimscval &= ~bitmask; |
649 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 650 | } |
040e5ecd | 651 | } |
2ec1d359 | 652 | |
b9df468d RV |
653 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
654 | int gpio, bool on) | |
655 | { | |
b982ff0e RV |
656 | /* |
657 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
658 | * disabled, since setting SLPM to 1 increases power consumption, and | |
659 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
660 | */ | |
661 | if (nmk_chip->sleepmode && on) { | |
33d78647 | 662 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, |
b982ff0e | 663 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
664 | } |
665 | ||
b9df468d RV |
666 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
667 | } | |
668 | ||
669 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 AR |
670 | { |
671 | int gpio; | |
672 | struct nmk_gpio_chip *nmk_chip; | |
673 | unsigned long flags; | |
040e5ecd | 674 | u32 bitmask; |
2ec1d359 | 675 | |
f272c00e LB |
676 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
677 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
678 | bitmask = nmk_gpio_get_bitmask(gpio); |
679 | if (!nmk_chip) | |
4d4e20f7 | 680 | return -EINVAL; |
2ec1d359 | 681 | |
3c0227d2 | 682 | clk_enable(nmk_chip->clk); |
b9df468d RV |
683 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
684 | spin_lock(&nmk_chip->lock); | |
685 | ||
686 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); | |
687 | ||
688 | if (!(nmk_chip->real_wake & bitmask)) | |
689 | __nmk_gpio_set_wake(nmk_chip, gpio, enable); | |
690 | ||
691 | spin_unlock(&nmk_chip->lock); | |
692 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 693 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
694 | |
695 | return 0; | |
2ec1d359 AR |
696 | } |
697 | ||
f272c00e | 698 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 699 | { |
b9df468d | 700 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 701 | } |
040e5ecd | 702 | |
f272c00e | 703 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 704 | { |
b9df468d | 705 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
706 | } |
707 | ||
f272c00e | 708 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 709 | { |
7e3f7e59 RV |
710 | struct nmk_gpio_chip *nmk_chip; |
711 | unsigned long flags; | |
b9df468d | 712 | u32 bitmask; |
7e3f7e59 RV |
713 | int gpio; |
714 | ||
f272c00e LB |
715 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
716 | nmk_chip = irq_data_get_irq_chip_data(d); | |
7e3f7e59 RV |
717 | if (!nmk_chip) |
718 | return -EINVAL; | |
b9df468d | 719 | bitmask = nmk_gpio_get_bitmask(gpio); |
7e3f7e59 | 720 | |
3c0227d2 | 721 | clk_enable(nmk_chip->clk); |
01727e61 RV |
722 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
723 | spin_lock(&nmk_chip->lock); | |
724 | ||
479a0c7e | 725 | if (irqd_irq_disabled(d)) |
b9df468d RV |
726 | __nmk_gpio_set_wake(nmk_chip, gpio, on); |
727 | ||
728 | if (on) | |
729 | nmk_chip->real_wake |= bitmask; | |
730 | else | |
731 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
732 | |
733 | spin_unlock(&nmk_chip->lock); | |
734 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 735 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
736 | |
737 | return 0; | |
040e5ecd RV |
738 | } |
739 | ||
f272c00e | 740 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 741 | { |
479a0c7e | 742 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 743 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
744 | int gpio; |
745 | struct nmk_gpio_chip *nmk_chip; | |
746 | unsigned long flags; | |
747 | u32 bitmask; | |
748 | ||
f272c00e LB |
749 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
750 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
751 | bitmask = nmk_gpio_get_bitmask(gpio); |
752 | if (!nmk_chip) | |
753 | return -EINVAL; | |
754 | ||
755 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
756 | return -EINVAL; | |
757 | if (type & IRQ_TYPE_LEVEL_LOW) | |
758 | return -EINVAL; | |
759 | ||
3c0227d2 | 760 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
761 | spin_lock_irqsave(&nmk_chip->lock, flags); |
762 | ||
7a852d80 | 763 | if (enabled) |
4d4e20f7 RV |
764 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
765 | ||
b9df468d | 766 | if (enabled || wake) |
4d4e20f7 | 767 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); |
7a852d80 | 768 | |
2ec1d359 AR |
769 | nmk_chip->edge_rising &= ~bitmask; |
770 | if (type & IRQ_TYPE_EDGE_RISING) | |
771 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
772 | |
773 | nmk_chip->edge_falling &= ~bitmask; | |
774 | if (type & IRQ_TYPE_EDGE_FALLING) | |
775 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 776 | |
7a852d80 | 777 | if (enabled) |
4d4e20f7 RV |
778 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
779 | ||
b9df468d | 780 | if (enabled || wake) |
4d4e20f7 | 781 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); |
2ec1d359 | 782 | |
7a852d80 | 783 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 784 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
785 | |
786 | return 0; | |
787 | } | |
788 | ||
3c0227d2 RV |
789 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
790 | { | |
791 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 792 | |
3c0227d2 RV |
793 | clk_enable(nmk_chip->clk); |
794 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
795 | return 0; |
796 | } | |
797 | ||
3c0227d2 RV |
798 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
799 | { | |
800 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
801 | ||
802 | nmk_gpio_irq_mask(d); | |
803 | clk_disable(nmk_chip->clk); | |
804 | } | |
805 | ||
2ec1d359 AR |
806 | static struct irq_chip nmk_gpio_irq_chip = { |
807 | .name = "Nomadik-GPIO", | |
f272c00e LB |
808 | .irq_ack = nmk_gpio_irq_ack, |
809 | .irq_mask = nmk_gpio_irq_mask, | |
810 | .irq_unmask = nmk_gpio_irq_unmask, | |
811 | .irq_set_type = nmk_gpio_irq_set_type, | |
812 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
813 | .irq_startup = nmk_gpio_irq_startup, |
814 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
2ec1d359 AR |
815 | }; |
816 | ||
33b744b3 RV |
817 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
818 | u32 status) | |
2ec1d359 AR |
819 | { |
820 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 821 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
822 | unsigned int first_irq; |
823 | ||
adfed159 | 824 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 825 | |
6845664a | 826 | nmk_chip = irq_get_handler_data(irq); |
2ec1d359 | 827 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
33b744b3 RV |
828 | while (status) { |
829 | int bit = __ffs(status); | |
830 | ||
831 | generic_handle_irq(first_irq + bit); | |
832 | status &= ~BIT(bit); | |
2ec1d359 | 833 | } |
aaedaa2b | 834 | |
adfed159 | 835 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
836 | } |
837 | ||
33b744b3 RV |
838 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
839 | { | |
6845664a | 840 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
841 | u32 status; |
842 | ||
843 | clk_enable(nmk_chip->clk); | |
844 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
845 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
846 | |
847 | __nmk_gpio_irq_handler(irq, desc, status); | |
848 | } | |
849 | ||
850 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
851 | struct irq_desc *desc) | |
852 | { | |
6845664a | 853 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
854 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
855 | ||
856 | __nmk_gpio_irq_handler(irq, desc, status); | |
857 | } | |
858 | ||
2ec1d359 AR |
859 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
860 | { | |
861 | unsigned int first_irq; | |
862 | int i; | |
863 | ||
864 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
e493e06f | 865 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
f38c02f3 TG |
866 | irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, |
867 | handle_edge_irq); | |
2ec1d359 | 868 | set_irq_flags(i, IRQF_VALID); |
6845664a TG |
869 | irq_set_chip_data(i, nmk_chip); |
870 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | |
2ec1d359 | 871 | } |
33b744b3 | 872 | |
6845664a TG |
873 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
874 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
875 | |
876 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 877 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 878 | nmk_gpio_secondary_irq_handler); |
6845664a | 879 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
880 | } |
881 | ||
2ec1d359 AR |
882 | return 0; |
883 | } | |
884 | ||
885 | /* I/O Functions */ | |
886 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
887 | { | |
888 | struct nmk_gpio_chip *nmk_chip = | |
889 | container_of(chip, struct nmk_gpio_chip, chip); | |
890 | ||
3c0227d2 RV |
891 | clk_enable(nmk_chip->clk); |
892 | ||
2ec1d359 | 893 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
894 | |
895 | clk_disable(nmk_chip->clk); | |
896 | ||
2ec1d359 AR |
897 | return 0; |
898 | } | |
899 | ||
2ec1d359 AR |
900 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
901 | { | |
902 | struct nmk_gpio_chip *nmk_chip = | |
903 | container_of(chip, struct nmk_gpio_chip, chip); | |
904 | u32 bit = 1 << offset; | |
3c0227d2 RV |
905 | int value; |
906 | ||
907 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 908 | |
3c0227d2 | 909 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 910 | |
3c0227d2 RV |
911 | clk_disable(nmk_chip->clk); |
912 | ||
913 | return value; | |
2ec1d359 AR |
914 | } |
915 | ||
916 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
917 | int val) | |
918 | { | |
919 | struct nmk_gpio_chip *nmk_chip = | |
920 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 921 | |
3c0227d2 RV |
922 | clk_enable(nmk_chip->clk); |
923 | ||
6720db7c | 924 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
925 | |
926 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
927 | } |
928 | ||
6647c6c0 RV |
929 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
930 | int val) | |
931 | { | |
932 | struct nmk_gpio_chip *nmk_chip = | |
933 | container_of(chip, struct nmk_gpio_chip, chip); | |
934 | ||
3c0227d2 RV |
935 | clk_enable(nmk_chip->clk); |
936 | ||
6720db7c | 937 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 938 | |
3c0227d2 RV |
939 | clk_disable(nmk_chip->clk); |
940 | ||
6647c6c0 RV |
941 | return 0; |
942 | } | |
943 | ||
0d2aec9c RV |
944 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
945 | { | |
946 | struct nmk_gpio_chip *nmk_chip = | |
947 | container_of(chip, struct nmk_gpio_chip, chip); | |
948 | ||
949 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
950 | } | |
951 | ||
d0b543c7 RV |
952 | #ifdef CONFIG_DEBUG_FS |
953 | ||
954 | #include <linux/seq_file.h> | |
955 | ||
956 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
957 | { | |
958 | int mode; | |
959 | unsigned i; | |
960 | unsigned gpio = chip->base; | |
961 | int is_out; | |
962 | struct nmk_gpio_chip *nmk_chip = | |
963 | container_of(chip, struct nmk_gpio_chip, chip); | |
964 | const char *modes[] = { | |
965 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
966 | [NMK_GPIO_ALT_A] = "altA", | |
967 | [NMK_GPIO_ALT_B] = "altB", | |
968 | [NMK_GPIO_ALT_C] = "altC", | |
969 | }; | |
970 | ||
3c0227d2 RV |
971 | clk_enable(nmk_chip->clk); |
972 | ||
d0b543c7 RV |
973 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
974 | const char *label = gpiochip_is_requested(chip, i); | |
975 | bool pull; | |
976 | u32 bit = 1 << i; | |
977 | ||
d0b543c7 RV |
978 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; |
979 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
980 | mode = nmk_gpio_get_mode(gpio); | |
981 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
8ea72a30 | 982 | gpio, label ?: "(none)", |
d0b543c7 RV |
983 | is_out ? "out" : "in ", |
984 | chip->get | |
985 | ? (chip->get(chip, i) ? "hi" : "lo") | |
986 | : "? ", | |
987 | (mode < 0) ? "unknown" : modes[mode], | |
988 | pull ? "pull" : "none"); | |
8ea72a30 RV |
989 | |
990 | if (label && !is_out) { | |
991 | int irq = gpio_to_irq(gpio); | |
992 | struct irq_desc *desc = irq_to_desc(irq); | |
993 | ||
994 | /* This races with request_irq(), set_irq_type(), | |
995 | * and set_irq_wake() ... but those are "rare". | |
996 | */ | |
997 | if (irq >= 0 && desc->action) { | |
998 | char *trigger; | |
999 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1000 | ||
1001 | if (nmk_chip->edge_rising & bitmask) | |
1002 | trigger = "edge-rising"; | |
1003 | else if (nmk_chip->edge_falling & bitmask) | |
1004 | trigger = "edge-falling"; | |
1005 | else | |
1006 | trigger = "edge-undefined"; | |
1007 | ||
1008 | seq_printf(s, " irq-%d %s%s", | |
1009 | irq, trigger, | |
1010 | irqd_is_wakeup_set(&desc->irq_data) | |
1011 | ? " wakeup" : ""); | |
1012 | } | |
1013 | } | |
1014 | ||
d0b543c7 RV |
1015 | seq_printf(s, "\n"); |
1016 | } | |
3c0227d2 RV |
1017 | |
1018 | clk_disable(nmk_chip->clk); | |
d0b543c7 RV |
1019 | } |
1020 | ||
1021 | #else | |
1022 | #define nmk_gpio_dbg_show NULL | |
1023 | #endif | |
1024 | ||
2ec1d359 AR |
1025 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1026 | static struct gpio_chip nmk_gpio_template = { | |
1027 | .direction_input = nmk_gpio_make_input, | |
1028 | .get = nmk_gpio_get_input, | |
1029 | .direction_output = nmk_gpio_make_output, | |
1030 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1031 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1032 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1033 | .can_sleep = 0, |
1034 | }; | |
1035 | ||
3c0227d2 RV |
1036 | void nmk_gpio_clocks_enable(void) |
1037 | { | |
1038 | int i; | |
1039 | ||
1040 | for (i = 0; i < NUM_BANKS; i++) { | |
1041 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1042 | ||
1043 | if (!chip) | |
1044 | continue; | |
1045 | ||
1046 | clk_enable(chip->clk); | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | void nmk_gpio_clocks_disable(void) | |
1051 | { | |
1052 | int i; | |
1053 | ||
1054 | for (i = 0; i < NUM_BANKS; i++) { | |
1055 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1056 | ||
1057 | if (!chip) | |
1058 | continue; | |
1059 | ||
1060 | clk_disable(chip->clk); | |
1061 | } | |
1062 | } | |
1063 | ||
b9df468d RV |
1064 | /* |
1065 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1066 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1067 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1068 | * cpuidle. | |
1069 | * | |
1070 | * PM ops are not used since this needs to be done at the end, after all the | |
1071 | * other drivers are done with their suspend callbacks. | |
1072 | */ | |
1073 | void nmk_gpio_wakeups_suspend(void) | |
1074 | { | |
1075 | int i; | |
1076 | ||
1077 | for (i = 0; i < NUM_BANKS; i++) { | |
1078 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1079 | ||
1080 | if (!chip) | |
1081 | break; | |
1082 | ||
3c0227d2 RV |
1083 | clk_enable(chip->clk); |
1084 | ||
b9df468d RV |
1085 | writel(chip->rwimsc & chip->real_wake, |
1086 | chip->addr + NMK_GPIO_RWIMSC); | |
1087 | writel(chip->fwimsc & chip->real_wake, | |
1088 | chip->addr + NMK_GPIO_FWIMSC); | |
1089 | ||
3c0227d2 | 1090 | clk_disable(chip->clk); |
b9df468d RV |
1091 | } |
1092 | } | |
1093 | ||
1094 | void nmk_gpio_wakeups_resume(void) | |
1095 | { | |
1096 | int i; | |
1097 | ||
1098 | for (i = 0; i < NUM_BANKS; i++) { | |
1099 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1100 | ||
1101 | if (!chip) | |
1102 | break; | |
1103 | ||
3c0227d2 RV |
1104 | clk_enable(chip->clk); |
1105 | ||
b9df468d RV |
1106 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1107 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1108 | ||
3c0227d2 | 1109 | clk_disable(chip->clk); |
b9df468d RV |
1110 | } |
1111 | } | |
1112 | ||
bc6f5cf6 RA |
1113 | /* |
1114 | * Read the pull up/pull down status. | |
1115 | * A bit set in 'pull_up' means that pull up | |
1116 | * is selected if pull is enabled in PDIS register. | |
1117 | * Note: only pull up/down set via this driver can | |
1118 | * be detected due to HW limitations. | |
1119 | */ | |
1120 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1121 | { | |
1122 | if (gpio_bank < NUM_BANKS) { | |
1123 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1124 | ||
1125 | if (!chip) | |
1126 | return; | |
1127 | ||
1128 | *pull_up = chip->pull_up; | |
1129 | } | |
1130 | } | |
1131 | ||
fd0d67d6 | 1132 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1133 | { |
3e3c62ca | 1134 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1135 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1136 | struct nmk_gpio_chip *nmk_chip; |
1137 | struct gpio_chip *chip; | |
3e3c62ca | 1138 | struct resource *res; |
af7dc228 | 1139 | struct clk *clk; |
33b744b3 | 1140 | int secondary_irq; |
8d91771c | 1141 | void __iomem *base; |
3e3c62ca | 1142 | int irq; |
2ec1d359 AR |
1143 | int ret; |
1144 | ||
513c27f8 LJ |
1145 | if (!pdata && !np) { |
1146 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1147 | return -ENODEV; |
513c27f8 LJ |
1148 | } |
1149 | ||
1150 | if (np) { | |
1151 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
1152 | if (!pdata) | |
1153 | return -ENOMEM; | |
1154 | ||
1155 | if (of_get_property(np, "supports-sleepmode", NULL)) | |
1156 | pdata->supports_sleepmode = true; | |
1157 | ||
1158 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1159 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1160 | ret = -EINVAL; | |
1161 | goto out_dt; | |
1162 | } | |
1163 | ||
1164 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1165 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1166 | } | |
3e3c62ca RV |
1167 | |
1168 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1169 | if (!res) { | |
1170 | ret = -ENOENT; | |
1171 | goto out; | |
1172 | } | |
1173 | ||
1174 | irq = platform_get_irq(dev, 0); | |
1175 | if (irq < 0) { | |
1176 | ret = irq; | |
1177 | goto out; | |
1178 | } | |
1179 | ||
33b744b3 RV |
1180 | secondary_irq = platform_get_irq(dev, 1); |
1181 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1182 | ret = -EINVAL; | |
1183 | goto out; | |
1184 | } | |
1185 | ||
3e3c62ca RV |
1186 | if (request_mem_region(res->start, resource_size(res), |
1187 | dev_name(&dev->dev)) == NULL) { | |
1188 | ret = -EBUSY; | |
1189 | goto out; | |
1190 | } | |
2ec1d359 | 1191 | |
8d91771c LW |
1192 | base = ioremap(res->start, resource_size(res)); |
1193 | if (!base) { | |
1194 | ret = -ENOMEM; | |
1195 | goto out_release; | |
1196 | } | |
1197 | ||
af7dc228 RV |
1198 | clk = clk_get(&dev->dev, NULL); |
1199 | if (IS_ERR(clk)) { | |
1200 | ret = PTR_ERR(clk); | |
8d91771c | 1201 | goto out_unmap; |
af7dc228 RV |
1202 | } |
1203 | ||
2ec1d359 AR |
1204 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
1205 | if (!nmk_chip) { | |
1206 | ret = -ENOMEM; | |
af7dc228 | 1207 | goto out_clk; |
2ec1d359 | 1208 | } |
513c27f8 | 1209 | |
2ec1d359 AR |
1210 | /* |
1211 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1212 | * so we can simply convert the resource address, without remapping | |
1213 | */ | |
33b744b3 | 1214 | nmk_chip->bank = dev->id; |
af7dc228 | 1215 | nmk_chip->clk = clk; |
8d91771c | 1216 | nmk_chip->addr = base; |
2ec1d359 | 1217 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1218 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1219 | nmk_chip->secondary_parent_irq = secondary_irq; |
1220 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1221 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1222 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1223 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1224 | |
1225 | chip = &nmk_chip->chip; | |
1226 | chip->base = pdata->first_gpio; | |
e493e06f | 1227 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1228 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1229 | chip->dev = &dev->dev; |
1230 | chip->owner = THIS_MODULE; | |
1231 | ||
ebc6178d RV |
1232 | clk_enable(nmk_chip->clk); |
1233 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1234 | clk_disable(nmk_chip->clk); | |
1235 | ||
513c27f8 LJ |
1236 | chip->of_node = np; |
1237 | ||
2ec1d359 AR |
1238 | ret = gpiochip_add(&nmk_chip->chip); |
1239 | if (ret) | |
1240 | goto out_free; | |
1241 | ||
01727e61 RV |
1242 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1243 | ||
1244 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1245 | |
3e3c62ca | 1246 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
1247 | |
1248 | nmk_gpio_init_irq(nmk_chip); | |
1249 | ||
513c27f8 LJ |
1250 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1251 | ||
2ec1d359 AR |
1252 | return 0; |
1253 | ||
3e3c62ca | 1254 | out_free: |
2ec1d359 | 1255 | kfree(nmk_chip); |
af7dc228 RV |
1256 | out_clk: |
1257 | clk_disable(clk); | |
1258 | clk_put(clk); | |
8d91771c LW |
1259 | out_unmap: |
1260 | iounmap(base); | |
3e3c62ca RV |
1261 | out_release: |
1262 | release_mem_region(res->start, resource_size(res)); | |
1263 | out: | |
2ec1d359 AR |
1264 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1265 | pdata->first_gpio, pdata->first_gpio+31); | |
513c27f8 LJ |
1266 | out_dt: |
1267 | if (np) | |
1268 | kfree(pdata); | |
1269 | ||
2ec1d359 AR |
1270 | return ret; |
1271 | } | |
1272 | ||
513c27f8 LJ |
1273 | static const struct of_device_id nmk_gpio_match[] = { |
1274 | { .compatible = "st,nomadik-gpio", }, | |
1275 | {} | |
1276 | }; | |
1277 | ||
3e3c62ca RV |
1278 | static struct platform_driver nmk_gpio_driver = { |
1279 | .driver = { | |
2ec1d359 AR |
1280 | .owner = THIS_MODULE, |
1281 | .name = "gpio", | |
513c27f8 | 1282 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1283 | }, |
2ec1d359 | 1284 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1285 | }; |
1286 | ||
1287 | static int __init nmk_gpio_init(void) | |
1288 | { | |
3e3c62ca | 1289 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
1290 | } |
1291 | ||
33f45ea9 | 1292 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1293 | |
1294 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1295 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1296 | MODULE_LICENSE("GPL"); |