Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
2ec1d359 | 26 | |
adfed159 WD |
27 | #include <asm/mach/irq.h> |
28 | ||
378be066 | 29 | #include <plat/pincfg.h> |
0f332861 | 30 | #include <plat/gpio-nomadik.h> |
2ec1d359 | 31 | #include <mach/hardware.h> |
75482dc3 | 32 | #include <asm/gpio.h> |
2ec1d359 AR |
33 | |
34 | /* | |
35 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
36 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 37 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
38 | * |
39 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
40 | */ | |
41 | ||
01727e61 RV |
42 | #define NMK_GPIO_PER_CHIP 32 |
43 | ||
2ec1d359 AR |
44 | struct nmk_gpio_chip { |
45 | struct gpio_chip chip; | |
46 | void __iomem *addr; | |
af7dc228 | 47 | struct clk *clk; |
33b744b3 | 48 | unsigned int bank; |
2ec1d359 | 49 | unsigned int parent_irq; |
2c8bb0eb | 50 | int secondary_parent_irq; |
33b744b3 | 51 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 52 | void (*set_ioforce)(bool enable); |
c0fcb8db | 53 | spinlock_t lock; |
33d78647 | 54 | bool sleepmode; |
2ec1d359 AR |
55 | /* Keep track of configured edges */ |
56 | u32 edge_rising; | |
57 | u32 edge_falling; | |
b9df468d RV |
58 | u32 real_wake; |
59 | u32 rwimsc; | |
60 | u32 fwimsc; | |
6c12fe88 RV |
61 | u32 rimsc; |
62 | u32 fimsc; | |
bc6f5cf6 | 63 | u32 pull_up; |
2ec1d359 AR |
64 | }; |
65 | ||
01727e61 RV |
66 | static struct nmk_gpio_chip * |
67 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
68 | ||
69 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
70 | ||
71 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
72 | ||
6f9a974c RV |
73 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
74 | unsigned offset, int gpio_mode) | |
75 | { | |
76 | u32 bit = 1 << offset; | |
77 | u32 afunc, bfunc; | |
78 | ||
79 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
80 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
81 | if (gpio_mode & NMK_GPIO_ALT_A) | |
82 | afunc |= bit; | |
83 | if (gpio_mode & NMK_GPIO_ALT_B) | |
84 | bfunc |= bit; | |
85 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
86 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
87 | } | |
88 | ||
81a3c298 RV |
89 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
90 | unsigned offset, enum nmk_gpio_slpm mode) | |
91 | { | |
92 | u32 bit = 1 << offset; | |
93 | u32 slpm; | |
94 | ||
95 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
96 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
97 | slpm |= bit; | |
98 | else | |
99 | slpm &= ~bit; | |
100 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
101 | } | |
102 | ||
5b327edf RV |
103 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
104 | unsigned offset, enum nmk_gpio_pull pull) | |
105 | { | |
106 | u32 bit = 1 << offset; | |
107 | u32 pdis; | |
108 | ||
109 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 110 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 111 | pdis |= bit; |
bc6f5cf6 RA |
112 | nmk_chip->pull_up &= ~bit; |
113 | } else { | |
5b327edf | 114 | pdis &= ~bit; |
bc6f5cf6 RA |
115 | } |
116 | ||
5b327edf RV |
117 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
118 | ||
bc6f5cf6 RA |
119 | if (pull == NMK_GPIO_PULL_UP) { |
120 | nmk_chip->pull_up |= bit; | |
5b327edf | 121 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
122 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
123 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 124 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 125 | } |
5b327edf RV |
126 | } |
127 | ||
378be066 RV |
128 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
129 | unsigned offset) | |
130 | { | |
131 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
132 | } | |
133 | ||
6720db7c RV |
134 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
135 | unsigned offset, int val) | |
136 | { | |
137 | if (val) | |
138 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
139 | else | |
140 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
141 | } | |
142 | ||
143 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
144 | unsigned offset, int val) | |
145 | { | |
146 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
147 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
148 | } | |
149 | ||
01727e61 RV |
150 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
151 | unsigned offset, int gpio_mode, | |
152 | bool glitch) | |
153 | { | |
6c12fe88 RV |
154 | u32 rwimsc = nmk_chip->rwimsc; |
155 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
156 | |
157 | if (glitch && nmk_chip->set_ioforce) { | |
158 | u32 bit = BIT(offset); | |
159 | ||
01727e61 RV |
160 | /* Prevent spurious wakeups */ |
161 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
162 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
163 | ||
164 | nmk_chip->set_ioforce(true); | |
165 | } | |
166 | ||
167 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
168 | ||
169 | if (glitch && nmk_chip->set_ioforce) { | |
170 | nmk_chip->set_ioforce(false); | |
171 | ||
172 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
173 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
174 | } | |
175 | } | |
176 | ||
378be066 | 177 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 178 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
179 | { |
180 | static const char *afnames[] = { | |
181 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
182 | [NMK_GPIO_ALT_A] = "A", | |
183 | [NMK_GPIO_ALT_B] = "B", | |
184 | [NMK_GPIO_ALT_C] = "C" | |
185 | }; | |
186 | static const char *pullnames[] = { | |
187 | [NMK_GPIO_PULL_NONE] = "none", | |
188 | [NMK_GPIO_PULL_UP] = "up", | |
189 | [NMK_GPIO_PULL_DOWN] = "down", | |
190 | [3] /* illegal */ = "??" | |
191 | }; | |
192 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
193 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
194 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
195 | }; |
196 | ||
197 | int pin = PIN_NUM(cfg); | |
198 | int pull = PIN_PULL(cfg); | |
199 | int af = PIN_ALT(cfg); | |
200 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
201 | int output = PIN_DIR(cfg); |
202 | int val = PIN_VAL(cfg); | |
01727e61 | 203 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 204 | |
dacdc96c RV |
205 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
206 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
207 | output ? "output " : "input", |
208 | output ? (val ? "high" : "low") : ""); | |
209 | ||
dacdc96c RV |
210 | if (sleep) { |
211 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
212 | int slpm_output = PIN_SLPM_DIR(cfg); | |
213 | int slpm_val = PIN_SLPM_VAL(cfg); | |
214 | ||
3546d15c RV |
215 | af = NMK_GPIO_ALT_GPIO; |
216 | ||
dacdc96c RV |
217 | /* |
218 | * The SLPM_* values are normal values + 1 to allow zero to | |
219 | * mean "same as normal". | |
220 | */ | |
221 | if (slpm_pull) | |
222 | pull = slpm_pull - 1; | |
223 | if (slpm_output) | |
224 | output = slpm_output - 1; | |
225 | if (slpm_val) | |
226 | val = slpm_val - 1; | |
227 | ||
228 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
229 | pin, | |
230 | slpm_pull ? pullnames[pull] : "same", | |
231 | slpm_output ? (output ? "output" : "input") : "same", | |
232 | slpm_val ? (val ? "high" : "low") : "same"); | |
233 | } | |
234 | ||
6720db7c RV |
235 | if (output) |
236 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
237 | else { | |
238 | __nmk_gpio_make_input(nmk_chip, offset); | |
239 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
240 | } | |
378be066 | 241 | |
01727e61 RV |
242 | /* |
243 | * If we've backed up the SLPM registers (glitch workaround), modify | |
244 | * the backups since they will be restored. | |
245 | */ | |
246 | if (slpmregs) { | |
247 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
248 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
249 | else | |
250 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
251 | } else | |
252 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
253 | ||
254 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
255 | } | |
256 | ||
257 | /* | |
258 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
259 | * - Save SLPM registers | |
260 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
261 | * - Configure the GPIO registers for the IOs that are being switched | |
262 | * - Set IOFORCE=1 | |
263 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
264 | * - Set IOFORCE=0 | |
265 | * - Restore SLPM registers | |
266 | * - Any spurious wake up event during switch sequence to be ignored and | |
267 | * cleared | |
268 | */ | |
269 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
270 | { | |
271 | int i; | |
272 | ||
273 | for (i = 0; i < NUM_BANKS; i++) { | |
274 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
275 | unsigned int temp = slpm[i]; | |
276 | ||
277 | if (!chip) | |
278 | break; | |
279 | ||
3c0227d2 RV |
280 | clk_enable(chip->clk); |
281 | ||
01727e61 RV |
282 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
283 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
284 | } | |
285 | } | |
286 | ||
287 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
288 | { | |
289 | int i; | |
290 | ||
291 | for (i = 0; i < NUM_BANKS; i++) { | |
292 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
293 | ||
294 | if (!chip) | |
295 | break; | |
296 | ||
297 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
298 | |
299 | clk_disable(chip->clk); | |
01727e61 RV |
300 | } |
301 | } | |
302 | ||
303 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
304 | { | |
305 | static unsigned int slpm[NUM_BANKS]; | |
306 | unsigned long flags; | |
307 | bool glitch = false; | |
308 | int ret = 0; | |
309 | int i; | |
310 | ||
311 | for (i = 0; i < num; i++) { | |
312 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
313 | glitch = true; | |
314 | break; | |
315 | } | |
316 | } | |
317 | ||
318 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
319 | ||
320 | if (glitch) { | |
321 | memset(slpm, 0xff, sizeof(slpm)); | |
322 | ||
323 | for (i = 0; i < num; i++) { | |
324 | int pin = PIN_NUM(cfgs[i]); | |
325 | int offset = pin % NMK_GPIO_PER_CHIP; | |
326 | ||
327 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
328 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
329 | } | |
330 | ||
331 | nmk_gpio_glitch_slpm_init(slpm); | |
332 | } | |
333 | ||
334 | for (i = 0; i < num; i++) { | |
335 | struct nmk_gpio_chip *nmk_chip; | |
336 | int pin = PIN_NUM(cfgs[i]); | |
337 | ||
6845664a | 338 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
01727e61 RV |
339 | if (!nmk_chip) { |
340 | ret = -EINVAL; | |
341 | break; | |
342 | } | |
343 | ||
3c0227d2 | 344 | clk_enable(nmk_chip->clk); |
01727e61 RV |
345 | spin_lock(&nmk_chip->lock); |
346 | __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, | |
347 | cfgs[i], sleep, glitch ? slpm : NULL); | |
348 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 349 | clk_disable(nmk_chip->clk); |
01727e61 RV |
350 | } |
351 | ||
352 | if (glitch) | |
353 | nmk_gpio_glitch_slpm_restore(slpm); | |
354 | ||
355 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
356 | ||
357 | return ret; | |
378be066 RV |
358 | } |
359 | ||
360 | /** | |
361 | * nmk_config_pin - configure a pin's mux attributes | |
362 | * @cfg: pin confguration | |
363 | * | |
364 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
365 | * and its sleep mode based on the specified configuration. The @cfg is | |
366 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
367 | * are constructed using, and can be further enhanced with, the macros in | |
368 | * plat/pincfg.h. | |
369 | * | |
370 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
371 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
372 | * calls. | |
373 | */ | |
dacdc96c | 374 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 375 | { |
01727e61 | 376 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
377 | } |
378 | EXPORT_SYMBOL(nmk_config_pin); | |
379 | ||
380 | /** | |
381 | * nmk_config_pins - configure several pins at once | |
382 | * @cfgs: array of pin configurations | |
383 | * @num: number of elments in the array | |
384 | * | |
385 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
386 | * further information. | |
387 | */ | |
388 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
389 | { | |
01727e61 | 390 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
391 | } |
392 | EXPORT_SYMBOL(nmk_config_pins); | |
393 | ||
dacdc96c RV |
394 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
395 | { | |
01727e61 | 396 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
397 | } |
398 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
399 | ||
81a3c298 RV |
400 | /** |
401 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
402 | * @gpio: pin number | |
403 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
404 | * | |
33d78647 LW |
405 | * This register is actually in the pinmux layer, not the GPIO block itself. |
406 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
407 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
408 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
409 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
410 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
411 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 412 | * |
33d78647 LW |
413 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
414 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
415 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
416 | * ENABLED. | |
417 | * | |
418 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
419 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
420 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
421 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
422 | * | |
423 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
424 | */ |
425 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
426 | { | |
427 | struct nmk_gpio_chip *nmk_chip; | |
428 | unsigned long flags; | |
429 | ||
6845664a | 430 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
81a3c298 RV |
431 | if (!nmk_chip) |
432 | return -EINVAL; | |
433 | ||
3c0227d2 | 434 | clk_enable(nmk_chip->clk); |
01727e61 RV |
435 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
436 | spin_lock(&nmk_chip->lock); | |
437 | ||
81a3c298 | 438 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); |
01727e61 RV |
439 | |
440 | spin_unlock(&nmk_chip->lock); | |
441 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 442 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
443 | |
444 | return 0; | |
445 | } | |
446 | ||
5b327edf RV |
447 | /** |
448 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
449 | * @gpio: pin number | |
450 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
451 | * | |
452 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
453 | * the pin is configured as an input (either explicitly or by the alternate | |
454 | * function). | |
455 | * | |
456 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
457 | * configured as an input. Otherwise, due to the way the controller registers | |
458 | * work, this function will change the value output on the pin. | |
459 | */ | |
460 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
461 | { | |
462 | struct nmk_gpio_chip *nmk_chip; | |
463 | unsigned long flags; | |
464 | ||
6845664a | 465 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
5b327edf RV |
466 | if (!nmk_chip) |
467 | return -EINVAL; | |
468 | ||
3c0227d2 | 469 | clk_enable(nmk_chip->clk); |
5b327edf RV |
470 | spin_lock_irqsave(&nmk_chip->lock, flags); |
471 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
472 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
3c0227d2 | 473 | clk_disable(nmk_chip->clk); |
5b327edf RV |
474 | |
475 | return 0; | |
476 | } | |
477 | ||
2ec1d359 | 478 | /* Mode functions */ |
9c66ee6f JA |
479 | /** |
480 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
481 | * @gpio: pin number | |
482 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
483 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
484 | * | |
485 | * Sets the mode of the specified pin to one of the alternate functions or | |
486 | * plain GPIO. | |
487 | */ | |
2ec1d359 AR |
488 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
489 | { | |
490 | struct nmk_gpio_chip *nmk_chip; | |
491 | unsigned long flags; | |
2ec1d359 | 492 | |
6845664a | 493 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
494 | if (!nmk_chip) |
495 | return -EINVAL; | |
496 | ||
3c0227d2 | 497 | clk_enable(nmk_chip->clk); |
2ec1d359 | 498 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 499 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 | 500 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 501 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
502 | |
503 | return 0; | |
504 | } | |
505 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
506 | ||
507 | int nmk_gpio_get_mode(int gpio) | |
508 | { | |
509 | struct nmk_gpio_chip *nmk_chip; | |
510 | u32 afunc, bfunc, bit; | |
511 | ||
6845664a | 512 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
513 | if (!nmk_chip) |
514 | return -EINVAL; | |
515 | ||
516 | bit = 1 << (gpio - nmk_chip->chip.base); | |
517 | ||
3c0227d2 RV |
518 | clk_enable(nmk_chip->clk); |
519 | ||
2ec1d359 AR |
520 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
521 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
522 | ||
3c0227d2 RV |
523 | clk_disable(nmk_chip->clk); |
524 | ||
2ec1d359 AR |
525 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
526 | } | |
527 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
528 | ||
529 | ||
530 | /* IRQ functions */ | |
531 | static inline int nmk_gpio_get_bitmask(int gpio) | |
532 | { | |
533 | return 1 << (gpio % 32); | |
534 | } | |
535 | ||
f272c00e | 536 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 AR |
537 | { |
538 | int gpio; | |
539 | struct nmk_gpio_chip *nmk_chip; | |
540 | ||
f272c00e LB |
541 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
542 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
543 | if (!nmk_chip) |
544 | return; | |
3c0227d2 RV |
545 | |
546 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 547 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 548 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
549 | } |
550 | ||
4d4e20f7 RV |
551 | enum nmk_gpio_irq_type { |
552 | NORMAL, | |
553 | WAKE, | |
554 | }; | |
555 | ||
040e5ecd | 556 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
557 | int gpio, enum nmk_gpio_irq_type which, |
558 | bool enable) | |
2ec1d359 | 559 | { |
040e5ecd | 560 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
561 | u32 *rimscval; |
562 | u32 *fimscval; | |
563 | u32 rimscreg; | |
564 | u32 fimscreg; | |
565 | ||
566 | if (which == NORMAL) { | |
567 | rimscreg = NMK_GPIO_RIMSC; | |
568 | fimscreg = NMK_GPIO_FIMSC; | |
569 | rimscval = &nmk_chip->rimsc; | |
570 | fimscval = &nmk_chip->fimsc; | |
571 | } else { | |
572 | rimscreg = NMK_GPIO_RWIMSC; | |
573 | fimscreg = NMK_GPIO_FWIMSC; | |
574 | rimscval = &nmk_chip->rwimsc; | |
575 | fimscval = &nmk_chip->fwimsc; | |
576 | } | |
2ec1d359 | 577 | |
040e5ecd | 578 | /* we must individually set/clear the two edges */ |
2ec1d359 | 579 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 580 | if (enable) |
6c12fe88 | 581 | *rimscval |= bitmask; |
040e5ecd | 582 | else |
6c12fe88 RV |
583 | *rimscval &= ~bitmask; |
584 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
585 | } |
586 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 587 | if (enable) |
6c12fe88 | 588 | *fimscval |= bitmask; |
040e5ecd | 589 | else |
6c12fe88 RV |
590 | *fimscval &= ~bitmask; |
591 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 592 | } |
040e5ecd | 593 | } |
2ec1d359 | 594 | |
b9df468d RV |
595 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
596 | int gpio, bool on) | |
597 | { | |
b982ff0e RV |
598 | /* |
599 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
600 | * disabled, since setting SLPM to 1 increases power consumption, and | |
601 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
602 | */ | |
603 | if (nmk_chip->sleepmode && on) { | |
33d78647 | 604 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, |
b982ff0e | 605 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
606 | } |
607 | ||
b9df468d RV |
608 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
609 | } | |
610 | ||
611 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 AR |
612 | { |
613 | int gpio; | |
614 | struct nmk_gpio_chip *nmk_chip; | |
615 | unsigned long flags; | |
040e5ecd | 616 | u32 bitmask; |
2ec1d359 | 617 | |
f272c00e LB |
618 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
619 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
620 | bitmask = nmk_gpio_get_bitmask(gpio); |
621 | if (!nmk_chip) | |
4d4e20f7 | 622 | return -EINVAL; |
2ec1d359 | 623 | |
3c0227d2 | 624 | clk_enable(nmk_chip->clk); |
b9df468d RV |
625 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
626 | spin_lock(&nmk_chip->lock); | |
627 | ||
628 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); | |
629 | ||
630 | if (!(nmk_chip->real_wake & bitmask)) | |
631 | __nmk_gpio_set_wake(nmk_chip, gpio, enable); | |
632 | ||
633 | spin_unlock(&nmk_chip->lock); | |
634 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 635 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
636 | |
637 | return 0; | |
2ec1d359 AR |
638 | } |
639 | ||
f272c00e | 640 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 641 | { |
b9df468d | 642 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 643 | } |
040e5ecd | 644 | |
f272c00e | 645 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 646 | { |
b9df468d | 647 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
648 | } |
649 | ||
f272c00e | 650 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 651 | { |
7e3f7e59 RV |
652 | struct nmk_gpio_chip *nmk_chip; |
653 | unsigned long flags; | |
b9df468d | 654 | u32 bitmask; |
7e3f7e59 RV |
655 | int gpio; |
656 | ||
f272c00e LB |
657 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
658 | nmk_chip = irq_data_get_irq_chip_data(d); | |
7e3f7e59 RV |
659 | if (!nmk_chip) |
660 | return -EINVAL; | |
b9df468d | 661 | bitmask = nmk_gpio_get_bitmask(gpio); |
7e3f7e59 | 662 | |
3c0227d2 | 663 | clk_enable(nmk_chip->clk); |
01727e61 RV |
664 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
665 | spin_lock(&nmk_chip->lock); | |
666 | ||
479a0c7e | 667 | if (irqd_irq_disabled(d)) |
b9df468d RV |
668 | __nmk_gpio_set_wake(nmk_chip, gpio, on); |
669 | ||
670 | if (on) | |
671 | nmk_chip->real_wake |= bitmask; | |
672 | else | |
673 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
674 | |
675 | spin_unlock(&nmk_chip->lock); | |
676 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 677 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
678 | |
679 | return 0; | |
040e5ecd RV |
680 | } |
681 | ||
f272c00e | 682 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 683 | { |
479a0c7e | 684 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 685 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
686 | int gpio; |
687 | struct nmk_gpio_chip *nmk_chip; | |
688 | unsigned long flags; | |
689 | u32 bitmask; | |
690 | ||
f272c00e LB |
691 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
692 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
693 | bitmask = nmk_gpio_get_bitmask(gpio); |
694 | if (!nmk_chip) | |
695 | return -EINVAL; | |
696 | ||
697 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
698 | return -EINVAL; | |
699 | if (type & IRQ_TYPE_LEVEL_LOW) | |
700 | return -EINVAL; | |
701 | ||
3c0227d2 | 702 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
703 | spin_lock_irqsave(&nmk_chip->lock, flags); |
704 | ||
7a852d80 | 705 | if (enabled) |
4d4e20f7 RV |
706 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
707 | ||
b9df468d | 708 | if (enabled || wake) |
4d4e20f7 | 709 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); |
7a852d80 | 710 | |
2ec1d359 AR |
711 | nmk_chip->edge_rising &= ~bitmask; |
712 | if (type & IRQ_TYPE_EDGE_RISING) | |
713 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
714 | |
715 | nmk_chip->edge_falling &= ~bitmask; | |
716 | if (type & IRQ_TYPE_EDGE_FALLING) | |
717 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 718 | |
7a852d80 | 719 | if (enabled) |
4d4e20f7 RV |
720 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
721 | ||
b9df468d | 722 | if (enabled || wake) |
4d4e20f7 | 723 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); |
2ec1d359 | 724 | |
7a852d80 | 725 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 726 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
727 | |
728 | return 0; | |
729 | } | |
730 | ||
3c0227d2 RV |
731 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
732 | { | |
733 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 734 | |
3c0227d2 RV |
735 | clk_enable(nmk_chip->clk); |
736 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
737 | return 0; |
738 | } | |
739 | ||
3c0227d2 RV |
740 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
741 | { | |
742 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
743 | ||
744 | nmk_gpio_irq_mask(d); | |
745 | clk_disable(nmk_chip->clk); | |
746 | } | |
747 | ||
2ec1d359 AR |
748 | static struct irq_chip nmk_gpio_irq_chip = { |
749 | .name = "Nomadik-GPIO", | |
f272c00e LB |
750 | .irq_ack = nmk_gpio_irq_ack, |
751 | .irq_mask = nmk_gpio_irq_mask, | |
752 | .irq_unmask = nmk_gpio_irq_unmask, | |
753 | .irq_set_type = nmk_gpio_irq_set_type, | |
754 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
755 | .irq_startup = nmk_gpio_irq_startup, |
756 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
2ec1d359 AR |
757 | }; |
758 | ||
33b744b3 RV |
759 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
760 | u32 status) | |
2ec1d359 AR |
761 | { |
762 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 763 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
764 | unsigned int first_irq; |
765 | ||
adfed159 | 766 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 767 | |
6845664a | 768 | nmk_chip = irq_get_handler_data(irq); |
2ec1d359 | 769 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
33b744b3 RV |
770 | while (status) { |
771 | int bit = __ffs(status); | |
772 | ||
773 | generic_handle_irq(first_irq + bit); | |
774 | status &= ~BIT(bit); | |
2ec1d359 | 775 | } |
aaedaa2b | 776 | |
adfed159 | 777 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
778 | } |
779 | ||
33b744b3 RV |
780 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
781 | { | |
6845664a | 782 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
783 | u32 status; |
784 | ||
785 | clk_enable(nmk_chip->clk); | |
786 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
787 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
788 | |
789 | __nmk_gpio_irq_handler(irq, desc, status); | |
790 | } | |
791 | ||
792 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
793 | struct irq_desc *desc) | |
794 | { | |
6845664a | 795 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
796 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
797 | ||
798 | __nmk_gpio_irq_handler(irq, desc, status); | |
799 | } | |
800 | ||
2ec1d359 AR |
801 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
802 | { | |
803 | unsigned int first_irq; | |
804 | int i; | |
805 | ||
806 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
e493e06f | 807 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
f38c02f3 TG |
808 | irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, |
809 | handle_edge_irq); | |
2ec1d359 | 810 | set_irq_flags(i, IRQF_VALID); |
6845664a TG |
811 | irq_set_chip_data(i, nmk_chip); |
812 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | |
2ec1d359 | 813 | } |
33b744b3 | 814 | |
6845664a TG |
815 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
816 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
817 | |
818 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 819 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 820 | nmk_gpio_secondary_irq_handler); |
6845664a | 821 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
822 | } |
823 | ||
2ec1d359 AR |
824 | return 0; |
825 | } | |
826 | ||
827 | /* I/O Functions */ | |
828 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
829 | { | |
830 | struct nmk_gpio_chip *nmk_chip = | |
831 | container_of(chip, struct nmk_gpio_chip, chip); | |
832 | ||
3c0227d2 RV |
833 | clk_enable(nmk_chip->clk); |
834 | ||
2ec1d359 | 835 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
836 | |
837 | clk_disable(nmk_chip->clk); | |
838 | ||
2ec1d359 AR |
839 | return 0; |
840 | } | |
841 | ||
2ec1d359 AR |
842 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
843 | { | |
844 | struct nmk_gpio_chip *nmk_chip = | |
845 | container_of(chip, struct nmk_gpio_chip, chip); | |
846 | u32 bit = 1 << offset; | |
3c0227d2 RV |
847 | int value; |
848 | ||
849 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 850 | |
3c0227d2 | 851 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 852 | |
3c0227d2 RV |
853 | clk_disable(nmk_chip->clk); |
854 | ||
855 | return value; | |
2ec1d359 AR |
856 | } |
857 | ||
858 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
859 | int val) | |
860 | { | |
861 | struct nmk_gpio_chip *nmk_chip = | |
862 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 863 | |
3c0227d2 RV |
864 | clk_enable(nmk_chip->clk); |
865 | ||
6720db7c | 866 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
867 | |
868 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
869 | } |
870 | ||
6647c6c0 RV |
871 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
872 | int val) | |
873 | { | |
874 | struct nmk_gpio_chip *nmk_chip = | |
875 | container_of(chip, struct nmk_gpio_chip, chip); | |
876 | ||
3c0227d2 RV |
877 | clk_enable(nmk_chip->clk); |
878 | ||
6720db7c | 879 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 880 | |
3c0227d2 RV |
881 | clk_disable(nmk_chip->clk); |
882 | ||
6647c6c0 RV |
883 | return 0; |
884 | } | |
885 | ||
0d2aec9c RV |
886 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
887 | { | |
888 | struct nmk_gpio_chip *nmk_chip = | |
889 | container_of(chip, struct nmk_gpio_chip, chip); | |
890 | ||
891 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
892 | } | |
893 | ||
d0b543c7 RV |
894 | #ifdef CONFIG_DEBUG_FS |
895 | ||
896 | #include <linux/seq_file.h> | |
897 | ||
898 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
899 | { | |
900 | int mode; | |
901 | unsigned i; | |
902 | unsigned gpio = chip->base; | |
903 | int is_out; | |
904 | struct nmk_gpio_chip *nmk_chip = | |
905 | container_of(chip, struct nmk_gpio_chip, chip); | |
906 | const char *modes[] = { | |
907 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
908 | [NMK_GPIO_ALT_A] = "altA", | |
909 | [NMK_GPIO_ALT_B] = "altB", | |
910 | [NMK_GPIO_ALT_C] = "altC", | |
911 | }; | |
912 | ||
3c0227d2 RV |
913 | clk_enable(nmk_chip->clk); |
914 | ||
d0b543c7 RV |
915 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
916 | const char *label = gpiochip_is_requested(chip, i); | |
917 | bool pull; | |
918 | u32 bit = 1 << i; | |
919 | ||
d0b543c7 RV |
920 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; |
921 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
922 | mode = nmk_gpio_get_mode(gpio); | |
923 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
8ea72a30 | 924 | gpio, label ?: "(none)", |
d0b543c7 RV |
925 | is_out ? "out" : "in ", |
926 | chip->get | |
927 | ? (chip->get(chip, i) ? "hi" : "lo") | |
928 | : "? ", | |
929 | (mode < 0) ? "unknown" : modes[mode], | |
930 | pull ? "pull" : "none"); | |
8ea72a30 RV |
931 | |
932 | if (label && !is_out) { | |
933 | int irq = gpio_to_irq(gpio); | |
934 | struct irq_desc *desc = irq_to_desc(irq); | |
935 | ||
936 | /* This races with request_irq(), set_irq_type(), | |
937 | * and set_irq_wake() ... but those are "rare". | |
938 | */ | |
939 | if (irq >= 0 && desc->action) { | |
940 | char *trigger; | |
941 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
942 | ||
943 | if (nmk_chip->edge_rising & bitmask) | |
944 | trigger = "edge-rising"; | |
945 | else if (nmk_chip->edge_falling & bitmask) | |
946 | trigger = "edge-falling"; | |
947 | else | |
948 | trigger = "edge-undefined"; | |
949 | ||
950 | seq_printf(s, " irq-%d %s%s", | |
951 | irq, trigger, | |
952 | irqd_is_wakeup_set(&desc->irq_data) | |
953 | ? " wakeup" : ""); | |
954 | } | |
955 | } | |
956 | ||
d0b543c7 RV |
957 | seq_printf(s, "\n"); |
958 | } | |
3c0227d2 RV |
959 | |
960 | clk_disable(nmk_chip->clk); | |
d0b543c7 RV |
961 | } |
962 | ||
963 | #else | |
964 | #define nmk_gpio_dbg_show NULL | |
965 | #endif | |
966 | ||
2ec1d359 AR |
967 | /* This structure is replicated for each GPIO block allocated at probe time */ |
968 | static struct gpio_chip nmk_gpio_template = { | |
969 | .direction_input = nmk_gpio_make_input, | |
970 | .get = nmk_gpio_get_input, | |
971 | .direction_output = nmk_gpio_make_output, | |
972 | .set = nmk_gpio_set_output, | |
0d2aec9c | 973 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 974 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
975 | .can_sleep = 0, |
976 | }; | |
977 | ||
3c0227d2 RV |
978 | void nmk_gpio_clocks_enable(void) |
979 | { | |
980 | int i; | |
981 | ||
982 | for (i = 0; i < NUM_BANKS; i++) { | |
983 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
984 | ||
985 | if (!chip) | |
986 | continue; | |
987 | ||
988 | clk_enable(chip->clk); | |
989 | } | |
990 | } | |
991 | ||
992 | void nmk_gpio_clocks_disable(void) | |
993 | { | |
994 | int i; | |
995 | ||
996 | for (i = 0; i < NUM_BANKS; i++) { | |
997 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
998 | ||
999 | if (!chip) | |
1000 | continue; | |
1001 | ||
1002 | clk_disable(chip->clk); | |
1003 | } | |
1004 | } | |
1005 | ||
b9df468d RV |
1006 | /* |
1007 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1008 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1009 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1010 | * cpuidle. | |
1011 | * | |
1012 | * PM ops are not used since this needs to be done at the end, after all the | |
1013 | * other drivers are done with their suspend callbacks. | |
1014 | */ | |
1015 | void nmk_gpio_wakeups_suspend(void) | |
1016 | { | |
1017 | int i; | |
1018 | ||
1019 | for (i = 0; i < NUM_BANKS; i++) { | |
1020 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1021 | ||
1022 | if (!chip) | |
1023 | break; | |
1024 | ||
3c0227d2 RV |
1025 | clk_enable(chip->clk); |
1026 | ||
b9df468d RV |
1027 | writel(chip->rwimsc & chip->real_wake, |
1028 | chip->addr + NMK_GPIO_RWIMSC); | |
1029 | writel(chip->fwimsc & chip->real_wake, | |
1030 | chip->addr + NMK_GPIO_FWIMSC); | |
1031 | ||
3c0227d2 | 1032 | clk_disable(chip->clk); |
b9df468d RV |
1033 | } |
1034 | } | |
1035 | ||
1036 | void nmk_gpio_wakeups_resume(void) | |
1037 | { | |
1038 | int i; | |
1039 | ||
1040 | for (i = 0; i < NUM_BANKS; i++) { | |
1041 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1042 | ||
1043 | if (!chip) | |
1044 | break; | |
1045 | ||
3c0227d2 RV |
1046 | clk_enable(chip->clk); |
1047 | ||
b9df468d RV |
1048 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1049 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1050 | ||
3c0227d2 | 1051 | clk_disable(chip->clk); |
b9df468d RV |
1052 | } |
1053 | } | |
1054 | ||
bc6f5cf6 RA |
1055 | /* |
1056 | * Read the pull up/pull down status. | |
1057 | * A bit set in 'pull_up' means that pull up | |
1058 | * is selected if pull is enabled in PDIS register. | |
1059 | * Note: only pull up/down set via this driver can | |
1060 | * be detected due to HW limitations. | |
1061 | */ | |
1062 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1063 | { | |
1064 | if (gpio_bank < NUM_BANKS) { | |
1065 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1066 | ||
1067 | if (!chip) | |
1068 | return; | |
1069 | ||
1070 | *pull_up = chip->pull_up; | |
1071 | } | |
1072 | } | |
1073 | ||
fd0d67d6 | 1074 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1075 | { |
3e3c62ca | 1076 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
2ec1d359 AR |
1077 | struct nmk_gpio_chip *nmk_chip; |
1078 | struct gpio_chip *chip; | |
3e3c62ca | 1079 | struct resource *res; |
af7dc228 | 1080 | struct clk *clk; |
33b744b3 | 1081 | int secondary_irq; |
3e3c62ca | 1082 | int irq; |
2ec1d359 AR |
1083 | int ret; |
1084 | ||
3e3c62ca RV |
1085 | if (!pdata) |
1086 | return -ENODEV; | |
1087 | ||
1088 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1089 | if (!res) { | |
1090 | ret = -ENOENT; | |
1091 | goto out; | |
1092 | } | |
1093 | ||
1094 | irq = platform_get_irq(dev, 0); | |
1095 | if (irq < 0) { | |
1096 | ret = irq; | |
1097 | goto out; | |
1098 | } | |
1099 | ||
33b744b3 RV |
1100 | secondary_irq = platform_get_irq(dev, 1); |
1101 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1102 | ret = -EINVAL; | |
1103 | goto out; | |
1104 | } | |
1105 | ||
3e3c62ca RV |
1106 | if (request_mem_region(res->start, resource_size(res), |
1107 | dev_name(&dev->dev)) == NULL) { | |
1108 | ret = -EBUSY; | |
1109 | goto out; | |
1110 | } | |
2ec1d359 | 1111 | |
af7dc228 RV |
1112 | clk = clk_get(&dev->dev, NULL); |
1113 | if (IS_ERR(clk)) { | |
1114 | ret = PTR_ERR(clk); | |
1115 | goto out_release; | |
1116 | } | |
1117 | ||
2ec1d359 AR |
1118 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
1119 | if (!nmk_chip) { | |
1120 | ret = -ENOMEM; | |
af7dc228 | 1121 | goto out_clk; |
2ec1d359 AR |
1122 | } |
1123 | /* | |
1124 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1125 | * so we can simply convert the resource address, without remapping | |
1126 | */ | |
33b744b3 | 1127 | nmk_chip->bank = dev->id; |
af7dc228 | 1128 | nmk_chip->clk = clk; |
3e3c62ca | 1129 | nmk_chip->addr = io_p2v(res->start); |
2ec1d359 | 1130 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1131 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1132 | nmk_chip->secondary_parent_irq = secondary_irq; |
1133 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1134 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1135 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1136 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1137 | |
1138 | chip = &nmk_chip->chip; | |
1139 | chip->base = pdata->first_gpio; | |
e493e06f | 1140 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1141 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1142 | chip->dev = &dev->dev; |
1143 | chip->owner = THIS_MODULE; | |
1144 | ||
1145 | ret = gpiochip_add(&nmk_chip->chip); | |
1146 | if (ret) | |
1147 | goto out_free; | |
1148 | ||
01727e61 RV |
1149 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1150 | ||
1151 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
3e3c62ca | 1152 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
1153 | |
1154 | nmk_gpio_init_irq(nmk_chip); | |
1155 | ||
64842aad GL |
1156 | dev_info(&dev->dev, "at address %p\n", |
1157 | nmk_chip->addr); | |
2ec1d359 AR |
1158 | return 0; |
1159 | ||
3e3c62ca | 1160 | out_free: |
2ec1d359 | 1161 | kfree(nmk_chip); |
af7dc228 RV |
1162 | out_clk: |
1163 | clk_disable(clk); | |
1164 | clk_put(clk); | |
3e3c62ca RV |
1165 | out_release: |
1166 | release_mem_region(res->start, resource_size(res)); | |
1167 | out: | |
2ec1d359 AR |
1168 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1169 | pdata->first_gpio, pdata->first_gpio+31); | |
1170 | return ret; | |
1171 | } | |
1172 | ||
3e3c62ca RV |
1173 | static struct platform_driver nmk_gpio_driver = { |
1174 | .driver = { | |
2ec1d359 AR |
1175 | .owner = THIS_MODULE, |
1176 | .name = "gpio", | |
5317e4d1 | 1177 | }, |
2ec1d359 | 1178 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1179 | }; |
1180 | ||
1181 | static int __init nmk_gpio_init(void) | |
1182 | { | |
3e3c62ca | 1183 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
1184 | } |
1185 | ||
33f45ea9 | 1186 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1187 | |
1188 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1189 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1190 | MODULE_LICENSE("GPL"); |