Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 TKD |
31 | #define OFF_MODE 1 |
32 | ||
03e128ca C |
33 | static LIST_HEAD(omap_gpio_list); |
34 | ||
6d62e216 C |
35 | struct gpio_regs { |
36 | u32 irqenable1; | |
37 | u32 irqenable2; | |
38 | u32 wake_en; | |
39 | u32 ctrl; | |
40 | u32 oe; | |
41 | u32 leveldetect0; | |
42 | u32 leveldetect1; | |
43 | u32 risingdetect; | |
44 | u32 fallingdetect; | |
45 | u32 dataout; | |
ae547354 NM |
46 | u32 debounce; |
47 | u32 debounce_en; | |
6d62e216 C |
48 | }; |
49 | ||
5e1c5ff4 | 50 | struct gpio_bank { |
03e128ca | 51 | struct list_head node; |
92105bb7 | 52 | void __iomem *base; |
5e1c5ff4 | 53 | u16 irq; |
3ac4fa99 JY |
54 | u32 non_wakeup_gpios; |
55 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 56 | struct gpio_regs context; |
3ac4fa99 | 57 | u32 saved_datain; |
b144ff6f | 58 | u32 level_mask; |
4318f36b | 59 | u32 toggle_mask; |
5e1c5ff4 | 60 | spinlock_t lock; |
52e31344 | 61 | struct gpio_chip chip; |
89db9482 | 62 | struct clk *dbck; |
058af1ea | 63 | u32 mod_usage; |
fa365e4d | 64 | u32 irq_usage; |
8865b9b6 | 65 | u32 dbck_enable_mask; |
72f83af9 | 66 | bool dbck_enabled; |
77640aab | 67 | struct device *dev; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
2dc983c5 TKD |
75 | int power_mode; |
76 | bool workaround_enabled; | |
fa87931a | 77 | |
04ebcbd8 | 78 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 79 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
80 | |
81 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
82 | }; |
83 | ||
c8eef65a | 84 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 85 | |
fa365e4d | 86 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 87 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 88 | |
3d009c8c TL |
89 | static void omap_gpio_unmask_irq(struct irq_data *d); |
90 | ||
a0e827c6 | 91 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 92 | { |
fb655f57 JMC |
93 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
94 | return container_of(chip, struct gpio_bank, chip); | |
25db711d BC |
95 | } |
96 | ||
a0e827c6 JMC |
97 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
98 | int is_input) | |
5e1c5ff4 | 99 | { |
92105bb7 | 100 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
101 | u32 l; |
102 | ||
fa87931a | 103 | reg += bank->regs->direction; |
661553b9 | 104 | l = readl_relaxed(reg); |
5e1c5ff4 | 105 | if (is_input) |
b1e9fec2 | 106 | l |= BIT(gpio); |
5e1c5ff4 | 107 | else |
b1e9fec2 | 108 | l &= ~(BIT(gpio)); |
661553b9 | 109 | writel_relaxed(l, reg); |
41d87cbd | 110 | bank->context.oe = l; |
5e1c5ff4 TL |
111 | } |
112 | ||
fa87931a KH |
113 | |
114 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 115 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 116 | int enable) |
5e1c5ff4 | 117 | { |
92105bb7 | 118 | void __iomem *reg = bank->base; |
04ebcbd8 | 119 | u32 l = BIT(offset); |
5e1c5ff4 | 120 | |
2c836f7e | 121 | if (enable) { |
fa87931a | 122 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
123 | bank->context.dataout |= l; |
124 | } else { | |
fa87931a | 125 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
126 | bank->context.dataout &= ~l; |
127 | } | |
5e1c5ff4 | 128 | |
661553b9 | 129 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
130 | } |
131 | ||
fa87931a | 132 | /* set data out value using mask register */ |
04ebcbd8 | 133 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 134 | int enable) |
5e1c5ff4 | 135 | { |
fa87931a | 136 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 137 | u32 gpio_bit = BIT(offset); |
fa87931a | 138 | u32 l; |
5e1c5ff4 | 139 | |
661553b9 | 140 | l = readl_relaxed(reg); |
fa87931a KH |
141 | if (enable) |
142 | l |= gpio_bit; | |
143 | else | |
144 | l &= ~gpio_bit; | |
661553b9 | 145 | writel_relaxed(l, reg); |
41d87cbd | 146 | bank->context.dataout = l; |
5e1c5ff4 TL |
147 | } |
148 | ||
a0e827c6 | 149 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 150 | { |
fa87931a | 151 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 152 | |
b1e9fec2 | 153 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 154 | } |
b37c45b8 | 155 | |
a0e827c6 | 156 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 157 | { |
fa87931a | 158 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 159 | |
b1e9fec2 | 160 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
161 | } |
162 | ||
a0e827c6 | 163 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 164 | { |
661553b9 | 165 | int l = readl_relaxed(base + reg); |
ece9528e | 166 | |
862ff640 | 167 | if (set) |
ece9528e KH |
168 | l |= mask; |
169 | else | |
170 | l &= ~mask; | |
171 | ||
661553b9 | 172 | writel_relaxed(l, base + reg); |
ece9528e | 173 | } |
92105bb7 | 174 | |
a0e827c6 | 175 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
176 | { |
177 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
345477ff | 178 | clk_prepare_enable(bank->dbck); |
72f83af9 | 179 | bank->dbck_enabled = true; |
9e303f22 | 180 | |
661553b9 | 181 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 182 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
183 | } |
184 | } | |
185 | ||
a0e827c6 | 186 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
187 | { |
188 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
189 | /* |
190 | * Disable debounce before cutting it's clock. If debounce is | |
191 | * enabled but the clock is not, GPIO module seems to be unable | |
192 | * to detect events and generate interrupts at least on OMAP3. | |
193 | */ | |
661553b9 | 194 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 195 | |
345477ff | 196 | clk_disable_unprepare(bank->dbck); |
72f83af9 TKD |
197 | bank->dbck_enabled = false; |
198 | } | |
199 | } | |
200 | ||
168ef3d9 | 201 | /** |
a0e827c6 | 202 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 203 | * @bank: the gpio bank we're acting upon |
4a58d229 | 204 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
205 | * @debounce: debounce time to use |
206 | * | |
207 | * OMAP's debounce time is in 31us steps so we need | |
208 | * to convert and round up to the closest unit. | |
209 | */ | |
4a58d229 | 210 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 211 | unsigned debounce) |
168ef3d9 | 212 | { |
9942da0e | 213 | void __iomem *reg; |
168ef3d9 FB |
214 | u32 val; |
215 | u32 l; | |
216 | ||
77640aab VC |
217 | if (!bank->dbck_flag) |
218 | return; | |
219 | ||
168ef3d9 FB |
220 | if (debounce < 32) |
221 | debounce = 0x01; | |
222 | else if (debounce > 7936) | |
223 | debounce = 0xff; | |
224 | else | |
225 | debounce = (debounce / 0x1f) - 1; | |
226 | ||
4a58d229 | 227 | l = BIT(offset); |
168ef3d9 | 228 | |
345477ff | 229 | clk_prepare_enable(bank->dbck); |
9942da0e | 230 | reg = bank->base + bank->regs->debounce; |
661553b9 | 231 | writel_relaxed(debounce, reg); |
168ef3d9 | 232 | |
9942da0e | 233 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 234 | val = readl_relaxed(reg); |
168ef3d9 | 235 | |
6fd9c421 | 236 | if (debounce) |
168ef3d9 | 237 | val |= l; |
6fd9c421 | 238 | else |
168ef3d9 | 239 | val &= ~l; |
f7ec0b0b | 240 | bank->dbck_enable_mask = val; |
168ef3d9 | 241 | |
661553b9 | 242 | writel_relaxed(val, reg); |
345477ff | 243 | clk_disable_unprepare(bank->dbck); |
6fd9c421 TKD |
244 | /* |
245 | * Enable debounce clock per module. | |
246 | * This call is mandatory because in omap_gpio_request() when | |
247 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
248 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
249 | * used within _gpio_dbck_enable() is still not initialized at | |
250 | * that point. Therefore we have to enable dbck here. | |
251 | */ | |
a0e827c6 | 252 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
253 | if (bank->dbck_enable_mask) { |
254 | bank->context.debounce = debounce; | |
255 | bank->context.debounce_en = val; | |
256 | } | |
168ef3d9 FB |
257 | } |
258 | ||
c9c55d92 | 259 | /** |
a0e827c6 | 260 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 261 | * @bank: the gpio bank we're acting upon |
4a58d229 | 262 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
263 | * |
264 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
265 | * this is the only gpio in this bank using debounce, then clear the debounce | |
266 | * time too. The debounce clock will also be disabled when calling this function | |
267 | * if this is the only gpio in the bank using debounce. | |
268 | */ | |
4a58d229 | 269 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 270 | { |
4a58d229 | 271 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
272 | |
273 | if (!bank->dbck_flag) | |
274 | return; | |
275 | ||
276 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
277 | return; | |
278 | ||
279 | bank->dbck_enable_mask &= ~gpio_bit; | |
280 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 281 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
282 | bank->base + bank->regs->debounce_en); |
283 | ||
284 | if (!bank->dbck_enable_mask) { | |
285 | bank->context.debounce = 0; | |
661553b9 | 286 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 287 | bank->regs->debounce); |
345477ff | 288 | clk_disable_unprepare(bank->dbck); |
c9c55d92 JH |
289 | bank->dbck_enabled = false; |
290 | } | |
291 | } | |
292 | ||
a0e827c6 | 293 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 294 | unsigned trigger) |
5e1c5ff4 | 295 | { |
3ac4fa99 | 296 | void __iomem *base = bank->base; |
b1e9fec2 | 297 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 298 | |
a0e827c6 JMC |
299 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
300 | trigger & IRQ_TYPE_LEVEL_LOW); | |
301 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
302 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
303 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
304 | trigger & IRQ_TYPE_EDGE_RISING); | |
305 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
306 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 307 | |
41d87cbd | 308 | bank->context.leveldetect0 = |
661553b9 | 309 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 310 | bank->context.leveldetect1 = |
661553b9 | 311 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 312 | bank->context.risingdetect = |
661553b9 | 313 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 314 | bank->context.fallingdetect = |
661553b9 | 315 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
316 | |
317 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 318 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 319 | bank->context.wake_en = |
661553b9 | 320 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 321 | } |
5e571f38 | 322 | |
55b220ca | 323 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
324 | if (!bank->regs->irqctrl) { |
325 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
326 | if (bank->non_wakeup_gpios) { | |
327 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
328 | goto exit; | |
329 | } | |
330 | ||
699117a6 CW |
331 | /* |
332 | * Log the edge gpio and manually trigger the IRQ | |
333 | * after resume if the input level changes | |
334 | * to avoid irq lost during PER RET/OFF mode | |
335 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
336 | */ | |
337 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
338 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
339 | else | |
340 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
341 | } | |
5eb3bb9c | 342 | |
5e571f38 | 343 | exit: |
9ea14d8c | 344 | bank->level_mask = |
661553b9 VK |
345 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
346 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
347 | } |
348 | ||
9198bcd3 | 349 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
350 | /* |
351 | * This only applies to chips that can't do both rising and falling edge | |
352 | * detection at once. For all other chips, this function is a noop. | |
353 | */ | |
a0e827c6 | 354 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
355 | { |
356 | void __iomem *reg = bank->base; | |
357 | u32 l = 0; | |
358 | ||
5e571f38 | 359 | if (!bank->regs->irqctrl) |
4318f36b | 360 | return; |
5e571f38 TKD |
361 | |
362 | reg += bank->regs->irqctrl; | |
4318f36b | 363 | |
661553b9 | 364 | l = readl_relaxed(reg); |
4318f36b | 365 | if ((l >> gpio) & 1) |
b1e9fec2 | 366 | l &= ~(BIT(gpio)); |
4318f36b | 367 | else |
b1e9fec2 | 368 | l |= BIT(gpio); |
4318f36b | 369 | |
661553b9 | 370 | writel_relaxed(l, reg); |
4318f36b | 371 | } |
5e571f38 | 372 | #else |
a0e827c6 | 373 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 374 | #endif |
4318f36b | 375 | |
a0e827c6 JMC |
376 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
377 | unsigned trigger) | |
92105bb7 TL |
378 | { |
379 | void __iomem *reg = bank->base; | |
5e571f38 | 380 | void __iomem *base = bank->base; |
92105bb7 | 381 | u32 l = 0; |
5e1c5ff4 | 382 | |
5e571f38 | 383 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 384 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
385 | } else if (bank->regs->irqctrl) { |
386 | reg += bank->regs->irqctrl; | |
387 | ||
661553b9 | 388 | l = readl_relaxed(reg); |
29501577 | 389 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 390 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 391 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 392 | l |= BIT(gpio); |
6cab4860 | 393 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 394 | l &= ~(BIT(gpio)); |
92105bb7 | 395 | else |
5e571f38 TKD |
396 | return -EINVAL; |
397 | ||
661553b9 | 398 | writel_relaxed(l, reg); |
5e571f38 | 399 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 400 | if (gpio & 0x08) |
5e571f38 | 401 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 402 | else |
5e571f38 TKD |
403 | reg += bank->regs->edgectrl1; |
404 | ||
5e1c5ff4 | 405 | gpio &= 0x07; |
661553b9 | 406 | l = readl_relaxed(reg); |
5e1c5ff4 | 407 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 408 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 409 | l |= 2 << (gpio << 1); |
6cab4860 | 410 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 411 | l |= BIT(gpio << 1); |
5e571f38 TKD |
412 | |
413 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 414 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 415 | bank->context.wake_en = |
661553b9 VK |
416 | readl_relaxed(bank->base + bank->regs->wkup_en); |
417 | writel_relaxed(l, reg); | |
5e1c5ff4 | 418 | } |
92105bb7 | 419 | return 0; |
5e1c5ff4 TL |
420 | } |
421 | ||
a0e827c6 | 422 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
423 | { |
424 | if (bank->regs->pinctrl) { | |
425 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
426 | ||
427 | /* Claim the pin for MPU */ | |
b1e9fec2 | 428 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
429 | } |
430 | ||
431 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
432 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
433 | u32 ctrl; | |
434 | ||
661553b9 | 435 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
436 | /* Module is enabled, clocks are not gated */ |
437 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 438 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
439 | bank->context.ctrl = ctrl; |
440 | } | |
441 | } | |
442 | ||
a0e827c6 | 443 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
444 | { |
445 | void __iomem *base = bank->base; | |
446 | ||
447 | if (bank->regs->wkup_en && | |
448 | !LINE_USED(bank->mod_usage, offset) && | |
449 | !LINE_USED(bank->irq_usage, offset)) { | |
450 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 451 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 452 | bank->context.wake_en = |
661553b9 | 453 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
454 | } |
455 | ||
456 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
457 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
458 | u32 ctrl; | |
459 | ||
661553b9 | 460 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
461 | /* Module is disabled, clocks are gated */ |
462 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 463 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
464 | bank->context.ctrl = ctrl; |
465 | } | |
466 | } | |
467 | ||
b2b20045 | 468 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
469 | { |
470 | void __iomem *reg = bank->base + bank->regs->direction; | |
471 | ||
b2b20045 | 472 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
473 | } |
474 | ||
37e14ecf | 475 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
476 | { |
477 | if (!LINE_USED(bank->mod_usage, offset)) { | |
478 | omap_enable_gpio_module(bank, offset); | |
479 | omap_set_gpio_direction(bank, offset, 1); | |
480 | } | |
37e14ecf | 481 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
482 | } |
483 | ||
a0e827c6 | 484 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 485 | { |
a0e827c6 | 486 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 487 | int retval; |
a6472533 | 488 | unsigned long flags; |
ea5fbe8d | 489 | unsigned offset = d->hwirq; |
92105bb7 | 490 | |
fac7fa16 JMC |
491 | if (!BANK_USED(bank)) |
492 | pm_runtime_get_sync(bank->dev); | |
8d4c277e | 493 | |
e5c56ed3 | 494 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 495 | return -EINVAL; |
e5c56ed3 | 496 | |
9ea14d8c TKD |
497 | if (!bank->regs->leveldetect0 && |
498 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
499 | return -EINVAL; |
500 | ||
a6472533 | 501 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 502 | retval = omap_set_gpio_triggering(bank, offset, type); |
37e14ecf | 503 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 504 | if (!omap_gpio_is_input(bank, offset)) { |
fac7fa16 JMC |
505 | spin_unlock_irqrestore(&bank->lock, flags); |
506 | return -EINVAL; | |
507 | } | |
a6472533 | 508 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
509 | |
510 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 511 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 512 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 513 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 514 | |
92105bb7 | 515 | return retval; |
5e1c5ff4 TL |
516 | } |
517 | ||
a0e827c6 | 518 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 519 | { |
92105bb7 | 520 | void __iomem *reg = bank->base; |
5e1c5ff4 | 521 | |
eef4bec7 | 522 | reg += bank->regs->irqstatus; |
661553b9 | 523 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
524 | |
525 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
526 | if (bank->regs->irqstatus2) { |
527 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 528 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 529 | } |
bedfd154 RQ |
530 | |
531 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 532 | readl_relaxed(reg); |
5e1c5ff4 TL |
533 | } |
534 | ||
9943f261 GS |
535 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
536 | unsigned offset) | |
5e1c5ff4 | 537 | { |
9943f261 | 538 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
539 | } |
540 | ||
a0e827c6 | 541 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
542 | { |
543 | void __iomem *reg = bank->base; | |
99c47707 | 544 | u32 l; |
b1e9fec2 | 545 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 546 | |
28f3b5a0 | 547 | reg += bank->regs->irqenable; |
661553b9 | 548 | l = readl_relaxed(reg); |
28f3b5a0 | 549 | if (bank->regs->irqenable_inv) |
99c47707 ID |
550 | l = ~l; |
551 | l &= mask; | |
552 | return l; | |
ea6dedd7 ID |
553 | } |
554 | ||
a0e827c6 | 555 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 556 | { |
92105bb7 | 557 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
558 | u32 l; |
559 | ||
28f3b5a0 KH |
560 | if (bank->regs->set_irqenable) { |
561 | reg += bank->regs->set_irqenable; | |
562 | l = gpio_mask; | |
2a900eb7 | 563 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
564 | } else { |
565 | reg += bank->regs->irqenable; | |
661553b9 | 566 | l = readl_relaxed(reg); |
28f3b5a0 KH |
567 | if (bank->regs->irqenable_inv) |
568 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
569 | else |
570 | l |= gpio_mask; | |
2a900eb7 | 571 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
572 | } |
573 | ||
661553b9 | 574 | writel_relaxed(l, reg); |
28f3b5a0 KH |
575 | } |
576 | ||
a0e827c6 | 577 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
578 | { |
579 | void __iomem *reg = bank->base; | |
580 | u32 l; | |
581 | ||
582 | if (bank->regs->clr_irqenable) { | |
583 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 584 | l = gpio_mask; |
2a900eb7 | 585 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
586 | } else { |
587 | reg += bank->regs->irqenable; | |
661553b9 | 588 | l = readl_relaxed(reg); |
28f3b5a0 | 589 | if (bank->regs->irqenable_inv) |
56739a69 | 590 | l |= gpio_mask; |
92105bb7 | 591 | else |
28f3b5a0 | 592 | l &= ~gpio_mask; |
2a900eb7 | 593 | bank->context.irqenable1 = l; |
5e1c5ff4 | 594 | } |
28f3b5a0 | 595 | |
661553b9 | 596 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
597 | } |
598 | ||
9943f261 GS |
599 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
600 | unsigned offset, int enable) | |
5e1c5ff4 | 601 | { |
8276536c | 602 | if (enable) |
9943f261 | 603 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 604 | else |
9943f261 | 605 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
606 | } |
607 | ||
92105bb7 TL |
608 | /* |
609 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
610 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
611 | * to the target, system will wake up always on GPIO events. While | |
612 | * system is running all registered GPIO interrupts need to have wake-up | |
613 | * enabled. When system is suspended, only selected GPIO interrupts need | |
614 | * to have wake-up enabled. | |
615 | */ | |
9943f261 GS |
616 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, |
617 | int enable) | |
92105bb7 | 618 | { |
9943f261 | 619 | u32 gpio_bit = BIT(offset); |
f64ad1a0 | 620 | unsigned long flags; |
a6472533 | 621 | |
f64ad1a0 | 622 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 623 | dev_err(bank->dev, |
9943f261 GS |
624 | "Unable to modify wakeup on non-wakeup GPIO%d\n", |
625 | offset); | |
92105bb7 TL |
626 | return -EINVAL; |
627 | } | |
f64ad1a0 KH |
628 | |
629 | spin_lock_irqsave(&bank->lock, flags); | |
630 | if (enable) | |
0aa27273 | 631 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 632 | else |
0aa27273 | 633 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 634 | |
661553b9 | 635 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
636 | spin_unlock_irqrestore(&bank->lock, flags); |
637 | ||
638 | return 0; | |
92105bb7 TL |
639 | } |
640 | ||
9943f261 | 641 | static void omap_reset_gpio(struct gpio_bank *bank, unsigned offset) |
4196dd6b | 642 | { |
9943f261 GS |
643 | omap_set_gpio_direction(bank, offset, 1); |
644 | omap_set_gpio_irqenable(bank, offset, 0); | |
645 | omap_clear_gpio_irqstatus(bank, offset); | |
646 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
647 | omap_clear_gpio_debounce(bank, offset); | |
4196dd6b TL |
648 | } |
649 | ||
92105bb7 | 650 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 651 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 652 | { |
a0e827c6 | 653 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 654 | unsigned offset = d->hwirq; |
92105bb7 | 655 | |
9943f261 | 656 | return omap_set_gpio_wakeup(bank, offset, enable); |
92105bb7 TL |
657 | } |
658 | ||
3ff164e1 | 659 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 660 | { |
3ff164e1 | 661 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 662 | unsigned long flags; |
52e31344 | 663 | |
55b93c32 TKD |
664 | /* |
665 | * If this is the first gpio_request for the bank, | |
666 | * enable the bank module. | |
667 | */ | |
fa365e4d | 668 | if (!BANK_USED(bank)) |
55b93c32 | 669 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 670 | |
55b93c32 | 671 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 672 | /* Set trigger to none. You need to enable the desired trigger with |
fac7fa16 JMC |
673 | * request_irq() or set_irq_type(). Only do this if the IRQ line has |
674 | * not already been requested. | |
4196dd6b | 675 | */ |
fac7fa16 | 676 | if (!LINE_USED(bank->irq_usage, offset)) { |
a0e827c6 JMC |
677 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
678 | omap_enable_gpio_module(bank, offset); | |
5e1c5ff4 | 679 | } |
b1e9fec2 | 680 | bank->mod_usage |= BIT(offset); |
a6472533 | 681 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
682 | |
683 | return 0; | |
684 | } | |
685 | ||
3ff164e1 | 686 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 687 | { |
3ff164e1 | 688 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 689 | unsigned long flags; |
5e1c5ff4 | 690 | |
a6472533 | 691 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 692 | bank->mod_usage &= ~(BIT(offset)); |
a0e827c6 | 693 | omap_disable_gpio_module(bank, offset); |
9943f261 | 694 | omap_reset_gpio(bank, offset); |
a6472533 | 695 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
696 | |
697 | /* | |
698 | * If this is the last gpio to be freed in the bank, | |
699 | * disable the bank module. | |
700 | */ | |
fa365e4d | 701 | if (!BANK_USED(bank)) |
55b93c32 | 702 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
703 | } |
704 | ||
705 | /* | |
706 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
707 | * avoid missing GPIO interrupts for other lines in the bank. | |
708 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
709 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
710 | * If we wait to unmask individual GPIO lines in the bank after the | |
711 | * line's interrupt handler has been run, we may miss some nested | |
712 | * interrupts. | |
713 | */ | |
a0e827c6 | 714 | static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 715 | { |
92105bb7 | 716 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 717 | u32 isr; |
3513cdec | 718 | unsigned int bit; |
5e1c5ff4 | 719 | struct gpio_bank *bank; |
ea6dedd7 | 720 | int unmasked = 0; |
fb655f57 JMC |
721 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
722 | struct gpio_chip *chip = irq_get_handler_data(irq); | |
5e1c5ff4 | 723 | |
fb655f57 | 724 | chained_irq_enter(irqchip, desc); |
5e1c5ff4 | 725 | |
fb655f57 | 726 | bank = container_of(chip, struct gpio_bank, chip); |
eef4bec7 | 727 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 728 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
729 | |
730 | if (WARN_ON(!isr_reg)) | |
731 | goto exit; | |
732 | ||
e83507b7 | 733 | while (1) { |
6e60e79a | 734 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 735 | u32 enabled; |
6e60e79a | 736 | |
a0e827c6 | 737 | enabled = omap_get_gpio_irqbank_mask(bank); |
661553b9 | 738 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 739 | |
9ea14d8c | 740 | if (bank->level_mask) |
b144ff6f | 741 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
742 | |
743 | /* clear edge sensitive interrupts before handler(s) are | |
744 | called so that we don't miss any interrupt occurred while | |
745 | executing them */ | |
a0e827c6 JMC |
746 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
747 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
748 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); | |
6e60e79a TL |
749 | |
750 | /* if there is only edge sensitive GPIO pin interrupts | |
751 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
752 | if (!level_mask && !unmasked) { |
753 | unmasked = 1; | |
fb655f57 | 754 | chained_irq_exit(irqchip, desc); |
ea6dedd7 | 755 | } |
92105bb7 TL |
756 | |
757 | if (!isr) | |
758 | break; | |
759 | ||
3513cdec JH |
760 | while (isr) { |
761 | bit = __ffs(isr); | |
b1e9fec2 | 762 | isr &= ~(BIT(bit)); |
25db711d | 763 | |
4318f36b CM |
764 | /* |
765 | * Some chips can't respond to both rising and falling | |
766 | * at the same time. If this irq was requested with | |
767 | * both flags, we need to flip the ICR data for the IRQ | |
768 | * to respond to the IRQ for the opposite direction. | |
769 | * This will be indicated in the bank toggle_mask. | |
770 | */ | |
b1e9fec2 | 771 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 772 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 773 | |
fb655f57 JMC |
774 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
775 | bit)); | |
92105bb7 | 776 | } |
1a8bfa1e | 777 | } |
ea6dedd7 ID |
778 | /* if bank has any level sensitive GPIO pin interrupt |
779 | configured, we must unmask the bank interrupt only after | |
780 | handler(s) are executed in order to avoid spurious bank | |
781 | interrupt */ | |
b1cc4c55 | 782 | exit: |
ea6dedd7 | 783 | if (!unmasked) |
fb655f57 | 784 | chained_irq_exit(irqchip, desc); |
55b93c32 | 785 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
786 | } |
787 | ||
3d009c8c TL |
788 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
789 | { | |
790 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 791 | unsigned long flags; |
37e14ecf | 792 | unsigned offset = d->hwirq; |
3d009c8c TL |
793 | |
794 | if (!BANK_USED(bank)) | |
795 | pm_runtime_get_sync(bank->dev); | |
796 | ||
797 | spin_lock_irqsave(&bank->lock, flags); | |
37e14ecf | 798 | omap_gpio_init_irq(bank, offset); |
3d009c8c TL |
799 | spin_unlock_irqrestore(&bank->lock, flags); |
800 | omap_gpio_unmask_irq(d); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
a0e827c6 | 805 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 806 | { |
a0e827c6 | 807 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 808 | unsigned long flags; |
9943f261 | 809 | unsigned offset = d->hwirq; |
4196dd6b | 810 | |
85ec7b97 | 811 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 812 | bank->irq_usage &= ~(BIT(offset)); |
a0e827c6 | 813 | omap_disable_gpio_module(bank, offset); |
9943f261 | 814 | omap_reset_gpio(bank, offset); |
85ec7b97 | 815 | spin_unlock_irqrestore(&bank->lock, flags); |
fac7fa16 JMC |
816 | |
817 | /* | |
818 | * If this is the last IRQ to be freed in the bank, | |
819 | * disable the bank module. | |
820 | */ | |
821 | if (!BANK_USED(bank)) | |
822 | pm_runtime_put(bank->dev); | |
4196dd6b TL |
823 | } |
824 | ||
a0e827c6 | 825 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 826 | { |
a0e827c6 | 827 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 828 | unsigned offset = d->hwirq; |
5e1c5ff4 | 829 | |
9943f261 | 830 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
831 | } |
832 | ||
a0e827c6 | 833 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 834 | { |
a0e827c6 | 835 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 836 | unsigned offset = d->hwirq; |
85ec7b97 | 837 | unsigned long flags; |
5e1c5ff4 | 838 | |
85ec7b97 | 839 | spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
840 | omap_set_gpio_irqenable(bank, offset, 0); |
841 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
85ec7b97 | 842 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
843 | } |
844 | ||
a0e827c6 | 845 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 846 | { |
a0e827c6 | 847 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 848 | unsigned offset = d->hwirq; |
8c04a176 | 849 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 850 | unsigned long flags; |
55b6019a | 851 | |
85ec7b97 | 852 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 853 | if (trigger) |
9943f261 | 854 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f KH |
855 | |
856 | /* For level-triggered GPIOs, the clearing must be done after | |
857 | * the HW source is cleared, thus after the handler has run */ | |
9943f261 GS |
858 | if (bank->level_mask & BIT(offset)) { |
859 | omap_set_gpio_irqenable(bank, offset, 0); | |
860 | omap_clear_gpio_irqstatus(bank, offset); | |
b144ff6f | 861 | } |
5e1c5ff4 | 862 | |
9943f261 | 863 | omap_set_gpio_irqenable(bank, offset, 1); |
85ec7b97 | 864 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
865 | } |
866 | ||
e5c56ed3 DB |
867 | /*---------------------------------------------------------------------*/ |
868 | ||
79ee031f | 869 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 870 | { |
79ee031f | 871 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 872 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
873 | void __iomem *mask_reg = bank->base + |
874 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 875 | unsigned long flags; |
11a78b79 | 876 | |
a6472533 | 877 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 878 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 879 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
880 | |
881 | return 0; | |
882 | } | |
883 | ||
79ee031f | 884 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 885 | { |
79ee031f | 886 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 887 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
888 | void __iomem *mask_reg = bank->base + |
889 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 890 | unsigned long flags; |
11a78b79 | 891 | |
a6472533 | 892 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 893 | writel_relaxed(bank->context.wake_en, mask_reg); |
a6472533 | 894 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
47145210 | 899 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
900 | .suspend_noirq = omap_mpuio_suspend_noirq, |
901 | .resume_noirq = omap_mpuio_resume_noirq, | |
902 | }; | |
903 | ||
3c437ffd | 904 | /* use platform_driver for this. */ |
11a78b79 | 905 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
906 | .driver = { |
907 | .name = "mpuio", | |
79ee031f | 908 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
909 | }, |
910 | }; | |
911 | ||
912 | static struct platform_device omap_mpuio_device = { | |
913 | .name = "mpuio", | |
914 | .id = -1, | |
915 | .dev = { | |
916 | .driver = &omap_mpuio_driver.driver, | |
917 | } | |
918 | /* could list the /proc/iomem resources */ | |
919 | }; | |
920 | ||
a0e827c6 | 921 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 922 | { |
77640aab | 923 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 924 | |
11a78b79 DB |
925 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
926 | (void) platform_device_register(&omap_mpuio_device); | |
927 | } | |
928 | ||
e5c56ed3 | 929 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 930 | |
a0e827c6 | 931 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
932 | { |
933 | struct gpio_bank *bank; | |
934 | unsigned long flags; | |
935 | void __iomem *reg; | |
936 | int dir; | |
937 | ||
938 | bank = container_of(chip, struct gpio_bank, chip); | |
939 | reg = bank->base + bank->regs->direction; | |
940 | spin_lock_irqsave(&bank->lock, flags); | |
941 | dir = !!(readl_relaxed(reg) & BIT(offset)); | |
942 | spin_unlock_irqrestore(&bank->lock, flags); | |
943 | return dir; | |
944 | } | |
945 | ||
a0e827c6 | 946 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
947 | { |
948 | struct gpio_bank *bank; | |
949 | unsigned long flags; | |
950 | ||
951 | bank = container_of(chip, struct gpio_bank, chip); | |
952 | spin_lock_irqsave(&bank->lock, flags); | |
a0e827c6 | 953 | omap_set_gpio_direction(bank, offset, 1); |
52e31344 DB |
954 | spin_unlock_irqrestore(&bank->lock, flags); |
955 | return 0; | |
956 | } | |
957 | ||
a0e827c6 | 958 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 959 | { |
b37c45b8 | 960 | struct gpio_bank *bank; |
b37c45b8 | 961 | |
a8be8daf | 962 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 963 | |
b2b20045 | 964 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 965 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 966 | else |
a0e827c6 | 967 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
968 | } |
969 | ||
a0e827c6 | 970 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
971 | { |
972 | struct gpio_bank *bank; | |
973 | unsigned long flags; | |
974 | ||
975 | bank = container_of(chip, struct gpio_bank, chip); | |
976 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 977 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 978 | omap_set_gpio_direction(bank, offset, 0); |
52e31344 | 979 | spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 980 | return 0; |
52e31344 DB |
981 | } |
982 | ||
a0e827c6 JMC |
983 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
984 | unsigned debounce) | |
168ef3d9 FB |
985 | { |
986 | struct gpio_bank *bank; | |
987 | unsigned long flags; | |
988 | ||
989 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 990 | |
168ef3d9 | 991 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 992 | omap2_set_gpio_debounce(bank, offset, debounce); |
168ef3d9 FB |
993 | spin_unlock_irqrestore(&bank->lock, flags); |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
a0e827c6 | 998 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
999 | { |
1000 | struct gpio_bank *bank; | |
1001 | unsigned long flags; | |
1002 | ||
1003 | bank = container_of(chip, struct gpio_bank, chip); | |
1004 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1005 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1006 | spin_unlock_irqrestore(&bank->lock, flags); |
1007 | } | |
1008 | ||
1009 | /*---------------------------------------------------------------------*/ | |
1010 | ||
9a748053 | 1011 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1012 | { |
e5ff4440 | 1013 | static bool called; |
9f7065da TL |
1014 | u32 rev; |
1015 | ||
e5ff4440 | 1016 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1017 | return; |
1018 | ||
661553b9 | 1019 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1020 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1021 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1022 | |
1023 | called = true; | |
9f7065da TL |
1024 | } |
1025 | ||
03e128ca | 1026 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1027 | { |
ab985f0f TKD |
1028 | void __iomem *base = bank->base; |
1029 | u32 l = 0xffffffff; | |
2fae7fbe | 1030 | |
ab985f0f TKD |
1031 | if (bank->width == 16) |
1032 | l = 0xffff; | |
1033 | ||
d0d665a8 | 1034 | if (bank->is_mpuio) { |
661553b9 | 1035 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1036 | return; |
2fae7fbe | 1037 | } |
ab985f0f | 1038 | |
a0e827c6 JMC |
1039 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1040 | bank->regs->irqenable_inv); | |
1041 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1042 | !bank->regs->irqenable_inv); | |
ab985f0f | 1043 | if (bank->regs->debounce_en) |
661553b9 | 1044 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1045 | |
2dc983c5 | 1046 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1047 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1048 | /* Initialize interface clk ungated, module enabled */ |
1049 | if (bank->regs->ctrl) | |
661553b9 | 1050 | writel_relaxed(0, base + bank->regs->ctrl); |
34672013 TKD |
1051 | |
1052 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1053 | if (IS_ERR(bank->dbck)) | |
1054 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1055 | } |
1056 | ||
3836309d | 1057 | static void |
f8b46b58 KH |
1058 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1059 | unsigned int num) | |
1060 | { | |
1061 | struct irq_chip_generic *gc; | |
1062 | struct irq_chip_type *ct; | |
1063 | ||
1064 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1065 | handle_simple_irq); | |
83233749 TP |
1066 | if (!gc) { |
1067 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1068 | return; | |
1069 | } | |
1070 | ||
f8b46b58 KH |
1071 | ct = gc->chip_types; |
1072 | ||
1073 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1074 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1075 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
a0e827c6 | 1076 | ct->chip.irq_set_type = omap_gpio_irq_type; |
6ed87c5b TKD |
1077 | |
1078 | if (bank->regs->wkup_en) | |
a0e827c6 | 1079 | ct->chip.irq_set_wake = omap_gpio_wake_enable; |
f8b46b58 KH |
1080 | |
1081 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1082 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1083 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1084 | } | |
1085 | ||
46824e22 | 1086 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1087 | { |
77640aab | 1088 | int j; |
2fae7fbe | 1089 | static int gpio; |
fb655f57 | 1090 | int irq_base = 0; |
6ef7f385 | 1091 | int ret; |
2fae7fbe | 1092 | |
2fae7fbe VC |
1093 | /* |
1094 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1095 | * over to the generic ones | |
1096 | */ | |
1097 | bank->chip.request = omap_gpio_request; | |
1098 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1099 | bank->chip.get_direction = omap_gpio_get_direction; |
1100 | bank->chip.direction_input = omap_gpio_input; | |
1101 | bank->chip.get = omap_gpio_get; | |
1102 | bank->chip.direction_output = omap_gpio_output; | |
1103 | bank->chip.set_debounce = omap_gpio_debounce; | |
1104 | bank->chip.set = omap_gpio_set; | |
d0d665a8 | 1105 | if (bank->is_mpuio) { |
2fae7fbe | 1106 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1107 | if (bank->regs->wkup_en) |
1108 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1109 | bank->chip.base = OMAP_MPUIO(0); |
1110 | } else { | |
1111 | bank->chip.label = "gpio"; | |
1112 | bank->chip.base = gpio; | |
d5f46247 | 1113 | gpio += bank->width; |
2fae7fbe | 1114 | } |
d5f46247 | 1115 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1116 | |
6ef7f385 JMC |
1117 | ret = gpiochip_add(&bank->chip); |
1118 | if (ret) { | |
fb655f57 | 1119 | dev_err(bank->dev, "Could not register gpio chip %d\n", ret); |
6ef7f385 JMC |
1120 | return ret; |
1121 | } | |
2fae7fbe | 1122 | |
fb655f57 JMC |
1123 | #ifdef CONFIG_ARCH_OMAP1 |
1124 | /* | |
1125 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1126 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1127 | */ | |
1128 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1129 | if (irq_base < 0) { | |
1130 | dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); | |
1131 | return -ENODEV; | |
1132 | } | |
1133 | #endif | |
1134 | ||
46824e22 | 1135 | ret = gpiochip_irqchip_add(&bank->chip, irqc, |
a0e827c6 | 1136 | irq_base, omap_gpio_irq_handler, |
fb655f57 JMC |
1137 | IRQ_TYPE_NONE); |
1138 | ||
1139 | if (ret) { | |
1140 | dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); | |
da26d5d8 | 1141 | gpiochip_remove(&bank->chip); |
fb655f57 JMC |
1142 | return -ENODEV; |
1143 | } | |
1144 | ||
46824e22 | 1145 | gpiochip_set_chained_irqchip(&bank->chip, irqc, |
a0e827c6 | 1146 | bank->irq, omap_gpio_irq_handler); |
fb655f57 | 1147 | |
ede4d7a5 | 1148 | for (j = 0; j < bank->width; j++) { |
fb655f57 | 1149 | int irq = irq_find_mapping(bank->chip.irqdomain, j); |
d0d665a8 | 1150 | if (bank->is_mpuio) { |
ede4d7a5 | 1151 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
fb655f57 JMC |
1152 | irq_set_chip_and_handler(irq, NULL, NULL); |
1153 | set_irq_flags(irq, 0); | |
f8b46b58 | 1154 | } |
2fae7fbe | 1155 | } |
fb655f57 JMC |
1156 | |
1157 | return 0; | |
2fae7fbe VC |
1158 | } |
1159 | ||
384ebe1c BC |
1160 | static const struct of_device_id omap_gpio_match[]; |
1161 | ||
3836309d | 1162 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1163 | { |
862ff640 | 1164 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1165 | struct device_node *node = dev->of_node; |
1166 | const struct of_device_id *match; | |
f6817a2c | 1167 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1168 | struct resource *res; |
5e1c5ff4 | 1169 | struct gpio_bank *bank; |
46824e22 | 1170 | struct irq_chip *irqc; |
6ef7f385 | 1171 | int ret; |
5e1c5ff4 | 1172 | |
384ebe1c BC |
1173 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1174 | ||
e56aee18 | 1175 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1176 | if (!pdata) |
96751fcb | 1177 | return -EINVAL; |
5492fb1a | 1178 | |
086d585f | 1179 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1180 | if (!bank) { |
862ff640 | 1181 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1182 | return -ENOMEM; |
03e128ca | 1183 | } |
92105bb7 | 1184 | |
46824e22 NM |
1185 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1186 | if (!irqc) | |
1187 | return -ENOMEM; | |
1188 | ||
3d009c8c | 1189 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1190 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1191 | irqc->irq_ack = omap_gpio_ack_irq, | |
1192 | irqc->irq_mask = omap_gpio_mask_irq, | |
1193 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1194 | irqc->irq_set_type = omap_gpio_irq_type, | |
1195 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1196 | irqc->name = dev_name(&pdev->dev); | |
1197 | ||
77640aab VC |
1198 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1199 | if (unlikely(!res)) { | |
862ff640 | 1200 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1201 | return -ENODEV; |
44169075 | 1202 | } |
5e1c5ff4 | 1203 | |
77640aab | 1204 | bank->irq = res->start; |
862ff640 | 1205 | bank->dev = dev; |
fb655f57 | 1206 | bank->chip.dev = dev; |
77640aab | 1207 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1208 | bank->stride = pdata->bank_stride; |
d5f46247 | 1209 | bank->width = pdata->bank_width; |
d0d665a8 | 1210 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1211 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1212 | bank->regs = pdata->regs; |
384ebe1c BC |
1213 | #ifdef CONFIG_OF_GPIO |
1214 | bank->chip.of_node = of_node_get(node); | |
1215 | #endif | |
a2797bea JH |
1216 | if (node) { |
1217 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1218 | bank->loses_context = true; | |
1219 | } else { | |
1220 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1221 | |
1222 | if (bank->loses_context) | |
1223 | bank->get_context_loss_count = | |
1224 | pdata->get_context_loss_count; | |
384ebe1c BC |
1225 | } |
1226 | ||
fa87931a | 1227 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1228 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1229 | else |
a0e827c6 | 1230 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1231 | |
77640aab | 1232 | spin_lock_init(&bank->lock); |
9f7065da | 1233 | |
77640aab VC |
1234 | /* Static mapping, never released */ |
1235 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1236 | bank->base = devm_ioremap_resource(dev, res); |
1237 | if (IS_ERR(bank->base)) { | |
fb655f57 | 1238 | irq_domain_remove(bank->chip.irqdomain); |
717f70e3 | 1239 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1240 | } |
1241 | ||
065cd795 TKD |
1242 | platform_set_drvdata(pdev, bank); |
1243 | ||
77640aab | 1244 | pm_runtime_enable(bank->dev); |
55b93c32 | 1245 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1246 | pm_runtime_get_sync(bank->dev); |
1247 | ||
d0d665a8 | 1248 | if (bank->is_mpuio) |
a0e827c6 | 1249 | omap_mpuio_init(bank); |
ab985f0f | 1250 | |
03e128ca | 1251 | omap_gpio_mod_init(bank); |
6ef7f385 | 1252 | |
46824e22 | 1253 | ret = omap_gpio_chip_init(bank, irqc); |
6ef7f385 JMC |
1254 | if (ret) |
1255 | return ret; | |
1256 | ||
9a748053 | 1257 | omap_gpio_show_rev(bank); |
9f7065da | 1258 | |
55b93c32 TKD |
1259 | pm_runtime_put(bank->dev); |
1260 | ||
03e128ca | 1261 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1262 | |
879fe324 | 1263 | return 0; |
5e1c5ff4 TL |
1264 | } |
1265 | ||
55b93c32 TKD |
1266 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1267 | ||
ecb2312f | 1268 | #if defined(CONFIG_PM) |
60a3437d | 1269 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1270 | |
2dc983c5 | 1271 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1272 | { |
2dc983c5 TKD |
1273 | struct platform_device *pdev = to_platform_device(dev); |
1274 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1275 | u32 l1 = 0, l2 = 0; | |
1276 | unsigned long flags; | |
68942edb | 1277 | u32 wake_low, wake_hi; |
8865b9b6 | 1278 | |
2dc983c5 | 1279 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1280 | |
1281 | /* | |
1282 | * Only edges can generate a wakeup event to the PRCM. | |
1283 | * | |
1284 | * Therefore, ensure any wake-up capable GPIOs have | |
1285 | * edge-detection enabled before going idle to ensure a wakeup | |
1286 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1287 | * NDA TRM 25.5.3.1) | |
1288 | * | |
1289 | * The normal values will be restored upon ->runtime_resume() | |
1290 | * by writing back the values saved in bank->context. | |
1291 | */ | |
1292 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1293 | if (wake_low) | |
661553b9 | 1294 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1295 | bank->base + bank->regs->fallingdetect); |
1296 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1297 | if (wake_hi) | |
661553b9 | 1298 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1299 | bank->base + bank->regs->risingdetect); |
1300 | ||
b3c64bc3 KH |
1301 | if (!bank->enabled_non_wakeup_gpios) |
1302 | goto update_gpio_context_count; | |
1303 | ||
2dc983c5 TKD |
1304 | if (bank->power_mode != OFF_MODE) { |
1305 | bank->power_mode = 0; | |
41d87cbd | 1306 | goto update_gpio_context_count; |
2dc983c5 TKD |
1307 | } |
1308 | /* | |
1309 | * If going to OFF, remove triggering for all | |
1310 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1311 | * generated. See OMAP2420 Errata item 1.101. | |
1312 | */ | |
661553b9 | 1313 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1314 | bank->regs->datain); |
c6f31c9e TKD |
1315 | l1 = bank->context.fallingdetect; |
1316 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1317 | |
2dc983c5 TKD |
1318 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1319 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1320 | |
661553b9 VK |
1321 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1322 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1323 | |
2dc983c5 | 1324 | bank->workaround_enabled = true; |
3f1686a9 | 1325 | |
41d87cbd | 1326 | update_gpio_context_count: |
2dc983c5 TKD |
1327 | if (bank->get_context_loss_count) |
1328 | bank->context_loss_count = | |
60a3437d TKD |
1329 | bank->get_context_loss_count(bank->dev); |
1330 | ||
a0e827c6 | 1331 | omap_gpio_dbck_disable(bank); |
2dc983c5 | 1332 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1333 | |
2dc983c5 | 1334 | return 0; |
3ac4fa99 JY |
1335 | } |
1336 | ||
352a2d5b JH |
1337 | static void omap_gpio_init_context(struct gpio_bank *p); |
1338 | ||
2dc983c5 | 1339 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1340 | { |
2dc983c5 TKD |
1341 | struct platform_device *pdev = to_platform_device(dev); |
1342 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1343 | u32 l = 0, gen, gen0, gen1; |
1344 | unsigned long flags; | |
a2797bea | 1345 | int c; |
8865b9b6 | 1346 | |
2dc983c5 | 1347 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1348 | |
1349 | /* | |
1350 | * On the first resume during the probe, the context has not | |
1351 | * been initialised and so initialise it now. Also initialise | |
1352 | * the context loss count. | |
1353 | */ | |
1354 | if (bank->loses_context && !bank->context_valid) { | |
1355 | omap_gpio_init_context(bank); | |
1356 | ||
1357 | if (bank->get_context_loss_count) | |
1358 | bank->context_loss_count = | |
1359 | bank->get_context_loss_count(bank->dev); | |
1360 | } | |
1361 | ||
a0e827c6 | 1362 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1363 | |
1364 | /* | |
1365 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1366 | * GPIOs were set to edge trigger also in order to be able to | |
1367 | * generate a PRCM wakeup. Here we restore the | |
1368 | * pre-runtime_suspend() values for edge triggering. | |
1369 | */ | |
661553b9 | 1370 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1371 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1372 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1373 | bank->base + bank->regs->risingdetect); |
1374 | ||
a2797bea JH |
1375 | if (bank->loses_context) { |
1376 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1377 | omap_gpio_restore_context(bank); |
1378 | } else { | |
a2797bea JH |
1379 | c = bank->get_context_loss_count(bank->dev); |
1380 | if (c != bank->context_loss_count) { | |
1381 | omap_gpio_restore_context(bank); | |
1382 | } else { | |
1383 | spin_unlock_irqrestore(&bank->lock, flags); | |
1384 | return 0; | |
1385 | } | |
60a3437d | 1386 | } |
2dc983c5 | 1387 | } |
43ffcd9a | 1388 | |
1b128703 TKD |
1389 | if (!bank->workaround_enabled) { |
1390 | spin_unlock_irqrestore(&bank->lock, flags); | |
1391 | return 0; | |
1392 | } | |
1393 | ||
661553b9 | 1394 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1395 | |
2dc983c5 TKD |
1396 | /* |
1397 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1398 | * state. If so, generate an IRQ by software. This is | |
1399 | * horribly racy, but it's the best we can do to work around | |
1400 | * this silicon bug. | |
1401 | */ | |
1402 | l ^= bank->saved_datain; | |
1403 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1404 | |
2dc983c5 TKD |
1405 | /* |
1406 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1407 | * configured with falling edge only; and vice versa. | |
1408 | */ | |
c6f31c9e | 1409 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1410 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1411 | |
c6f31c9e | 1412 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1413 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1414 | |
2dc983c5 | 1415 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1416 | gen = l & (~(bank->context.fallingdetect) & |
1417 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1418 | /* Consider all GPIO IRQs needed to be updated */ |
1419 | gen |= gen0 | gen1; | |
82dbb9d3 | 1420 | |
2dc983c5 TKD |
1421 | if (gen) { |
1422 | u32 old0, old1; | |
82dbb9d3 | 1423 | |
661553b9 VK |
1424 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1425 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1426 | |
4e962e89 | 1427 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1428 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1429 | bank->regs->leveldetect0); |
661553b9 | 1430 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1431 | bank->regs->leveldetect1); |
2dc983c5 | 1432 | } |
9ea14d8c | 1433 | |
4e962e89 | 1434 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1435 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1436 | bank->regs->leveldetect0); |
661553b9 | 1437 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1438 | bank->regs->leveldetect1); |
3ac4fa99 | 1439 | } |
661553b9 VK |
1440 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1441 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1442 | } |
1443 | ||
1444 | bank->workaround_enabled = false; | |
1445 | spin_unlock_irqrestore(&bank->lock, flags); | |
1446 | ||
1447 | return 0; | |
1448 | } | |
ecb2312f | 1449 | #endif /* CONFIG_PM */ |
2dc983c5 TKD |
1450 | |
1451 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1452 | { | |
1453 | struct gpio_bank *bank; | |
1454 | ||
1455 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1456 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1457 | continue; |
1458 | ||
1459 | bank->power_mode = pwr_mode; | |
1460 | ||
2dc983c5 TKD |
1461 | pm_runtime_put_sync_suspend(bank->dev); |
1462 | } | |
1463 | } | |
1464 | ||
1465 | void omap2_gpio_resume_after_idle(void) | |
1466 | { | |
1467 | struct gpio_bank *bank; | |
1468 | ||
1469 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1470 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1471 | continue; |
1472 | ||
2dc983c5 | 1473 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1474 | } |
3ac4fa99 JY |
1475 | } |
1476 | ||
ecb2312f | 1477 | #if defined(CONFIG_PM) |
352a2d5b JH |
1478 | static void omap_gpio_init_context(struct gpio_bank *p) |
1479 | { | |
1480 | struct omap_gpio_reg_offs *regs = p->regs; | |
1481 | void __iomem *base = p->base; | |
1482 | ||
661553b9 VK |
1483 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1484 | p->context.oe = readl_relaxed(base + regs->direction); | |
1485 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1486 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1487 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1488 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1489 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1490 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1491 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1492 | |
1493 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1494 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1495 | else |
661553b9 | 1496 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1497 | |
1498 | p->context_valid = true; | |
1499 | } | |
1500 | ||
60a3437d | 1501 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1502 | { |
661553b9 | 1503 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1504 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1505 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1506 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1507 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1508 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1509 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1510 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1511 | bank->base + bank->regs->risingdetect); |
661553b9 | 1512 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1513 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1514 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1515 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1516 | bank->base + bank->regs->set_dataout); |
1517 | else | |
661553b9 | 1518 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1519 | bank->base + bank->regs->dataout); |
661553b9 | 1520 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1521 | |
ae547354 | 1522 | if (bank->dbck_enable_mask) { |
661553b9 | 1523 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1524 | bank->regs->debounce); |
661553b9 | 1525 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1526 | bank->base + bank->regs->debounce_en); |
1527 | } | |
ba805be5 | 1528 | |
661553b9 | 1529 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1530 | bank->base + bank->regs->irqenable); |
661553b9 | 1531 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1532 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1533 | } |
ecb2312f | 1534 | #endif /* CONFIG_PM */ |
55b93c32 | 1535 | #else |
2dc983c5 TKD |
1536 | #define omap_gpio_runtime_suspend NULL |
1537 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1538 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1539 | #endif |
1540 | ||
55b93c32 | 1541 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1542 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1543 | NULL) | |
55b93c32 TKD |
1544 | }; |
1545 | ||
384ebe1c BC |
1546 | #if defined(CONFIG_OF) |
1547 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1548 | .revision = OMAP24XX_GPIO_REVISION, | |
1549 | .direction = OMAP24XX_GPIO_OE, | |
1550 | .datain = OMAP24XX_GPIO_DATAIN, | |
1551 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1552 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1553 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1554 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1555 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1556 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1557 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1558 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1559 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1560 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1561 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1562 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1563 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1564 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1565 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1566 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1567 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1568 | }; | |
1569 | ||
1570 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1571 | .revision = OMAP4_GPIO_REVISION, | |
1572 | .direction = OMAP4_GPIO_OE, | |
1573 | .datain = OMAP4_GPIO_DATAIN, | |
1574 | .dataout = OMAP4_GPIO_DATAOUT, | |
1575 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1576 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1577 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1578 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1579 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1580 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1581 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1582 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1583 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1584 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1585 | .ctrl = OMAP4_GPIO_CTRL, | |
1586 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1587 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1588 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1589 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1590 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1591 | }; | |
1592 | ||
e9a65bb6 | 1593 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1594 | .regs = &omap2_gpio_regs, |
1595 | .bank_width = 32, | |
1596 | .dbck_flag = false, | |
1597 | }; | |
1598 | ||
e9a65bb6 | 1599 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1600 | .regs = &omap2_gpio_regs, |
1601 | .bank_width = 32, | |
1602 | .dbck_flag = true, | |
1603 | }; | |
1604 | ||
e9a65bb6 | 1605 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1606 | .regs = &omap4_gpio_regs, |
1607 | .bank_width = 32, | |
1608 | .dbck_flag = true, | |
1609 | }; | |
1610 | ||
1611 | static const struct of_device_id omap_gpio_match[] = { | |
1612 | { | |
1613 | .compatible = "ti,omap4-gpio", | |
1614 | .data = &omap4_pdata, | |
1615 | }, | |
1616 | { | |
1617 | .compatible = "ti,omap3-gpio", | |
1618 | .data = &omap3_pdata, | |
1619 | }, | |
1620 | { | |
1621 | .compatible = "ti,omap2-gpio", | |
1622 | .data = &omap2_pdata, | |
1623 | }, | |
1624 | { }, | |
1625 | }; | |
1626 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1627 | #endif | |
1628 | ||
77640aab VC |
1629 | static struct platform_driver omap_gpio_driver = { |
1630 | .probe = omap_gpio_probe, | |
1631 | .driver = { | |
1632 | .name = "omap_gpio", | |
55b93c32 | 1633 | .pm = &gpio_pm_ops, |
384ebe1c | 1634 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1635 | }, |
1636 | }; | |
1637 | ||
5e1c5ff4 | 1638 | /* |
77640aab VC |
1639 | * gpio driver register needs to be done before |
1640 | * machine_init functions access gpio APIs. | |
1641 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1642 | */ |
77640aab | 1643 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1644 | { |
77640aab | 1645 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1646 | } |
77640aab | 1647 | postcore_initcall(omap_gpio_drv_reg); |