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gpio/omap: remove suspend_wakeup field from struct gpio_bank
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
96751fcb 22#include <linux/device.h>
77640aab 23#include <linux/pm_runtime.h>
55b93c32 24#include <linux/pm.h>
384ebe1c
BC		 25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
5e1c5ff4 28
a09e64fb 29#include <mach/hardware.h>
5e1c5ff4 30#include <asm/irq.h>
a09e64fb 31#include <mach/irqs.h>
1bc857f7 32#include <asm/gpio.h>
5e1c5ff4
TL		 33#include <asm/mach/irq.h>
34
2dc983c5
TKD		 35#define OFF_MODE 1
36
03e128ca
C		 37static LIST_HEAD(omap_gpio_list);
38
6d62e216
C		 39struct gpio_regs {
40 u32 irqenable1;
41 u32 irqenable2;
42 u32 wake_en;
43 u32 ctrl;
44 u32 oe;
45 u32 leveldetect0;
46 u32 leveldetect1;
47 u32 risingdetect;
48 u32 fallingdetect;
49 u32 dataout;
ae547354
NM		 50 u32 debounce;
51 u32 debounce_en;
6d62e216
C		 52};
53
5e1c5ff4 54struct gpio_bank {
03e128ca 55 struct list_head node;
92105bb7 56 void __iomem *base;
5e1c5ff4 57 u16 irq;
384ebe1c
BC		 58 int irq_base;
59 struct irq_domain *domain;
92105bb7 60 u32 saved_wakeup;
3ac4fa99
JY		 61 u32 non_wakeup_gpios;
62 u32 enabled_non_wakeup_gpios;
6d62e216 63 struct gpio_regs context;
3ac4fa99 64 u32 saved_datain;
b144ff6f 65 u32 level_mask;
4318f36b 66 u32 toggle_mask;
5e1c5ff4 67 spinlock_t lock;
52e31344 68 struct gpio_chip chip;
89db9482 69 struct clk *dbck;
058af1ea 70 u32 mod_usage;
8865b9b6 71 u32 dbck_enable_mask;
72f83af9 72 bool dbck_enabled;
77640aab 73 struct device *dev;
d0d665a8 74 bool is_mpuio;
77640aab 75 bool dbck_flag;
0cde8d03 76 bool loses_context;
5de62b86 77 int stride;
d5f46247 78 u32 width;
60a3437d 79 int context_loss_count;
2dc983c5
TKD		 80 int power_mode;
81 bool workaround_enabled;
fa87931a
KH		 82
83 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60a3437d 84 int (*get_context_loss_count)(struct device *dev);
fa87931a
KH		 85
86 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 87};
88
129fd223
KH		 89#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
90#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
c8eef65a 91#define GPIO_MOD_CTRL_BIT BIT(0)
5e1c5ff4 92
25db711d
BC		 93static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
94{
95 return gpio_irq - bank->irq_base + bank->chip.base;
96}
97
5e1c5ff4
TL		 98static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
99{
92105bb7 100 void __iomem *reg = bank->base;
5e1c5ff4
TL		 101 u32 l;
102
fa87931a 103 reg += bank->regs->direction;
5e1c5ff4
TL		 104 l = __raw_readl(reg);
105 if (is_input)
106 l |= 1 << gpio;
107 else
108 l &= ~(1 << gpio);
109 __raw_writel(l, reg);
41d87cbd 110 bank->context.oe = l;
5e1c5ff4
TL		 111}
112
fa87931a
KH		 113
114/* set data out value using dedicate set/clear register */
115static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 116{
92105bb7 117 void __iomem *reg = bank->base;
fa87931a 118 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 119
2c836f7e 120 if (enable) {
fa87931a 121 reg += bank->regs->set_dataout;
2c836f7e
TKD		 122 bank->context.dataout |= l;
123 } else {
fa87931a 124 reg += bank->regs->clr_dataout;
2c836f7e
TKD		 125 bank->context.dataout &= ~l;
126 }
5e1c5ff4 127
5e1c5ff4
TL		 128 __raw_writel(l, reg);
129}
130
fa87931a
KH		 131/* set data out value using mask register */
132static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 133{
fa87931a
KH		 134 void __iomem *reg = bank->base + bank->regs->dataout;
135 u32 gpio_bit = GPIO_BIT(bank, gpio);
136 u32 l;
5e1c5ff4 137
fa87931a
KH		 138 l = __raw_readl(reg);
139 if (enable)
140 l |= gpio_bit;
141 else
142 l &= ~gpio_bit;
5e1c5ff4 143 __raw_writel(l, reg);
41d87cbd 144 bank->context.dataout = l;
5e1c5ff4
TL		 145}
146
7fcca715 147static int _get_gpio_datain(struct gpio_bank *bank, int offset)
b37c45b8 148{
fa87931a 149 void __iomem *reg = bank->base + bank->regs->datain;
b37c45b8 150
7fcca715 151 return (__raw_readl(reg) & (1 << offset)) != 0;
5e1c5ff4 152}
b37c45b8 153
7fcca715 154static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
b37c45b8 155{
fa87931a 156 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8 157
7fcca715 158 return (__raw_readl(reg) & (1 << offset)) != 0;
b37c45b8
RQ		 159}
160
ece9528e
KH		 161static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
162{
163 int l = __raw_readl(base + reg);
164
862ff640 165 if (set)
ece9528e
KH		 166 l |= mask;
167 else
168 l &= ~mask;
169
170 __raw_writel(l, base + reg);
171}
92105bb7 172
72f83af9
TKD		 173static inline void _gpio_dbck_enable(struct gpio_bank *bank)
174{
175 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
176 clk_enable(bank->dbck);
177 bank->dbck_enabled = true;
178 }
179}
180
181static inline void _gpio_dbck_disable(struct gpio_bank *bank)
182{
183 if (bank->dbck_enable_mask && bank->dbck_enabled) {
184 clk_disable(bank->dbck);
185 bank->dbck_enabled = false;
186 }
187}
188
168ef3d9
FB		 189/**
190 * _set_gpio_debounce - low level gpio debounce time
191 * @bank: the gpio bank we're acting upon
192 * @gpio: the gpio number on this @gpio
193 * @debounce: debounce time to use
194 *
195 * OMAP's debounce time is in 31us steps so we need
196 * to convert and round up to the closest unit.
197 */
198static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
199 unsigned debounce)
200{
9942da0e 201 void __iomem *reg;
168ef3d9
FB		 202 u32 val;
203 u32 l;
204
77640aab
VC		 205 if (!bank->dbck_flag)
206 return;
207
168ef3d9
FB		 208 if (debounce < 32)
209 debounce = 0x01;
210 else if (debounce > 7936)
211 debounce = 0xff;
212 else
213 debounce = (debounce / 0x1f) - 1;
214
129fd223 215 l = GPIO_BIT(bank, gpio);
168ef3d9 216
6fd9c421 217 clk_enable(bank->dbck);
9942da0e 218 reg = bank->base + bank->regs->debounce;
168ef3d9
FB		 219 __raw_writel(debounce, reg);
220
9942da0e 221 reg = bank->base + bank->regs->debounce_en;
168ef3d9
FB		 222 val = __raw_readl(reg);
223
6fd9c421 224 if (debounce)
168ef3d9 225 val |= l;
6fd9c421 226 else
168ef3d9 227 val &= ~l;
f7ec0b0b 228 bank->dbck_enable_mask = val;
168ef3d9
FB		 229
230 __raw_writel(val, reg);
6fd9c421
TKD		 231 clk_disable(bank->dbck);
232 /*
233 * Enable debounce clock per module.
234 * This call is mandatory because in omap_gpio_request() when
235 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
236 * runtime callbck fails to turn on dbck because dbck_enable_mask
237 * used within _gpio_dbck_enable() is still not initialized at
238 * that point. Therefore we have to enable dbck here.
239 */
240 _gpio_dbck_enable(bank);
ae547354
NM		 241 if (bank->dbck_enable_mask) {
242 bank->context.debounce = debounce;
243 bank->context.debounce_en = val;
244 }
168ef3d9
FB		 245}
246
5e571f38 247static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
00ece7e4 248 unsigned trigger)
5e1c5ff4 249{
3ac4fa99 250 void __iomem *base = bank->base;
92105bb7
TL		 251 u32 gpio_bit = 1 << gpio;
252
5e571f38
TKD		 253 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
254 trigger & IRQ_TYPE_LEVEL_LOW);
255 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
256 trigger & IRQ_TYPE_LEVEL_HIGH);
257 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
258 trigger & IRQ_TYPE_EDGE_RISING);
259 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
260 trigger & IRQ_TYPE_EDGE_FALLING);
261
41d87cbd
TKD		 262 bank->context.leveldetect0 =
263 __raw_readl(bank->base + bank->regs->leveldetect0);
264 bank->context.leveldetect1 =
265 __raw_readl(bank->base + bank->regs->leveldetect1);
266 bank->context.risingdetect =
267 __raw_readl(bank->base + bank->regs->risingdetect);
268 bank->context.fallingdetect =
269 __raw_readl(bank->base + bank->regs->fallingdetect);
270
271 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
5e571f38 272 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
41d87cbd
TKD		 273 bank->context.wake_en =
274 __raw_readl(bank->base + bank->regs->wkup_en);
275 }
5e571f38 276
55b220ca 277 /* This part needs to be executed always for OMAP{34xx, 44xx} */
5e571f38
TKD		 278 if (!bank->regs->irqctrl) {
279 /* On omap24xx proceed only when valid GPIO bit is set */
280 if (bank->non_wakeup_gpios) {
281 if (!(bank->non_wakeup_gpios & gpio_bit))
282 goto exit;
283 }
284
699117a6
CW		 285 /*
286 * Log the edge gpio and manually trigger the IRQ
287 * after resume if the input level changes
288 * to avoid irq lost during PER RET/OFF mode
289 * Applies for omap2 non-wakeup gpio and all omap3 gpios
290 */
291 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 292 bank->enabled_non_wakeup_gpios |= gpio_bit;
293 else
294 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
295 }
5eb3bb9c 296
5e571f38 297exit:
9ea14d8c
TKD		 298 bank->level_mask =
299 __raw_readl(bank->base + bank->regs->leveldetect0) |
300 __raw_readl(bank->base + bank->regs->leveldetect1);
92105bb7
TL		 301}
302
9198bcd3 303#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 304/*
305 * This only applies to chips that can't do both rising and falling edge
306 * detection at once. For all other chips, this function is a noop.
307 */
308static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
309{
310 void __iomem *reg = bank->base;
311 u32 l = 0;
312
5e571f38 313 if (!bank->regs->irqctrl)
4318f36b 314 return;
5e571f38
TKD		 315
316 reg += bank->regs->irqctrl;
4318f36b
CM		 317
318 l = __raw_readl(reg);
319 if ((l >> gpio) & 1)
320 l &= ~(1 << gpio);
321 else
322 l |= 1 << gpio;
323
324 __raw_writel(l, reg);
325}
5e571f38
TKD		 326#else
327static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
9198bcd3 328#endif
4318f36b 329
00ece7e4
TKD		 330static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
331 unsigned trigger)
92105bb7
TL		 332{
333 void __iomem *reg = bank->base;
5e571f38 334 void __iomem *base = bank->base;
92105bb7 335 u32 l = 0;
5e1c5ff4 336
5e571f38
TKD		 337 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
338 set_gpio_trigger(bank, gpio, trigger);
339 } else if (bank->regs->irqctrl) {
340 reg += bank->regs->irqctrl;
341
5e1c5ff4 342 l = __raw_readl(reg);
29501577 343 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 344 bank->toggle_mask |= 1 << gpio;
6cab4860 345 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 346 l |= 1 << gpio;
6cab4860 347 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 348 l &= ~(1 << gpio);
92105bb7 349 else
5e571f38
TKD		 350 return -EINVAL;
351
352 __raw_writel(l, reg);
353 } else if (bank->regs->edgectrl1) {
5e1c5ff4 354 if (gpio & 0x08)
5e571f38 355 reg += bank->regs->edgectrl2;
5e1c5ff4 356 else
5e571f38
TKD		 357 reg += bank->regs->edgectrl1;
358
5e1c5ff4
TL		 359 gpio &= 0x07;
360 l = __raw_readl(reg);
361 l &= ~(3 << (gpio << 1));
6cab4860 362 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 363 l |= 2 << (gpio << 1);
6cab4860 364 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 365 l |= 1 << (gpio << 1);
5e571f38
TKD		 366
367 /* Enable wake-up during idle for dynamic tick */
368 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
41d87cbd
TKD		 369 bank->context.wake_en =
370 __raw_readl(bank->base + bank->regs->wkup_en);
5e571f38 371 __raw_writel(l, reg);
5e1c5ff4 372 }
92105bb7 373 return 0;
5e1c5ff4
TL		 374}
375
e9191028 376static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4 377{
25db711d 378 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
92105bb7
TL		 379 unsigned gpio;
380 int retval;
a6472533 381 unsigned long flags;
92105bb7 382
e9191028
LB		 383 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
384 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 385 else
25db711d 386 gpio = irq_to_gpio(bank, d->irq);
5e1c5ff4 387
e5c56ed3 388 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 389 return -EINVAL;
e5c56ed3 390
9ea14d8c
TKD		 391 if (!bank->regs->leveldetect0 &&
392 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 393 return -EINVAL;
394
a6472533 395 spin_lock_irqsave(&bank->lock, flags);
129fd223 396 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 397 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 398
399 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 400 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 401 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 402 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 403
92105bb7 404 return retval;
5e1c5ff4
TL		 405}
406
407static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
408{
92105bb7 409 void __iomem *reg = bank->base;
5e1c5ff4 410
eef4bec7 411 reg += bank->regs->irqstatus;
5e1c5ff4 412 __raw_writel(gpio_mask, reg);
bee7930f
HD		 413
414 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 415 if (bank->regs->irqstatus2) {
416 reg = bank->base + bank->regs->irqstatus2;
bedfd154 417 __raw_writel(gpio_mask, reg);
eef4bec7 418 }
bedfd154
RQ		 419
420 /* Flush posted write for the irq status to avoid spurious interrupts */
421 __raw_readl(reg);
5e1c5ff4
TL		 422}
423
424static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
425{
129fd223 426 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 427}
428
ea6dedd7
ID		 429static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
430{
431 void __iomem *reg = bank->base;
99c47707 432 u32 l;
c390aad0 433 u32 mask = (1 << bank->width) - 1;
ea6dedd7 434
28f3b5a0 435 reg += bank->regs->irqenable;
99c47707 436 l = __raw_readl(reg);
28f3b5a0 437 if (bank->regs->irqenable_inv)
99c47707
ID		 438 l = ~l;
439 l &= mask;
440 return l;
ea6dedd7
ID		 441}
442
28f3b5a0 443static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
5e1c5ff4 444{
92105bb7 445 void __iomem *reg = bank->base;
5e1c5ff4
TL		 446 u32 l;
447
28f3b5a0
KH		 448 if (bank->regs->set_irqenable) {
449 reg += bank->regs->set_irqenable;
450 l = gpio_mask;
2a900eb7 451 bank->context.irqenable1 |= gpio_mask;
28f3b5a0
KH		 452 } else {
453 reg += bank->regs->irqenable;
5e1c5ff4 454 l = __raw_readl(reg);
28f3b5a0
KH		 455 if (bank->regs->irqenable_inv)
456 l &= ~gpio_mask;
5e1c5ff4
TL		 457 else
458 l |= gpio_mask;
2a900eb7 459 bank->context.irqenable1 = l;
28f3b5a0
KH		 460 }
461
462 __raw_writel(l, reg);
463}
464
465static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
466{
467 void __iomem *reg = bank->base;
468 u32 l;
469
470 if (bank->regs->clr_irqenable) {
471 reg += bank->regs->clr_irqenable;
5e1c5ff4 472 l = gpio_mask;
2a900eb7 473 bank->context.irqenable1 &= ~gpio_mask;
28f3b5a0
KH		 474 } else {
475 reg += bank->regs->irqenable;
56739a69 476 l = __raw_readl(reg);
28f3b5a0 477 if (bank->regs->irqenable_inv)
56739a69 478 l |= gpio_mask;
92105bb7 479 else
28f3b5a0 480 l &= ~gpio_mask;
2a900eb7 481 bank->context.irqenable1 = l;
5e1c5ff4 482 }
28f3b5a0 483
5e1c5ff4
TL		 484 __raw_writel(l, reg);
485}
486
487static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
488{
8276536c
TKD		 489 if (enable)
490 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
491 else
492 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 493}
494
92105bb7
TL		 495/*
496 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
497 * 1510 does not seem to have a wake-up register. If JTAG is connected
498 * to the target, system will wake up always on GPIO events. While
499 * system is running all registered GPIO interrupts need to have wake-up
500 * enabled. When system is suspended, only selected GPIO interrupts need
501 * to have wake-up enabled.
502 */
503static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
504{
f64ad1a0
KH		 505 u32 gpio_bit = GPIO_BIT(bank, gpio);
506 unsigned long flags;
a6472533 507
f64ad1a0 508 if (bank->non_wakeup_gpios & gpio_bit) {
862ff640 509 dev_err(bank->dev,
f64ad1a0 510 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
92105bb7
TL		 511 return -EINVAL;
512 }
f64ad1a0
KH		 513
514 spin_lock_irqsave(&bank->lock, flags);
515 if (enable)
0aa27273 516 bank->context.wake_en |= gpio_bit;
f64ad1a0 517 else
0aa27273 518 bank->context.wake_en &= ~gpio_bit;
f64ad1a0 519
0aa27273 520 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
f64ad1a0
KH		 521 spin_unlock_irqrestore(&bank->lock, flags);
522
523 return 0;
92105bb7
TL		 524}
525
4196dd6b
TL		 526static void _reset_gpio(struct gpio_bank *bank, int gpio)
527{
129fd223 528 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 529 _set_gpio_irqenable(bank, gpio, 0);
530 _clear_gpio_irqstatus(bank, gpio);
129fd223 531 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 532}
533
92105bb7 534/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 535static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 536{
25db711d
BC		 537 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
538 unsigned int gpio = irq_to_gpio(bank, d->irq);
92105bb7 539
25db711d 540 return _set_gpio_wakeup(bank, gpio, enable);
92105bb7
TL		 541}
542
3ff164e1 543static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 544{
3ff164e1 545 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 546 unsigned long flags;
52e31344 547
55b93c32
TKD		 548 /*
549 * If this is the first gpio_request for the bank,
550 * enable the bank module.
551 */
552 if (!bank->mod_usage)
553 pm_runtime_get_sync(bank->dev);
92105bb7 554
55b93c32 555 spin_lock_irqsave(&bank->lock, flags);
4196dd6b
TL		 556 /* Set trigger to none. You need to enable the desired trigger with
557 * request_irq() or set_irq_type().
558 */
3ff164e1 559 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 560
fad96ea8
C		 561 if (bank->regs->pinctrl) {
562 void __iomem *reg = bank->base + bank->regs->pinctrl;
5e1c5ff4 563
92105bb7 564 /* Claim the pin for MPU */
3ff164e1 565 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4 566 }
fad96ea8 567
c8eef65a
C		 568 if (bank->regs->ctrl && !bank->mod_usage) {
569 void __iomem *reg = bank->base + bank->regs->ctrl;
570 u32 ctrl;
571
572 ctrl = __raw_readl(reg);
573 /* Module is enabled, clocks are not gated */
574 ctrl &= ~GPIO_MOD_CTRL_BIT;
575 __raw_writel(ctrl, reg);
41d87cbd 576 bank->context.ctrl = ctrl;
058af1ea 577 }
c8eef65a
C		 578
579 bank->mod_usage |= 1 << offset;
580
a6472533 581 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 582
583 return 0;
584}
585
3ff164e1 586static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 587{
3ff164e1 588 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
6ed87c5b 589 void __iomem *base = bank->base;
a6472533 590 unsigned long flags;
5e1c5ff4 591
a6472533 592 spin_lock_irqsave(&bank->lock, flags);
6ed87c5b 593
41d87cbd 594 if (bank->regs->wkup_en) {
9f096868 595 /* Disable wake-up during idle for dynamic tick */
6ed87c5b 596 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
41d87cbd
TKD		 597 bank->context.wake_en =
598 __raw_readl(bank->base + bank->regs->wkup_en);
599 }
6ed87c5b 600
c8eef65a
C		 601 bank->mod_usage &= ~(1 << offset);
602
603 if (bank->regs->ctrl && !bank->mod_usage) {
604 void __iomem *reg = bank->base + bank->regs->ctrl;
605 u32 ctrl;
606
607 ctrl = __raw_readl(reg);
608 /* Module is disabled, clocks are gated */
609 ctrl |= GPIO_MOD_CTRL_BIT;
610 __raw_writel(ctrl, reg);
41d87cbd 611 bank->context.ctrl = ctrl;
058af1ea 612 }
c8eef65a 613
3ff164e1 614 _reset_gpio(bank, bank->chip.base + offset);
a6472533 615 spin_unlock_irqrestore(&bank->lock, flags);
55b93c32
TKD		 616
617 /*
618 * If this is the last gpio to be freed in the bank,
619 * disable the bank module.
620 */
621 if (!bank->mod_usage)
622 pm_runtime_put(bank->dev);
5e1c5ff4
TL		 623}
624
625/*
626 * We need to unmask the GPIO bank interrupt as soon as possible to
627 * avoid missing GPIO interrupts for other lines in the bank.
628 * Then we need to mask-read-clear-unmask the triggered GPIO lines
629 * in the bank to avoid missing nested interrupts for a GPIO line.
630 * If we wait to unmask individual GPIO lines in the bank after the
631 * line's interrupt handler has been run, we may miss some nested
632 * interrupts.
633 */
10dd5ce2 634static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 635{
92105bb7 636 void __iomem *isr_reg = NULL;
5e1c5ff4 637 u32 isr;
4318f36b 638 unsigned int gpio_irq, gpio_index;
5e1c5ff4 639 struct gpio_bank *bank;
ea6dedd7
ID		 640 u32 retrigger = 0;
641 int unmasked = 0;
ee144182 642 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 643
ee144182 644 chained_irq_enter(chip, desc);
5e1c5ff4 645
6845664a 646 bank = irq_get_handler_data(irq);
eef4bec7 647 isr_reg = bank->base + bank->regs->irqstatus;
55b93c32 648 pm_runtime_get_sync(bank->dev);
b1cc4c55
EK		 649
650 if (WARN_ON(!isr_reg))
651 goto exit;
652
92105bb7 653 while(1) {
6e60e79a 654 u32 isr_saved, level_mask = 0;
ea6dedd7 655 u32 enabled;
6e60e79a 656
ea6dedd7
ID		 657 enabled = _get_gpio_irqbank_mask(bank);
658 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a 659
9ea14d8c 660 if (bank->level_mask)
b144ff6f 661 level_mask = bank->level_mask & enabled;
6e60e79a
TL		 662
663 /* clear edge sensitive interrupts before handler(s) are
664 called so that we don't miss any interrupt occurred while
665 executing them */
28f3b5a0 666 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a 667 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
28f3b5a0 668 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a
TL		 669
670 /* if there is only edge sensitive GPIO pin interrupts
671 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 672 if (!level_mask && !unmasked) {
673 unmasked = 1;
ee144182 674 chained_irq_exit(chip, desc);
ea6dedd7 675 }
92105bb7 676
ea6dedd7
ID		 677 isr |= retrigger;
678 retrigger = 0;
92105bb7
TL		 679 if (!isr)
680 break;
681
384ebe1c 682 gpio_irq = bank->irq_base;
92105bb7 683 for (; isr != 0; isr >>= 1, gpio_irq++) {
25db711d 684 int gpio = irq_to_gpio(bank, gpio_irq);
4318f36b 685
92105bb7
TL		 686 if (!(isr & 1))
687 continue;
29454dde 688
25db711d
BC		 689 gpio_index = GPIO_INDEX(bank, gpio);
690
4318f36b
CM		 691 /*
692 * Some chips can't respond to both rising and falling
693 * at the same time. If this irq was requested with
694 * both flags, we need to flip the ICR data for the IRQ
695 * to respond to the IRQ for the opposite direction.
696 * This will be indicated in the bank toggle_mask.
697 */
698 if (bank->toggle_mask & (1 << gpio_index))
699 _toggle_gpio_edge_triggering(bank, gpio_index);
4318f36b 700
d8aa0251 701 generic_handle_irq(gpio_irq);
92105bb7 702 }
1a8bfa1e 703 }
ea6dedd7
ID		 704 /* if bank has any level sensitive GPIO pin interrupt
705 configured, we must unmask the bank interrupt only after
706 handler(s) are executed in order to avoid spurious bank
707 interrupt */
b1cc4c55 708exit:
ea6dedd7 709 if (!unmasked)
ee144182 710 chained_irq_exit(chip, desc);
55b93c32 711 pm_runtime_put(bank->dev);
5e1c5ff4
TL		 712}
713
e9191028 714static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 715{
e9191028 716 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 717 unsigned int gpio = irq_to_gpio(bank, d->irq);
85ec7b97 718 unsigned long flags;
4196dd6b 719
85ec7b97 720 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 721 _reset_gpio(bank, gpio);
85ec7b97 722 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 723}
724
e9191028 725static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 726{
e9191028 727 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 728 unsigned int gpio = irq_to_gpio(bank, d->irq);
5e1c5ff4
TL		 729
730 _clear_gpio_irqstatus(bank, gpio);
731}
732
e9191028 733static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 734{
e9191028 735 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 736 unsigned int gpio = irq_to_gpio(bank, d->irq);
85ec7b97 737 unsigned long flags;
5e1c5ff4 738
85ec7b97 739 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 740 _set_gpio_irqenable(bank, gpio, 0);
129fd223 741 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 742 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 743}
744
e9191028 745static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 746{
e9191028 747 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 748 unsigned int gpio = irq_to_gpio(bank, d->irq);
129fd223 749 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 750 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 751 unsigned long flags;
55b6019a 752
85ec7b97 753 spin_lock_irqsave(&bank->lock, flags);
55b6019a 754 if (trigger)
129fd223 755 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 756
757 /* For level-triggered GPIOs, the clearing must be done after
758 * the HW source is cleared, thus after the handler has run */
759 if (bank->level_mask & irq_mask) {
760 _set_gpio_irqenable(bank, gpio, 0);
761 _clear_gpio_irqstatus(bank, gpio);
762 }
5e1c5ff4 763
4de8c75b 764 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 765 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 766}
767
e5c56ed3
DB		 768static struct irq_chip gpio_irq_chip = {
769 .name = "GPIO",
e9191028
LB		 770 .irq_shutdown = gpio_irq_shutdown,
771 .irq_ack = gpio_ack_irq,
772 .irq_mask = gpio_mask_irq,
773 .irq_unmask = gpio_unmask_irq,
774 .irq_set_type = gpio_irq_type,
775 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 776};
777
778/*---------------------------------------------------------------------*/
779
79ee031f 780static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 781{
79ee031f 782 struct platform_device *pdev = to_platform_device(dev);
11a78b79 783 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 784 void __iomem *mask_reg = bank->base +
785 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 786 unsigned long flags;
11a78b79 787
a6472533 788 spin_lock_irqsave(&bank->lock, flags);
11a78b79 789 bank->saved_wakeup = __raw_readl(mask_reg);
0aa27273 790 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
a6472533 791 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 792
793 return 0;
794}
795
79ee031f 796static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 797{
79ee031f 798 struct platform_device *pdev = to_platform_device(dev);
11a78b79 799 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 800 void __iomem *mask_reg = bank->base +
801 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 802 unsigned long flags;
11a78b79 803
a6472533 804 spin_lock_irqsave(&bank->lock, flags);
11a78b79 805 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 806 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 807
808 return 0;
809}
810
47145210 811static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 812 .suspend_noirq = omap_mpuio_suspend_noirq,
813 .resume_noirq = omap_mpuio_resume_noirq,
814};
815
3c437ffd 816/* use platform_driver for this. */
11a78b79 817static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 818 .driver = {
819 .name = "mpuio",
79ee031f 820 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 821 },
822};
823
824static struct platform_device omap_mpuio_device = {
825 .name = "mpuio",
826 .id = -1,
827 .dev = {
828 .driver = &omap_mpuio_driver.driver,
829 }
830 /* could list the /proc/iomem resources */
831};
832
03e128ca 833static inline void mpuio_init(struct gpio_bank *bank)
11a78b79 834{
77640aab 835 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 836
11a78b79
DB		 837 if (platform_driver_register(&omap_mpuio_driver) == 0)
838 (void) platform_device_register(&omap_mpuio_device);
839}
840
e5c56ed3 841/*---------------------------------------------------------------------*/
5e1c5ff4 842
52e31344
DB		 843static int gpio_input(struct gpio_chip *chip, unsigned offset)
844{
845 struct gpio_bank *bank;
846 unsigned long flags;
847
848 bank = container_of(chip, struct gpio_bank, chip);
849 spin_lock_irqsave(&bank->lock, flags);
850 _set_gpio_direction(bank, offset, 1);
851 spin_unlock_irqrestore(&bank->lock, flags);
852 return 0;
853}
854
b37c45b8
RQ		 855static int gpio_is_input(struct gpio_bank *bank, int mask)
856{
fa87931a 857 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 858
b37c45b8
RQ		 859 return __raw_readl(reg) & mask;
860}
861
52e31344
DB		 862static int gpio_get(struct gpio_chip *chip, unsigned offset)
863{
b37c45b8 864 struct gpio_bank *bank;
b37c45b8
RQ		 865 u32 mask;
866
a8be8daf 867 bank = container_of(chip, struct gpio_bank, chip);
7fcca715 868 mask = (1 << offset);
b37c45b8
RQ		 869
870 if (gpio_is_input(bank, mask))
7fcca715 871 return _get_gpio_datain(bank, offset);
b37c45b8 872 else
7fcca715 873 return _get_gpio_dataout(bank, offset);
52e31344
DB		 874}
875
876static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
877{
878 struct gpio_bank *bank;
879 unsigned long flags;
880
881 bank = container_of(chip, struct gpio_bank, chip);
882 spin_lock_irqsave(&bank->lock, flags);
fa87931a 883 bank->set_dataout(bank, offset, value);
52e31344
DB		 884 _set_gpio_direction(bank, offset, 0);
885 spin_unlock_irqrestore(&bank->lock, flags);
886 return 0;
887}
888
168ef3d9
FB		 889static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
890 unsigned debounce)
891{
892 struct gpio_bank *bank;
893 unsigned long flags;
894
895 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 896
897 if (!bank->dbck) {
898 bank->dbck = clk_get(bank->dev, "dbclk");
899 if (IS_ERR(bank->dbck))
900 dev_err(bank->dev, "Could not get gpio dbck\n");
901 }
902
168ef3d9
FB		 903 spin_lock_irqsave(&bank->lock, flags);
904 _set_gpio_debounce(bank, offset, debounce);
905 spin_unlock_irqrestore(&bank->lock, flags);
906
907 return 0;
908}
909
52e31344
DB		 910static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
911{
912 struct gpio_bank *bank;
913 unsigned long flags;
914
915 bank = container_of(chip, struct gpio_bank, chip);
916 spin_lock_irqsave(&bank->lock, flags);
fa87931a 917 bank->set_dataout(bank, offset, value);
52e31344
DB		 918 spin_unlock_irqrestore(&bank->lock, flags);
919}
920
a007b709
DB		 921static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
922{
923 struct gpio_bank *bank;
924
925 bank = container_of(chip, struct gpio_bank, chip);
384ebe1c 926 return bank->irq_base + offset;
a007b709
DB		 927}
928
52e31344
DB		 929/*---------------------------------------------------------------------*/
930
9a748053 931static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da 932{
e5ff4440 933 static bool called;
9f7065da
TL		 934 u32 rev;
935
e5ff4440 936 if (called || bank->regs->revision == USHRT_MAX)
9f7065da
TL		 937 return;
938
e5ff4440
KH		 939 rev = __raw_readw(bank->base + bank->regs->revision);
940 pr_info("OMAP GPIO hardware version %d.%d\n",
9f7065da 941 (rev >> 4) & 0x0f, rev & 0x0f);
e5ff4440
KH		 942
943 called = true;
9f7065da
TL		 944}
945
8ba55c5c
DB		 946/* This lock class tells lockdep that GPIO irqs are in a different
947 * category than their parents, so it won't report false recursion.
948 */
949static struct lock_class_key gpio_lock_class;
950
03e128ca 951static void omap_gpio_mod_init(struct gpio_bank *bank)
2fae7fbe 952{
ab985f0f
TKD		 953 void __iomem *base = bank->base;
954 u32 l = 0xffffffff;
2fae7fbe 955
ab985f0f
TKD		 956 if (bank->width == 16)
957 l = 0xffff;
958
d0d665a8 959 if (bank->is_mpuio) {
ab985f0f
TKD		 960 __raw_writel(l, bank->base + bank->regs->irqenable);
961 return;
2fae7fbe 962 }
ab985f0f
TKD		 963
964 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
6edd94db 965 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
ab985f0f 966 if (bank->regs->debounce_en)
6edd94db 967 __raw_writel(0, base + bank->regs->debounce_en);
ab985f0f 968
2dc983c5
TKD		 969 /* Save OE default value (0xffffffff) in the context */
970 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
ab985f0f
TKD		 971 /* Initialize interface clk ungated, module enabled */
972 if (bank->regs->ctrl)
6edd94db 973 __raw_writel(0, base + bank->regs->ctrl);
2fae7fbe
VC		 974}
975
8805f410 976static __devinit void
f8b46b58
KH		 977omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
978 unsigned int num)
979{
980 struct irq_chip_generic *gc;
981 struct irq_chip_type *ct;
982
983 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
984 handle_simple_irq);
83233749
TP		 985 if (!gc) {
986 dev_err(bank->dev, "Memory alloc failed for gc\n");
987 return;
988 }
989
f8b46b58
KH		 990 ct = gc->chip_types;
991
992 /* NOTE: No ack required, reading IRQ status clears it. */
993 ct->chip.irq_mask = irq_gc_mask_set_bit;
994 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
995 ct->chip.irq_set_type = gpio_irq_type;
6ed87c5b
TKD		 996
997 if (bank->regs->wkup_en)
f8b46b58
KH		 998 ct->chip.irq_set_wake = gpio_wake_enable,
999
1000 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1001 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1002 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1003}
1004
d52b31de 1005static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1006{
77640aab 1007 int j;
2fae7fbe
VC		 1008 static int gpio;
1009
2fae7fbe
VC		 1010 /*
1011 * REVISIT eventually switch from OMAP-specific gpio structs
1012 * over to the generic ones
1013 */
1014 bank->chip.request = omap_gpio_request;
1015 bank->chip.free = omap_gpio_free;
1016 bank->chip.direction_input = gpio_input;
1017 bank->chip.get = gpio_get;
1018 bank->chip.direction_output = gpio_output;
1019 bank->chip.set_debounce = gpio_debounce;
1020 bank->chip.set = gpio_set;
1021 bank->chip.to_irq = gpio_2irq;
d0d665a8 1022 if (bank->is_mpuio) {
2fae7fbe 1023 bank->chip.label = "mpuio";
6ed87c5b
TKD		 1024 if (bank->regs->wkup_en)
1025 bank->chip.dev = &omap_mpuio_device.dev;
2fae7fbe
VC		 1026 bank->chip.base = OMAP_MPUIO(0);
1027 } else {
1028 bank->chip.label = "gpio";
1029 bank->chip.base = gpio;
d5f46247 1030 gpio += bank->width;
2fae7fbe 1031 }
d5f46247 1032 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1033
1034 gpiochip_add(&bank->chip);
1035
384ebe1c 1036 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1475b85d 1037 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1038 irq_set_chip_data(j, bank);
d0d665a8 1039 if (bank->is_mpuio) {
f8b46b58
KH		 1040 omap_mpuio_alloc_gc(bank, j, bank->width);
1041 } else {
6845664a 1042 irq_set_chip(j, &gpio_irq_chip);
f8b46b58
KH		 1043 irq_set_handler(j, handle_simple_irq);
1044 set_irq_flags(j, IRQF_VALID);
1045 }
2fae7fbe 1046 }
6845664a
TG		 1047 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1048 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1049}
1050
384ebe1c
BC		 1051static const struct of_device_id omap_gpio_match[];
1052
77640aab 1053static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1054{
862ff640 1055 struct device *dev = &pdev->dev;
384ebe1c
BC		 1056 struct device_node *node = dev->of_node;
1057 const struct of_device_id *match;
77640aab
VC		 1058 struct omap_gpio_platform_data *pdata;
1059 struct resource *res;
5e1c5ff4 1060 struct gpio_bank *bank;
03e128ca 1061 int ret = 0;
5e1c5ff4 1062
384ebe1c
BC		 1063 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1064
1065 pdata = match ? match->data : dev->platform_data;
1066 if (!pdata)
96751fcb 1067 return -EINVAL;
5492fb1a 1068
96751fcb 1069 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
03e128ca 1070 if (!bank) {
862ff640 1071 dev_err(dev, "Memory alloc failed\n");
96751fcb 1072 return -ENOMEM;
03e128ca 1073 }
92105bb7 1074
77640aab
VC		 1075 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1076 if (unlikely(!res)) {
862ff640 1077 dev_err(dev, "Invalid IRQ resource\n");
96751fcb 1078 return -ENODEV;
44169075 1079 }
5e1c5ff4 1080
77640aab 1081 bank->irq = res->start;
862ff640 1082 bank->dev = dev;
77640aab 1083 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1084 bank->stride = pdata->bank_stride;
d5f46247 1085 bank->width = pdata->bank_width;
d0d665a8 1086 bank->is_mpuio = pdata->is_mpuio;
803a2434 1087 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
0cde8d03 1088 bank->loses_context = pdata->loses_context;
60a3437d 1089 bank->get_context_loss_count = pdata->get_context_loss_count;
fa87931a 1090 bank->regs = pdata->regs;
384ebe1c
BC		 1091#ifdef CONFIG_OF_GPIO
1092 bank->chip.of_node = of_node_get(node);
1093#endif
1094
1095 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1096 if (bank->irq_base < 0) {
1097 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1098 return -ENODEV;
1099 }
1100
1101 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1102 0, &irq_domain_simple_ops, NULL);
fa87931a
KH		 1103
1104 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1105 bank->set_dataout = _set_gpio_dataout_reg;
1106 else
1107 bank->set_dataout = _set_gpio_dataout_mask;
9f7065da 1108
77640aab 1109 spin_lock_init(&bank->lock);
9f7065da 1110
77640aab
VC		 1111 /* Static mapping, never released */
1112 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1113 if (unlikely(!res)) {
862ff640 1114 dev_err(dev, "Invalid mem resource\n");
96751fcb
BC		 1115 return -ENODEV;
1116 }
1117
1118 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1119 pdev->name)) {
1120 dev_err(dev, "Region already claimed\n");
1121 return -EBUSY;
77640aab 1122 }
89db9482 1123
96751fcb 1124 bank->base = devm_ioremap(dev, res->start, resource_size(res));
77640aab 1125 if (!bank->base) {
862ff640 1126 dev_err(dev, "Could not ioremap\n");
96751fcb 1127 return -ENOMEM;
5e1c5ff4
TL		 1128 }
1129
065cd795
TKD		 1130 platform_set_drvdata(pdev, bank);
1131
77640aab 1132 pm_runtime_enable(bank->dev);
55b93c32 1133 pm_runtime_irq_safe(bank->dev);
77640aab
VC		 1134 pm_runtime_get_sync(bank->dev);
1135
d0d665a8 1136 if (bank->is_mpuio)
ab985f0f
TKD		 1137 mpuio_init(bank);
1138
03e128ca 1139 omap_gpio_mod_init(bank);
77640aab 1140 omap_gpio_chip_init(bank);
9a748053 1141 omap_gpio_show_rev(bank);
9f7065da 1142
55b93c32
TKD		 1143 pm_runtime_put(bank->dev);
1144
03e128ca 1145 list_add_tail(&bank->node, &omap_gpio_list);
77640aab 1146
03e128ca 1147 return ret;
5e1c5ff4
TL		 1148}
1149
55b93c32
TKD		 1150#ifdef CONFIG_ARCH_OMAP2PLUS
1151
1152#if defined(CONFIG_PM_SLEEP)
1153static int omap_gpio_suspend(struct device *dev)
92105bb7 1154{
065cd795
TKD		 1155 struct platform_device *pdev = to_platform_device(dev);
1156 struct gpio_bank *bank = platform_get_drvdata(pdev);
1157 void __iomem *base = bank->base;
1158 void __iomem *wakeup_enable;
1159 unsigned long flags;
92105bb7 1160
065cd795
TKD		 1161 if (!bank->mod_usage || !bank->loses_context)
1162 return 0;
92105bb7 1163
0aa27273 1164 if (!bank->regs->wkup_en || !bank->context.wake_en)
065cd795 1165 return 0;
6ed87c5b 1166
065cd795 1167 wakeup_enable = bank->base + bank->regs->wkup_en;
92105bb7 1168
065cd795
TKD		 1169 spin_lock_irqsave(&bank->lock, flags);
1170 bank->saved_wakeup = __raw_readl(wakeup_enable);
1171 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
0aa27273 1172 _gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
065cd795 1173 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1174
1175 return 0;
1176}
1177
55b93c32 1178static int omap_gpio_resume(struct device *dev)
92105bb7 1179{
065cd795
TKD		 1180 struct platform_device *pdev = to_platform_device(dev);
1181 struct gpio_bank *bank = platform_get_drvdata(pdev);
1182 void __iomem *base = bank->base;
1183 unsigned long flags;
92105bb7 1184
065cd795
TKD		 1185 if (!bank->mod_usage || !bank->loses_context)
1186 return 0;
92105bb7 1187
065cd795
TKD		 1188 if (!bank->regs->wkup_en || !bank->saved_wakeup)
1189 return 0;
92105bb7 1190
065cd795
TKD		 1191 spin_lock_irqsave(&bank->lock, flags);
1192 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1193 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1194 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1195
55b93c32
TKD		 1196 return 0;
1197}
1198#endif /* CONFIG_PM_SLEEP */
3ac4fa99 1199
2dc983c5 1200#if defined(CONFIG_PM_RUNTIME)
60a3437d 1201static void omap_gpio_restore_context(struct gpio_bank *bank);
3ac4fa99 1202
2dc983c5 1203static int omap_gpio_runtime_suspend(struct device *dev)
3ac4fa99 1204{
2dc983c5
TKD		 1205 struct platform_device *pdev = to_platform_device(dev);
1206 struct gpio_bank *bank = platform_get_drvdata(pdev);
1207 u32 l1 = 0, l2 = 0;
1208 unsigned long flags;
68942edb 1209 u32 wake_low, wake_hi;
8865b9b6 1210
2dc983c5 1211 spin_lock_irqsave(&bank->lock, flags);
68942edb
KH		 1212
1213 /*
1214 * Only edges can generate a wakeup event to the PRCM.
1215 *
1216 * Therefore, ensure any wake-up capable GPIOs have
1217 * edge-detection enabled before going idle to ensure a wakeup
1218 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1219 * NDA TRM 25.5.3.1)
1220 *
1221 * The normal values will be restored upon ->runtime_resume()
1222 * by writing back the values saved in bank->context.
1223 */
1224 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1225 if (wake_low)
1226 __raw_writel(wake_low | bank->context.fallingdetect,
1227 bank->base + bank->regs->fallingdetect);
1228 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1229 if (wake_hi)
1230 __raw_writel(wake_hi | bank->context.risingdetect,
1231 bank->base + bank->regs->risingdetect);
1232
2dc983c5
TKD		 1233 if (bank->power_mode != OFF_MODE) {
1234 bank->power_mode = 0;
41d87cbd 1235 goto update_gpio_context_count;
2dc983c5
TKD		 1236 }
1237 /*
1238 * If going to OFF, remove triggering for all
1239 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1240 * generated. See OMAP2420 Errata item 1.101.
1241 */
2dc983c5
TKD		 1242 bank->saved_datain = __raw_readl(bank->base +
1243 bank->regs->datain);
c6f31c9e
TKD		 1244 l1 = bank->context.fallingdetect;
1245 l2 = bank->context.risingdetect;
3f1686a9 1246
2dc983c5
TKD		 1247 l1 &= ~bank->enabled_non_wakeup_gpios;
1248 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9 1249
2dc983c5
TKD		 1250 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1251 __raw_writel(l2, bank->base + bank->regs->risingdetect);
3f1686a9 1252
2dc983c5 1253 bank->workaround_enabled = true;
3f1686a9 1254
41d87cbd 1255update_gpio_context_count:
2dc983c5
TKD		 1256 if (bank->get_context_loss_count)
1257 bank->context_loss_count =
60a3437d
TKD		 1258 bank->get_context_loss_count(bank->dev);
1259
72f83af9 1260 _gpio_dbck_disable(bank);
2dc983c5 1261 spin_unlock_irqrestore(&bank->lock, flags);
55b93c32 1262
2dc983c5 1263 return 0;
3ac4fa99
JY		 1264}
1265
2dc983c5 1266static int omap_gpio_runtime_resume(struct device *dev)
3ac4fa99 1267{
2dc983c5
TKD		 1268 struct platform_device *pdev = to_platform_device(dev);
1269 struct gpio_bank *bank = platform_get_drvdata(pdev);
1270 int context_lost_cnt_after;
1271 u32 l = 0, gen, gen0, gen1;
1272 unsigned long flags;
8865b9b6 1273
2dc983c5 1274 spin_lock_irqsave(&bank->lock, flags);
72f83af9 1275 _gpio_dbck_enable(bank);
68942edb
KH		 1276
1277 /*
1278 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1279 * GPIOs were set to edge trigger also in order to be able to
1280 * generate a PRCM wakeup. Here we restore the
1281 * pre-runtime_suspend() values for edge triggering.
1282 */
1283 __raw_writel(bank->context.fallingdetect,
1284 bank->base + bank->regs->fallingdetect);
1285 __raw_writel(bank->context.risingdetect,
1286 bank->base + bank->regs->risingdetect);
1287
960edffe 1288 if (!bank->workaround_enabled) {
2dc983c5
TKD		 1289 spin_unlock_irqrestore(&bank->lock, flags);
1290 return 0;
1291 }
55b93c32 1292
2dc983c5
TKD		 1293 if (bank->get_context_loss_count) {
1294 context_lost_cnt_after =
1295 bank->get_context_loss_count(bank->dev);
1296 if (context_lost_cnt_after != bank->context_loss_count ||
1297 !context_lost_cnt_after) {
1298 omap_gpio_restore_context(bank);
1299 } else {
1300 spin_unlock_irqrestore(&bank->lock, flags);
1301 return 0;
60a3437d 1302 }
2dc983c5 1303 }
43ffcd9a 1304
c6f31c9e 1305 __raw_writel(bank->context.fallingdetect,
2dc983c5 1306 bank->base + bank->regs->fallingdetect);
c6f31c9e 1307 __raw_writel(bank->context.risingdetect,
2dc983c5
TKD		 1308 bank->base + bank->regs->risingdetect);
1309 l = __raw_readl(bank->base + bank->regs->datain);
3f1686a9 1310
2dc983c5
TKD		 1311 /*
1312 * Check if any of the non-wakeup interrupt GPIOs have changed
1313 * state. If so, generate an IRQ by software. This is
1314 * horribly racy, but it's the best we can do to work around
1315 * this silicon bug.
1316 */
1317 l ^= bank->saved_datain;
1318 l &= bank->enabled_non_wakeup_gpios;
3f1686a9 1319
2dc983c5
TKD		 1320 /*
1321 * No need to generate IRQs for the rising edge for gpio IRQs
1322 * configured with falling edge only; and vice versa.
1323 */
c6f31c9e 1324 gen0 = l & bank->context.fallingdetect;
2dc983c5 1325 gen0 &= bank->saved_datain;
82dbb9d3 1326
c6f31c9e 1327 gen1 = l & bank->context.risingdetect;
2dc983c5 1328 gen1 &= ~(bank->saved_datain);
82dbb9d3 1329
2dc983c5 1330 /* FIXME: Consider GPIO IRQs with level detections properly! */
c6f31c9e
TKD		 1331 gen = l & (~(bank->context.fallingdetect) &
1332 ~(bank->context.risingdetect));
2dc983c5
TKD		 1333 /* Consider all GPIO IRQs needed to be updated */
1334 gen |= gen0 | gen1;
82dbb9d3 1335
2dc983c5
TKD		 1336 if (gen) {
1337 u32 old0, old1;
82dbb9d3 1338
2dc983c5
TKD		 1339 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1340 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
3f1686a9 1341
2dc983c5
TKD		 1342 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1343 __raw_writel(old0 | gen, bank->base +
9ea14d8c 1344 bank->regs->leveldetect0);
2dc983c5 1345 __raw_writel(old1 | gen, bank->base +
9ea14d8c 1346 bank->regs->leveldetect1);
2dc983c5 1347 }
9ea14d8c 1348
2dc983c5
TKD		 1349 if (cpu_is_omap44xx()) {
1350 __raw_writel(old0 | l, bank->base +
9ea14d8c 1351 bank->regs->leveldetect0);
2dc983c5 1352 __raw_writel(old1 | l, bank->base +
9ea14d8c 1353 bank->regs->leveldetect1);
3ac4fa99 1354 }
2dc983c5
TKD		 1355 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1356 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1357 }
1358
1359 bank->workaround_enabled = false;
1360 spin_unlock_irqrestore(&bank->lock, flags);
1361
1362 return 0;
1363}
1364#endif /* CONFIG_PM_RUNTIME */
1365
1366void omap2_gpio_prepare_for_idle(int pwr_mode)
1367{
1368 struct gpio_bank *bank;
1369
1370 list_for_each_entry(bank, &omap_gpio_list, node) {
2dc983c5
TKD		 1371 if (!bank->mod_usage || !bank->loses_context)
1372 continue;
1373
1374 bank->power_mode = pwr_mode;
1375
2dc983c5
TKD		 1376 pm_runtime_put_sync_suspend(bank->dev);
1377 }
1378}
1379
1380void omap2_gpio_resume_after_idle(void)
1381{
1382 struct gpio_bank *bank;
1383
1384 list_for_each_entry(bank, &omap_gpio_list, node) {
2dc983c5
TKD		 1385 if (!bank->mod_usage || !bank->loses_context)
1386 continue;
1387
2dc983c5 1388 pm_runtime_get_sync(bank->dev);
3ac4fa99 1389 }
3ac4fa99
JY		 1390}
1391
2dc983c5 1392#if defined(CONFIG_PM_RUNTIME)
60a3437d 1393static void omap_gpio_restore_context(struct gpio_bank *bank)
40c670f0 1394{
60a3437d 1395 __raw_writel(bank->context.wake_en,
ae10f233
TKD		 1396 bank->base + bank->regs->wkup_en);
1397 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
60a3437d 1398 __raw_writel(bank->context.leveldetect0,
ae10f233 1399 bank->base + bank->regs->leveldetect0);
60a3437d 1400 __raw_writel(bank->context.leveldetect1,
ae10f233 1401 bank->base + bank->regs->leveldetect1);
60a3437d 1402 __raw_writel(bank->context.risingdetect,
ae10f233 1403 bank->base + bank->regs->risingdetect);
60a3437d 1404 __raw_writel(bank->context.fallingdetect,
ae10f233 1405 bank->base + bank->regs->fallingdetect);
f86bcc30
NM		 1406 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1407 __raw_writel(bank->context.dataout,
1408 bank->base + bank->regs->set_dataout);
1409 else
1410 __raw_writel(bank->context.dataout,
1411 bank->base + bank->regs->dataout);
6d13eaaf
NM		 1412 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1413
ae547354
NM		 1414 if (bank->dbck_enable_mask) {
1415 __raw_writel(bank->context.debounce, bank->base +
1416 bank->regs->debounce);
1417 __raw_writel(bank->context.debounce_en,
1418 bank->base + bank->regs->debounce_en);
1419 }
ba805be5
NM		 1420
1421 __raw_writel(bank->context.irqenable1,
1422 bank->base + bank->regs->irqenable);
1423 __raw_writel(bank->context.irqenable2,
1424 bank->base + bank->regs->irqenable2);
40c670f0 1425}
2dc983c5 1426#endif /* CONFIG_PM_RUNTIME */
55b93c32
TKD		 1427#else
1428#define omap_gpio_suspend NULL
1429#define omap_gpio_resume NULL
2dc983c5
TKD		 1430#define omap_gpio_runtime_suspend NULL
1431#define omap_gpio_runtime_resume NULL
40c670f0
RN		 1432#endif
1433
55b93c32
TKD		 1434static const struct dev_pm_ops gpio_pm_ops = {
1435 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
2dc983c5
TKD		 1436 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1437 NULL)
55b93c32
TKD		 1438};
1439
384ebe1c
BC		 1440#if defined(CONFIG_OF)
1441static struct omap_gpio_reg_offs omap2_gpio_regs = {
1442 .revision = OMAP24XX_GPIO_REVISION,
1443 .direction = OMAP24XX_GPIO_OE,
1444 .datain = OMAP24XX_GPIO_DATAIN,
1445 .dataout = OMAP24XX_GPIO_DATAOUT,
1446 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1447 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1448 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1449 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1450 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1451 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1452 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1453 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1454 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1455 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1456 .ctrl = OMAP24XX_GPIO_CTRL,
1457 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1458 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1459 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1460 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1461 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1462};
1463
1464static struct omap_gpio_reg_offs omap4_gpio_regs = {
1465 .revision = OMAP4_GPIO_REVISION,
1466 .direction = OMAP4_GPIO_OE,
1467 .datain = OMAP4_GPIO_DATAIN,
1468 .dataout = OMAP4_GPIO_DATAOUT,
1469 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1470 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1471 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1472 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1473 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1474 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1475 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1476 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1477 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1478 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1479 .ctrl = OMAP4_GPIO_CTRL,
1480 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1481 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1482 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1483 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1484 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1485};
1486
1487static struct omap_gpio_platform_data omap2_pdata = {
1488 .regs = &omap2_gpio_regs,
1489 .bank_width = 32,
1490 .dbck_flag = false,
1491};
1492
1493static struct omap_gpio_platform_data omap3_pdata = {
1494 .regs = &omap2_gpio_regs,
1495 .bank_width = 32,
1496 .dbck_flag = true,
1497};
1498
1499static struct omap_gpio_platform_data omap4_pdata = {
1500 .regs = &omap4_gpio_regs,
1501 .bank_width = 32,
1502 .dbck_flag = true,
1503};
1504
1505static const struct of_device_id omap_gpio_match[] = {
1506 {
1507 .compatible = "ti,omap4-gpio",
1508 .data = &omap4_pdata,
1509 },
1510 {
1511 .compatible = "ti,omap3-gpio",
1512 .data = &omap3_pdata,
1513 },
1514 {
1515 .compatible = "ti,omap2-gpio",
1516 .data = &omap2_pdata,
1517 },
1518 { },
1519};
1520MODULE_DEVICE_TABLE(of, omap_gpio_match);
1521#endif
1522
77640aab
VC		 1523static struct platform_driver omap_gpio_driver = {
1524 .probe = omap_gpio_probe,
1525 .driver = {
1526 .name = "omap_gpio",
55b93c32 1527 .pm = &gpio_pm_ops,
384ebe1c 1528 .of_match_table = of_match_ptr(omap_gpio_match),
77640aab
VC		 1529 },
1530};
1531
5e1c5ff4 1532/*
77640aab
VC		 1533 * gpio driver register needs to be done before
1534 * machine_init functions access gpio APIs.
1535 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1536 */
77640aab 1537static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1538{
77640aab 1539 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1540}
77640aab 1541postcore_initcall(omap_gpio_drv_reg);
Linux kernel - Deliverables
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