Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
de88cbb7 | 27 | #include <linux/irqchip/chained_irq.h> |
4b25408f | 28 | #include <linux/gpio.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
5e1c5ff4 | 54 | u16 irq; |
3ac4fa99 JY |
55 | u32 non_wakeup_gpios; |
56 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 57 | struct gpio_regs context; |
3ac4fa99 | 58 | u32 saved_datain; |
b144ff6f | 59 | u32 level_mask; |
4318f36b | 60 | u32 toggle_mask; |
5e1c5ff4 | 61 | spinlock_t lock; |
52e31344 | 62 | struct gpio_chip chip; |
89db9482 | 63 | struct clk *dbck; |
058af1ea | 64 | u32 mod_usage; |
fa365e4d | 65 | u32 irq_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
72f83af9 | 67 | bool dbck_enabled; |
77640aab | 68 | struct device *dev; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
352a2d5b | 72 | bool context_valid; |
5de62b86 | 73 | int stride; |
d5f46247 | 74 | u32 width; |
60a3437d | 75 | int context_loss_count; |
2dc983c5 TKD |
76 | int power_mode; |
77 | bool workaround_enabled; | |
fa87931a KH |
78 | |
79 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 80 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
81 | |
82 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
83 | }; |
84 | ||
129fd223 KH |
85 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
86 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 87 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 88 | |
fa365e4d JMC |
89 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
90 | #define LINE_USED(line, offset) (line & (1 << offset)) | |
91 | ||
25db711d BC |
92 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
93 | { | |
ede4d7a5 JH |
94 | return bank->chip.base + gpio_irq; |
95 | } | |
96 | ||
fb655f57 | 97 | static inline struct gpio_bank *_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 98 | { |
fb655f57 JMC |
99 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
100 | return container_of(chip, struct gpio_bank, chip); | |
25db711d BC |
101 | } |
102 | ||
5e1c5ff4 TL |
103 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
104 | { | |
92105bb7 | 105 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
106 | u32 l; |
107 | ||
fa87931a | 108 | reg += bank->regs->direction; |
661553b9 | 109 | l = readl_relaxed(reg); |
5e1c5ff4 TL |
110 | if (is_input) |
111 | l |= 1 << gpio; | |
112 | else | |
113 | l &= ~(1 << gpio); | |
661553b9 | 114 | writel_relaxed(l, reg); |
41d87cbd | 115 | bank->context.oe = l; |
5e1c5ff4 TL |
116 | } |
117 | ||
fa87931a KH |
118 | |
119 | /* set data out value using dedicate set/clear register */ | |
120 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 121 | { |
92105bb7 | 122 | void __iomem *reg = bank->base; |
fa87931a | 123 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 124 | |
2c836f7e | 125 | if (enable) { |
fa87931a | 126 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
127 | bank->context.dataout |= l; |
128 | } else { | |
fa87931a | 129 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
130 | bank->context.dataout &= ~l; |
131 | } | |
5e1c5ff4 | 132 | |
661553b9 | 133 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
134 | } |
135 | ||
fa87931a KH |
136 | /* set data out value using mask register */ |
137 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 138 | { |
fa87931a KH |
139 | void __iomem *reg = bank->base + bank->regs->dataout; |
140 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
141 | u32 l; | |
5e1c5ff4 | 142 | |
661553b9 | 143 | l = readl_relaxed(reg); |
fa87931a KH |
144 | if (enable) |
145 | l |= gpio_bit; | |
146 | else | |
147 | l &= ~gpio_bit; | |
661553b9 | 148 | writel_relaxed(l, reg); |
41d87cbd | 149 | bank->context.dataout = l; |
5e1c5ff4 TL |
150 | } |
151 | ||
7fcca715 | 152 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 153 | { |
fa87931a | 154 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 155 | |
661553b9 | 156 | return (readl_relaxed(reg) & (1 << offset)) != 0; |
5e1c5ff4 | 157 | } |
b37c45b8 | 158 | |
7fcca715 | 159 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 160 | { |
fa87931a | 161 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 162 | |
661553b9 | 163 | return (readl_relaxed(reg) & (1 << offset)) != 0; |
b37c45b8 RQ |
164 | } |
165 | ||
ece9528e KH |
166 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
167 | { | |
661553b9 | 168 | int l = readl_relaxed(base + reg); |
ece9528e | 169 | |
862ff640 | 170 | if (set) |
ece9528e KH |
171 | l |= mask; |
172 | else | |
173 | l &= ~mask; | |
174 | ||
661553b9 | 175 | writel_relaxed(l, base + reg); |
ece9528e | 176 | } |
92105bb7 | 177 | |
72f83af9 TKD |
178 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
179 | { | |
180 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
181 | clk_enable(bank->dbck); | |
182 | bank->dbck_enabled = true; | |
9e303f22 | 183 | |
661553b9 | 184 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 185 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
186 | } |
187 | } | |
188 | ||
189 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
190 | { | |
191 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
192 | /* |
193 | * Disable debounce before cutting it's clock. If debounce is | |
194 | * enabled but the clock is not, GPIO module seems to be unable | |
195 | * to detect events and generate interrupts at least on OMAP3. | |
196 | */ | |
661553b9 | 197 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 198 | |
72f83af9 TKD |
199 | clk_disable(bank->dbck); |
200 | bank->dbck_enabled = false; | |
201 | } | |
202 | } | |
203 | ||
168ef3d9 FB |
204 | /** |
205 | * _set_gpio_debounce - low level gpio debounce time | |
206 | * @bank: the gpio bank we're acting upon | |
207 | * @gpio: the gpio number on this @gpio | |
208 | * @debounce: debounce time to use | |
209 | * | |
210 | * OMAP's debounce time is in 31us steps so we need | |
211 | * to convert and round up to the closest unit. | |
212 | */ | |
213 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
214 | unsigned debounce) | |
215 | { | |
9942da0e | 216 | void __iomem *reg; |
168ef3d9 FB |
217 | u32 val; |
218 | u32 l; | |
219 | ||
77640aab VC |
220 | if (!bank->dbck_flag) |
221 | return; | |
222 | ||
168ef3d9 FB |
223 | if (debounce < 32) |
224 | debounce = 0x01; | |
225 | else if (debounce > 7936) | |
226 | debounce = 0xff; | |
227 | else | |
228 | debounce = (debounce / 0x1f) - 1; | |
229 | ||
129fd223 | 230 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 231 | |
6fd9c421 | 232 | clk_enable(bank->dbck); |
9942da0e | 233 | reg = bank->base + bank->regs->debounce; |
661553b9 | 234 | writel_relaxed(debounce, reg); |
168ef3d9 | 235 | |
9942da0e | 236 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 237 | val = readl_relaxed(reg); |
168ef3d9 | 238 | |
6fd9c421 | 239 | if (debounce) |
168ef3d9 | 240 | val |= l; |
6fd9c421 | 241 | else |
168ef3d9 | 242 | val &= ~l; |
f7ec0b0b | 243 | bank->dbck_enable_mask = val; |
168ef3d9 | 244 | |
661553b9 | 245 | writel_relaxed(val, reg); |
6fd9c421 TKD |
246 | clk_disable(bank->dbck); |
247 | /* | |
248 | * Enable debounce clock per module. | |
249 | * This call is mandatory because in omap_gpio_request() when | |
250 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
251 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
252 | * used within _gpio_dbck_enable() is still not initialized at | |
253 | * that point. Therefore we have to enable dbck here. | |
254 | */ | |
255 | _gpio_dbck_enable(bank); | |
ae547354 NM |
256 | if (bank->dbck_enable_mask) { |
257 | bank->context.debounce = debounce; | |
258 | bank->context.debounce_en = val; | |
259 | } | |
168ef3d9 FB |
260 | } |
261 | ||
c9c55d92 JH |
262 | /** |
263 | * _clear_gpio_debounce - clear debounce settings for a gpio | |
264 | * @bank: the gpio bank we're acting upon | |
265 | * @gpio: the gpio number on this @gpio | |
266 | * | |
267 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
268 | * this is the only gpio in this bank using debounce, then clear the debounce | |
269 | * time too. The debounce clock will also be disabled when calling this function | |
270 | * if this is the only gpio in the bank using debounce. | |
271 | */ | |
272 | static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | |
273 | { | |
274 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
275 | ||
276 | if (!bank->dbck_flag) | |
277 | return; | |
278 | ||
279 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
280 | return; | |
281 | ||
282 | bank->dbck_enable_mask &= ~gpio_bit; | |
283 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 284 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
285 | bank->base + bank->regs->debounce_en); |
286 | ||
287 | if (!bank->dbck_enable_mask) { | |
288 | bank->context.debounce = 0; | |
661553b9 | 289 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 JH |
290 | bank->regs->debounce); |
291 | clk_disable(bank->dbck); | |
292 | bank->dbck_enabled = false; | |
293 | } | |
294 | } | |
295 | ||
5e571f38 | 296 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 297 | unsigned trigger) |
5e1c5ff4 | 298 | { |
3ac4fa99 | 299 | void __iomem *base = bank->base; |
92105bb7 TL |
300 | u32 gpio_bit = 1 << gpio; |
301 | ||
5e571f38 TKD |
302 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
303 | trigger & IRQ_TYPE_LEVEL_LOW); | |
304 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
305 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
306 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
307 | trigger & IRQ_TYPE_EDGE_RISING); | |
308 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
309 | trigger & IRQ_TYPE_EDGE_FALLING); | |
310 | ||
41d87cbd | 311 | bank->context.leveldetect0 = |
661553b9 | 312 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 313 | bank->context.leveldetect1 = |
661553b9 | 314 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 315 | bank->context.risingdetect = |
661553b9 | 316 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 317 | bank->context.fallingdetect = |
661553b9 | 318 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
319 | |
320 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 321 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 322 | bank->context.wake_en = |
661553b9 | 323 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 324 | } |
5e571f38 | 325 | |
55b220ca | 326 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
327 | if (!bank->regs->irqctrl) { |
328 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
329 | if (bank->non_wakeup_gpios) { | |
330 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
331 | goto exit; | |
332 | } | |
333 | ||
699117a6 CW |
334 | /* |
335 | * Log the edge gpio and manually trigger the IRQ | |
336 | * after resume if the input level changes | |
337 | * to avoid irq lost during PER RET/OFF mode | |
338 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
339 | */ | |
340 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
341 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
342 | else | |
343 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
344 | } | |
5eb3bb9c | 345 | |
5e571f38 | 346 | exit: |
9ea14d8c | 347 | bank->level_mask = |
661553b9 VK |
348 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
349 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
350 | } |
351 | ||
9198bcd3 | 352 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
353 | /* |
354 | * This only applies to chips that can't do both rising and falling edge | |
355 | * detection at once. For all other chips, this function is a noop. | |
356 | */ | |
357 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
358 | { | |
359 | void __iomem *reg = bank->base; | |
360 | u32 l = 0; | |
361 | ||
5e571f38 | 362 | if (!bank->regs->irqctrl) |
4318f36b | 363 | return; |
5e571f38 TKD |
364 | |
365 | reg += bank->regs->irqctrl; | |
4318f36b | 366 | |
661553b9 | 367 | l = readl_relaxed(reg); |
4318f36b CM |
368 | if ((l >> gpio) & 1) |
369 | l &= ~(1 << gpio); | |
370 | else | |
371 | l |= 1 << gpio; | |
372 | ||
661553b9 | 373 | writel_relaxed(l, reg); |
4318f36b | 374 | } |
5e571f38 TKD |
375 | #else |
376 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 377 | #endif |
4318f36b | 378 | |
00ece7e4 TKD |
379 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, |
380 | unsigned trigger) | |
92105bb7 TL |
381 | { |
382 | void __iomem *reg = bank->base; | |
5e571f38 | 383 | void __iomem *base = bank->base; |
92105bb7 | 384 | u32 l = 0; |
5e1c5ff4 | 385 | |
5e571f38 TKD |
386 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
387 | set_gpio_trigger(bank, gpio, trigger); | |
388 | } else if (bank->regs->irqctrl) { | |
389 | reg += bank->regs->irqctrl; | |
390 | ||
661553b9 | 391 | l = readl_relaxed(reg); |
29501577 | 392 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 393 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 394 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 395 | l |= 1 << gpio; |
6cab4860 | 396 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 397 | l &= ~(1 << gpio); |
92105bb7 | 398 | else |
5e571f38 TKD |
399 | return -EINVAL; |
400 | ||
661553b9 | 401 | writel_relaxed(l, reg); |
5e571f38 | 402 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 403 | if (gpio & 0x08) |
5e571f38 | 404 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 405 | else |
5e571f38 TKD |
406 | reg += bank->regs->edgectrl1; |
407 | ||
5e1c5ff4 | 408 | gpio &= 0x07; |
661553b9 | 409 | l = readl_relaxed(reg); |
5e1c5ff4 | 410 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 411 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 412 | l |= 2 << (gpio << 1); |
6cab4860 | 413 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 414 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
415 | |
416 | /* Enable wake-up during idle for dynamic tick */ | |
417 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd | 418 | bank->context.wake_en = |
661553b9 VK |
419 | readl_relaxed(bank->base + bank->regs->wkup_en); |
420 | writel_relaxed(l, reg); | |
5e1c5ff4 | 421 | } |
92105bb7 | 422 | return 0; |
5e1c5ff4 TL |
423 | } |
424 | ||
fac7fa16 JMC |
425 | static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
426 | { | |
427 | if (bank->regs->pinctrl) { | |
428 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
429 | ||
430 | /* Claim the pin for MPU */ | |
661553b9 | 431 | writel_relaxed(readl_relaxed(reg) | (1 << offset), reg); |
fac7fa16 JMC |
432 | } |
433 | ||
434 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
435 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
436 | u32 ctrl; | |
437 | ||
661553b9 | 438 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
439 | /* Module is enabled, clocks are not gated */ |
440 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 441 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
442 | bank->context.ctrl = ctrl; |
443 | } | |
444 | } | |
445 | ||
446 | static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset) | |
447 | { | |
448 | void __iomem *base = bank->base; | |
449 | ||
450 | if (bank->regs->wkup_en && | |
451 | !LINE_USED(bank->mod_usage, offset) && | |
452 | !LINE_USED(bank->irq_usage, offset)) { | |
453 | /* Disable wake-up during idle for dynamic tick */ | |
454 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); | |
455 | bank->context.wake_en = | |
661553b9 | 456 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
457 | } |
458 | ||
459 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
460 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
461 | u32 ctrl; | |
462 | ||
661553b9 | 463 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
464 | /* Module is disabled, clocks are gated */ |
465 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 466 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
467 | bank->context.ctrl = ctrl; |
468 | } | |
469 | } | |
470 | ||
fa365e4d JMC |
471 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
472 | { | |
473 | void __iomem *reg = bank->base + bank->regs->direction; | |
474 | ||
661553b9 | 475 | return readl_relaxed(reg) & mask; |
fa365e4d JMC |
476 | } |
477 | ||
e9191028 | 478 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 479 | { |
fb655f57 | 480 | struct gpio_bank *bank = _irq_data_get_bank(d); |
4b25408f | 481 | unsigned gpio = 0; |
92105bb7 | 482 | int retval; |
a6472533 | 483 | unsigned long flags; |
fac7fa16 | 484 | unsigned offset; |
92105bb7 | 485 | |
fac7fa16 JMC |
486 | if (!BANK_USED(bank)) |
487 | pm_runtime_get_sync(bank->dev); | |
8d4c277e | 488 | |
4b25408f TL |
489 | #ifdef CONFIG_ARCH_OMAP1 |
490 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 491 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
492 | #endif |
493 | ||
494 | if (!gpio) | |
ede4d7a5 | 495 | gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 | 496 | |
e5c56ed3 | 497 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 498 | return -EINVAL; |
e5c56ed3 | 499 | |
9ea14d8c TKD |
500 | if (!bank->regs->leveldetect0 && |
501 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
502 | return -EINVAL; |
503 | ||
a6472533 | 504 | spin_lock_irqsave(&bank->lock, flags); |
fac7fa16 JMC |
505 | offset = GPIO_INDEX(bank, gpio); |
506 | retval = _set_gpio_triggering(bank, offset, type); | |
507 | if (!LINE_USED(bank->mod_usage, offset)) { | |
508 | _enable_gpio_module(bank, offset); | |
509 | _set_gpio_direction(bank, offset, 1); | |
510 | } else if (!gpio_is_input(bank, 1 << offset)) { | |
511 | spin_unlock_irqrestore(&bank->lock, flags); | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
fa365e4d | 515 | bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio); |
a6472533 | 516 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
517 | |
518 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 519 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 520 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 521 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 522 | |
92105bb7 | 523 | return retval; |
5e1c5ff4 TL |
524 | } |
525 | ||
526 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
527 | { | |
92105bb7 | 528 | void __iomem *reg = bank->base; |
5e1c5ff4 | 529 | |
eef4bec7 | 530 | reg += bank->regs->irqstatus; |
661553b9 | 531 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
532 | |
533 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
534 | if (bank->regs->irqstatus2) { |
535 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 536 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 537 | } |
bedfd154 RQ |
538 | |
539 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 540 | readl_relaxed(reg); |
5e1c5ff4 TL |
541 | } |
542 | ||
543 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
544 | { | |
129fd223 | 545 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
546 | } |
547 | ||
ea6dedd7 ID |
548 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
549 | { | |
550 | void __iomem *reg = bank->base; | |
99c47707 | 551 | u32 l; |
c390aad0 | 552 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 553 | |
28f3b5a0 | 554 | reg += bank->regs->irqenable; |
661553b9 | 555 | l = readl_relaxed(reg); |
28f3b5a0 | 556 | if (bank->regs->irqenable_inv) |
99c47707 ID |
557 | l = ~l; |
558 | l &= mask; | |
559 | return l; | |
ea6dedd7 ID |
560 | } |
561 | ||
28f3b5a0 | 562 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 563 | { |
92105bb7 | 564 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
565 | u32 l; |
566 | ||
28f3b5a0 KH |
567 | if (bank->regs->set_irqenable) { |
568 | reg += bank->regs->set_irqenable; | |
569 | l = gpio_mask; | |
2a900eb7 | 570 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
571 | } else { |
572 | reg += bank->regs->irqenable; | |
661553b9 | 573 | l = readl_relaxed(reg); |
28f3b5a0 KH |
574 | if (bank->regs->irqenable_inv) |
575 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
576 | else |
577 | l |= gpio_mask; | |
2a900eb7 | 578 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
579 | } |
580 | ||
661553b9 | 581 | writel_relaxed(l, reg); |
28f3b5a0 KH |
582 | } |
583 | ||
584 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
585 | { | |
586 | void __iomem *reg = bank->base; | |
587 | u32 l; | |
588 | ||
589 | if (bank->regs->clr_irqenable) { | |
590 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 591 | l = gpio_mask; |
2a900eb7 | 592 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
593 | } else { |
594 | reg += bank->regs->irqenable; | |
661553b9 | 595 | l = readl_relaxed(reg); |
28f3b5a0 | 596 | if (bank->regs->irqenable_inv) |
56739a69 | 597 | l |= gpio_mask; |
92105bb7 | 598 | else |
28f3b5a0 | 599 | l &= ~gpio_mask; |
2a900eb7 | 600 | bank->context.irqenable1 = l; |
5e1c5ff4 | 601 | } |
28f3b5a0 | 602 | |
661553b9 | 603 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
604 | } |
605 | ||
606 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
607 | { | |
8276536c TKD |
608 | if (enable) |
609 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
610 | else | |
611 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
5e1c5ff4 TL |
612 | } |
613 | ||
92105bb7 TL |
614 | /* |
615 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
616 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
617 | * to the target, system will wake up always on GPIO events. While | |
618 | * system is running all registered GPIO interrupts need to have wake-up | |
619 | * enabled. When system is suspended, only selected GPIO interrupts need | |
620 | * to have wake-up enabled. | |
621 | */ | |
622 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
623 | { | |
f64ad1a0 KH |
624 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
625 | unsigned long flags; | |
a6472533 | 626 | |
f64ad1a0 | 627 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 628 | dev_err(bank->dev, |
f64ad1a0 | 629 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
630 | return -EINVAL; |
631 | } | |
f64ad1a0 KH |
632 | |
633 | spin_lock_irqsave(&bank->lock, flags); | |
634 | if (enable) | |
0aa27273 | 635 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 636 | else |
0aa27273 | 637 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 638 | |
661553b9 | 639 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
640 | spin_unlock_irqrestore(&bank->lock, flags); |
641 | ||
642 | return 0; | |
92105bb7 TL |
643 | } |
644 | ||
4196dd6b TL |
645 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
646 | { | |
129fd223 | 647 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
648 | _set_gpio_irqenable(bank, gpio, 0); |
649 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 650 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
c9c55d92 | 651 | _clear_gpio_debounce(bank, gpio); |
4196dd6b TL |
652 | } |
653 | ||
92105bb7 | 654 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 655 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 656 | { |
fb655f57 | 657 | struct gpio_bank *bank = _irq_data_get_bank(d); |
ede4d7a5 | 658 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
92105bb7 | 659 | |
25db711d | 660 | return _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
661 | } |
662 | ||
3ff164e1 | 663 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 664 | { |
3ff164e1 | 665 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 666 | unsigned long flags; |
52e31344 | 667 | |
55b93c32 TKD |
668 | /* |
669 | * If this is the first gpio_request for the bank, | |
670 | * enable the bank module. | |
671 | */ | |
fa365e4d | 672 | if (!BANK_USED(bank)) |
55b93c32 | 673 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 674 | |
55b93c32 | 675 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 676 | /* Set trigger to none. You need to enable the desired trigger with |
fac7fa16 JMC |
677 | * request_irq() or set_irq_type(). Only do this if the IRQ line has |
678 | * not already been requested. | |
4196dd6b | 679 | */ |
fac7fa16 JMC |
680 | if (!LINE_USED(bank->irq_usage, offset)) { |
681 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
682 | _enable_gpio_module(bank, offset); | |
5e1c5ff4 | 683 | } |
c8eef65a | 684 | bank->mod_usage |= 1 << offset; |
a6472533 | 685 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
686 | |
687 | return 0; | |
688 | } | |
689 | ||
3ff164e1 | 690 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 691 | { |
3ff164e1 | 692 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 693 | unsigned long flags; |
5e1c5ff4 | 694 | |
a6472533 | 695 | spin_lock_irqsave(&bank->lock, flags); |
c8eef65a | 696 | bank->mod_usage &= ~(1 << offset); |
fac7fa16 | 697 | _disable_gpio_module(bank, offset); |
3ff164e1 | 698 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 699 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
700 | |
701 | /* | |
702 | * If this is the last gpio to be freed in the bank, | |
703 | * disable the bank module. | |
704 | */ | |
fa365e4d | 705 | if (!BANK_USED(bank)) |
55b93c32 | 706 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
707 | } |
708 | ||
709 | /* | |
710 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
711 | * avoid missing GPIO interrupts for other lines in the bank. | |
712 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
713 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
714 | * If we wait to unmask individual GPIO lines in the bank after the | |
715 | * line's interrupt handler has been run, we may miss some nested | |
716 | * interrupts. | |
717 | */ | |
10dd5ce2 | 718 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 719 | { |
92105bb7 | 720 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 721 | u32 isr; |
3513cdec | 722 | unsigned int bit; |
5e1c5ff4 | 723 | struct gpio_bank *bank; |
ea6dedd7 | 724 | int unmasked = 0; |
fb655f57 JMC |
725 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
726 | struct gpio_chip *chip = irq_get_handler_data(irq); | |
5e1c5ff4 | 727 | |
fb655f57 | 728 | chained_irq_enter(irqchip, desc); |
5e1c5ff4 | 729 | |
fb655f57 | 730 | bank = container_of(chip, struct gpio_bank, chip); |
eef4bec7 | 731 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 732 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
733 | |
734 | if (WARN_ON(!isr_reg)) | |
735 | goto exit; | |
736 | ||
e83507b7 | 737 | while (1) { |
6e60e79a | 738 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 739 | u32 enabled; |
6e60e79a | 740 | |
ea6dedd7 | 741 | enabled = _get_gpio_irqbank_mask(bank); |
661553b9 | 742 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 743 | |
9ea14d8c | 744 | if (bank->level_mask) |
b144ff6f | 745 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
746 | |
747 | /* clear edge sensitive interrupts before handler(s) are | |
748 | called so that we don't miss any interrupt occurred while | |
749 | executing them */ | |
28f3b5a0 | 750 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 751 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 752 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
753 | |
754 | /* if there is only edge sensitive GPIO pin interrupts | |
755 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
756 | if (!level_mask && !unmasked) { |
757 | unmasked = 1; | |
fb655f57 | 758 | chained_irq_exit(irqchip, desc); |
ea6dedd7 | 759 | } |
92105bb7 TL |
760 | |
761 | if (!isr) | |
762 | break; | |
763 | ||
3513cdec JH |
764 | while (isr) { |
765 | bit = __ffs(isr); | |
766 | isr &= ~(1 << bit); | |
25db711d | 767 | |
4318f36b CM |
768 | /* |
769 | * Some chips can't respond to both rising and falling | |
770 | * at the same time. If this irq was requested with | |
771 | * both flags, we need to flip the ICR data for the IRQ | |
772 | * to respond to the IRQ for the opposite direction. | |
773 | * This will be indicated in the bank toggle_mask. | |
774 | */ | |
3513cdec JH |
775 | if (bank->toggle_mask & (1 << bit)) |
776 | _toggle_gpio_edge_triggering(bank, bit); | |
4318f36b | 777 | |
fb655f57 JMC |
778 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
779 | bit)); | |
92105bb7 | 780 | } |
1a8bfa1e | 781 | } |
ea6dedd7 ID |
782 | /* if bank has any level sensitive GPIO pin interrupt |
783 | configured, we must unmask the bank interrupt only after | |
784 | handler(s) are executed in order to avoid spurious bank | |
785 | interrupt */ | |
b1cc4c55 | 786 | exit: |
ea6dedd7 | 787 | if (!unmasked) |
fb655f57 | 788 | chained_irq_exit(irqchip, desc); |
55b93c32 | 789 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
790 | } |
791 | ||
e9191028 | 792 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 793 | { |
fb655f57 | 794 | struct gpio_bank *bank = _irq_data_get_bank(d); |
ede4d7a5 | 795 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 796 | unsigned long flags; |
fa365e4d | 797 | unsigned offset = GPIO_INDEX(bank, gpio); |
4196dd6b | 798 | |
85ec7b97 | 799 | spin_lock_irqsave(&bank->lock, flags); |
2f56e0a5 | 800 | gpio_unlock_as_irq(&bank->chip, offset); |
fa365e4d | 801 | bank->irq_usage &= ~(1 << offset); |
fac7fa16 | 802 | _disable_gpio_module(bank, offset); |
4196dd6b | 803 | _reset_gpio(bank, gpio); |
85ec7b97 | 804 | spin_unlock_irqrestore(&bank->lock, flags); |
fac7fa16 JMC |
805 | |
806 | /* | |
807 | * If this is the last IRQ to be freed in the bank, | |
808 | * disable the bank module. | |
809 | */ | |
810 | if (!BANK_USED(bank)) | |
811 | pm_runtime_put(bank->dev); | |
4196dd6b TL |
812 | } |
813 | ||
e9191028 | 814 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 815 | { |
fb655f57 | 816 | struct gpio_bank *bank = _irq_data_get_bank(d); |
ede4d7a5 | 817 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 TL |
818 | |
819 | _clear_gpio_irqstatus(bank, gpio); | |
820 | } | |
821 | ||
e9191028 | 822 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 823 | { |
fb655f57 | 824 | struct gpio_bank *bank = _irq_data_get_bank(d); |
ede4d7a5 | 825 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 826 | unsigned long flags; |
5e1c5ff4 | 827 | |
85ec7b97 | 828 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 829 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 830 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 831 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
832 | } |
833 | ||
e9191028 | 834 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 835 | { |
fb655f57 | 836 | struct gpio_bank *bank = _irq_data_get_bank(d); |
ede4d7a5 | 837 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
129fd223 | 838 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 839 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 840 | unsigned long flags; |
55b6019a | 841 | |
85ec7b97 | 842 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 843 | if (trigger) |
129fd223 | 844 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
845 | |
846 | /* For level-triggered GPIOs, the clearing must be done after | |
847 | * the HW source is cleared, thus after the handler has run */ | |
848 | if (bank->level_mask & irq_mask) { | |
849 | _set_gpio_irqenable(bank, gpio, 0); | |
850 | _clear_gpio_irqstatus(bank, gpio); | |
851 | } | |
5e1c5ff4 | 852 | |
4de8c75b | 853 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 854 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
855 | } |
856 | ||
e5c56ed3 DB |
857 | static struct irq_chip gpio_irq_chip = { |
858 | .name = "GPIO", | |
e9191028 LB |
859 | .irq_shutdown = gpio_irq_shutdown, |
860 | .irq_ack = gpio_ack_irq, | |
861 | .irq_mask = gpio_mask_irq, | |
862 | .irq_unmask = gpio_unmask_irq, | |
863 | .irq_set_type = gpio_irq_type, | |
864 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
865 | }; |
866 | ||
867 | /*---------------------------------------------------------------------*/ | |
868 | ||
79ee031f | 869 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 870 | { |
79ee031f | 871 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 872 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
873 | void __iomem *mask_reg = bank->base + |
874 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 875 | unsigned long flags; |
11a78b79 | 876 | |
a6472533 | 877 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 878 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 879 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
880 | |
881 | return 0; | |
882 | } | |
883 | ||
79ee031f | 884 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 885 | { |
79ee031f | 886 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 887 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
888 | void __iomem *mask_reg = bank->base + |
889 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 890 | unsigned long flags; |
11a78b79 | 891 | |
a6472533 | 892 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 893 | writel_relaxed(bank->context.wake_en, mask_reg); |
a6472533 | 894 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
47145210 | 899 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
900 | .suspend_noirq = omap_mpuio_suspend_noirq, |
901 | .resume_noirq = omap_mpuio_resume_noirq, | |
902 | }; | |
903 | ||
3c437ffd | 904 | /* use platform_driver for this. */ |
11a78b79 | 905 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
906 | .driver = { |
907 | .name = "mpuio", | |
79ee031f | 908 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
909 | }, |
910 | }; | |
911 | ||
912 | static struct platform_device omap_mpuio_device = { | |
913 | .name = "mpuio", | |
914 | .id = -1, | |
915 | .dev = { | |
916 | .driver = &omap_mpuio_driver.driver, | |
917 | } | |
918 | /* could list the /proc/iomem resources */ | |
919 | }; | |
920 | ||
03e128ca | 921 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 922 | { |
77640aab | 923 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 924 | |
11a78b79 DB |
925 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
926 | (void) platform_device_register(&omap_mpuio_device); | |
927 | } | |
928 | ||
e5c56ed3 | 929 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 930 | |
9370084e YY |
931 | static int gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
932 | { | |
933 | struct gpio_bank *bank; | |
934 | unsigned long flags; | |
935 | void __iomem *reg; | |
936 | int dir; | |
937 | ||
938 | bank = container_of(chip, struct gpio_bank, chip); | |
939 | reg = bank->base + bank->regs->direction; | |
940 | spin_lock_irqsave(&bank->lock, flags); | |
941 | dir = !!(readl_relaxed(reg) & BIT(offset)); | |
942 | spin_unlock_irqrestore(&bank->lock, flags); | |
943 | return dir; | |
944 | } | |
945 | ||
52e31344 DB |
946 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
947 | { | |
948 | struct gpio_bank *bank; | |
949 | unsigned long flags; | |
950 | ||
951 | bank = container_of(chip, struct gpio_bank, chip); | |
952 | spin_lock_irqsave(&bank->lock, flags); | |
953 | _set_gpio_direction(bank, offset, 1); | |
954 | spin_unlock_irqrestore(&bank->lock, flags); | |
955 | return 0; | |
956 | } | |
957 | ||
958 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | |
959 | { | |
b37c45b8 | 960 | struct gpio_bank *bank; |
b37c45b8 RQ |
961 | u32 mask; |
962 | ||
a8be8daf | 963 | bank = container_of(chip, struct gpio_bank, chip); |
7fcca715 | 964 | mask = (1 << offset); |
b37c45b8 RQ |
965 | |
966 | if (gpio_is_input(bank, mask)) | |
7fcca715 | 967 | return _get_gpio_datain(bank, offset); |
b37c45b8 | 968 | else |
7fcca715 | 969 | return _get_gpio_dataout(bank, offset); |
52e31344 DB |
970 | } |
971 | ||
972 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
973 | { | |
974 | struct gpio_bank *bank; | |
975 | unsigned long flags; | |
976 | ||
977 | bank = container_of(chip, struct gpio_bank, chip); | |
978 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 979 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
980 | _set_gpio_direction(bank, offset, 0); |
981 | spin_unlock_irqrestore(&bank->lock, flags); | |
2f56e0a5 | 982 | return 0; |
52e31344 DB |
983 | } |
984 | ||
168ef3d9 FB |
985 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
986 | unsigned debounce) | |
987 | { | |
988 | struct gpio_bank *bank; | |
989 | unsigned long flags; | |
990 | ||
991 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 992 | |
168ef3d9 FB |
993 | spin_lock_irqsave(&bank->lock, flags); |
994 | _set_gpio_debounce(bank, offset, debounce); | |
995 | spin_unlock_irqrestore(&bank->lock, flags); | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
52e31344 DB |
1000 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1001 | { | |
1002 | struct gpio_bank *bank; | |
1003 | unsigned long flags; | |
1004 | ||
1005 | bank = container_of(chip, struct gpio_bank, chip); | |
1006 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1007 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1008 | spin_unlock_irqrestore(&bank->lock, flags); |
1009 | } | |
1010 | ||
1011 | /*---------------------------------------------------------------------*/ | |
1012 | ||
9a748053 | 1013 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1014 | { |
e5ff4440 | 1015 | static bool called; |
9f7065da TL |
1016 | u32 rev; |
1017 | ||
e5ff4440 | 1018 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1019 | return; |
1020 | ||
661553b9 | 1021 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1022 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1023 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1024 | |
1025 | called = true; | |
9f7065da TL |
1026 | } |
1027 | ||
8ba55c5c DB |
1028 | /* This lock class tells lockdep that GPIO irqs are in a different |
1029 | * category than their parents, so it won't report false recursion. | |
1030 | */ | |
1031 | static struct lock_class_key gpio_lock_class; | |
1032 | ||
03e128ca | 1033 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1034 | { |
ab985f0f TKD |
1035 | void __iomem *base = bank->base; |
1036 | u32 l = 0xffffffff; | |
2fae7fbe | 1037 | |
ab985f0f TKD |
1038 | if (bank->width == 16) |
1039 | l = 0xffff; | |
1040 | ||
d0d665a8 | 1041 | if (bank->is_mpuio) { |
661553b9 | 1042 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1043 | return; |
2fae7fbe | 1044 | } |
ab985f0f TKD |
1045 | |
1046 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
6edd94db | 1047 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); |
ab985f0f | 1048 | if (bank->regs->debounce_en) |
661553b9 | 1049 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1050 | |
2dc983c5 | 1051 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1052 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1053 | /* Initialize interface clk ungated, module enabled */ |
1054 | if (bank->regs->ctrl) | |
661553b9 | 1055 | writel_relaxed(0, base + bank->regs->ctrl); |
34672013 TKD |
1056 | |
1057 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1058 | if (IS_ERR(bank->dbck)) | |
1059 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1060 | } |
1061 | ||
3836309d | 1062 | static void |
f8b46b58 KH |
1063 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1064 | unsigned int num) | |
1065 | { | |
1066 | struct irq_chip_generic *gc; | |
1067 | struct irq_chip_type *ct; | |
1068 | ||
1069 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1070 | handle_simple_irq); | |
83233749 TP |
1071 | if (!gc) { |
1072 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1073 | return; | |
1074 | } | |
1075 | ||
f8b46b58 KH |
1076 | ct = gc->chip_types; |
1077 | ||
1078 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1079 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1080 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
1081 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
1082 | |
1083 | if (bank->regs->wkup_en) | |
388f4308 | 1084 | ct->chip.irq_set_wake = gpio_wake_enable; |
f8b46b58 KH |
1085 | |
1086 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1087 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1088 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1089 | } | |
1090 | ||
6ef7f385 | 1091 | static int omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1092 | { |
77640aab | 1093 | int j; |
2fae7fbe | 1094 | static int gpio; |
fb655f57 | 1095 | int irq_base = 0; |
6ef7f385 | 1096 | int ret; |
2fae7fbe | 1097 | |
2fae7fbe VC |
1098 | /* |
1099 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1100 | * over to the generic ones | |
1101 | */ | |
1102 | bank->chip.request = omap_gpio_request; | |
1103 | bank->chip.free = omap_gpio_free; | |
9370084e | 1104 | bank->chip.get_direction = gpio_get_direction; |
2fae7fbe VC |
1105 | bank->chip.direction_input = gpio_input; |
1106 | bank->chip.get = gpio_get; | |
1107 | bank->chip.direction_output = gpio_output; | |
1108 | bank->chip.set_debounce = gpio_debounce; | |
1109 | bank->chip.set = gpio_set; | |
d0d665a8 | 1110 | if (bank->is_mpuio) { |
2fae7fbe | 1111 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1112 | if (bank->regs->wkup_en) |
1113 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1114 | bank->chip.base = OMAP_MPUIO(0); |
1115 | } else { | |
1116 | bank->chip.label = "gpio"; | |
1117 | bank->chip.base = gpio; | |
d5f46247 | 1118 | gpio += bank->width; |
2fae7fbe | 1119 | } |
d5f46247 | 1120 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1121 | |
6ef7f385 JMC |
1122 | ret = gpiochip_add(&bank->chip); |
1123 | if (ret) { | |
fb655f57 | 1124 | dev_err(bank->dev, "Could not register gpio chip %d\n", ret); |
6ef7f385 JMC |
1125 | return ret; |
1126 | } | |
2fae7fbe | 1127 | |
fb655f57 JMC |
1128 | #ifdef CONFIG_ARCH_OMAP1 |
1129 | /* | |
1130 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1131 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1132 | */ | |
1133 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1134 | if (irq_base < 0) { | |
1135 | dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); | |
1136 | return -ENODEV; | |
1137 | } | |
1138 | #endif | |
1139 | ||
1140 | ret = gpiochip_irqchip_add(&bank->chip, &gpio_irq_chip, | |
1141 | irq_base, gpio_irq_handler, | |
1142 | IRQ_TYPE_NONE); | |
1143 | ||
1144 | if (ret) { | |
1145 | dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); | |
1146 | ret = gpiochip_remove(&bank->chip); | |
1147 | return -ENODEV; | |
1148 | } | |
1149 | ||
1150 | gpiochip_set_chained_irqchip(&bank->chip, &gpio_irq_chip, | |
1151 | bank->irq, gpio_irq_handler); | |
1152 | ||
ede4d7a5 | 1153 | for (j = 0; j < bank->width; j++) { |
fb655f57 | 1154 | int irq = irq_find_mapping(bank->chip.irqdomain, j); |
ede4d7a5 | 1155 | irq_set_lockdep_class(irq, &gpio_lock_class); |
d0d665a8 | 1156 | if (bank->is_mpuio) { |
ede4d7a5 | 1157 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
fb655f57 JMC |
1158 | irq_set_chip_and_handler(irq, NULL, NULL); |
1159 | set_irq_flags(irq, 0); | |
f8b46b58 | 1160 | } |
2fae7fbe | 1161 | } |
fb655f57 JMC |
1162 | |
1163 | return 0; | |
2fae7fbe VC |
1164 | } |
1165 | ||
384ebe1c BC |
1166 | static const struct of_device_id omap_gpio_match[]; |
1167 | ||
3836309d | 1168 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1169 | { |
862ff640 | 1170 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1171 | struct device_node *node = dev->of_node; |
1172 | const struct of_device_id *match; | |
f6817a2c | 1173 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1174 | struct resource *res; |
5e1c5ff4 | 1175 | struct gpio_bank *bank; |
6ef7f385 | 1176 | int ret; |
5e1c5ff4 | 1177 | |
384ebe1c BC |
1178 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1179 | ||
e56aee18 | 1180 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1181 | if (!pdata) |
96751fcb | 1182 | return -EINVAL; |
5492fb1a | 1183 | |
086d585f | 1184 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1185 | if (!bank) { |
862ff640 | 1186 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1187 | return -ENOMEM; |
03e128ca | 1188 | } |
92105bb7 | 1189 | |
77640aab VC |
1190 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1191 | if (unlikely(!res)) { | |
862ff640 | 1192 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1193 | return -ENODEV; |
44169075 | 1194 | } |
5e1c5ff4 | 1195 | |
77640aab | 1196 | bank->irq = res->start; |
862ff640 | 1197 | bank->dev = dev; |
fb655f57 | 1198 | bank->chip.dev = dev; |
77640aab | 1199 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1200 | bank->stride = pdata->bank_stride; |
d5f46247 | 1201 | bank->width = pdata->bank_width; |
d0d665a8 | 1202 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1203 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1204 | bank->regs = pdata->regs; |
384ebe1c BC |
1205 | #ifdef CONFIG_OF_GPIO |
1206 | bank->chip.of_node = of_node_get(node); | |
1207 | #endif | |
a2797bea JH |
1208 | if (node) { |
1209 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1210 | bank->loses_context = true; | |
1211 | } else { | |
1212 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1213 | |
1214 | if (bank->loses_context) | |
1215 | bank->get_context_loss_count = | |
1216 | pdata->get_context_loss_count; | |
384ebe1c BC |
1217 | } |
1218 | ||
fa87931a KH |
1219 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1220 | bank->set_dataout = _set_gpio_dataout_reg; | |
1221 | else | |
1222 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1223 | |
77640aab | 1224 | spin_lock_init(&bank->lock); |
9f7065da | 1225 | |
77640aab VC |
1226 | /* Static mapping, never released */ |
1227 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1228 | bank->base = devm_ioremap_resource(dev, res); |
1229 | if (IS_ERR(bank->base)) { | |
fb655f57 | 1230 | irq_domain_remove(bank->chip.irqdomain); |
717f70e3 | 1231 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1232 | } |
1233 | ||
065cd795 TKD |
1234 | platform_set_drvdata(pdev, bank); |
1235 | ||
77640aab | 1236 | pm_runtime_enable(bank->dev); |
55b93c32 | 1237 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1238 | pm_runtime_get_sync(bank->dev); |
1239 | ||
d0d665a8 | 1240 | if (bank->is_mpuio) |
ab985f0f TKD |
1241 | mpuio_init(bank); |
1242 | ||
03e128ca | 1243 | omap_gpio_mod_init(bank); |
6ef7f385 JMC |
1244 | |
1245 | ret = omap_gpio_chip_init(bank); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | ||
9a748053 | 1249 | omap_gpio_show_rev(bank); |
9f7065da | 1250 | |
55b93c32 TKD |
1251 | pm_runtime_put(bank->dev); |
1252 | ||
03e128ca | 1253 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1254 | |
879fe324 | 1255 | return 0; |
5e1c5ff4 TL |
1256 | } |
1257 | ||
55b93c32 TKD |
1258 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1259 | ||
2dc983c5 | 1260 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1261 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1262 | |
2dc983c5 | 1263 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1264 | { |
2dc983c5 TKD |
1265 | struct platform_device *pdev = to_platform_device(dev); |
1266 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1267 | u32 l1 = 0, l2 = 0; | |
1268 | unsigned long flags; | |
68942edb | 1269 | u32 wake_low, wake_hi; |
8865b9b6 | 1270 | |
2dc983c5 | 1271 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1272 | |
1273 | /* | |
1274 | * Only edges can generate a wakeup event to the PRCM. | |
1275 | * | |
1276 | * Therefore, ensure any wake-up capable GPIOs have | |
1277 | * edge-detection enabled before going idle to ensure a wakeup | |
1278 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1279 | * NDA TRM 25.5.3.1) | |
1280 | * | |
1281 | * The normal values will be restored upon ->runtime_resume() | |
1282 | * by writing back the values saved in bank->context. | |
1283 | */ | |
1284 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1285 | if (wake_low) | |
661553b9 | 1286 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1287 | bank->base + bank->regs->fallingdetect); |
1288 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1289 | if (wake_hi) | |
661553b9 | 1290 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1291 | bank->base + bank->regs->risingdetect); |
1292 | ||
b3c64bc3 KH |
1293 | if (!bank->enabled_non_wakeup_gpios) |
1294 | goto update_gpio_context_count; | |
1295 | ||
2dc983c5 TKD |
1296 | if (bank->power_mode != OFF_MODE) { |
1297 | bank->power_mode = 0; | |
41d87cbd | 1298 | goto update_gpio_context_count; |
2dc983c5 TKD |
1299 | } |
1300 | /* | |
1301 | * If going to OFF, remove triggering for all | |
1302 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1303 | * generated. See OMAP2420 Errata item 1.101. | |
1304 | */ | |
661553b9 | 1305 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1306 | bank->regs->datain); |
c6f31c9e TKD |
1307 | l1 = bank->context.fallingdetect; |
1308 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1309 | |
2dc983c5 TKD |
1310 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1311 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1312 | |
661553b9 VK |
1313 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1314 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1315 | |
2dc983c5 | 1316 | bank->workaround_enabled = true; |
3f1686a9 | 1317 | |
41d87cbd | 1318 | update_gpio_context_count: |
2dc983c5 TKD |
1319 | if (bank->get_context_loss_count) |
1320 | bank->context_loss_count = | |
60a3437d TKD |
1321 | bank->get_context_loss_count(bank->dev); |
1322 | ||
72f83af9 | 1323 | _gpio_dbck_disable(bank); |
2dc983c5 | 1324 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1325 | |
2dc983c5 | 1326 | return 0; |
3ac4fa99 JY |
1327 | } |
1328 | ||
352a2d5b JH |
1329 | static void omap_gpio_init_context(struct gpio_bank *p); |
1330 | ||
2dc983c5 | 1331 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1332 | { |
2dc983c5 TKD |
1333 | struct platform_device *pdev = to_platform_device(dev); |
1334 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1335 | u32 l = 0, gen, gen0, gen1; |
1336 | unsigned long flags; | |
a2797bea | 1337 | int c; |
8865b9b6 | 1338 | |
2dc983c5 | 1339 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1340 | |
1341 | /* | |
1342 | * On the first resume during the probe, the context has not | |
1343 | * been initialised and so initialise it now. Also initialise | |
1344 | * the context loss count. | |
1345 | */ | |
1346 | if (bank->loses_context && !bank->context_valid) { | |
1347 | omap_gpio_init_context(bank); | |
1348 | ||
1349 | if (bank->get_context_loss_count) | |
1350 | bank->context_loss_count = | |
1351 | bank->get_context_loss_count(bank->dev); | |
1352 | } | |
1353 | ||
72f83af9 | 1354 | _gpio_dbck_enable(bank); |
68942edb KH |
1355 | |
1356 | /* | |
1357 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1358 | * GPIOs were set to edge trigger also in order to be able to | |
1359 | * generate a PRCM wakeup. Here we restore the | |
1360 | * pre-runtime_suspend() values for edge triggering. | |
1361 | */ | |
661553b9 | 1362 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1363 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1364 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1365 | bank->base + bank->regs->risingdetect); |
1366 | ||
a2797bea JH |
1367 | if (bank->loses_context) { |
1368 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1369 | omap_gpio_restore_context(bank); |
1370 | } else { | |
a2797bea JH |
1371 | c = bank->get_context_loss_count(bank->dev); |
1372 | if (c != bank->context_loss_count) { | |
1373 | omap_gpio_restore_context(bank); | |
1374 | } else { | |
1375 | spin_unlock_irqrestore(&bank->lock, flags); | |
1376 | return 0; | |
1377 | } | |
60a3437d | 1378 | } |
2dc983c5 | 1379 | } |
43ffcd9a | 1380 | |
1b128703 TKD |
1381 | if (!bank->workaround_enabled) { |
1382 | spin_unlock_irqrestore(&bank->lock, flags); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
661553b9 | 1386 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1387 | |
2dc983c5 TKD |
1388 | /* |
1389 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1390 | * state. If so, generate an IRQ by software. This is | |
1391 | * horribly racy, but it's the best we can do to work around | |
1392 | * this silicon bug. | |
1393 | */ | |
1394 | l ^= bank->saved_datain; | |
1395 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1396 | |
2dc983c5 TKD |
1397 | /* |
1398 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1399 | * configured with falling edge only; and vice versa. | |
1400 | */ | |
c6f31c9e | 1401 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1402 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1403 | |
c6f31c9e | 1404 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1405 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1406 | |
2dc983c5 | 1407 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1408 | gen = l & (~(bank->context.fallingdetect) & |
1409 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1410 | /* Consider all GPIO IRQs needed to be updated */ |
1411 | gen |= gen0 | gen1; | |
82dbb9d3 | 1412 | |
2dc983c5 TKD |
1413 | if (gen) { |
1414 | u32 old0, old1; | |
82dbb9d3 | 1415 | |
661553b9 VK |
1416 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1417 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1418 | |
4e962e89 | 1419 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1420 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1421 | bank->regs->leveldetect0); |
661553b9 | 1422 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1423 | bank->regs->leveldetect1); |
2dc983c5 | 1424 | } |
9ea14d8c | 1425 | |
4e962e89 | 1426 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1427 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1428 | bank->regs->leveldetect0); |
661553b9 | 1429 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1430 | bank->regs->leveldetect1); |
3ac4fa99 | 1431 | } |
661553b9 VK |
1432 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1433 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1434 | } |
1435 | ||
1436 | bank->workaround_enabled = false; | |
1437 | spin_unlock_irqrestore(&bank->lock, flags); | |
1438 | ||
1439 | return 0; | |
1440 | } | |
1441 | #endif /* CONFIG_PM_RUNTIME */ | |
1442 | ||
1443 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1444 | { | |
1445 | struct gpio_bank *bank; | |
1446 | ||
1447 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1448 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1449 | continue; |
1450 | ||
1451 | bank->power_mode = pwr_mode; | |
1452 | ||
2dc983c5 TKD |
1453 | pm_runtime_put_sync_suspend(bank->dev); |
1454 | } | |
1455 | } | |
1456 | ||
1457 | void omap2_gpio_resume_after_idle(void) | |
1458 | { | |
1459 | struct gpio_bank *bank; | |
1460 | ||
1461 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1462 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1463 | continue; |
1464 | ||
2dc983c5 | 1465 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1466 | } |
3ac4fa99 JY |
1467 | } |
1468 | ||
2dc983c5 | 1469 | #if defined(CONFIG_PM_RUNTIME) |
352a2d5b JH |
1470 | static void omap_gpio_init_context(struct gpio_bank *p) |
1471 | { | |
1472 | struct omap_gpio_reg_offs *regs = p->regs; | |
1473 | void __iomem *base = p->base; | |
1474 | ||
661553b9 VK |
1475 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1476 | p->context.oe = readl_relaxed(base + regs->direction); | |
1477 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1478 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1479 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1480 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1481 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1482 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1483 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1484 | |
1485 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1486 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1487 | else |
661553b9 | 1488 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1489 | |
1490 | p->context_valid = true; | |
1491 | } | |
1492 | ||
60a3437d | 1493 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1494 | { |
661553b9 | 1495 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1496 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1497 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1498 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1499 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1500 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1501 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1502 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1503 | bank->base + bank->regs->risingdetect); |
661553b9 | 1504 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1505 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1506 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1507 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1508 | bank->base + bank->regs->set_dataout); |
1509 | else | |
661553b9 | 1510 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1511 | bank->base + bank->regs->dataout); |
661553b9 | 1512 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1513 | |
ae547354 | 1514 | if (bank->dbck_enable_mask) { |
661553b9 | 1515 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1516 | bank->regs->debounce); |
661553b9 | 1517 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1518 | bank->base + bank->regs->debounce_en); |
1519 | } | |
ba805be5 | 1520 | |
661553b9 | 1521 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1522 | bank->base + bank->regs->irqenable); |
661553b9 | 1523 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1524 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1525 | } |
2dc983c5 | 1526 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 | 1527 | #else |
2dc983c5 TKD |
1528 | #define omap_gpio_runtime_suspend NULL |
1529 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1530 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1531 | #endif |
1532 | ||
55b93c32 | 1533 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1534 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1535 | NULL) | |
55b93c32 TKD |
1536 | }; |
1537 | ||
384ebe1c BC |
1538 | #if defined(CONFIG_OF) |
1539 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1540 | .revision = OMAP24XX_GPIO_REVISION, | |
1541 | .direction = OMAP24XX_GPIO_OE, | |
1542 | .datain = OMAP24XX_GPIO_DATAIN, | |
1543 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1544 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1545 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1546 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1547 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1548 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1549 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1550 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1551 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1552 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1553 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1554 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1555 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1556 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1557 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1558 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1559 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1560 | }; | |
1561 | ||
1562 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1563 | .revision = OMAP4_GPIO_REVISION, | |
1564 | .direction = OMAP4_GPIO_OE, | |
1565 | .datain = OMAP4_GPIO_DATAIN, | |
1566 | .dataout = OMAP4_GPIO_DATAOUT, | |
1567 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1568 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1569 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1570 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1571 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1572 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1573 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1574 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1575 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1576 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1577 | .ctrl = OMAP4_GPIO_CTRL, | |
1578 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1579 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1580 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1581 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1582 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1583 | }; | |
1584 | ||
e9a65bb6 | 1585 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1586 | .regs = &omap2_gpio_regs, |
1587 | .bank_width = 32, | |
1588 | .dbck_flag = false, | |
1589 | }; | |
1590 | ||
e9a65bb6 | 1591 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1592 | .regs = &omap2_gpio_regs, |
1593 | .bank_width = 32, | |
1594 | .dbck_flag = true, | |
1595 | }; | |
1596 | ||
e9a65bb6 | 1597 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1598 | .regs = &omap4_gpio_regs, |
1599 | .bank_width = 32, | |
1600 | .dbck_flag = true, | |
1601 | }; | |
1602 | ||
1603 | static const struct of_device_id omap_gpio_match[] = { | |
1604 | { | |
1605 | .compatible = "ti,omap4-gpio", | |
1606 | .data = &omap4_pdata, | |
1607 | }, | |
1608 | { | |
1609 | .compatible = "ti,omap3-gpio", | |
1610 | .data = &omap3_pdata, | |
1611 | }, | |
1612 | { | |
1613 | .compatible = "ti,omap2-gpio", | |
1614 | .data = &omap2_pdata, | |
1615 | }, | |
1616 | { }, | |
1617 | }; | |
1618 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1619 | #endif | |
1620 | ||
77640aab VC |
1621 | static struct platform_driver omap_gpio_driver = { |
1622 | .probe = omap_gpio_probe, | |
1623 | .driver = { | |
1624 | .name = "omap_gpio", | |
55b93c32 | 1625 | .pm = &gpio_pm_ops, |
384ebe1c | 1626 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1627 | }, |
1628 | }; | |
1629 | ||
5e1c5ff4 | 1630 | /* |
77640aab VC |
1631 | * gpio driver register needs to be done before |
1632 | * machine_init functions access gpio APIs. | |
1633 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1634 | */ |
77640aab | 1635 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1636 | { |
77640aab | 1637 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1638 | } |
77640aab | 1639 | postcore_initcall(omap_gpio_drv_reg); |