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gpio/omap: move bank width into struct gpio_bank
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
140455fa 37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 38 u32 suspend_wakeup;
39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
d5f46247 57 u32 width;
5e1c5ff4
TL		 58};
59
a8eb7ca0 60#ifdef CONFIG_ARCH_OMAP3
40c670f0 61struct omap3_gpio_regs {
40c670f0
RN		 62 u32 irqenable1;
63 u32 irqenable2;
64 u32 wake_en;
65 u32 ctrl;
66 u32 oe;
67 u32 leveldetect0;
68 u32 leveldetect1;
69 u32 risingdetect;
70 u32 fallingdetect;
71 u32 dataout;
5492fb1a
SMK		 72};
73
40c670f0 74static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 75#endif
76
77640aab
VC		 77/*
78 * TODO: Cleanup gpio_bank usage as it is having information
79 * related to all instances of the device
80 */
81static struct gpio_bank *gpio_bank;
44169075 82
c95d10bc
VC		 83/* TODO: Analyze removing gpio_bank_count usage from driver code */
84int gpio_bank_count;
5e1c5ff4
TL		 85
86static inline struct gpio_bank *get_gpio_bank(int gpio)
87{
6e60e79a 88 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 89 if (OMAP_GPIO_IS_MPUIO(gpio))
90 return &gpio_bank[0];
91 return &gpio_bank[1];
92 }
5e1c5ff4
TL		 93 if (cpu_is_omap16xx()) {
94 if (OMAP_GPIO_IS_MPUIO(gpio))
95 return &gpio_bank[0];
96 return &gpio_bank[1 + (gpio >> 4)];
97 }
56739a69 98 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 99 if (OMAP_GPIO_IS_MPUIO(gpio))
100 return &gpio_bank[0];
101 return &gpio_bank[1 + (gpio >> 5)];
102 }
92105bb7
TL		 103 if (cpu_is_omap24xx())
104 return &gpio_bank[gpio >> 5];
44169075 105 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 106 return &gpio_bank[gpio >> 5];
e031ab23
DB		 107 BUG();
108 return NULL;
5e1c5ff4
TL		 109}
110
111static inline int get_gpio_index(int gpio)
112{
56739a69 113 if (cpu_is_omap7xx())
5e1c5ff4 114 return gpio & 0x1f;
92105bb7
TL		 115 if (cpu_is_omap24xx())
116 return gpio & 0x1f;
44169075 117 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 118 return gpio & 0x1f;
92105bb7 119 return gpio & 0x0f;
5e1c5ff4
TL		 120}
121
122static inline int gpio_valid(int gpio)
123{
124 if (gpio < 0)
125 return -1;
d11ac979 126 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 127 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 128 return -1;
129 return 0;
130 }
6e60e79a 131 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 132 return 0;
5e1c5ff4
TL		 133 if ((cpu_is_omap16xx()) && gpio < 64)
134 return 0;
56739a69 135 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 136 return 0;
25d6f630
TL		 137 if (cpu_is_omap2420() && gpio < 128)
138 return 0;
139 if (cpu_is_omap2430() && gpio < 160)
92105bb7 140 return 0;
44169075 141 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 142 return 0;
5e1c5ff4
TL		 143 return -1;
144}
145
146static int check_gpio(int gpio)
147{
d32b20fc 148 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 149 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
150 dump_stack();
151 return -1;
152 }
153 return 0;
154}
155
156static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
157{
92105bb7 158 void __iomem *reg = bank->base;
5e1c5ff4
TL		 159 u32 l;
160
161 switch (bank->method) {
e5c56ed3 162#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 163 case METHOD_MPUIO:
5de62b86 164 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
5e1c5ff4 165 break;
e5c56ed3
DB		 166#endif
167#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 168 case METHOD_GPIO_1510:
169 reg += OMAP1510_GPIO_DIR_CONTROL;
170 break;
e5c56ed3
DB		 171#endif
172#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 173 case METHOD_GPIO_1610:
174 reg += OMAP1610_GPIO_DIRECTION;
175 break;
e5c56ed3 176#endif
b718aa81 177#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 178 case METHOD_GPIO_7XX:
179 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 180 break;
181#endif
a8eb7ca0 182#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 183 case METHOD_GPIO_24XX:
184 reg += OMAP24XX_GPIO_OE;
185 break;
78a1a6d3
SR		 186#endif
187#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 188 case METHOD_GPIO_44XX:
78a1a6d3
SR		 189 reg += OMAP4_GPIO_OE;
190 break;
e5c56ed3
DB		 191#endif
192 default:
193 WARN_ON(1);
194 return;
5e1c5ff4
TL		 195 }
196 l = __raw_readl(reg);
197 if (is_input)
198 l |= 1 << gpio;
199 else
200 l &= ~(1 << gpio);
201 __raw_writel(l, reg);
202}
203
5e1c5ff4
TL		 204static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
205{
92105bb7 206 void __iomem *reg = bank->base;
5e1c5ff4
TL		 207 u32 l = 0;
208
209 switch (bank->method) {
e5c56ed3 210#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 211 case METHOD_MPUIO:
5de62b86 212 reg += OMAP_MPUIO_OUTPUT / bank->stride;
5e1c5ff4
TL		 213 l = __raw_readl(reg);
214 if (enable)
215 l |= 1 << gpio;
216 else
217 l &= ~(1 << gpio);
218 break;
e5c56ed3
DB		 219#endif
220#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 221 case METHOD_GPIO_1510:
222 reg += OMAP1510_GPIO_DATA_OUTPUT;
223 l = __raw_readl(reg);
224 if (enable)
225 l |= 1 << gpio;
226 else
227 l &= ~(1 << gpio);
228 break;
e5c56ed3
DB		 229#endif
230#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 231 case METHOD_GPIO_1610:
232 if (enable)
233 reg += OMAP1610_GPIO_SET_DATAOUT;
234 else
235 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
236 l = 1 << gpio;
237 break;
e5c56ed3 238#endif
b718aa81 239#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 240 case METHOD_GPIO_7XX:
241 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 242 l = __raw_readl(reg);
243 if (enable)
244 l |= 1 << gpio;
245 else
246 l &= ~(1 << gpio);
247 break;
248#endif
a8eb7ca0 249#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 250 case METHOD_GPIO_24XX:
251 if (enable)
252 reg += OMAP24XX_GPIO_SETDATAOUT;
253 else
254 reg += OMAP24XX_GPIO_CLEARDATAOUT;
255 l = 1 << gpio;
256 break;
78a1a6d3
SR		 257#endif
258#ifdef CONFIG_ARCH_OMAP4
3f1686a9 259 case METHOD_GPIO_44XX:
78a1a6d3
SR		 260 if (enable)
261 reg += OMAP4_GPIO_SETDATAOUT;
262 else
263 reg += OMAP4_GPIO_CLEARDATAOUT;
264 l = 1 << gpio;
265 break;
e5c56ed3 266#endif
5e1c5ff4 267 default:
e5c56ed3 268 WARN_ON(1);
5e1c5ff4
TL		 269 return;
270 }
271 __raw_writel(l, reg);
272}
273
b37c45b8 274static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 275{
92105bb7 276 void __iomem *reg;
5e1c5ff4
TL		 277
278 if (check_gpio(gpio) < 0)
e5c56ed3 279 return -EINVAL;
5e1c5ff4
TL		 280 reg = bank->base;
281 switch (bank->method) {
e5c56ed3 282#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 283 case METHOD_MPUIO:
5de62b86 284 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
5e1c5ff4 285 break;
e5c56ed3
DB		 286#endif
287#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 288 case METHOD_GPIO_1510:
289 reg += OMAP1510_GPIO_DATA_INPUT;
290 break;
e5c56ed3
DB		 291#endif
292#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 293 case METHOD_GPIO_1610:
294 reg += OMAP1610_GPIO_DATAIN;
295 break;
e5c56ed3 296#endif
b718aa81 297#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 298 case METHOD_GPIO_7XX:
299 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 300 break;
301#endif
a8eb7ca0 302#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 303 case METHOD_GPIO_24XX:
304 reg += OMAP24XX_GPIO_DATAIN;
305 break;
78a1a6d3
SR		 306#endif
307#ifdef CONFIG_ARCH_OMAP4
3f1686a9 308 case METHOD_GPIO_44XX:
78a1a6d3
SR		 309 reg += OMAP4_GPIO_DATAIN;
310 break;
e5c56ed3 311#endif
5e1c5ff4 312 default:
e5c56ed3 313 return -EINVAL;
5e1c5ff4 314 }
92105bb7
TL		 315 return (__raw_readl(reg)
316 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 317}
318
b37c45b8
RQ		 319static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
320{
321 void __iomem *reg;
322
323 if (check_gpio(gpio) < 0)
324 return -EINVAL;
325 reg = bank->base;
326
327 switch (bank->method) {
328#ifdef CONFIG_ARCH_OMAP1
329 case METHOD_MPUIO:
5de62b86 330 reg += OMAP_MPUIO_OUTPUT / bank->stride;
b37c45b8
RQ		 331 break;
332#endif
333#ifdef CONFIG_ARCH_OMAP15XX
334 case METHOD_GPIO_1510:
335 reg += OMAP1510_GPIO_DATA_OUTPUT;
336 break;
337#endif
338#ifdef CONFIG_ARCH_OMAP16XX
339 case METHOD_GPIO_1610:
340 reg += OMAP1610_GPIO_DATAOUT;
341 break;
342#endif
b718aa81 343#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 344 case METHOD_GPIO_7XX:
345 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 346 break;
347#endif
9f096868 348#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 349 case METHOD_GPIO_24XX:
350 reg += OMAP24XX_GPIO_DATAOUT;
351 break;
9f096868
C		 352#endif
353#ifdef CONFIG_ARCH_OMAP4
354 case METHOD_GPIO_44XX:
355 reg += OMAP4_GPIO_DATAOUT;
356 break;
b37c45b8
RQ		 357#endif
358 default:
359 return -EINVAL;
360 }
361
362 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
363}
364
92105bb7
TL		 365#define MOD_REG_BIT(reg, bit_mask, set) \
366do { \
367 int l = __raw_readl(base + reg); \
368 if (set) l |= bit_mask; \
369 else l &= ~bit_mask; \
370 __raw_writel(l, base + reg); \
371} while(0)
372
168ef3d9
FB		 373/**
374 * _set_gpio_debounce - low level gpio debounce time
375 * @bank: the gpio bank we're acting upon
376 * @gpio: the gpio number on this @gpio
377 * @debounce: debounce time to use
378 *
379 * OMAP's debounce time is in 31us steps so we need
380 * to convert and round up to the closest unit.
381 */
382static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
383 unsigned debounce)
384{
385 void __iomem *reg = bank->base;
386 u32 val;
387 u32 l;
388
77640aab
VC		 389 if (!bank->dbck_flag)
390 return;
391
168ef3d9
FB		 392 if (debounce < 32)
393 debounce = 0x01;
394 else if (debounce > 7936)
395 debounce = 0xff;
396 else
397 debounce = (debounce / 0x1f) - 1;
398
399 l = 1 << get_gpio_index(gpio);
400
77640aab 401 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 402 reg += OMAP4_GPIO_DEBOUNCINGTIME;
403 else
404 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
405
406 __raw_writel(debounce, reg);
407
408 reg = bank->base;
77640aab 409 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 410 reg += OMAP4_GPIO_DEBOUNCENABLE;
411 else
412 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
413
414 val = __raw_readl(reg);
415
416 if (debounce) {
417 val |= l;
77640aab 418 clk_enable(bank->dbck);
168ef3d9
FB		 419 } else {
420 val &= ~l;
77640aab 421 clk_disable(bank->dbck);
168ef3d9 422 }
f7ec0b0b 423 bank->dbck_enable_mask = val;
168ef3d9
FB		 424
425 __raw_writel(val, reg);
426}
427
140455fa 428#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 429static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
430 int trigger)
5e1c5ff4 431{
3ac4fa99 432 void __iomem *base = bank->base;
92105bb7
TL		 433 u32 gpio_bit = 1 << gpio;
434
78a1a6d3
SR		 435 if (cpu_is_omap44xx()) {
436 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
437 trigger & IRQ_TYPE_LEVEL_LOW);
438 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
439 trigger & IRQ_TYPE_LEVEL_HIGH);
440 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
441 trigger & IRQ_TYPE_EDGE_RISING);
442 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
443 trigger & IRQ_TYPE_EDGE_FALLING);
444 } else {
445 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
446 trigger & IRQ_TYPE_LEVEL_LOW);
447 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
448 trigger & IRQ_TYPE_LEVEL_HIGH);
449 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
450 trigger & IRQ_TYPE_EDGE_RISING);
451 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
452 trigger & IRQ_TYPE_EDGE_FALLING);
453 }
3ac4fa99 454 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 455 if (cpu_is_omap44xx()) {
0622b25b
CC		 456 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
457 trigger != 0);
78a1a6d3 458 } else {
699117a6
CW		 459 /*
460 * GPIO wakeup request can only be generated on edge
461 * transitions
462 */
463 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 464 __raw_writel(1 << gpio, bank->base
5eb3bb9c 465 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 466 else
467 __raw_writel(1 << gpio, bank->base
5eb3bb9c 468 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 469 }
a118b5f3
TK		 470 }
471 /* This part needs to be executed always for OMAP34xx */
472 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 473 /*
474 * Log the edge gpio and manually trigger the IRQ
475 * after resume if the input level changes
476 * to avoid irq lost during PER RET/OFF mode
477 * Applies for omap2 non-wakeup gpio and all omap3 gpios
478 */
479 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 480 bank->enabled_non_wakeup_gpios |= gpio_bit;
481 else
482 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
483 }
5eb3bb9c 484
78a1a6d3
SR		 485 if (cpu_is_omap44xx()) {
486 bank->level_mask =
487 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
488 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
489 } else {
490 bank->level_mask =
491 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
492 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
493 }
92105bb7 494}
3ac4fa99 495#endif
92105bb7 496
9198bcd3 497#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 498/*
499 * This only applies to chips that can't do both rising and falling edge
500 * detection at once. For all other chips, this function is a noop.
501 */
502static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
503{
504 void __iomem *reg = bank->base;
505 u32 l = 0;
506
507 switch (bank->method) {
4318f36b 508 case METHOD_MPUIO:
5de62b86 509 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 510 break;
4318f36b
CM		 511#ifdef CONFIG_ARCH_OMAP15XX
512 case METHOD_GPIO_1510:
513 reg += OMAP1510_GPIO_INT_CONTROL;
514 break;
515#endif
516#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
517 case METHOD_GPIO_7XX:
518 reg += OMAP7XX_GPIO_INT_CONTROL;
519 break;
520#endif
521 default:
522 return;
523 }
524
525 l = __raw_readl(reg);
526 if ((l >> gpio) & 1)
527 l &= ~(1 << gpio);
528 else
529 l |= 1 << gpio;
530
531 __raw_writel(l, reg);
532}
9198bcd3 533#endif
4318f36b 534
92105bb7
TL		 535static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
536{
537 void __iomem *reg = bank->base;
538 u32 l = 0;
5e1c5ff4
TL		 539
540 switch (bank->method) {
e5c56ed3 541#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 542 case METHOD_MPUIO:
5de62b86 543 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 544 l = __raw_readl(reg);
29501577 545 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 546 bank->toggle_mask |= 1 << gpio;
6cab4860 547 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 548 l |= 1 << gpio;
6cab4860 549 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 550 l &= ~(1 << gpio);
92105bb7
TL		 551 else
552 goto bad;
5e1c5ff4 553 break;
e5c56ed3
DB		 554#endif
555#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 556 case METHOD_GPIO_1510:
557 reg += OMAP1510_GPIO_INT_CONTROL;
558 l = __raw_readl(reg);
29501577 559 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 560 bank->toggle_mask |= 1 << gpio;
6cab4860 561 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 562 l |= 1 << gpio;
6cab4860 563 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 564 l &= ~(1 << gpio);
92105bb7
TL		 565 else
566 goto bad;
5e1c5ff4 567 break;
e5c56ed3 568#endif
3ac4fa99 569#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 570 case METHOD_GPIO_1610:
5e1c5ff4
TL		 571 if (gpio & 0x08)
572 reg += OMAP1610_GPIO_EDGE_CTRL2;
573 else
574 reg += OMAP1610_GPIO_EDGE_CTRL1;
575 gpio &= 0x07;
576 l = __raw_readl(reg);
577 l &= ~(3 << (gpio << 1));
6cab4860 578 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 579 l |= 2 << (gpio << 1);
6cab4860 580 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 581 l |= 1 << (gpio << 1);
3ac4fa99
JY		 582 if (trigger)
583 /* Enable wake-up during idle for dynamic tick */
584 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
585 else
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 587 break;
3ac4fa99 588#endif
b718aa81 589#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 590 case METHOD_GPIO_7XX:
591 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 592 l = __raw_readl(reg);
29501577 593 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 594 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 595 if (trigger & IRQ_TYPE_EDGE_RISING)
596 l |= 1 << gpio;
597 else if (trigger & IRQ_TYPE_EDGE_FALLING)
598 l &= ~(1 << gpio);
599 else
600 goto bad;
601 break;
602#endif
140455fa 603#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 604 case METHOD_GPIO_24XX:
3f1686a9 605 case METHOD_GPIO_44XX:
3ac4fa99 606 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 607 return 0;
3ac4fa99 608#endif
5e1c5ff4 609 default:
92105bb7 610 goto bad;
5e1c5ff4 611 }
92105bb7
TL		 612 __raw_writel(l, reg);
613 return 0;
614bad:
615 return -EINVAL;
5e1c5ff4
TL		 616}
617
e9191028 618static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 619{
620 struct gpio_bank *bank;
92105bb7
TL		 621 unsigned gpio;
622 int retval;
a6472533 623 unsigned long flags;
92105bb7 624
e9191028
LB		 625 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
626 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 627 else
e9191028 628 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4
TL		 629
630 if (check_gpio(gpio) < 0)
92105bb7
TL		 631 return -EINVAL;
632
e5c56ed3 633 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 634 return -EINVAL;
e5c56ed3
DB		 635
636 /* OMAP1 allows only only edge triggering */
5492fb1a 637 if (!cpu_class_is_omap2()
e5c56ed3 638 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 639 return -EINVAL;
640
e9191028 641 bank = irq_data_get_irq_chip_data(d);
a6472533 642 spin_lock_irqsave(&bank->lock, flags);
92105bb7 643 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
a6472533 644 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 645
646 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 647 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 648 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 649 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 650
92105bb7 651 return retval;
5e1c5ff4
TL		 652}
653
654static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
655{
92105bb7 656 void __iomem *reg = bank->base;
5e1c5ff4
TL		 657
658 switch (bank->method) {
e5c56ed3 659#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 660 case METHOD_GPIO_1510:
661 reg += OMAP1510_GPIO_INT_STATUS;
662 break;
e5c56ed3
DB		 663#endif
664#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 665 case METHOD_GPIO_1610:
666 reg += OMAP1610_GPIO_IRQSTATUS1;
667 break;
e5c56ed3 668#endif
b718aa81 669#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 670 case METHOD_GPIO_7XX:
671 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 672 break;
673#endif
a8eb7ca0 674#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 675 case METHOD_GPIO_24XX:
676 reg += OMAP24XX_GPIO_IRQSTATUS1;
677 break;
78a1a6d3
SR		 678#endif
679#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 680 case METHOD_GPIO_44XX:
78a1a6d3
SR		 681 reg += OMAP4_GPIO_IRQSTATUS0;
682 break;
e5c56ed3 683#endif
5e1c5ff4 684 default:
e5c56ed3 685 WARN_ON(1);
5e1c5ff4
TL		 686 return;
687 }
688 __raw_writel(gpio_mask, reg);
bee7930f
HD		 689
690 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 691 if (cpu_is_omap24xx() || cpu_is_omap34xx())
692 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
693 else if (cpu_is_omap44xx())
694 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
695
df3c8517 696 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx())
bedfd154
RQ		 697 __raw_writel(gpio_mask, reg);
698
699 /* Flush posted write for the irq status to avoid spurious interrupts */
700 __raw_readl(reg);
5e1c5ff4
TL		 701}
702
703static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
704{
705 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
706}
707
ea6dedd7
ID		 708static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
709{
710 void __iomem *reg = bank->base;
99c47707
ID		 711 int inv = 0;
712 u32 l;
713 u32 mask;
ea6dedd7
ID		 714
715 switch (bank->method) {
e5c56ed3 716#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 717 case METHOD_MPUIO:
5de62b86 718 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707
ID		 719 mask = 0xffff;
720 inv = 1;
ea6dedd7 721 break;
e5c56ed3
DB		 722#endif
723#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 724 case METHOD_GPIO_1510:
725 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 726 mask = 0xffff;
727 inv = 1;
ea6dedd7 728 break;
e5c56ed3
DB		 729#endif
730#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 731 case METHOD_GPIO_1610:
732 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 733 mask = 0xffff;
ea6dedd7 734 break;
e5c56ed3 735#endif
b718aa81 736#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 737 case METHOD_GPIO_7XX:
738 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 739 mask = 0xffffffff;
740 inv = 1;
741 break;
742#endif
a8eb7ca0 743#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 744 case METHOD_GPIO_24XX:
745 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 746 mask = 0xffffffff;
ea6dedd7 747 break;
78a1a6d3
SR		 748#endif
749#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 750 case METHOD_GPIO_44XX:
78a1a6d3
SR		 751 reg += OMAP4_GPIO_IRQSTATUSSET0;
752 mask = 0xffffffff;
753 break;
e5c56ed3 754#endif
ea6dedd7 755 default:
e5c56ed3 756 WARN_ON(1);
ea6dedd7
ID		 757 return 0;
758 }
759
99c47707
ID		 760 l = __raw_readl(reg);
761 if (inv)
762 l = ~l;
763 l &= mask;
764 return l;
ea6dedd7
ID		 765}
766
5e1c5ff4
TL		 767static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
768{
92105bb7 769 void __iomem *reg = bank->base;
5e1c5ff4
TL		 770 u32 l;
771
772 switch (bank->method) {
e5c56ed3 773#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 774 case METHOD_MPUIO:
5de62b86 775 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 776 l = __raw_readl(reg);
777 if (enable)
778 l &= ~(gpio_mask);
779 else
780 l |= gpio_mask;
781 break;
e5c56ed3
DB		 782#endif
783#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 784 case METHOD_GPIO_1510:
785 reg += OMAP1510_GPIO_INT_MASK;
786 l = __raw_readl(reg);
787 if (enable)
788 l &= ~(gpio_mask);
789 else
790 l |= gpio_mask;
791 break;
e5c56ed3
DB		 792#endif
793#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 794 case METHOD_GPIO_1610:
795 if (enable)
796 reg += OMAP1610_GPIO_SET_IRQENABLE1;
797 else
798 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
799 l = gpio_mask;
800 break;
e5c56ed3 801#endif
b718aa81 802#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 803 case METHOD_GPIO_7XX:
804 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 805 l = __raw_readl(reg);
806 if (enable)
807 l &= ~(gpio_mask);
808 else
809 l |= gpio_mask;
810 break;
811#endif
a8eb7ca0 812#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 813 case METHOD_GPIO_24XX:
814 if (enable)
815 reg += OMAP24XX_GPIO_SETIRQENABLE1;
816 else
817 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
818 l = gpio_mask;
819 break;
78a1a6d3
SR		 820#endif
821#ifdef CONFIG_ARCH_OMAP4
3f1686a9 822 case METHOD_GPIO_44XX:
78a1a6d3
SR		 823 if (enable)
824 reg += OMAP4_GPIO_IRQSTATUSSET0;
825 else
826 reg += OMAP4_GPIO_IRQSTATUSCLR0;
827 l = gpio_mask;
828 break;
e5c56ed3 829#endif
5e1c5ff4 830 default:
e5c56ed3 831 WARN_ON(1);
5e1c5ff4
TL		 832 return;
833 }
834 __raw_writel(l, reg);
835}
836
837static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
838{
839 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
840}
841
92105bb7
TL		 842/*
843 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
844 * 1510 does not seem to have a wake-up register. If JTAG is connected
845 * to the target, system will wake up always on GPIO events. While
846 * system is running all registered GPIO interrupts need to have wake-up
847 * enabled. When system is suspended, only selected GPIO interrupts need
848 * to have wake-up enabled.
849 */
850static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
851{
4cc6420c 852 unsigned long uninitialized_var(flags);
a6472533 853
92105bb7 854 switch (bank->method) {
3ac4fa99 855#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 856 case METHOD_MPUIO:
92105bb7 857 case METHOD_GPIO_1610:
a6472533 858 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 859 if (enable)
92105bb7 860 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 861 else
92105bb7 862 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 863 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 864 return 0;
3ac4fa99 865#endif
140455fa 866#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 867 case METHOD_GPIO_24XX:
3f1686a9 868 case METHOD_GPIO_44XX:
11a78b79
DB		 869 if (bank->non_wakeup_gpios & (1 << gpio)) {
870 printk(KERN_ERR "Unable to modify wakeup on "
871 "non-wakeup GPIO%d\n",
d5f46247 872 (bank - gpio_bank) * bank->width + gpio);
11a78b79
DB		 873 return -EINVAL;
874 }
a6472533 875 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 876 if (enable)
3ac4fa99 877 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 878 else
3ac4fa99 879 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 880 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 881 return 0;
882#endif
92105bb7
TL		 883 default:
884 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
885 bank->method);
886 return -EINVAL;
887 }
888}
889
4196dd6b
TL		 890static void _reset_gpio(struct gpio_bank *bank, int gpio)
891{
892 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
893 _set_gpio_irqenable(bank, gpio, 0);
894 _clear_gpio_irqstatus(bank, gpio);
6cab4860 895 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 896}
897
92105bb7 898/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 899static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 900{
e9191028 901 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 902 struct gpio_bank *bank;
903 int retval;
904
905 if (check_gpio(gpio) < 0)
906 return -ENODEV;
e9191028 907 bank = irq_data_get_irq_chip_data(d);
92105bb7 908 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 909
910 return retval;
911}
912
3ff164e1 913static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 914{
3ff164e1 915 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 916 unsigned long flags;
52e31344 917
a6472533 918 spin_lock_irqsave(&bank->lock, flags);
92105bb7 919
4196dd6b
TL		 920 /* Set trigger to none. You need to enable the desired trigger with
921 * request_irq() or set_irq_type().
922 */
3ff164e1 923 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 924
1a8bfa1e 925#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 926 if (bank->method == METHOD_GPIO_1510) {
92105bb7 927 void __iomem *reg;
5e1c5ff4 928
92105bb7 929 /* Claim the pin for MPU */
5e1c5ff4 930 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 931 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 932 }
933#endif
058af1ea
C		 934 if (!cpu_class_is_omap1()) {
935 if (!bank->mod_usage) {
9f096868 936 void __iomem *reg = bank->base;
058af1ea 937 u32 ctrl;
9f096868
C		 938
939 if (cpu_is_omap24xx() || cpu_is_omap34xx())
940 reg += OMAP24XX_GPIO_CTRL;
941 else if (cpu_is_omap44xx())
942 reg += OMAP4_GPIO_CTRL;
943 ctrl = __raw_readl(reg);
058af1ea 944 /* Module is enabled, clocks are not gated */
9f096868
C		 945 ctrl &= 0xFFFFFFFE;
946 __raw_writel(ctrl, reg);
058af1ea
C		 947 }
948 bank->mod_usage |= 1 << offset;
949 }
a6472533 950 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 951
952 return 0;
953}
954
3ff164e1 955static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 956{
3ff164e1 957 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 958 unsigned long flags;
5e1c5ff4 959
a6472533 960 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 961#ifdef CONFIG_ARCH_OMAP16XX
962 if (bank->method == METHOD_GPIO_1610) {
963 /* Disable wake-up during idle for dynamic tick */
964 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 965 __raw_writel(1 << offset, reg);
92105bb7
TL		 966 }
967#endif
9f096868
C		 968#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
969 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 970 /* Disable wake-up during idle for dynamic tick */
971 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 972 __raw_writel(1 << offset, reg);
92105bb7 973 }
9f096868
C		 974#endif
975#ifdef CONFIG_ARCH_OMAP4
976 if (bank->method == METHOD_GPIO_44XX) {
977 /* Disable wake-up during idle for dynamic tick */
978 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
979 __raw_writel(1 << offset, reg);
980 }
92105bb7 981#endif
058af1ea
C		 982 if (!cpu_class_is_omap1()) {
983 bank->mod_usage &= ~(1 << offset);
984 if (!bank->mod_usage) {
9f096868 985 void __iomem *reg = bank->base;
058af1ea 986 u32 ctrl;
9f096868
C		 987
988 if (cpu_is_omap24xx() || cpu_is_omap34xx())
989 reg += OMAP24XX_GPIO_CTRL;
990 else if (cpu_is_omap44xx())
991 reg += OMAP4_GPIO_CTRL;
992 ctrl = __raw_readl(reg);
058af1ea
C		 993 /* Module is disabled, clocks are gated */
994 ctrl |= 1;
9f096868 995 __raw_writel(ctrl, reg);
058af1ea
C		 996 }
997 }
3ff164e1 998 _reset_gpio(bank, bank->chip.base + offset);
a6472533 999 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1000}
1001
1002/*
1003 * We need to unmask the GPIO bank interrupt as soon as possible to
1004 * avoid missing GPIO interrupts for other lines in the bank.
1005 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1006 * in the bank to avoid missing nested interrupts for a GPIO line.
1007 * If we wait to unmask individual GPIO lines in the bank after the
1008 * line's interrupt handler has been run, we may miss some nested
1009 * interrupts.
1010 */
10dd5ce2 1011static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1012{
92105bb7 1013 void __iomem *isr_reg = NULL;
5e1c5ff4 1014 u32 isr;
4318f36b 1015 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1016 struct gpio_bank *bank;
ea6dedd7
ID		 1017 u32 retrigger = 0;
1018 int unmasked = 0;
ee144182 1019 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 1020
ee144182 1021 chained_irq_enter(chip, desc);
5e1c5ff4 1022
6845664a 1023 bank = irq_get_handler_data(irq);
e5c56ed3 1024#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 1025 if (bank->method == METHOD_MPUIO)
5de62b86
TL		 1026 isr_reg = bank->base +
1027 OMAP_MPUIO_GPIO_INT / bank->stride;
e5c56ed3 1028#endif
1a8bfa1e 1029#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1030 if (bank->method == METHOD_GPIO_1510)
1031 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1032#endif
1033#if defined(CONFIG_ARCH_OMAP16XX)
1034 if (bank->method == METHOD_GPIO_1610)
1035 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1036#endif
b718aa81 1037#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1038 if (bank->method == METHOD_GPIO_7XX)
1039 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1040#endif
a8eb7ca0 1041#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1042 if (bank->method == METHOD_GPIO_24XX)
1043 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1044#endif
1045#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1046 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1047 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1048#endif
b1cc4c55
EK		 1049
1050 if (WARN_ON(!isr_reg))
1051 goto exit;
1052
92105bb7 1053 while(1) {
6e60e79a 1054 u32 isr_saved, level_mask = 0;
ea6dedd7 1055 u32 enabled;
6e60e79a 1056
ea6dedd7
ID		 1057 enabled = _get_gpio_irqbank_mask(bank);
1058 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1059
1060 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1061 isr &= 0x0000ffff;
1062
5492fb1a 1063 if (cpu_class_is_omap2()) {
b144ff6f 1064 level_mask = bank->level_mask & enabled;
ea6dedd7 1065 }
6e60e79a
TL		 1066
1067 /* clear edge sensitive interrupts before handler(s) are
1068 called so that we don't miss any interrupt occurred while
1069 executing them */
1070 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1071 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1072 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1073
1074 /* if there is only edge sensitive GPIO pin interrupts
1075 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1076 if (!level_mask && !unmasked) {
1077 unmasked = 1;
ee144182 1078 chained_irq_exit(chip, desc);
ea6dedd7 1079 }
92105bb7 1080
ea6dedd7
ID		 1081 isr |= retrigger;
1082 retrigger = 0;
92105bb7
TL		 1083 if (!isr)
1084 break;
1085
1086 gpio_irq = bank->virtual_irq_start;
1087 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1088 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1089
92105bb7
TL		 1090 if (!(isr & 1))
1091 continue;
29454dde 1092
4318f36b
CM		 1093#ifdef CONFIG_ARCH_OMAP1
1094 /*
1095 * Some chips can't respond to both rising and falling
1096 * at the same time. If this irq was requested with
1097 * both flags, we need to flip the ICR data for the IRQ
1098 * to respond to the IRQ for the opposite direction.
1099 * This will be indicated in the bank toggle_mask.
1100 */
1101 if (bank->toggle_mask & (1 << gpio_index))
1102 _toggle_gpio_edge_triggering(bank, gpio_index);
1103#endif
1104
d8aa0251 1105 generic_handle_irq(gpio_irq);
92105bb7 1106 }
1a8bfa1e 1107 }
ea6dedd7
ID		 1108 /* if bank has any level sensitive GPIO pin interrupt
1109 configured, we must unmask the bank interrupt only after
1110 handler(s) are executed in order to avoid spurious bank
1111 interrupt */
b1cc4c55 1112exit:
ea6dedd7 1113 if (!unmasked)
ee144182 1114 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 1115}
1116
e9191028 1117static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 1118{
e9191028
LB		 1119 unsigned int gpio = d->irq - IH_GPIO_BASE;
1120 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 1121 unsigned long flags;
4196dd6b 1122
85ec7b97 1123 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 1124 _reset_gpio(bank, gpio);
85ec7b97 1125 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 1126}
1127
e9191028 1128static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 1129{
e9191028
LB		 1130 unsigned int gpio = d->irq - IH_GPIO_BASE;
1131 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1132
1133 _clear_gpio_irqstatus(bank, gpio);
1134}
1135
e9191028 1136static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 1137{
e9191028
LB		 1138 unsigned int gpio = d->irq - IH_GPIO_BASE;
1139 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 1140 unsigned long flags;
5e1c5ff4 1141
85ec7b97 1142 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 1143 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1144 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
85ec7b97 1145 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1146}
1147
e9191028 1148static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 1149{
e9191028
LB		 1150 unsigned int gpio = d->irq - IH_GPIO_BASE;
1151 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
b144ff6f 1152 unsigned int irq_mask = 1 << get_gpio_index(gpio);
8c04a176 1153 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 1154 unsigned long flags;
55b6019a 1155
85ec7b97 1156 spin_lock_irqsave(&bank->lock, flags);
55b6019a
KH		 1157 if (trigger)
1158 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1159
1160 /* For level-triggered GPIOs, the clearing must be done after
1161 * the HW source is cleared, thus after the handler has run */
1162 if (bank->level_mask & irq_mask) {
1163 _set_gpio_irqenable(bank, gpio, 0);
1164 _clear_gpio_irqstatus(bank, gpio);
1165 }
5e1c5ff4 1166
4de8c75b 1167 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 1168 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1169}
1170
e5c56ed3
DB		 1171static struct irq_chip gpio_irq_chip = {
1172 .name = "GPIO",
e9191028
LB		 1173 .irq_shutdown = gpio_irq_shutdown,
1174 .irq_ack = gpio_ack_irq,
1175 .irq_mask = gpio_mask_irq,
1176 .irq_unmask = gpio_unmask_irq,
1177 .irq_set_type = gpio_irq_type,
1178 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 1179};
1180
1181/*---------------------------------------------------------------------*/
1182
1183#ifdef CONFIG_ARCH_OMAP1
1184
1185/* MPUIO uses the always-on 32k clock */
1186
e9191028 1187static void mpuio_ack_irq(struct irq_data *d)
5e1c5ff4
TL		 1188{
1189 /* The ISR is reset automatically, so do nothing here. */
1190}
1191
e9191028 1192static void mpuio_mask_irq(struct irq_data *d)
5e1c5ff4 1193{
e9191028
LB		 1194 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1195 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1196
1197 _set_gpio_irqenable(bank, gpio, 0);
1198}
1199
e9191028 1200static void mpuio_unmask_irq(struct irq_data *d)
5e1c5ff4 1201{
e9191028
LB		 1202 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1203 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1204
1205 _set_gpio_irqenable(bank, gpio, 1);
1206}
1207
e5c56ed3
DB		 1208static struct irq_chip mpuio_irq_chip = {
1209 .name = "MPUIO",
e9191028
LB		 1210 .irq_ack = mpuio_ack_irq,
1211 .irq_mask = mpuio_mask_irq,
1212 .irq_unmask = mpuio_unmask_irq,
1213 .irq_set_type = gpio_irq_type,
11a78b79
DB		 1214#ifdef CONFIG_ARCH_OMAP16XX
1215 /* REVISIT: assuming only 16xx supports MPUIO wake events */
e9191028 1216 .irq_set_wake = gpio_wake_enable,
11a78b79 1217#endif
5e1c5ff4
TL		 1218};
1219
e5c56ed3
DB		 1220
1221#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1222
11a78b79
DB		 1223
1224#ifdef CONFIG_ARCH_OMAP16XX
1225
1226#include <linux/platform_device.h>
1227
79ee031f 1228static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1229{
79ee031f 1230 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1231 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1232 void __iomem *mask_reg = bank->base +
1233 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1234 unsigned long flags;
11a78b79 1235
a6472533 1236 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1237 bank->saved_wakeup = __raw_readl(mask_reg);
1238 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1239 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1240
1241 return 0;
1242}
1243
79ee031f 1244static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1245{
79ee031f 1246 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1247 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1248 void __iomem *mask_reg = bank->base +
1249 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1250 unsigned long flags;
11a78b79 1251
a6472533 1252 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1253 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1254 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1255
1256 return 0;
1257}
1258
47145210 1259static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1260 .suspend_noirq = omap_mpuio_suspend_noirq,
1261 .resume_noirq = omap_mpuio_resume_noirq,
1262};
1263
3c437ffd 1264/* use platform_driver for this. */
11a78b79 1265static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1266 .driver = {
1267 .name = "mpuio",
79ee031f 1268 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1269 },
1270};
1271
1272static struct platform_device omap_mpuio_device = {
1273 .name = "mpuio",
1274 .id = -1,
1275 .dev = {
1276 .driver = &omap_mpuio_driver.driver,
1277 }
1278 /* could list the /proc/iomem resources */
1279};
1280
1281static inline void mpuio_init(void)
1282{
77640aab
VC		 1283 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1284 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1285
11a78b79
DB		 1286 if (platform_driver_register(&omap_mpuio_driver) == 0)
1287 (void) platform_device_register(&omap_mpuio_device);
1288}
1289
1290#else
1291static inline void mpuio_init(void) {}
1292#endif /* 16xx */
1293
e5c56ed3
DB		 1294#else
1295
1296extern struct irq_chip mpuio_irq_chip;
1297
1298#define bank_is_mpuio(bank) 0
11a78b79 1299static inline void mpuio_init(void) {}
e5c56ed3
DB		 1300
1301#endif
1302
1303/*---------------------------------------------------------------------*/
5e1c5ff4 1304
52e31344
DB		 1305/* REVISIT these are stupid implementations! replace by ones that
1306 * don't switch on METHOD_* and which mostly avoid spinlocks
1307 */
1308
1309static int gpio_input(struct gpio_chip *chip, unsigned offset)
1310{
1311 struct gpio_bank *bank;
1312 unsigned long flags;
1313
1314 bank = container_of(chip, struct gpio_bank, chip);
1315 spin_lock_irqsave(&bank->lock, flags);
1316 _set_gpio_direction(bank, offset, 1);
1317 spin_unlock_irqrestore(&bank->lock, flags);
1318 return 0;
1319}
1320
b37c45b8
RQ		 1321static int gpio_is_input(struct gpio_bank *bank, int mask)
1322{
1323 void __iomem *reg = bank->base;
1324
1325 switch (bank->method) {
1326 case METHOD_MPUIO:
5de62b86 1327 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
b37c45b8
RQ		 1328 break;
1329 case METHOD_GPIO_1510:
1330 reg += OMAP1510_GPIO_DIR_CONTROL;
1331 break;
1332 case METHOD_GPIO_1610:
1333 reg += OMAP1610_GPIO_DIRECTION;
1334 break;
7c006926
AB		 1335 case METHOD_GPIO_7XX:
1336 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1337 break;
1338 case METHOD_GPIO_24XX:
1339 reg += OMAP24XX_GPIO_OE;
1340 break;
9f096868
C		 1341 case METHOD_GPIO_44XX:
1342 reg += OMAP4_GPIO_OE;
1343 break;
1344 default:
1345 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1346 return -EINVAL;
b37c45b8
RQ		 1347 }
1348 return __raw_readl(reg) & mask;
1349}
1350
52e31344
DB		 1351static int gpio_get(struct gpio_chip *chip, unsigned offset)
1352{
b37c45b8
RQ		 1353 struct gpio_bank *bank;
1354 void __iomem *reg;
1355 int gpio;
1356 u32 mask;
1357
1358 gpio = chip->base + offset;
1359 bank = get_gpio_bank(gpio);
1360 reg = bank->base;
1361 mask = 1 << get_gpio_index(gpio);
1362
1363 if (gpio_is_input(bank, mask))
1364 return _get_gpio_datain(bank, gpio);
1365 else
1366 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1367}
1368
1369static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1370{
1371 struct gpio_bank *bank;
1372 unsigned long flags;
1373
1374 bank = container_of(chip, struct gpio_bank, chip);
1375 spin_lock_irqsave(&bank->lock, flags);
1376 _set_gpio_dataout(bank, offset, value);
1377 _set_gpio_direction(bank, offset, 0);
1378 spin_unlock_irqrestore(&bank->lock, flags);
1379 return 0;
1380}
1381
168ef3d9
FB		 1382static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1383 unsigned debounce)
1384{
1385 struct gpio_bank *bank;
1386 unsigned long flags;
1387
1388 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1389
1390 if (!bank->dbck) {
1391 bank->dbck = clk_get(bank->dev, "dbclk");
1392 if (IS_ERR(bank->dbck))
1393 dev_err(bank->dev, "Could not get gpio dbck\n");
1394 }
1395
168ef3d9
FB		 1396 spin_lock_irqsave(&bank->lock, flags);
1397 _set_gpio_debounce(bank, offset, debounce);
1398 spin_unlock_irqrestore(&bank->lock, flags);
1399
1400 return 0;
1401}
1402
52e31344
DB		 1403static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1404{
1405 struct gpio_bank *bank;
1406 unsigned long flags;
1407
1408 bank = container_of(chip, struct gpio_bank, chip);
1409 spin_lock_irqsave(&bank->lock, flags);
1410 _set_gpio_dataout(bank, offset, value);
1411 spin_unlock_irqrestore(&bank->lock, flags);
1412}
1413
a007b709
DB		 1414static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1415{
1416 struct gpio_bank *bank;
1417
1418 bank = container_of(chip, struct gpio_bank, chip);
1419 return bank->virtual_irq_start + offset;
1420}
1421
52e31344
DB		 1422/*---------------------------------------------------------------------*/
1423
9a748053 1424static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1425{
1426 u32 rev;
1427
9a748053
TL		 1428 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1429 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1430 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1431 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1432 else if (cpu_is_omap44xx())
9a748053 1433 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1434 else
1435 return;
1436
1437 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1438 (rev >> 4) & 0x0f, rev & 0x0f);
1439}
1440
8ba55c5c
DB		 1441/* This lock class tells lockdep that GPIO irqs are in a different
1442 * category than their parents, so it won't report false recursion.
1443 */
1444static struct lock_class_key gpio_lock_class;
1445
77640aab
VC		 1446static inline int init_gpio_info(struct platform_device *pdev)
1447{
1448 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1449 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1450 GFP_KERNEL);
1451 if (!gpio_bank) {
1452 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1453 return -ENOMEM;
1454 }
1455 return 0;
1456}
1457
1458/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1459static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1460{
1461 if (cpu_class_is_omap2()) {
1462 if (cpu_is_omap44xx()) {
1463 __raw_writel(0xffffffff, bank->base +
1464 OMAP4_GPIO_IRQSTATUSCLR0);
1465 __raw_writel(0x00000000, bank->base +
1466 OMAP4_GPIO_DEBOUNCENABLE);
1467 /* Initialize interface clk ungated, module enabled */
1468 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1469 } else if (cpu_is_omap34xx()) {
1470 __raw_writel(0x00000000, bank->base +
1471 OMAP24XX_GPIO_IRQENABLE1);
1472 __raw_writel(0xffffffff, bank->base +
1473 OMAP24XX_GPIO_IRQSTATUS1);
1474 __raw_writel(0x00000000, bank->base +
1475 OMAP24XX_GPIO_DEBOUNCE_EN);
1476
1477 /* Initialize interface clk ungated, module enabled */
1478 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1479 } else if (cpu_is_omap24xx()) {
1480 static const u32 non_wakeup_gpios[] = {
1481 0xe203ffc0, 0x08700040
1482 };
1483 if (id < ARRAY_SIZE(non_wakeup_gpios))
1484 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1485 }
1486 } else if (cpu_class_is_omap1()) {
1487 if (bank_is_mpuio(bank))
5de62b86
TL		 1488 __raw_writew(0xffff, bank->base +
1489 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1490 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1491 __raw_writew(0xffff, bank->base
1492 + OMAP1510_GPIO_INT_MASK);
1493 __raw_writew(0x0000, bank->base
1494 + OMAP1510_GPIO_INT_STATUS);
1495 }
1496 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1497 __raw_writew(0x0000, bank->base
1498 + OMAP1610_GPIO_IRQENABLE1);
1499 __raw_writew(0xffff, bank->base
1500 + OMAP1610_GPIO_IRQSTATUS1);
1501 __raw_writew(0x0014, bank->base
1502 + OMAP1610_GPIO_SYSCONFIG);
1503
1504 /*
1505 * Enable system clock for GPIO module.
1506 * The CAM_CLK_CTRL *is* really the right place.
1507 */
1508 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1509 ULPD_CAM_CLK_CTRL);
1510 }
1511 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1512 __raw_writel(0xffffffff, bank->base
1513 + OMAP7XX_GPIO_INT_MASK);
1514 __raw_writel(0x00000000, bank->base
1515 + OMAP7XX_GPIO_INT_STATUS);
1516 }
1517 }
1518}
1519
d52b31de 1520static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1521{
77640aab 1522 int j;
2fae7fbe
VC		 1523 static int gpio;
1524
2fae7fbe
VC		 1525 bank->mod_usage = 0;
1526 /*
1527 * REVISIT eventually switch from OMAP-specific gpio structs
1528 * over to the generic ones
1529 */
1530 bank->chip.request = omap_gpio_request;
1531 bank->chip.free = omap_gpio_free;
1532 bank->chip.direction_input = gpio_input;
1533 bank->chip.get = gpio_get;
1534 bank->chip.direction_output = gpio_output;
1535 bank->chip.set_debounce = gpio_debounce;
1536 bank->chip.set = gpio_set;
1537 bank->chip.to_irq = gpio_2irq;
1538 if (bank_is_mpuio(bank)) {
1539 bank->chip.label = "mpuio";
1540#ifdef CONFIG_ARCH_OMAP16XX
1541 bank->chip.dev = &omap_mpuio_device.dev;
1542#endif
1543 bank->chip.base = OMAP_MPUIO(0);
1544 } else {
1545 bank->chip.label = "gpio";
1546 bank->chip.base = gpio;
d5f46247 1547 gpio += bank->width;
2fae7fbe 1548 }
d5f46247 1549 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1550
1551 gpiochip_add(&bank->chip);
1552
1553 for (j = bank->virtual_irq_start;
d5f46247 1554 j < bank->virtual_irq_start + bank->width; j++) {
1475b85d 1555 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1556 irq_set_chip_data(j, bank);
2fae7fbe 1557 if (bank_is_mpuio(bank))
6845664a 1558 irq_set_chip(j, &mpuio_irq_chip);
2fae7fbe 1559 else
6845664a
TG		 1560 irq_set_chip(j, &gpio_irq_chip);
1561 irq_set_handler(j, handle_simple_irq);
2fae7fbe
VC		 1562 set_irq_flags(j, IRQF_VALID);
1563 }
6845664a
TG		 1564 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1565 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1566}
1567
77640aab 1568static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1569{
77640aab
VC		 1570 static int gpio_init_done;
1571 struct omap_gpio_platform_data *pdata;
1572 struct resource *res;
1573 int id;
5e1c5ff4
TL		 1574 struct gpio_bank *bank;
1575
77640aab
VC		 1576 if (!pdev->dev.platform_data)
1577 return -EINVAL;
5e1c5ff4 1578
77640aab 1579 pdata = pdev->dev.platform_data;
56a25641 1580
77640aab
VC		 1581 if (!gpio_init_done) {
1582 int ret;
5492fb1a 1583
77640aab
VC		 1584 ret = init_gpio_info(pdev);
1585 if (ret)
1586 return ret;
5492fb1a 1587 }
5492fb1a 1588
77640aab
VC		 1589 id = pdev->id;
1590 bank = &gpio_bank[id];
92105bb7 1591
77640aab
VC		 1592 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1593 if (unlikely(!res)) {
1594 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1595 return -ENODEV;
44169075 1596 }
5e1c5ff4 1597
77640aab
VC		 1598 bank->irq = res->start;
1599 bank->virtual_irq_start = pdata->virtual_irq_start;
1600 bank->method = pdata->bank_type;
1601 bank->dev = &pdev->dev;
1602 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1603 bank->stride = pdata->bank_stride;
d5f46247 1604 bank->width = pdata->bank_width;
9f7065da 1605
77640aab 1606 spin_lock_init(&bank->lock);
9f7065da 1607
77640aab
VC		 1608 /* Static mapping, never released */
1609 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1610 if (unlikely(!res)) {
1611 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1612 return -ENODEV;
1613 }
89db9482 1614
77640aab
VC		 1615 bank->base = ioremap(res->start, resource_size(res));
1616 if (!bank->base) {
1617 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1618 return -ENOMEM;
5e1c5ff4
TL		 1619 }
1620
77640aab
VC		 1621 pm_runtime_enable(bank->dev);
1622 pm_runtime_get_sync(bank->dev);
1623
1624 omap_gpio_mod_init(bank, id);
1625 omap_gpio_chip_init(bank);
9a748053 1626 omap_gpio_show_rev(bank);
9f7065da 1627
77640aab
VC		 1628 if (!gpio_init_done)
1629 gpio_init_done = 1;
1630
5e1c5ff4
TL		 1631 return 0;
1632}
1633
140455fa 1634#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1635static int omap_gpio_suspend(void)
92105bb7
TL		 1636{
1637 int i;
1638
5492fb1a 1639 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1640 return 0;
1641
1642 for (i = 0; i < gpio_bank_count; i++) {
1643 struct gpio_bank *bank = &gpio_bank[i];
1644 void __iomem *wake_status;
1645 void __iomem *wake_clear;
1646 void __iomem *wake_set;
a6472533 1647 unsigned long flags;
92105bb7
TL		 1648
1649 switch (bank->method) {
e5c56ed3 1650#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1651 case METHOD_GPIO_1610:
1652 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1653 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1654 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1655 break;
e5c56ed3 1656#endif
a8eb7ca0 1657#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1658 case METHOD_GPIO_24XX:
723fdb78 1659 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1660 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1661 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1662 break;
78a1a6d3
SR		 1663#endif
1664#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1665 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1666 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1667 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1668 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1669 break;
e5c56ed3 1670#endif
92105bb7
TL		 1671 default:
1672 continue;
1673 }
1674
a6472533 1675 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1676 bank->saved_wakeup = __raw_readl(wake_status);
1677 __raw_writel(0xffffffff, wake_clear);
1678 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1679 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1680 }
1681
1682 return 0;
1683}
1684
3c437ffd 1685static void omap_gpio_resume(void)
92105bb7
TL		 1686{
1687 int i;
1688
723fdb78 1689 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1690 return;
92105bb7
TL		 1691
1692 for (i = 0; i < gpio_bank_count; i++) {
1693 struct gpio_bank *bank = &gpio_bank[i];
1694 void __iomem *wake_clear;
1695 void __iomem *wake_set;
a6472533 1696 unsigned long flags;
92105bb7
TL		 1697
1698 switch (bank->method) {
e5c56ed3 1699#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1700 case METHOD_GPIO_1610:
1701 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1702 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1703 break;
e5c56ed3 1704#endif
a8eb7ca0 1705#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1706 case METHOD_GPIO_24XX:
0d9356cb
TL		 1707 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1708 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1709 break;
78a1a6d3
SR		 1710#endif
1711#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1712 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1713 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1714 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1715 break;
e5c56ed3 1716#endif
92105bb7
TL		 1717 default:
1718 continue;
1719 }
1720
a6472533 1721 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1722 __raw_writel(0xffffffff, wake_clear);
1723 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1724 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1725 }
92105bb7
TL		 1726}
1727
3c437ffd 1728static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1729 .suspend = omap_gpio_suspend,
1730 .resume = omap_gpio_resume,
1731};
1732
3ac4fa99
JY		 1733#endif
1734
140455fa 1735#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1736
1737static int workaround_enabled;
1738
72e06d08 1739void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1740{
1741 int i, c = 0;
a118b5f3 1742 int min = 0;
3ac4fa99 1743
a118b5f3
TK		 1744 if (cpu_is_omap34xx())
1745 min = 1;
43ffcd9a 1746
a118b5f3 1747 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1748 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1749 u32 l1 = 0, l2 = 0;
0aed0435 1750 int j;
3ac4fa99 1751
0aed0435 1752 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1753 clk_disable(bank->dbck);
1754
72e06d08 1755 if (!off_mode)
43ffcd9a
KH		 1756 continue;
1757
1758 /* If going to OFF, remove triggering for all
1759 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1760 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1761 if (!(bank->enabled_non_wakeup_gpios))
1762 continue;
3f1686a9
TL		 1763
1764 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1765 bank->saved_datain = __raw_readl(bank->base +
1766 OMAP24XX_GPIO_DATAIN);
1767 l1 = __raw_readl(bank->base +
1768 OMAP24XX_GPIO_FALLINGDETECT);
1769 l2 = __raw_readl(bank->base +
1770 OMAP24XX_GPIO_RISINGDETECT);
1771 }
1772
1773 if (cpu_is_omap44xx()) {
1774 bank->saved_datain = __raw_readl(bank->base +
1775 OMAP4_GPIO_DATAIN);
1776 l1 = __raw_readl(bank->base +
1777 OMAP4_GPIO_FALLINGDETECT);
1778 l2 = __raw_readl(bank->base +
1779 OMAP4_GPIO_RISINGDETECT);
1780 }
1781
3ac4fa99
JY		 1782 bank->saved_fallingdetect = l1;
1783 bank->saved_risingdetect = l2;
1784 l1 &= ~bank->enabled_non_wakeup_gpios;
1785 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1786
1787 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1788 __raw_writel(l1, bank->base +
1789 OMAP24XX_GPIO_FALLINGDETECT);
1790 __raw_writel(l2, bank->base +
1791 OMAP24XX_GPIO_RISINGDETECT);
1792 }
1793
1794 if (cpu_is_omap44xx()) {
1795 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1796 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1797 }
1798
3ac4fa99
JY		 1799 c++;
1800 }
1801 if (!c) {
1802 workaround_enabled = 0;
1803 return;
1804 }
1805 workaround_enabled = 1;
1806}
1807
43ffcd9a 1808void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1809{
1810 int i;
a118b5f3 1811 int min = 0;
3ac4fa99 1812
a118b5f3
TK		 1813 if (cpu_is_omap34xx())
1814 min = 1;
1815 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1816 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1817 u32 l = 0, gen, gen0, gen1;
0aed0435 1818 int j;
3ac4fa99 1819
0aed0435 1820 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1821 clk_enable(bank->dbck);
1822
43ffcd9a
KH		 1823 if (!workaround_enabled)
1824 continue;
1825
3ac4fa99
JY		 1826 if (!(bank->enabled_non_wakeup_gpios))
1827 continue;
3f1686a9
TL		 1828
1829 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1830 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1831 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1832 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1833 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1834 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1835 }
1836
1837 if (cpu_is_omap44xx()) {
1838 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1839 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1840 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1841 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1842 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1843 }
1844
3ac4fa99
JY		 1845 /* Check if any of the non-wakeup interrupt GPIOs have changed
1846 * state. If so, generate an IRQ by software. This is
1847 * horribly racy, but it's the best we can do to work around
1848 * this silicon bug. */
3ac4fa99 1849 l ^= bank->saved_datain;
a118b5f3 1850 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1851
1852 /*
1853 * No need to generate IRQs for the rising edge for gpio IRQs
1854 * configured with falling edge only; and vice versa.
1855 */
1856 gen0 = l & bank->saved_fallingdetect;
1857 gen0 &= bank->saved_datain;
1858
1859 gen1 = l & bank->saved_risingdetect;
1860 gen1 &= ~(bank->saved_datain);
1861
1862 /* FIXME: Consider GPIO IRQs with level detections properly! */
1863 gen = l & (~(bank->saved_fallingdetect) &
1864 ~(bank->saved_risingdetect));
1865 /* Consider all GPIO IRQs needed to be updated */
1866 gen |= gen0 | gen1;
1867
1868 if (gen) {
3ac4fa99 1869 u32 old0, old1;
3f1686a9 1870
f00d6497 1871 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1872 old0 = __raw_readl(bank->base +
1873 OMAP24XX_GPIO_LEVELDETECT0);
1874 old1 = __raw_readl(bank->base +
1875 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1876 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1877 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1878 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1879 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1880 __raw_writel(old0, bank->base +
3f1686a9 1881 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1882 __raw_writel(old1, bank->base +
3f1686a9
TL		 1883 OMAP24XX_GPIO_LEVELDETECT1);
1884 }
1885
1886 if (cpu_is_omap44xx()) {
1887 old0 = __raw_readl(bank->base +
78a1a6d3 1888 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1889 old1 = __raw_readl(bank->base +
78a1a6d3 1890 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1891 __raw_writel(old0 | l, bank->base +
78a1a6d3 1892 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1893 __raw_writel(old1 | l, bank->base +
78a1a6d3 1894 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1895 __raw_writel(old0, bank->base +
78a1a6d3 1896 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1897 __raw_writel(old1, bank->base +
78a1a6d3 1898 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1899 }
3ac4fa99
JY		 1900 }
1901 }
1902
1903}
1904
92105bb7
TL		 1905#endif
1906
a8eb7ca0 1907#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1908/* save the registers of bank 2-6 */
1909void omap_gpio_save_context(void)
1910{
1911 int i;
1912
1913 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1914 for (i = 1; i < gpio_bank_count; i++) {
1915 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1916 gpio_context[i].irqenable1 =
1917 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1918 gpio_context[i].irqenable2 =
1919 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1920 gpio_context[i].wake_en =
1921 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1922 gpio_context[i].ctrl =
1923 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1924 gpio_context[i].oe =
1925 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1926 gpio_context[i].leveldetect0 =
1927 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1928 gpio_context[i].leveldetect1 =
1929 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1930 gpio_context[i].risingdetect =
1931 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1932 gpio_context[i].fallingdetect =
1933 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1934 gpio_context[i].dataout =
1935 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1936 }
1937}
1938
1939/* restore the required registers of bank 2-6 */
1940void omap_gpio_restore_context(void)
1941{
1942 int i;
1943
1944 for (i = 1; i < gpio_bank_count; i++) {
1945 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1946 __raw_writel(gpio_context[i].irqenable1,
1947 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1948 __raw_writel(gpio_context[i].irqenable2,
1949 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1950 __raw_writel(gpio_context[i].wake_en,
1951 bank->base + OMAP24XX_GPIO_WAKE_EN);
1952 __raw_writel(gpio_context[i].ctrl,
1953 bank->base + OMAP24XX_GPIO_CTRL);
1954 __raw_writel(gpio_context[i].oe,
1955 bank->base + OMAP24XX_GPIO_OE);
1956 __raw_writel(gpio_context[i].leveldetect0,
1957 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1958 __raw_writel(gpio_context[i].leveldetect1,
1959 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1960 __raw_writel(gpio_context[i].risingdetect,
1961 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1962 __raw_writel(gpio_context[i].fallingdetect,
1963 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1964 __raw_writel(gpio_context[i].dataout,
1965 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1966 }
1967}
1968#endif
1969
77640aab
VC		 1970static struct platform_driver omap_gpio_driver = {
1971 .probe = omap_gpio_probe,
1972 .driver = {
1973 .name = "omap_gpio",
1974 },
1975};
1976
5e1c5ff4 1977/*
77640aab
VC		 1978 * gpio driver register needs to be done before
1979 * machine_init functions access gpio APIs.
1980 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1981 */
77640aab 1982static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1983{
77640aab 1984 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1985}
77640aab 1986postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1987
92105bb7
TL		 1988static int __init omap_gpio_sysinit(void)
1989{
11a78b79
DB		 1990 mpuio_init();
1991
140455fa 1992#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1993 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1994 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 1995#endif
1996
3c437ffd 1997 return 0;
92105bb7
TL		 1998}
1999
92105bb7 2000arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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