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gpio/omap: consolidate IRQ status handling, remove #ifdefs
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
140455fa 37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 38 u32 suspend_wakeup;
39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
d5f46247 57 u32 width;
fa87931a
KH		 58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 62};
63
a8eb7ca0 64#ifdef CONFIG_ARCH_OMAP3
40c670f0 65struct omap3_gpio_regs {
40c670f0
RN		 66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
5492fb1a
SMK		 76};
77
40c670f0 78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 79#endif
80
77640aab
VC		 81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
44169075 86
c95d10bc
VC		 87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
5e1c5ff4 89
129fd223
KH		 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92
5e1c5ff4
TL		 93static inline int gpio_valid(int gpio)
94{
95 if (gpio < 0)
96 return -1;
d11ac979 97 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 98 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 99 return -1;
100 return 0;
101 }
6e60e79a 102 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 103 return 0;
5e1c5ff4
TL		 104 if ((cpu_is_omap16xx()) && gpio < 64)
105 return 0;
56739a69 106 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 107 return 0;
25d6f630
TL		 108 if (cpu_is_omap2420() && gpio < 128)
109 return 0;
110 if (cpu_is_omap2430() && gpio < 160)
92105bb7 111 return 0;
44169075 112 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 113 return 0;
5e1c5ff4
TL		 114 return -1;
115}
116
117static int check_gpio(int gpio)
118{
d32b20fc 119 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 120 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
121 dump_stack();
122 return -1;
123 }
124 return 0;
125}
126
127static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
128{
92105bb7 129 void __iomem *reg = bank->base;
5e1c5ff4
TL		 130 u32 l;
131
fa87931a 132 reg += bank->regs->direction;
5e1c5ff4
TL		 133 l = __raw_readl(reg);
134 if (is_input)
135 l |= 1 << gpio;
136 else
137 l &= ~(1 << gpio);
138 __raw_writel(l, reg);
139}
140
fa87931a
KH		 141
142/* set data out value using dedicate set/clear register */
143static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 144{
92105bb7 145 void __iomem *reg = bank->base;
fa87931a 146 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 147
fa87931a
KH		 148 if (enable)
149 reg += bank->regs->set_dataout;
150 else
151 reg += bank->regs->clr_dataout;
152
153 __raw_writel(l, reg);
154}
155
156/* set data out value using mask register */
157static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
158{
159 void __iomem *reg = bank->base + bank->regs->dataout;
160 u32 gpio_bit = GPIO_BIT(bank, gpio);
161 u32 l;
162
163 l = __raw_readl(reg);
164 if (enable)
165 l |= gpio_bit;
166 else
167 l &= ~gpio_bit;
5e1c5ff4
TL		 168 __raw_writel(l, reg);
169}
170
b37c45b8 171static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 172{
fa87931a 173 void __iomem *reg = bank->base + bank->regs->datain;
5e1c5ff4
TL		 174
175 if (check_gpio(gpio) < 0)
e5c56ed3 176 return -EINVAL;
fa87931a
KH		 177
178 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
5e1c5ff4
TL		 179}
180
b37c45b8
RQ		 181static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
182{
fa87931a 183 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8
RQ		 184
185 if (check_gpio(gpio) < 0)
186 return -EINVAL;
b37c45b8 187
129fd223 188 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
b37c45b8
RQ		 189}
190
92105bb7
TL		 191#define MOD_REG_BIT(reg, bit_mask, set) \
192do { \
193 int l = __raw_readl(base + reg); \
194 if (set) l |= bit_mask; \
195 else l &= ~bit_mask; \
196 __raw_writel(l, base + reg); \
197} while(0)
198
168ef3d9
FB		 199/**
200 * _set_gpio_debounce - low level gpio debounce time
201 * @bank: the gpio bank we're acting upon
202 * @gpio: the gpio number on this @gpio
203 * @debounce: debounce time to use
204 *
205 * OMAP's debounce time is in 31us steps so we need
206 * to convert and round up to the closest unit.
207 */
208static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
209 unsigned debounce)
210{
211 void __iomem *reg = bank->base;
212 u32 val;
213 u32 l;
214
77640aab
VC		 215 if (!bank->dbck_flag)
216 return;
217
168ef3d9
FB		 218 if (debounce < 32)
219 debounce = 0x01;
220 else if (debounce > 7936)
221 debounce = 0xff;
222 else
223 debounce = (debounce / 0x1f) - 1;
224
129fd223 225 l = GPIO_BIT(bank, gpio);
168ef3d9 226
77640aab 227 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 228 reg += OMAP4_GPIO_DEBOUNCINGTIME;
229 else
230 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
231
232 __raw_writel(debounce, reg);
233
234 reg = bank->base;
77640aab 235 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 236 reg += OMAP4_GPIO_DEBOUNCENABLE;
237 else
238 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
239
240 val = __raw_readl(reg);
241
242 if (debounce) {
243 val |= l;
77640aab 244 clk_enable(bank->dbck);
168ef3d9
FB		 245 } else {
246 val &= ~l;
77640aab 247 clk_disable(bank->dbck);
168ef3d9 248 }
f7ec0b0b 249 bank->dbck_enable_mask = val;
168ef3d9
FB		 250
251 __raw_writel(val, reg);
252}
253
140455fa 254#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 255static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
256 int trigger)
5e1c5ff4 257{
3ac4fa99 258 void __iomem *base = bank->base;
92105bb7
TL		 259 u32 gpio_bit = 1 << gpio;
260
78a1a6d3
SR		 261 if (cpu_is_omap44xx()) {
262 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
263 trigger & IRQ_TYPE_LEVEL_LOW);
264 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
265 trigger & IRQ_TYPE_LEVEL_HIGH);
266 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
267 trigger & IRQ_TYPE_EDGE_RISING);
268 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
269 trigger & IRQ_TYPE_EDGE_FALLING);
270 } else {
271 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
272 trigger & IRQ_TYPE_LEVEL_LOW);
273 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
274 trigger & IRQ_TYPE_LEVEL_HIGH);
275 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
276 trigger & IRQ_TYPE_EDGE_RISING);
277 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
278 trigger & IRQ_TYPE_EDGE_FALLING);
279 }
3ac4fa99 280 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 281 if (cpu_is_omap44xx()) {
0622b25b
CC		 282 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
283 trigger != 0);
78a1a6d3 284 } else {
699117a6
CW		 285 /*
286 * GPIO wakeup request can only be generated on edge
287 * transitions
288 */
289 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 290 __raw_writel(1 << gpio, bank->base
5eb3bb9c 291 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 292 else
293 __raw_writel(1 << gpio, bank->base
5eb3bb9c 294 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 295 }
a118b5f3
TK		 296 }
297 /* This part needs to be executed always for OMAP34xx */
298 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 299 /*
300 * Log the edge gpio and manually trigger the IRQ
301 * after resume if the input level changes
302 * to avoid irq lost during PER RET/OFF mode
303 * Applies for omap2 non-wakeup gpio and all omap3 gpios
304 */
305 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 306 bank->enabled_non_wakeup_gpios |= gpio_bit;
307 else
308 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
309 }
5eb3bb9c 310
78a1a6d3
SR		 311 if (cpu_is_omap44xx()) {
312 bank->level_mask =
313 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
314 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
315 } else {
316 bank->level_mask =
317 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
318 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
319 }
92105bb7 320}
3ac4fa99 321#endif
92105bb7 322
9198bcd3 323#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 324/*
325 * This only applies to chips that can't do both rising and falling edge
326 * detection at once. For all other chips, this function is a noop.
327 */
328static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
329{
330 void __iomem *reg = bank->base;
331 u32 l = 0;
332
333 switch (bank->method) {
4318f36b 334 case METHOD_MPUIO:
5de62b86 335 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 336 break;
4318f36b
CM		 337#ifdef CONFIG_ARCH_OMAP15XX
338 case METHOD_GPIO_1510:
339 reg += OMAP1510_GPIO_INT_CONTROL;
340 break;
341#endif
342#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
343 case METHOD_GPIO_7XX:
344 reg += OMAP7XX_GPIO_INT_CONTROL;
345 break;
346#endif
347 default:
348 return;
349 }
350
351 l = __raw_readl(reg);
352 if ((l >> gpio) & 1)
353 l &= ~(1 << gpio);
354 else
355 l |= 1 << gpio;
356
357 __raw_writel(l, reg);
358}
9198bcd3 359#endif
4318f36b 360
92105bb7
TL		 361static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
362{
363 void __iomem *reg = bank->base;
364 u32 l = 0;
5e1c5ff4
TL		 365
366 switch (bank->method) {
e5c56ed3 367#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 368 case METHOD_MPUIO:
5de62b86 369 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 370 l = __raw_readl(reg);
29501577 371 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 372 bank->toggle_mask |= 1 << gpio;
6cab4860 373 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 374 l |= 1 << gpio;
6cab4860 375 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 376 l &= ~(1 << gpio);
92105bb7
TL		 377 else
378 goto bad;
5e1c5ff4 379 break;
e5c56ed3
DB		 380#endif
381#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 382 case METHOD_GPIO_1510:
383 reg += OMAP1510_GPIO_INT_CONTROL;
384 l = __raw_readl(reg);
29501577 385 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 386 bank->toggle_mask |= 1 << gpio;
6cab4860 387 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 388 l |= 1 << gpio;
6cab4860 389 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 390 l &= ~(1 << gpio);
92105bb7
TL		 391 else
392 goto bad;
5e1c5ff4 393 break;
e5c56ed3 394#endif
3ac4fa99 395#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 396 case METHOD_GPIO_1610:
5e1c5ff4
TL		 397 if (gpio & 0x08)
398 reg += OMAP1610_GPIO_EDGE_CTRL2;
399 else
400 reg += OMAP1610_GPIO_EDGE_CTRL1;
401 gpio &= 0x07;
402 l = __raw_readl(reg);
403 l &= ~(3 << (gpio << 1));
6cab4860 404 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 405 l |= 2 << (gpio << 1);
6cab4860 406 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 407 l |= 1 << (gpio << 1);
3ac4fa99
JY		 408 if (trigger)
409 /* Enable wake-up during idle for dynamic tick */
410 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
411 else
412 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 413 break;
3ac4fa99 414#endif
b718aa81 415#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 416 case METHOD_GPIO_7XX:
417 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 418 l = __raw_readl(reg);
29501577 419 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 420 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 421 if (trigger & IRQ_TYPE_EDGE_RISING)
422 l |= 1 << gpio;
423 else if (trigger & IRQ_TYPE_EDGE_FALLING)
424 l &= ~(1 << gpio);
425 else
426 goto bad;
427 break;
428#endif
140455fa 429#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 430 case METHOD_GPIO_24XX:
3f1686a9 431 case METHOD_GPIO_44XX:
3ac4fa99 432 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 433 return 0;
3ac4fa99 434#endif
5e1c5ff4 435 default:
92105bb7 436 goto bad;
5e1c5ff4 437 }
92105bb7
TL		 438 __raw_writel(l, reg);
439 return 0;
440bad:
441 return -EINVAL;
5e1c5ff4
TL		 442}
443
e9191028 444static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 445{
446 struct gpio_bank *bank;
92105bb7
TL		 447 unsigned gpio;
448 int retval;
a6472533 449 unsigned long flags;
92105bb7 450
e9191028
LB		 451 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
452 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 453 else
e9191028 454 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4
TL		 455
456 if (check_gpio(gpio) < 0)
92105bb7
TL		 457 return -EINVAL;
458
e5c56ed3 459 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 460 return -EINVAL;
e5c56ed3
DB		 461
462 /* OMAP1 allows only only edge triggering */
5492fb1a 463 if (!cpu_class_is_omap2()
e5c56ed3 464 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 465 return -EINVAL;
466
e9191028 467 bank = irq_data_get_irq_chip_data(d);
a6472533 468 spin_lock_irqsave(&bank->lock, flags);
129fd223 469 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 470 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 471
472 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 473 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 474 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 475 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 476
92105bb7 477 return retval;
5e1c5ff4
TL		 478}
479
480static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
481{
92105bb7 482 void __iomem *reg = bank->base;
5e1c5ff4 483
eef4bec7 484 reg += bank->regs->irqstatus;
5e1c5ff4 485 __raw_writel(gpio_mask, reg);
bee7930f
HD		 486
487 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 488 if (bank->regs->irqstatus2) {
489 reg = bank->base + bank->regs->irqstatus2;
bedfd154 490 __raw_writel(gpio_mask, reg);
eef4bec7 491 }
bedfd154
RQ		 492
493 /* Flush posted write for the irq status to avoid spurious interrupts */
494 __raw_readl(reg);
5e1c5ff4
TL		 495}
496
497static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
498{
129fd223 499 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 500}
501
ea6dedd7
ID		 502static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
503{
504 void __iomem *reg = bank->base;
99c47707
ID		 505 int inv = 0;
506 u32 l;
c390aad0 507 u32 mask = (1 << bank->width) - 1;
ea6dedd7
ID		 508
509 switch (bank->method) {
e5c56ed3 510#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 511 case METHOD_MPUIO:
5de62b86 512 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707 513 inv = 1;
ea6dedd7 514 break;
e5c56ed3
DB		 515#endif
516#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 517 case METHOD_GPIO_1510:
518 reg += OMAP1510_GPIO_INT_MASK;
99c47707 519 inv = 1;
ea6dedd7 520 break;
e5c56ed3
DB		 521#endif
522#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 523 case METHOD_GPIO_1610:
524 reg += OMAP1610_GPIO_IRQENABLE1;
525 break;
e5c56ed3 526#endif
b718aa81 527#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 528 case METHOD_GPIO_7XX:
529 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 530 inv = 1;
531 break;
532#endif
a8eb7ca0 533#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 534 case METHOD_GPIO_24XX:
535 reg += OMAP24XX_GPIO_IRQENABLE1;
536 break;
78a1a6d3
SR		 537#endif
538#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 539 case METHOD_GPIO_44XX:
78a1a6d3 540 reg += OMAP4_GPIO_IRQSTATUSSET0;
78a1a6d3 541 break;
e5c56ed3 542#endif
ea6dedd7 543 default:
e5c56ed3 544 WARN_ON(1);
ea6dedd7
ID		 545 return 0;
546 }
547
99c47707
ID		 548 l = __raw_readl(reg);
549 if (inv)
550 l = ~l;
551 l &= mask;
552 return l;
ea6dedd7
ID		 553}
554
5e1c5ff4
TL		 555static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
556{
92105bb7 557 void __iomem *reg = bank->base;
5e1c5ff4
TL		 558 u32 l;
559
560 switch (bank->method) {
e5c56ed3 561#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 562 case METHOD_MPUIO:
5de62b86 563 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 564 l = __raw_readl(reg);
565 if (enable)
566 l &= ~(gpio_mask);
567 else
568 l |= gpio_mask;
569 break;
e5c56ed3
DB		 570#endif
571#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 572 case METHOD_GPIO_1510:
573 reg += OMAP1510_GPIO_INT_MASK;
574 l = __raw_readl(reg);
575 if (enable)
576 l &= ~(gpio_mask);
577 else
578 l |= gpio_mask;
579 break;
e5c56ed3
DB		 580#endif
581#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 582 case METHOD_GPIO_1610:
583 if (enable)
584 reg += OMAP1610_GPIO_SET_IRQENABLE1;
585 else
586 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
587 l = gpio_mask;
588 break;
e5c56ed3 589#endif
b718aa81 590#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 591 case METHOD_GPIO_7XX:
592 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 593 l = __raw_readl(reg);
594 if (enable)
595 l &= ~(gpio_mask);
596 else
597 l |= gpio_mask;
598 break;
599#endif
a8eb7ca0 600#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 601 case METHOD_GPIO_24XX:
602 if (enable)
603 reg += OMAP24XX_GPIO_SETIRQENABLE1;
604 else
605 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
606 l = gpio_mask;
607 break;
78a1a6d3
SR		 608#endif
609#ifdef CONFIG_ARCH_OMAP4
3f1686a9 610 case METHOD_GPIO_44XX:
78a1a6d3
SR		 611 if (enable)
612 reg += OMAP4_GPIO_IRQSTATUSSET0;
613 else
614 reg += OMAP4_GPIO_IRQSTATUSCLR0;
615 l = gpio_mask;
616 break;
e5c56ed3 617#endif
5e1c5ff4 618 default:
e5c56ed3 619 WARN_ON(1);
5e1c5ff4
TL		 620 return;
621 }
622 __raw_writel(l, reg);
623}
624
625static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
626{
129fd223 627 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio), enable);
5e1c5ff4
TL		 628}
629
92105bb7
TL		 630/*
631 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
632 * 1510 does not seem to have a wake-up register. If JTAG is connected
633 * to the target, system will wake up always on GPIO events. While
634 * system is running all registered GPIO interrupts need to have wake-up
635 * enabled. When system is suspended, only selected GPIO interrupts need
636 * to have wake-up enabled.
637 */
638static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
639{
4cc6420c 640 unsigned long uninitialized_var(flags);
a6472533 641
92105bb7 642 switch (bank->method) {
3ac4fa99 643#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 644 case METHOD_MPUIO:
92105bb7 645 case METHOD_GPIO_1610:
a6472533 646 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 647 if (enable)
92105bb7 648 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 649 else
92105bb7 650 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 651 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 652 return 0;
3ac4fa99 653#endif
140455fa 654#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 655 case METHOD_GPIO_24XX:
3f1686a9 656 case METHOD_GPIO_44XX:
11a78b79
DB		 657 if (bank->non_wakeup_gpios & (1 << gpio)) {
658 printk(KERN_ERR "Unable to modify wakeup on "
659 "non-wakeup GPIO%d\n",
d5f46247 660 (bank - gpio_bank) * bank->width + gpio);
11a78b79
DB		 661 return -EINVAL;
662 }
a6472533 663 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 664 if (enable)
3ac4fa99 665 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 666 else
3ac4fa99 667 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 668 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 669 return 0;
670#endif
92105bb7
TL		 671 default:
672 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
673 bank->method);
674 return -EINVAL;
675 }
676}
677
4196dd6b
TL		 678static void _reset_gpio(struct gpio_bank *bank, int gpio)
679{
129fd223 680 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 681 _set_gpio_irqenable(bank, gpio, 0);
682 _clear_gpio_irqstatus(bank, gpio);
129fd223 683 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 684}
685
92105bb7 686/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 687static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 688{
e9191028 689 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 690 struct gpio_bank *bank;
691 int retval;
692
693 if (check_gpio(gpio) < 0)
694 return -ENODEV;
e9191028 695 bank = irq_data_get_irq_chip_data(d);
129fd223 696 retval = _set_gpio_wakeup(bank, GPIO_INDEX(bank, gpio), enable);
92105bb7
TL		 697
698 return retval;
699}
700
3ff164e1 701static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 702{
3ff164e1 703 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 704 unsigned long flags;
52e31344 705
a6472533 706 spin_lock_irqsave(&bank->lock, flags);
92105bb7 707
4196dd6b
TL		 708 /* Set trigger to none. You need to enable the desired trigger with
709 * request_irq() or set_irq_type().
710 */
3ff164e1 711 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 712
1a8bfa1e 713#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 714 if (bank->method == METHOD_GPIO_1510) {
92105bb7 715 void __iomem *reg;
5e1c5ff4 716
92105bb7 717 /* Claim the pin for MPU */
5e1c5ff4 718 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 719 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 720 }
721#endif
058af1ea
C		 722 if (!cpu_class_is_omap1()) {
723 if (!bank->mod_usage) {
9f096868 724 void __iomem *reg = bank->base;
058af1ea 725 u32 ctrl;
9f096868
C		 726
727 if (cpu_is_omap24xx() || cpu_is_omap34xx())
728 reg += OMAP24XX_GPIO_CTRL;
729 else if (cpu_is_omap44xx())
730 reg += OMAP4_GPIO_CTRL;
731 ctrl = __raw_readl(reg);
058af1ea 732 /* Module is enabled, clocks are not gated */
9f096868
C		 733 ctrl &= 0xFFFFFFFE;
734 __raw_writel(ctrl, reg);
058af1ea
C		 735 }
736 bank->mod_usage |= 1 << offset;
737 }
a6472533 738 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 739
740 return 0;
741}
742
3ff164e1 743static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 744{
3ff164e1 745 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 746 unsigned long flags;
5e1c5ff4 747
a6472533 748 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 749#ifdef CONFIG_ARCH_OMAP16XX
750 if (bank->method == METHOD_GPIO_1610) {
751 /* Disable wake-up during idle for dynamic tick */
752 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 753 __raw_writel(1 << offset, reg);
92105bb7
TL		 754 }
755#endif
9f096868
C		 756#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
757 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 758 /* Disable wake-up during idle for dynamic tick */
759 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 760 __raw_writel(1 << offset, reg);
92105bb7 761 }
9f096868
C		 762#endif
763#ifdef CONFIG_ARCH_OMAP4
764 if (bank->method == METHOD_GPIO_44XX) {
765 /* Disable wake-up during idle for dynamic tick */
766 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
767 __raw_writel(1 << offset, reg);
768 }
92105bb7 769#endif
058af1ea
C		 770 if (!cpu_class_is_omap1()) {
771 bank->mod_usage &= ~(1 << offset);
772 if (!bank->mod_usage) {
9f096868 773 void __iomem *reg = bank->base;
058af1ea 774 u32 ctrl;
9f096868
C		 775
776 if (cpu_is_omap24xx() || cpu_is_omap34xx())
777 reg += OMAP24XX_GPIO_CTRL;
778 else if (cpu_is_omap44xx())
779 reg += OMAP4_GPIO_CTRL;
780 ctrl = __raw_readl(reg);
058af1ea
C		 781 /* Module is disabled, clocks are gated */
782 ctrl |= 1;
9f096868 783 __raw_writel(ctrl, reg);
058af1ea
C		 784 }
785 }
3ff164e1 786 _reset_gpio(bank, bank->chip.base + offset);
a6472533 787 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 788}
789
790/*
791 * We need to unmask the GPIO bank interrupt as soon as possible to
792 * avoid missing GPIO interrupts for other lines in the bank.
793 * Then we need to mask-read-clear-unmask the triggered GPIO lines
794 * in the bank to avoid missing nested interrupts for a GPIO line.
795 * If we wait to unmask individual GPIO lines in the bank after the
796 * line's interrupt handler has been run, we may miss some nested
797 * interrupts.
798 */
10dd5ce2 799static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 800{
92105bb7 801 void __iomem *isr_reg = NULL;
5e1c5ff4 802 u32 isr;
4318f36b 803 unsigned int gpio_irq, gpio_index;
5e1c5ff4 804 struct gpio_bank *bank;
ea6dedd7
ID		 805 u32 retrigger = 0;
806 int unmasked = 0;
ee144182 807 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 808
ee144182 809 chained_irq_enter(chip, desc);
5e1c5ff4 810
6845664a 811 bank = irq_get_handler_data(irq);
eef4bec7 812 isr_reg = bank->base + bank->regs->irqstatus;
b1cc4c55
EK		 813
814 if (WARN_ON(!isr_reg))
815 goto exit;
816
92105bb7 817 while(1) {
6e60e79a 818 u32 isr_saved, level_mask = 0;
ea6dedd7 819 u32 enabled;
6e60e79a 820
ea6dedd7
ID		 821 enabled = _get_gpio_irqbank_mask(bank);
822 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 823
824 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
825 isr &= 0x0000ffff;
826
5492fb1a 827 if (cpu_class_is_omap2()) {
b144ff6f 828 level_mask = bank->level_mask & enabled;
ea6dedd7 829 }
6e60e79a
TL		 830
831 /* clear edge sensitive interrupts before handler(s) are
832 called so that we don't miss any interrupt occurred while
833 executing them */
834 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
835 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
836 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
837
838 /* if there is only edge sensitive GPIO pin interrupts
839 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 840 if (!level_mask && !unmasked) {
841 unmasked = 1;
ee144182 842 chained_irq_exit(chip, desc);
ea6dedd7 843 }
92105bb7 844
ea6dedd7
ID		 845 isr |= retrigger;
846 retrigger = 0;
92105bb7
TL		 847 if (!isr)
848 break;
849
850 gpio_irq = bank->virtual_irq_start;
851 for (; isr != 0; isr >>= 1, gpio_irq++) {
129fd223 852 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
4318f36b 853
92105bb7
TL		 854 if (!(isr & 1))
855 continue;
29454dde 856
4318f36b
CM		 857#ifdef CONFIG_ARCH_OMAP1
858 /*
859 * Some chips can't respond to both rising and falling
860 * at the same time. If this irq was requested with
861 * both flags, we need to flip the ICR data for the IRQ
862 * to respond to the IRQ for the opposite direction.
863 * This will be indicated in the bank toggle_mask.
864 */
865 if (bank->toggle_mask & (1 << gpio_index))
866 _toggle_gpio_edge_triggering(bank, gpio_index);
867#endif
868
d8aa0251 869 generic_handle_irq(gpio_irq);
92105bb7 870 }
1a8bfa1e 871 }
ea6dedd7
ID		 872 /* if bank has any level sensitive GPIO pin interrupt
873 configured, we must unmask the bank interrupt only after
874 handler(s) are executed in order to avoid spurious bank
875 interrupt */
b1cc4c55 876exit:
ea6dedd7 877 if (!unmasked)
ee144182 878 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 879}
880
e9191028 881static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 882{
e9191028
LB		 883 unsigned int gpio = d->irq - IH_GPIO_BASE;
884 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 885 unsigned long flags;
4196dd6b 886
85ec7b97 887 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 888 _reset_gpio(bank, gpio);
85ec7b97 889 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 890}
891
e9191028 892static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 893{
e9191028
LB		 894 unsigned int gpio = d->irq - IH_GPIO_BASE;
895 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 896
897 _clear_gpio_irqstatus(bank, gpio);
898}
899
e9191028 900static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 901{
e9191028
LB		 902 unsigned int gpio = d->irq - IH_GPIO_BASE;
903 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 904 unsigned long flags;
5e1c5ff4 905
85ec7b97 906 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 907 _set_gpio_irqenable(bank, gpio, 0);
129fd223 908 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 909 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 910}
911
e9191028 912static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 913{
e9191028
LB		 914 unsigned int gpio = d->irq - IH_GPIO_BASE;
915 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
129fd223 916 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 917 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 918 unsigned long flags;
55b6019a 919
85ec7b97 920 spin_lock_irqsave(&bank->lock, flags);
55b6019a 921 if (trigger)
129fd223 922 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 923
924 /* For level-triggered GPIOs, the clearing must be done after
925 * the HW source is cleared, thus after the handler has run */
926 if (bank->level_mask & irq_mask) {
927 _set_gpio_irqenable(bank, gpio, 0);
928 _clear_gpio_irqstatus(bank, gpio);
929 }
5e1c5ff4 930
4de8c75b 931 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 932 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 933}
934
e5c56ed3
DB		 935static struct irq_chip gpio_irq_chip = {
936 .name = "GPIO",
e9191028
LB		 937 .irq_shutdown = gpio_irq_shutdown,
938 .irq_ack = gpio_ack_irq,
939 .irq_mask = gpio_mask_irq,
940 .irq_unmask = gpio_unmask_irq,
941 .irq_set_type = gpio_irq_type,
942 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 943};
944
945/*---------------------------------------------------------------------*/
946
947#ifdef CONFIG_ARCH_OMAP1
948
949/* MPUIO uses the always-on 32k clock */
950
e9191028 951static void mpuio_ack_irq(struct irq_data *d)
5e1c5ff4
TL		 952{
953 /* The ISR is reset automatically, so do nothing here. */
954}
955
e9191028 956static void mpuio_mask_irq(struct irq_data *d)
5e1c5ff4 957{
e9191028
LB		 958 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
959 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 960
961 _set_gpio_irqenable(bank, gpio, 0);
962}
963
e9191028 964static void mpuio_unmask_irq(struct irq_data *d)
5e1c5ff4 965{
e9191028
LB		 966 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
967 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 968
969 _set_gpio_irqenable(bank, gpio, 1);
970}
971
e5c56ed3
DB		 972static struct irq_chip mpuio_irq_chip = {
973 .name = "MPUIO",
e9191028
LB		 974 .irq_ack = mpuio_ack_irq,
975 .irq_mask = mpuio_mask_irq,
976 .irq_unmask = mpuio_unmask_irq,
977 .irq_set_type = gpio_irq_type,
11a78b79
DB		 978#ifdef CONFIG_ARCH_OMAP16XX
979 /* REVISIT: assuming only 16xx supports MPUIO wake events */
e9191028 980 .irq_set_wake = gpio_wake_enable,
11a78b79 981#endif
5e1c5ff4
TL		 982};
983
e5c56ed3
DB		 984
985#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
986
11a78b79
DB		 987
988#ifdef CONFIG_ARCH_OMAP16XX
989
990#include <linux/platform_device.h>
991
79ee031f 992static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 993{
79ee031f 994 struct platform_device *pdev = to_platform_device(dev);
11a78b79 995 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 996 void __iomem *mask_reg = bank->base +
997 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 998 unsigned long flags;
11a78b79 999
a6472533 1000 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1001 bank->saved_wakeup = __raw_readl(mask_reg);
1002 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1003 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1004
1005 return 0;
1006}
1007
79ee031f 1008static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1009{
79ee031f 1010 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1011 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1012 void __iomem *mask_reg = bank->base +
1013 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1014 unsigned long flags;
11a78b79 1015
a6472533 1016 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1017 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1018 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1019
1020 return 0;
1021}
1022
47145210 1023static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1024 .suspend_noirq = omap_mpuio_suspend_noirq,
1025 .resume_noirq = omap_mpuio_resume_noirq,
1026};
1027
3c437ffd 1028/* use platform_driver for this. */
11a78b79 1029static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1030 .driver = {
1031 .name = "mpuio",
79ee031f 1032 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1033 },
1034};
1035
1036static struct platform_device omap_mpuio_device = {
1037 .name = "mpuio",
1038 .id = -1,
1039 .dev = {
1040 .driver = &omap_mpuio_driver.driver,
1041 }
1042 /* could list the /proc/iomem resources */
1043};
1044
1045static inline void mpuio_init(void)
1046{
a8be8daf 1047 struct gpio_bank *bank = &gpio_bank[0];
77640aab 1048 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1049
11a78b79
DB		 1050 if (platform_driver_register(&omap_mpuio_driver) == 0)
1051 (void) platform_device_register(&omap_mpuio_device);
1052}
1053
1054#else
1055static inline void mpuio_init(void) {}
1056#endif /* 16xx */
1057
e5c56ed3
DB		 1058#else
1059
1060extern struct irq_chip mpuio_irq_chip;
1061
1062#define bank_is_mpuio(bank) 0
11a78b79 1063static inline void mpuio_init(void) {}
e5c56ed3
DB		 1064
1065#endif
1066
1067/*---------------------------------------------------------------------*/
5e1c5ff4 1068
52e31344
DB		 1069/* REVISIT these are stupid implementations! replace by ones that
1070 * don't switch on METHOD_* and which mostly avoid spinlocks
1071 */
1072
1073static int gpio_input(struct gpio_chip *chip, unsigned offset)
1074{
1075 struct gpio_bank *bank;
1076 unsigned long flags;
1077
1078 bank = container_of(chip, struct gpio_bank, chip);
1079 spin_lock_irqsave(&bank->lock, flags);
1080 _set_gpio_direction(bank, offset, 1);
1081 spin_unlock_irqrestore(&bank->lock, flags);
1082 return 0;
1083}
1084
b37c45b8
RQ		 1085static int gpio_is_input(struct gpio_bank *bank, int mask)
1086{
fa87931a 1087 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 1088
b37c45b8
RQ		 1089 return __raw_readl(reg) & mask;
1090}
1091
52e31344
DB		 1092static int gpio_get(struct gpio_chip *chip, unsigned offset)
1093{
b37c45b8
RQ		 1094 struct gpio_bank *bank;
1095 void __iomem *reg;
1096 int gpio;
1097 u32 mask;
1098
1099 gpio = chip->base + offset;
a8be8daf 1100 bank = container_of(chip, struct gpio_bank, chip);
b37c45b8 1101 reg = bank->base;
129fd223 1102 mask = GPIO_BIT(bank, gpio);
b37c45b8
RQ		 1103
1104 if (gpio_is_input(bank, mask))
1105 return _get_gpio_datain(bank, gpio);
1106 else
1107 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1108}
1109
1110static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1111{
1112 struct gpio_bank *bank;
1113 unsigned long flags;
1114
1115 bank = container_of(chip, struct gpio_bank, chip);
1116 spin_lock_irqsave(&bank->lock, flags);
fa87931a 1117 bank->set_dataout(bank, offset, value);
52e31344
DB		 1118 _set_gpio_direction(bank, offset, 0);
1119 spin_unlock_irqrestore(&bank->lock, flags);
1120 return 0;
1121}
1122
168ef3d9
FB		 1123static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1124 unsigned debounce)
1125{
1126 struct gpio_bank *bank;
1127 unsigned long flags;
1128
1129 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1130
1131 if (!bank->dbck) {
1132 bank->dbck = clk_get(bank->dev, "dbclk");
1133 if (IS_ERR(bank->dbck))
1134 dev_err(bank->dev, "Could not get gpio dbck\n");
1135 }
1136
168ef3d9
FB		 1137 spin_lock_irqsave(&bank->lock, flags);
1138 _set_gpio_debounce(bank, offset, debounce);
1139 spin_unlock_irqrestore(&bank->lock, flags);
1140
1141 return 0;
1142}
1143
52e31344
DB		 1144static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1145{
1146 struct gpio_bank *bank;
1147 unsigned long flags;
1148
1149 bank = container_of(chip, struct gpio_bank, chip);
1150 spin_lock_irqsave(&bank->lock, flags);
fa87931a 1151 bank->set_dataout(bank, offset, value);
52e31344
DB		 1152 spin_unlock_irqrestore(&bank->lock, flags);
1153}
1154
a007b709
DB		 1155static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1156{
1157 struct gpio_bank *bank;
1158
1159 bank = container_of(chip, struct gpio_bank, chip);
1160 return bank->virtual_irq_start + offset;
1161}
1162
52e31344
DB		 1163/*---------------------------------------------------------------------*/
1164
9a748053 1165static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1166{
1167 u32 rev;
1168
9a748053
TL		 1169 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1170 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1171 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1172 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1173 else if (cpu_is_omap44xx())
9a748053 1174 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1175 else
1176 return;
1177
1178 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1179 (rev >> 4) & 0x0f, rev & 0x0f);
1180}
1181
8ba55c5c
DB		 1182/* This lock class tells lockdep that GPIO irqs are in a different
1183 * category than their parents, so it won't report false recursion.
1184 */
1185static struct lock_class_key gpio_lock_class;
1186
77640aab
VC		 1187static inline int init_gpio_info(struct platform_device *pdev)
1188{
1189 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1190 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1191 GFP_KERNEL);
1192 if (!gpio_bank) {
1193 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1194 return -ENOMEM;
1195 }
1196 return 0;
1197}
1198
1199/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1200static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1201{
1202 if (cpu_class_is_omap2()) {
1203 if (cpu_is_omap44xx()) {
1204 __raw_writel(0xffffffff, bank->base +
1205 OMAP4_GPIO_IRQSTATUSCLR0);
1206 __raw_writel(0x00000000, bank->base +
1207 OMAP4_GPIO_DEBOUNCENABLE);
1208 /* Initialize interface clk ungated, module enabled */
1209 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1210 } else if (cpu_is_omap34xx()) {
1211 __raw_writel(0x00000000, bank->base +
1212 OMAP24XX_GPIO_IRQENABLE1);
1213 __raw_writel(0xffffffff, bank->base +
1214 OMAP24XX_GPIO_IRQSTATUS1);
1215 __raw_writel(0x00000000, bank->base +
1216 OMAP24XX_GPIO_DEBOUNCE_EN);
1217
1218 /* Initialize interface clk ungated, module enabled */
1219 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1220 } else if (cpu_is_omap24xx()) {
1221 static const u32 non_wakeup_gpios[] = {
1222 0xe203ffc0, 0x08700040
1223 };
1224 if (id < ARRAY_SIZE(non_wakeup_gpios))
1225 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1226 }
1227 } else if (cpu_class_is_omap1()) {
1228 if (bank_is_mpuio(bank))
5de62b86
TL		 1229 __raw_writew(0xffff, bank->base +
1230 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1231 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1232 __raw_writew(0xffff, bank->base
1233 + OMAP1510_GPIO_INT_MASK);
1234 __raw_writew(0x0000, bank->base
1235 + OMAP1510_GPIO_INT_STATUS);
1236 }
1237 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1238 __raw_writew(0x0000, bank->base
1239 + OMAP1610_GPIO_IRQENABLE1);
1240 __raw_writew(0xffff, bank->base
1241 + OMAP1610_GPIO_IRQSTATUS1);
1242 __raw_writew(0x0014, bank->base
1243 + OMAP1610_GPIO_SYSCONFIG);
1244
1245 /*
1246 * Enable system clock for GPIO module.
1247 * The CAM_CLK_CTRL *is* really the right place.
1248 */
1249 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1250 ULPD_CAM_CLK_CTRL);
1251 }
1252 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1253 __raw_writel(0xffffffff, bank->base
1254 + OMAP7XX_GPIO_INT_MASK);
1255 __raw_writel(0x00000000, bank->base
1256 + OMAP7XX_GPIO_INT_STATUS);
1257 }
1258 }
1259}
1260
d52b31de 1261static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1262{
77640aab 1263 int j;
2fae7fbe
VC		 1264 static int gpio;
1265
2fae7fbe
VC		 1266 bank->mod_usage = 0;
1267 /*
1268 * REVISIT eventually switch from OMAP-specific gpio structs
1269 * over to the generic ones
1270 */
1271 bank->chip.request = omap_gpio_request;
1272 bank->chip.free = omap_gpio_free;
1273 bank->chip.direction_input = gpio_input;
1274 bank->chip.get = gpio_get;
1275 bank->chip.direction_output = gpio_output;
1276 bank->chip.set_debounce = gpio_debounce;
1277 bank->chip.set = gpio_set;
1278 bank->chip.to_irq = gpio_2irq;
1279 if (bank_is_mpuio(bank)) {
1280 bank->chip.label = "mpuio";
1281#ifdef CONFIG_ARCH_OMAP16XX
1282 bank->chip.dev = &omap_mpuio_device.dev;
1283#endif
1284 bank->chip.base = OMAP_MPUIO(0);
1285 } else {
1286 bank->chip.label = "gpio";
1287 bank->chip.base = gpio;
d5f46247 1288 gpio += bank->width;
2fae7fbe 1289 }
d5f46247 1290 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1291
1292 gpiochip_add(&bank->chip);
1293
1294 for (j = bank->virtual_irq_start;
d5f46247 1295 j < bank->virtual_irq_start + bank->width; j++) {
1475b85d 1296 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1297 irq_set_chip_data(j, bank);
2fae7fbe 1298 if (bank_is_mpuio(bank))
6845664a 1299 irq_set_chip(j, &mpuio_irq_chip);
2fae7fbe 1300 else
6845664a
TG		 1301 irq_set_chip(j, &gpio_irq_chip);
1302 irq_set_handler(j, handle_simple_irq);
2fae7fbe
VC		 1303 set_irq_flags(j, IRQF_VALID);
1304 }
6845664a
TG		 1305 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1306 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1307}
1308
77640aab 1309static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1310{
77640aab
VC		 1311 static int gpio_init_done;
1312 struct omap_gpio_platform_data *pdata;
1313 struct resource *res;
1314 int id;
5e1c5ff4
TL		 1315 struct gpio_bank *bank;
1316
77640aab
VC		 1317 if (!pdev->dev.platform_data)
1318 return -EINVAL;
5e1c5ff4 1319
77640aab 1320 pdata = pdev->dev.platform_data;
56a25641 1321
77640aab
VC		 1322 if (!gpio_init_done) {
1323 int ret;
5492fb1a 1324
77640aab
VC		 1325 ret = init_gpio_info(pdev);
1326 if (ret)
1327 return ret;
5492fb1a 1328 }
5492fb1a 1329
77640aab
VC		 1330 id = pdev->id;
1331 bank = &gpio_bank[id];
92105bb7 1332
77640aab
VC		 1333 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1334 if (unlikely(!res)) {
1335 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1336 return -ENODEV;
44169075 1337 }
5e1c5ff4 1338
77640aab
VC		 1339 bank->irq = res->start;
1340 bank->virtual_irq_start = pdata->virtual_irq_start;
1341 bank->method = pdata->bank_type;
1342 bank->dev = &pdev->dev;
1343 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1344 bank->stride = pdata->bank_stride;
d5f46247 1345 bank->width = pdata->bank_width;
9f7065da 1346
fa87931a
KH		 1347 bank->regs = pdata->regs;
1348
1349 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1350 bank->set_dataout = _set_gpio_dataout_reg;
1351 else
1352 bank->set_dataout = _set_gpio_dataout_mask;
1353
77640aab 1354 spin_lock_init(&bank->lock);
9f7065da 1355
77640aab
VC		 1356 /* Static mapping, never released */
1357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 if (unlikely(!res)) {
1359 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1360 return -ENODEV;
1361 }
89db9482 1362
77640aab
VC		 1363 bank->base = ioremap(res->start, resource_size(res));
1364 if (!bank->base) {
1365 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1366 return -ENOMEM;
5e1c5ff4
TL		 1367 }
1368
77640aab
VC		 1369 pm_runtime_enable(bank->dev);
1370 pm_runtime_get_sync(bank->dev);
1371
1372 omap_gpio_mod_init(bank, id);
1373 omap_gpio_chip_init(bank);
9a748053 1374 omap_gpio_show_rev(bank);
9f7065da 1375
77640aab
VC		 1376 if (!gpio_init_done)
1377 gpio_init_done = 1;
1378
5e1c5ff4
TL		 1379 return 0;
1380}
1381
140455fa 1382#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1383static int omap_gpio_suspend(void)
92105bb7
TL		 1384{
1385 int i;
1386
5492fb1a 1387 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1388 return 0;
1389
1390 for (i = 0; i < gpio_bank_count; i++) {
1391 struct gpio_bank *bank = &gpio_bank[i];
1392 void __iomem *wake_status;
1393 void __iomem *wake_clear;
1394 void __iomem *wake_set;
a6472533 1395 unsigned long flags;
92105bb7
TL		 1396
1397 switch (bank->method) {
e5c56ed3 1398#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1399 case METHOD_GPIO_1610:
1400 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1401 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1402 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1403 break;
e5c56ed3 1404#endif
a8eb7ca0 1405#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1406 case METHOD_GPIO_24XX:
723fdb78 1407 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1408 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1409 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1410 break;
78a1a6d3
SR		 1411#endif
1412#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1413 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1414 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1415 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1416 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1417 break;
e5c56ed3 1418#endif
92105bb7
TL		 1419 default:
1420 continue;
1421 }
1422
a6472533 1423 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1424 bank->saved_wakeup = __raw_readl(wake_status);
1425 __raw_writel(0xffffffff, wake_clear);
1426 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1427 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1428 }
1429
1430 return 0;
1431}
1432
3c437ffd 1433static void omap_gpio_resume(void)
92105bb7
TL		 1434{
1435 int i;
1436
723fdb78 1437 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1438 return;
92105bb7
TL		 1439
1440 for (i = 0; i < gpio_bank_count; i++) {
1441 struct gpio_bank *bank = &gpio_bank[i];
1442 void __iomem *wake_clear;
1443 void __iomem *wake_set;
a6472533 1444 unsigned long flags;
92105bb7
TL		 1445
1446 switch (bank->method) {
e5c56ed3 1447#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1448 case METHOD_GPIO_1610:
1449 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1450 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1451 break;
e5c56ed3 1452#endif
a8eb7ca0 1453#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1454 case METHOD_GPIO_24XX:
0d9356cb
TL		 1455 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1456 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1457 break;
78a1a6d3
SR		 1458#endif
1459#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1460 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1461 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1462 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1463 break;
e5c56ed3 1464#endif
92105bb7
TL		 1465 default:
1466 continue;
1467 }
1468
a6472533 1469 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1470 __raw_writel(0xffffffff, wake_clear);
1471 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1472 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1473 }
92105bb7
TL		 1474}
1475
3c437ffd 1476static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1477 .suspend = omap_gpio_suspend,
1478 .resume = omap_gpio_resume,
1479};
1480
3ac4fa99
JY		 1481#endif
1482
140455fa 1483#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1484
1485static int workaround_enabled;
1486
72e06d08 1487void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1488{
1489 int i, c = 0;
a118b5f3 1490 int min = 0;
3ac4fa99 1491
a118b5f3
TK		 1492 if (cpu_is_omap34xx())
1493 min = 1;
43ffcd9a 1494
a118b5f3 1495 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1496 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1497 u32 l1 = 0, l2 = 0;
0aed0435 1498 int j;
3ac4fa99 1499
0aed0435 1500 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1501 clk_disable(bank->dbck);
1502
72e06d08 1503 if (!off_mode)
43ffcd9a
KH		 1504 continue;
1505
1506 /* If going to OFF, remove triggering for all
1507 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1508 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1509 if (!(bank->enabled_non_wakeup_gpios))
1510 continue;
3f1686a9
TL		 1511
1512 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1513 bank->saved_datain = __raw_readl(bank->base +
1514 OMAP24XX_GPIO_DATAIN);
1515 l1 = __raw_readl(bank->base +
1516 OMAP24XX_GPIO_FALLINGDETECT);
1517 l2 = __raw_readl(bank->base +
1518 OMAP24XX_GPIO_RISINGDETECT);
1519 }
1520
1521 if (cpu_is_omap44xx()) {
1522 bank->saved_datain = __raw_readl(bank->base +
1523 OMAP4_GPIO_DATAIN);
1524 l1 = __raw_readl(bank->base +
1525 OMAP4_GPIO_FALLINGDETECT);
1526 l2 = __raw_readl(bank->base +
1527 OMAP4_GPIO_RISINGDETECT);
1528 }
1529
3ac4fa99
JY		 1530 bank->saved_fallingdetect = l1;
1531 bank->saved_risingdetect = l2;
1532 l1 &= ~bank->enabled_non_wakeup_gpios;
1533 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1534
1535 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1536 __raw_writel(l1, bank->base +
1537 OMAP24XX_GPIO_FALLINGDETECT);
1538 __raw_writel(l2, bank->base +
1539 OMAP24XX_GPIO_RISINGDETECT);
1540 }
1541
1542 if (cpu_is_omap44xx()) {
1543 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1544 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1545 }
1546
3ac4fa99
JY		 1547 c++;
1548 }
1549 if (!c) {
1550 workaround_enabled = 0;
1551 return;
1552 }
1553 workaround_enabled = 1;
1554}
1555
43ffcd9a 1556void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1557{
1558 int i;
a118b5f3 1559 int min = 0;
3ac4fa99 1560
a118b5f3
TK		 1561 if (cpu_is_omap34xx())
1562 min = 1;
1563 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1564 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1565 u32 l = 0, gen, gen0, gen1;
0aed0435 1566 int j;
3ac4fa99 1567
0aed0435 1568 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1569 clk_enable(bank->dbck);
1570
43ffcd9a
KH		 1571 if (!workaround_enabled)
1572 continue;
1573
3ac4fa99
JY		 1574 if (!(bank->enabled_non_wakeup_gpios))
1575 continue;
3f1686a9
TL		 1576
1577 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1578 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1579 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1580 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1581 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1582 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1583 }
1584
1585 if (cpu_is_omap44xx()) {
1586 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1587 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1588 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1589 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1590 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1591 }
1592
3ac4fa99
JY		 1593 /* Check if any of the non-wakeup interrupt GPIOs have changed
1594 * state. If so, generate an IRQ by software. This is
1595 * horribly racy, but it's the best we can do to work around
1596 * this silicon bug. */
3ac4fa99 1597 l ^= bank->saved_datain;
a118b5f3 1598 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1599
1600 /*
1601 * No need to generate IRQs for the rising edge for gpio IRQs
1602 * configured with falling edge only; and vice versa.
1603 */
1604 gen0 = l & bank->saved_fallingdetect;
1605 gen0 &= bank->saved_datain;
1606
1607 gen1 = l & bank->saved_risingdetect;
1608 gen1 &= ~(bank->saved_datain);
1609
1610 /* FIXME: Consider GPIO IRQs with level detections properly! */
1611 gen = l & (~(bank->saved_fallingdetect) &
1612 ~(bank->saved_risingdetect));
1613 /* Consider all GPIO IRQs needed to be updated */
1614 gen |= gen0 | gen1;
1615
1616 if (gen) {
3ac4fa99 1617 u32 old0, old1;
3f1686a9 1618
f00d6497 1619 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1620 old0 = __raw_readl(bank->base +
1621 OMAP24XX_GPIO_LEVELDETECT0);
1622 old1 = __raw_readl(bank->base +
1623 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1624 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1625 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1626 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1627 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1628 __raw_writel(old0, bank->base +
3f1686a9 1629 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1630 __raw_writel(old1, bank->base +
3f1686a9
TL		 1631 OMAP24XX_GPIO_LEVELDETECT1);
1632 }
1633
1634 if (cpu_is_omap44xx()) {
1635 old0 = __raw_readl(bank->base +
78a1a6d3 1636 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1637 old1 = __raw_readl(bank->base +
78a1a6d3 1638 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1639 __raw_writel(old0 | l, bank->base +
78a1a6d3 1640 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1641 __raw_writel(old1 | l, bank->base +
78a1a6d3 1642 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1643 __raw_writel(old0, bank->base +
78a1a6d3 1644 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1645 __raw_writel(old1, bank->base +
78a1a6d3 1646 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1647 }
3ac4fa99
JY		 1648 }
1649 }
1650
1651}
1652
92105bb7
TL		 1653#endif
1654
a8eb7ca0 1655#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1656/* save the registers of bank 2-6 */
1657void omap_gpio_save_context(void)
1658{
1659 int i;
1660
1661 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1662 for (i = 1; i < gpio_bank_count; i++) {
1663 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1664 gpio_context[i].irqenable1 =
1665 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1666 gpio_context[i].irqenable2 =
1667 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1668 gpio_context[i].wake_en =
1669 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1670 gpio_context[i].ctrl =
1671 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1672 gpio_context[i].oe =
1673 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1674 gpio_context[i].leveldetect0 =
1675 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1676 gpio_context[i].leveldetect1 =
1677 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1678 gpio_context[i].risingdetect =
1679 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1680 gpio_context[i].fallingdetect =
1681 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1682 gpio_context[i].dataout =
1683 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1684 }
1685}
1686
1687/* restore the required registers of bank 2-6 */
1688void omap_gpio_restore_context(void)
1689{
1690 int i;
1691
1692 for (i = 1; i < gpio_bank_count; i++) {
1693 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1694 __raw_writel(gpio_context[i].irqenable1,
1695 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1696 __raw_writel(gpio_context[i].irqenable2,
1697 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1698 __raw_writel(gpio_context[i].wake_en,
1699 bank->base + OMAP24XX_GPIO_WAKE_EN);
1700 __raw_writel(gpio_context[i].ctrl,
1701 bank->base + OMAP24XX_GPIO_CTRL);
1702 __raw_writel(gpio_context[i].oe,
1703 bank->base + OMAP24XX_GPIO_OE);
1704 __raw_writel(gpio_context[i].leveldetect0,
1705 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1706 __raw_writel(gpio_context[i].leveldetect1,
1707 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1708 __raw_writel(gpio_context[i].risingdetect,
1709 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1710 __raw_writel(gpio_context[i].fallingdetect,
1711 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1712 __raw_writel(gpio_context[i].dataout,
1713 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1714 }
1715}
1716#endif
1717
77640aab
VC		 1718static struct platform_driver omap_gpio_driver = {
1719 .probe = omap_gpio_probe,
1720 .driver = {
1721 .name = "omap_gpio",
1722 },
1723};
1724
5e1c5ff4 1725/*
77640aab
VC		 1726 * gpio driver register needs to be done before
1727 * machine_init functions access gpio APIs.
1728 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1729 */
77640aab 1730static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1731{
77640aab 1732 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1733}
77640aab 1734postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1735
92105bb7
TL		 1736static int __init omap_gpio_sysinit(void)
1737{
11a78b79
DB		 1738 mpuio_init();
1739
140455fa 1740#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1741 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1742 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 1743#endif
1744
3c437ffd 1745 return 0;
92105bb7
TL		 1746}
1747
92105bb7 1748arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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