Commit | Line | Data |
---|---|---|
9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1965d303 NC |
21 | #ifdef CONFIG_OF_GPIO |
22 | #include <linux/of_platform.h> | |
1965d303 | 23 | #endif |
9e60fdcf | 24 | |
33226ffd HZ |
25 | #define PCA953X_INPUT 0 |
26 | #define PCA953X_OUTPUT 1 | |
27 | #define PCA953X_INVERT 2 | |
28 | #define PCA953X_DIRECTION 3 | |
29 | ||
ae79c190 AS |
30 | #define REG_ADDR_AI 0x80 |
31 | ||
33226ffd HZ |
32 | #define PCA957X_IN 0 |
33 | #define PCA957X_INVRT 1 | |
34 | #define PCA957X_BKEN 2 | |
35 | #define PCA957X_PUPD 3 | |
36 | #define PCA957X_CFG 4 | |
37 | #define PCA957X_OUT 5 | |
38 | #define PCA957X_MSK 6 | |
39 | #define PCA957X_INTS 7 | |
40 | ||
41 | #define PCA_GPIO_MASK 0x00FF | |
42 | #define PCA_INT 0x0100 | |
43 | #define PCA953X_TYPE 0x1000 | |
44 | #define PCA957X_TYPE 0x2000 | |
89ea8bbe | 45 | |
3760f736 | 46 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 47 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
48 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
49 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
50 | { "pca9536", 4 | PCA953X_TYPE, }, | |
51 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
52 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
53 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
54 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
55 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
56 | { "pca9556", 8 | PCA953X_TYPE, }, | |
57 | { "pca9557", 8 | PCA953X_TYPE, }, | |
58 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
59 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 60 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd HZ |
61 | |
62 | { "max7310", 8 | PCA953X_TYPE, }, | |
63 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
65 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
66 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
67 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
68 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 69 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 70 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 71 | { } |
f5e8ff48 | 72 | }; |
3760f736 | 73 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 74 | |
f5f0b7aa GC |
75 | #define MAX_BANK 5 |
76 | #define BANK_SZ 8 | |
77 | ||
78 | #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ) | |
79 | ||
f3dc3630 | 80 | struct pca953x_chip { |
9e60fdcf | 81 | unsigned gpio_start; |
f5f0b7aa GC |
82 | u8 reg_output[MAX_BANK]; |
83 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 84 | struct mutex i2c_lock; |
9e60fdcf | 85 | |
89ea8bbe MZ |
86 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
87 | struct mutex irq_lock; | |
f5f0b7aa GC |
88 | u8 irq_mask[MAX_BANK]; |
89 | u8 irq_stat[MAX_BANK]; | |
90 | u8 irq_trig_raise[MAX_BANK]; | |
91 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
92 | #endif |
93 | ||
9e60fdcf | 94 | struct i2c_client *client; |
95 | struct gpio_chip gpio_chip; | |
62154991 | 96 | const char *const *names; |
33226ffd | 97 | int chip_type; |
9e60fdcf | 98 | }; |
99 | ||
7bcbce55 LW |
100 | static inline struct pca953x_chip *to_pca(struct gpio_chip *gc) |
101 | { | |
102 | return container_of(gc, struct pca953x_chip, gpio_chip); | |
103 | } | |
104 | ||
f5f0b7aa GC |
105 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
106 | int off) | |
107 | { | |
108 | int ret; | |
109 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
110 | int offset = off / BANK_SZ; | |
111 | ||
112 | ret = i2c_smbus_read_byte_data(chip->client, | |
113 | (reg << bank_shift) + offset); | |
114 | *val = ret; | |
115 | ||
116 | if (ret < 0) { | |
117 | dev_err(&chip->client->dev, "failed reading register\n"); | |
118 | return ret; | |
119 | } | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
124 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
125 | int off) | |
126 | { | |
127 | int ret = 0; | |
128 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
129 | int offset = off / BANK_SZ; | |
130 | ||
131 | ret = i2c_smbus_write_byte_data(chip->client, | |
132 | (reg << bank_shift) + offset, val); | |
133 | ||
134 | if (ret < 0) { | |
135 | dev_err(&chip->client->dev, "failed writing register\n"); | |
136 | return ret; | |
137 | } | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
9e60fdcf | 143 | { |
33226ffd | 144 | int ret = 0; |
f5e8ff48 GL |
145 | |
146 | if (chip->gpio_chip.ngpio <= 8) | |
f5f0b7aa GC |
147 | ret = i2c_smbus_write_byte_data(chip->client, reg, *val); |
148 | else if (chip->gpio_chip.ngpio >= 24) { | |
149 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
96b70641 | 150 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
f5f0b7aa GC |
151 | (reg << bank_shift) | REG_ADDR_AI, |
152 | NBANK(chip), val); | |
50e44430 | 153 | } else { |
33226ffd HZ |
154 | switch (chip->chip_type) { |
155 | case PCA953X_TYPE: | |
156 | ret = i2c_smbus_write_word_data(chip->client, | |
f5f0b7aa | 157 | reg << 1, (u16) *val); |
33226ffd HZ |
158 | break; |
159 | case PCA957X_TYPE: | |
160 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
f5f0b7aa | 161 | val[0]); |
33226ffd HZ |
162 | if (ret < 0) |
163 | break; | |
164 | ret = i2c_smbus_write_byte_data(chip->client, | |
165 | (reg << 1) + 1, | |
f5f0b7aa | 166 | val[1]); |
33226ffd HZ |
167 | break; |
168 | } | |
169 | } | |
f5e8ff48 GL |
170 | |
171 | if (ret < 0) { | |
172 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 173 | return ret; |
f5e8ff48 GL |
174 | } |
175 | ||
176 | return 0; | |
9e60fdcf | 177 | } |
178 | ||
f5f0b7aa | 179 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 180 | { |
181 | int ret; | |
182 | ||
96b70641 | 183 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 184 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 185 | *val = ret; |
f5f0b7aa GC |
186 | } else if (chip->gpio_chip.ngpio >= 24) { |
187 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
188 | ||
96b70641 | 189 | ret = i2c_smbus_read_i2c_block_data(chip->client, |
f5f0b7aa GC |
190 | (reg << bank_shift) | REG_ADDR_AI, |
191 | NBANK(chip), val); | |
96b70641 | 192 | } else { |
f5e8ff48 | 193 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
f5f0b7aa GC |
194 | val[0] = (u16)ret & 0xFF; |
195 | val[1] = (u16)ret >> 8; | |
96b70641 | 196 | } |
9e60fdcf | 197 | if (ret < 0) { |
198 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 199 | return ret; |
9e60fdcf | 200 | } |
201 | ||
9e60fdcf | 202 | return 0; |
203 | } | |
204 | ||
f3dc3630 | 205 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 206 | { |
7bcbce55 | 207 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 208 | u8 reg_val; |
33226ffd | 209 | int ret, offset = 0; |
9e60fdcf | 210 | |
6e20fb18 | 211 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 212 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd HZ |
213 | |
214 | switch (chip->chip_type) { | |
215 | case PCA953X_TYPE: | |
216 | offset = PCA953X_DIRECTION; | |
217 | break; | |
218 | case PCA957X_TYPE: | |
219 | offset = PCA957X_CFG; | |
220 | break; | |
221 | } | |
f5f0b7aa | 222 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 223 | if (ret) |
6e20fb18 | 224 | goto exit; |
9e60fdcf | 225 | |
f5f0b7aa | 226 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
227 | ret = 0; |
228 | exit: | |
229 | mutex_unlock(&chip->i2c_lock); | |
230 | return ret; | |
9e60fdcf | 231 | } |
232 | ||
f3dc3630 | 233 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 234 | unsigned off, int val) |
235 | { | |
7bcbce55 | 236 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 237 | u8 reg_val; |
33226ffd | 238 | int ret, offset = 0; |
9e60fdcf | 239 | |
6e20fb18 | 240 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 241 | /* set output level */ |
242 | if (val) | |
f5f0b7aa GC |
243 | reg_val = chip->reg_output[off / BANK_SZ] |
244 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 245 | else |
f5f0b7aa GC |
246 | reg_val = chip->reg_output[off / BANK_SZ] |
247 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 248 | |
33226ffd HZ |
249 | switch (chip->chip_type) { |
250 | case PCA953X_TYPE: | |
251 | offset = PCA953X_OUTPUT; | |
252 | break; | |
253 | case PCA957X_TYPE: | |
254 | offset = PCA957X_OUT; | |
255 | break; | |
256 | } | |
f5f0b7aa | 257 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 258 | if (ret) |
6e20fb18 | 259 | goto exit; |
9e60fdcf | 260 | |
f5f0b7aa | 261 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 262 | |
263 | /* then direction */ | |
f5f0b7aa | 264 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
33226ffd HZ |
265 | switch (chip->chip_type) { |
266 | case PCA953X_TYPE: | |
267 | offset = PCA953X_DIRECTION; | |
268 | break; | |
269 | case PCA957X_TYPE: | |
270 | offset = PCA957X_CFG; | |
271 | break; | |
272 | } | |
f5f0b7aa | 273 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 274 | if (ret) |
6e20fb18 | 275 | goto exit; |
9e60fdcf | 276 | |
f5f0b7aa | 277 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
278 | ret = 0; |
279 | exit: | |
280 | mutex_unlock(&chip->i2c_lock); | |
281 | return ret; | |
9e60fdcf | 282 | } |
283 | ||
f3dc3630 | 284 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 285 | { |
7bcbce55 | 286 | struct pca953x_chip *chip = to_pca(gc); |
ae79c190 | 287 | u32 reg_val; |
33226ffd | 288 | int ret, offset = 0; |
9e60fdcf | 289 | |
6e20fb18 | 290 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
291 | switch (chip->chip_type) { |
292 | case PCA953X_TYPE: | |
293 | offset = PCA953X_INPUT; | |
294 | break; | |
295 | case PCA957X_TYPE: | |
296 | offset = PCA957X_IN; | |
297 | break; | |
298 | } | |
f5f0b7aa | 299 | ret = pca953x_read_single(chip, offset, ®_val, off); |
6e20fb18 | 300 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 301 | if (ret < 0) { |
302 | /* NOTE: diagnostic already emitted; that's all we should | |
303 | * do unless gpio_*_value_cansleep() calls become different | |
304 | * from their nonsleeping siblings (and report faults). | |
305 | */ | |
306 | return 0; | |
307 | } | |
308 | ||
40a625da | 309 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 310 | } |
311 | ||
f3dc3630 | 312 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 313 | { |
7bcbce55 | 314 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 315 | u8 reg_val; |
33226ffd | 316 | int ret, offset = 0; |
9e60fdcf | 317 | |
6e20fb18 | 318 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 319 | if (val) |
f5f0b7aa GC |
320 | reg_val = chip->reg_output[off / BANK_SZ] |
321 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 322 | else |
f5f0b7aa GC |
323 | reg_val = chip->reg_output[off / BANK_SZ] |
324 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 325 | |
33226ffd HZ |
326 | switch (chip->chip_type) { |
327 | case PCA953X_TYPE: | |
328 | offset = PCA953X_OUTPUT; | |
329 | break; | |
330 | case PCA957X_TYPE: | |
331 | offset = PCA957X_OUT; | |
332 | break; | |
333 | } | |
f5f0b7aa | 334 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 335 | if (ret) |
6e20fb18 | 336 | goto exit; |
9e60fdcf | 337 | |
f5f0b7aa | 338 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
339 | exit: |
340 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 341 | } |
342 | ||
f5e8ff48 | 343 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 344 | { |
345 | struct gpio_chip *gc; | |
346 | ||
347 | gc = &chip->gpio_chip; | |
348 | ||
f3dc3630 GL |
349 | gc->direction_input = pca953x_gpio_direction_input; |
350 | gc->direction_output = pca953x_gpio_direction_output; | |
351 | gc->get = pca953x_gpio_get_value; | |
352 | gc->set = pca953x_gpio_set_value; | |
9fb1f39e | 353 | gc->can_sleep = true; |
9e60fdcf | 354 | |
355 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
356 | gc->ngpio = gpios; |
357 | gc->label = chip->client->name; | |
d8f388d8 | 358 | gc->dev = &chip->client->dev; |
d72cbed0 | 359 | gc->owner = THIS_MODULE; |
77906a54 | 360 | gc->names = chip->names; |
9e60fdcf | 361 | } |
362 | ||
89ea8bbe | 363 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 364 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 365 | { |
7bcbce55 LW |
366 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
367 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe | 368 | |
f5f0b7aa | 369 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
370 | } |
371 | ||
6f5cfc0e | 372 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 373 | { |
7bcbce55 LW |
374 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
375 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe | 376 | |
f5f0b7aa | 377 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
378 | } |
379 | ||
6f5cfc0e | 380 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 381 | { |
7bcbce55 LW |
382 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
383 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe MZ |
384 | |
385 | mutex_lock(&chip->irq_lock); | |
386 | } | |
387 | ||
6f5cfc0e | 388 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 389 | { |
7bcbce55 LW |
390 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
391 | struct pca953x_chip *chip = to_pca(gc); | |
f5f0b7aa GC |
392 | u8 new_irqs; |
393 | int level, i; | |
a2cb9aeb MZ |
394 | |
395 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
396 | for (i = 0; i < NBANK(chip); i++) { |
397 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
398 | new_irqs &= ~chip->reg_direction[i]; | |
399 | ||
400 | while (new_irqs) { | |
401 | level = __ffs(new_irqs); | |
402 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
403 | level + (BANK_SZ * i)); | |
404 | new_irqs &= ~(1 << level); | |
405 | } | |
a2cb9aeb | 406 | } |
89ea8bbe MZ |
407 | |
408 | mutex_unlock(&chip->irq_lock); | |
409 | } | |
410 | ||
6f5cfc0e | 411 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 412 | { |
7bcbce55 LW |
413 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
414 | struct pca953x_chip *chip = to_pca(gc); | |
f5f0b7aa GC |
415 | int bank_nb = d->hwirq / BANK_SZ; |
416 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
417 | |
418 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
419 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 420 | d->irq, type); |
89ea8bbe MZ |
421 | return -EINVAL; |
422 | } | |
423 | ||
424 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 425 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 426 | else |
f5f0b7aa | 427 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
428 | |
429 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 430 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 431 | else |
f5f0b7aa | 432 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 433 | |
a2cb9aeb | 434 | return 0; |
89ea8bbe MZ |
435 | } |
436 | ||
437 | static struct irq_chip pca953x_irq_chip = { | |
438 | .name = "pca953x", | |
6f5cfc0e LB |
439 | .irq_mask = pca953x_irq_mask, |
440 | .irq_unmask = pca953x_irq_unmask, | |
441 | .irq_bus_lock = pca953x_irq_bus_lock, | |
442 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
443 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
444 | }; |
445 | ||
b6ac1280 | 446 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 447 | { |
f5f0b7aa GC |
448 | u8 cur_stat[MAX_BANK]; |
449 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
450 | bool pending_seen = false; |
451 | bool trigger_seen = false; | |
452 | u8 trigger[MAX_BANK]; | |
f5f0b7aa | 453 | int ret, i, offset = 0; |
33226ffd HZ |
454 | |
455 | switch (chip->chip_type) { | |
456 | case PCA953X_TYPE: | |
457 | offset = PCA953X_INPUT; | |
458 | break; | |
459 | case PCA957X_TYPE: | |
460 | offset = PCA957X_IN; | |
461 | break; | |
462 | } | |
f5f0b7aa | 463 | ret = pca953x_read_regs(chip, offset, cur_stat); |
89ea8bbe | 464 | if (ret) |
b6ac1280 | 465 | return false; |
89ea8bbe MZ |
466 | |
467 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
468 | for (i = 0; i < NBANK(chip); i++) |
469 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 470 | |
f5f0b7aa | 471 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 472 | |
f5f0b7aa GC |
473 | for (i = 0; i < NBANK(chip); i++) { |
474 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
475 | if (trigger[i]) |
476 | trigger_seen = true; | |
f5f0b7aa GC |
477 | } |
478 | ||
b6ac1280 JS |
479 | if (!trigger_seen) |
480 | return false; | |
89ea8bbe | 481 | |
f5f0b7aa | 482 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 483 | |
f5f0b7aa GC |
484 | for (i = 0; i < NBANK(chip); i++) { |
485 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
486 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
487 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
488 | if (pending[i]) |
489 | pending_seen = true; | |
f5f0b7aa | 490 | } |
89ea8bbe | 491 | |
b6ac1280 | 492 | return pending_seen; |
89ea8bbe MZ |
493 | } |
494 | ||
495 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
496 | { | |
497 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
498 | u8 pending[MAX_BANK]; |
499 | u8 level; | |
3275d072 | 500 | unsigned nhandled = 0; |
f5f0b7aa | 501 | int i; |
89ea8bbe | 502 | |
f5f0b7aa | 503 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 504 | return IRQ_NONE; |
89ea8bbe | 505 | |
f5f0b7aa GC |
506 | for (i = 0; i < NBANK(chip); i++) { |
507 | while (pending[i]) { | |
508 | level = __ffs(pending[i]); | |
7bcbce55 | 509 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
510 | level + (BANK_SZ * i))); |
511 | pending[i] &= ~(1 << level); | |
3275d072 | 512 | nhandled++; |
f5f0b7aa GC |
513 | } |
514 | } | |
89ea8bbe | 515 | |
3275d072 | 516 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
517 | } |
518 | ||
519 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 DJ |
520 | const struct i2c_device_id *id, |
521 | int irq_base) | |
89ea8bbe MZ |
522 | { |
523 | struct i2c_client *client = chip->client; | |
f5f0b7aa | 524 | int ret, i, offset = 0; |
89ea8bbe | 525 | |
4bb93349 | 526 | if (client->irq && irq_base != -1 |
33226ffd | 527 | && (id->driver_data & PCA_INT)) { |
89ea8bbe | 528 | |
33226ffd HZ |
529 | switch (chip->chip_type) { |
530 | case PCA953X_TYPE: | |
531 | offset = PCA953X_INPUT; | |
532 | break; | |
533 | case PCA957X_TYPE: | |
534 | offset = PCA957X_IN; | |
535 | break; | |
536 | } | |
f5f0b7aa | 537 | ret = pca953x_read_regs(chip, offset, chip->irq_stat); |
89ea8bbe | 538 | if (ret) |
b42748c9 | 539 | return ret; |
89ea8bbe MZ |
540 | |
541 | /* | |
542 | * There is no way to know which GPIO line generated the | |
543 | * interrupt. We have to rely on the previous read for | |
544 | * this purpose. | |
545 | */ | |
f5f0b7aa GC |
546 | for (i = 0; i < NBANK(chip); i++) |
547 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
548 | mutex_init(&chip->irq_lock); |
549 | ||
b42748c9 LW |
550 | ret = devm_request_threaded_irq(&client->dev, |
551 | client->irq, | |
89ea8bbe MZ |
552 | NULL, |
553 | pca953x_irq_handler, | |
91329132 TS |
554 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
555 | IRQF_SHARED, | |
89ea8bbe MZ |
556 | dev_name(&client->dev), chip); |
557 | if (ret) { | |
558 | dev_err(&client->dev, "failed to request irq %d\n", | |
559 | client->irq); | |
0e8f2fda | 560 | return ret; |
89ea8bbe MZ |
561 | } |
562 | ||
7bcbce55 LW |
563 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
564 | &pca953x_irq_chip, | |
565 | irq_base, | |
566 | handle_simple_irq, | |
567 | IRQ_TYPE_NONE); | |
568 | if (ret) { | |
569 | dev_err(&client->dev, | |
570 | "could not connect irqchip to gpiochip\n"); | |
571 | return ret; | |
572 | } | |
89ea8bbe MZ |
573 | } |
574 | ||
575 | return 0; | |
89ea8bbe MZ |
576 | } |
577 | ||
89ea8bbe MZ |
578 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
579 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 DJ |
580 | const struct i2c_device_id *id, |
581 | int irq_base) | |
89ea8bbe MZ |
582 | { |
583 | struct i2c_client *client = chip->client; | |
89ea8bbe | 584 | |
c6dcf592 | 585 | if (irq_base != -1 && (id->driver_data & PCA_INT)) |
89ea8bbe MZ |
586 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
587 | ||
588 | return 0; | |
589 | } | |
89ea8bbe MZ |
590 | #endif |
591 | ||
3836309d | 592 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
593 | { |
594 | int ret; | |
f5f0b7aa | 595 | u8 val[MAX_BANK]; |
33226ffd | 596 | |
f5f0b7aa | 597 | ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output); |
33226ffd HZ |
598 | if (ret) |
599 | goto out; | |
600 | ||
f5f0b7aa GC |
601 | ret = pca953x_read_regs(chip, PCA953X_DIRECTION, |
602 | chip->reg_direction); | |
33226ffd HZ |
603 | if (ret) |
604 | goto out; | |
605 | ||
606 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
607 | if (invert) |
608 | memset(val, 0xFF, NBANK(chip)); | |
609 | else | |
610 | memset(val, 0, NBANK(chip)); | |
611 | ||
612 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
613 | out: |
614 | return ret; | |
615 | } | |
616 | ||
3836309d | 617 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
618 | { |
619 | int ret; | |
f5f0b7aa | 620 | u8 val[MAX_BANK]; |
33226ffd | 621 | |
f5f0b7aa | 622 | ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output); |
33226ffd HZ |
623 | if (ret) |
624 | goto out; | |
f5f0b7aa | 625 | ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction); |
33226ffd HZ |
626 | if (ret) |
627 | goto out; | |
628 | ||
629 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
630 | if (invert) |
631 | memset(val, 0xFF, NBANK(chip)); | |
632 | else | |
633 | memset(val, 0, NBANK(chip)); | |
634 | pca953x_write_regs(chip, PCA957X_INVRT, val); | |
33226ffd | 635 | |
20a8a968 | 636 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa GC |
637 | memset(val, 0x02, NBANK(chip)); |
638 | pca953x_write_regs(chip, PCA957X_BKEN, val); | |
33226ffd HZ |
639 | |
640 | return 0; | |
641 | out: | |
642 | return ret; | |
643 | } | |
644 | ||
3836309d | 645 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 646 | const struct i2c_device_id *id) |
9e60fdcf | 647 | { |
f3dc3630 GL |
648 | struct pca953x_platform_data *pdata; |
649 | struct pca953x_chip *chip; | |
6a7b36aa | 650 | int irq_base = 0; |
7ea2aa20 | 651 | int ret; |
6a7b36aa | 652 | u32 invert = 0; |
9e60fdcf | 653 | |
b42748c9 LW |
654 | chip = devm_kzalloc(&client->dev, |
655 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
656 | if (chip == NULL) |
657 | return -ENOMEM; | |
658 | ||
e56aee18 | 659 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
660 | if (pdata) { |
661 | irq_base = pdata->irq_base; | |
662 | chip->gpio_start = pdata->gpio_base; | |
663 | invert = pdata->invert; | |
664 | chip->names = pdata->names; | |
665 | } else { | |
4bb93349 MP |
666 | chip->gpio_start = -1; |
667 | irq_base = 0; | |
1965d303 | 668 | } |
9e60fdcf | 669 | |
670 | chip->client = client; | |
671 | ||
33226ffd | 672 | chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE); |
77906a54 | 673 | |
6e20fb18 RS |
674 | mutex_init(&chip->i2c_lock); |
675 | ||
9e60fdcf | 676 | /* initialize cached registers from their original values. |
677 | * we can't share this chip with another i2c master. | |
678 | */ | |
33226ffd | 679 | pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 680 | |
33226ffd | 681 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 682 | ret = device_pca953x_init(chip, invert); |
33226ffd | 683 | else |
7ea2aa20 WS |
684 | ret = device_pca957x_init(chip, invert); |
685 | if (ret) | |
b42748c9 | 686 | return ret; |
9e60fdcf | 687 | |
7bcbce55 | 688 | ret = gpiochip_add(&chip->gpio_chip); |
89ea8bbe | 689 | if (ret) |
b42748c9 | 690 | return ret; |
f5e8ff48 | 691 | |
7bcbce55 | 692 | ret = pca953x_irq_setup(chip, id, irq_base); |
9e60fdcf | 693 | if (ret) |
b42748c9 | 694 | return ret; |
9e60fdcf | 695 | |
c6dcf592 | 696 | if (pdata && pdata->setup) { |
9e60fdcf | 697 | ret = pdata->setup(client, chip->gpio_chip.base, |
698 | chip->gpio_chip.ngpio, pdata->context); | |
699 | if (ret < 0) | |
700 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
701 | } | |
702 | ||
703 | i2c_set_clientdata(client, chip); | |
704 | return 0; | |
9e60fdcf | 705 | } |
706 | ||
f3dc3630 | 707 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 708 | { |
e56aee18 | 709 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 710 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
9e60fdcf | 711 | int ret = 0; |
712 | ||
c6dcf592 | 713 | if (pdata && pdata->teardown) { |
9e60fdcf | 714 | ret = pdata->teardown(client, chip->gpio_chip.base, |
715 | chip->gpio_chip.ngpio, pdata->context); | |
716 | if (ret < 0) { | |
717 | dev_err(&client->dev, "%s failed, %d\n", | |
718 | "teardown", ret); | |
719 | return ret; | |
720 | } | |
721 | } | |
722 | ||
9f5132ae | 723 | gpiochip_remove(&chip->gpio_chip); |
9e60fdcf | 724 | |
9e60fdcf | 725 | return 0; |
726 | } | |
727 | ||
ed32620e | 728 | static const struct of_device_id pca953x_dt_ids[] = { |
89f5df01 | 729 | { .compatible = "nxp,pca9505", }, |
ed32620e MR |
730 | { .compatible = "nxp,pca9534", }, |
731 | { .compatible = "nxp,pca9535", }, | |
732 | { .compatible = "nxp,pca9536", }, | |
733 | { .compatible = "nxp,pca9537", }, | |
734 | { .compatible = "nxp,pca9538", }, | |
735 | { .compatible = "nxp,pca9539", }, | |
736 | { .compatible = "nxp,pca9554", }, | |
737 | { .compatible = "nxp,pca9555", }, | |
738 | { .compatible = "nxp,pca9556", }, | |
739 | { .compatible = "nxp,pca9557", }, | |
740 | { .compatible = "nxp,pca9574", }, | |
741 | { .compatible = "nxp,pca9575", }, | |
eb32b5aa | 742 | { .compatible = "nxp,pca9698", }, |
ed32620e MR |
743 | |
744 | { .compatible = "maxim,max7310", }, | |
745 | { .compatible = "maxim,max7312", }, | |
746 | { .compatible = "maxim,max7313", }, | |
747 | { .compatible = "maxim,max7315", }, | |
748 | ||
749 | { .compatible = "ti,pca6107", }, | |
750 | { .compatible = "ti,tca6408", }, | |
751 | { .compatible = "ti,tca6416", }, | |
752 | { .compatible = "ti,tca6424", }, | |
e73760a6 AS |
753 | |
754 | { .compatible = "exar,xra1202", }, | |
ed32620e MR |
755 | { } |
756 | }; | |
757 | ||
758 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
759 | ||
f3dc3630 | 760 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 761 | .driver = { |
f3dc3630 | 762 | .name = "pca953x", |
ed32620e | 763 | .of_match_table = pca953x_dt_ids, |
9e60fdcf | 764 | }, |
f3dc3630 GL |
765 | .probe = pca953x_probe, |
766 | .remove = pca953x_remove, | |
3760f736 | 767 | .id_table = pca953x_id, |
9e60fdcf | 768 | }; |
769 | ||
f3dc3630 | 770 | static int __init pca953x_init(void) |
9e60fdcf | 771 | { |
f3dc3630 | 772 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 773 | } |
2f8d1197 DB |
774 | /* register after i2c postcore initcall and before |
775 | * subsys initcalls that may rely on these GPIOs | |
776 | */ | |
777 | subsys_initcall(pca953x_init); | |
9e60fdcf | 778 | |
f3dc3630 | 779 | static void __exit pca953x_exit(void) |
9e60fdcf | 780 | { |
f3dc3630 | 781 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 782 | } |
f3dc3630 | 783 | module_exit(pca953x_exit); |
9e60fdcf | 784 | |
785 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 786 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 787 | MODULE_LICENSE("GPL"); |