Commit | Line | Data |
---|---|---|
9e60fdcf | 1 | /* |
c103de24 | 2 | * PCA953x 4/8/16 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe MZ |
17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> | |
9e60fdcf | 19 | #include <linux/i2c.h> |
d1c057e3 | 20 | #include <linux/i2c/pca953x.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1965d303 NC |
22 | #ifdef CONFIG_OF_GPIO |
23 | #include <linux/of_platform.h> | |
1965d303 | 24 | #endif |
9e60fdcf | 25 | |
33226ffd HZ |
26 | #define PCA953X_INPUT 0 |
27 | #define PCA953X_OUTPUT 1 | |
28 | #define PCA953X_INVERT 2 | |
29 | #define PCA953X_DIRECTION 3 | |
30 | ||
31 | #define PCA957X_IN 0 | |
32 | #define PCA957X_INVRT 1 | |
33 | #define PCA957X_BKEN 2 | |
34 | #define PCA957X_PUPD 3 | |
35 | #define PCA957X_CFG 4 | |
36 | #define PCA957X_OUT 5 | |
37 | #define PCA957X_MSK 6 | |
38 | #define PCA957X_INTS 7 | |
39 | ||
40 | #define PCA_GPIO_MASK 0x00FF | |
41 | #define PCA_INT 0x0100 | |
42 | #define PCA953X_TYPE 0x1000 | |
43 | #define PCA957X_TYPE 0x2000 | |
89ea8bbe | 44 | |
3760f736 | 45 | static const struct i2c_device_id pca953x_id[] = { |
33226ffd HZ |
46 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
47 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
48 | { "pca9536", 4 | PCA953X_TYPE, }, | |
49 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
50 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
51 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
52 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
53 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
54 | { "pca9556", 8 | PCA953X_TYPE, }, | |
55 | { "pca9557", 8 | PCA953X_TYPE, }, | |
56 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
57 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
58 | ||
59 | { "max7310", 8 | PCA953X_TYPE, }, | |
60 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
61 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
62 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
63 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
65 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ab5dc372 | 66 | /* NYET: { "tca6424", 24, }, */ |
3760f736 | 67 | { } |
f5e8ff48 | 68 | }; |
3760f736 | 69 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 70 | |
f3dc3630 | 71 | struct pca953x_chip { |
9e60fdcf | 72 | unsigned gpio_start; |
73 | uint16_t reg_output; | |
74 | uint16_t reg_direction; | |
6e20fb18 | 75 | struct mutex i2c_lock; |
9e60fdcf | 76 | |
89ea8bbe MZ |
77 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
78 | struct mutex irq_lock; | |
79 | uint16_t irq_mask; | |
80 | uint16_t irq_stat; | |
81 | uint16_t irq_trig_raise; | |
82 | uint16_t irq_trig_fall; | |
83 | int irq_base; | |
84 | #endif | |
85 | ||
9e60fdcf | 86 | struct i2c_client *client; |
87 | struct gpio_chip gpio_chip; | |
62154991 | 88 | const char *const *names; |
33226ffd | 89 | int chip_type; |
9e60fdcf | 90 | }; |
91 | ||
f3dc3630 | 92 | static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val) |
9e60fdcf | 93 | { |
33226ffd | 94 | int ret = 0; |
f5e8ff48 GL |
95 | |
96 | if (chip->gpio_chip.ngpio <= 8) | |
97 | ret = i2c_smbus_write_byte_data(chip->client, reg, val); | |
33226ffd HZ |
98 | else { |
99 | switch (chip->chip_type) { | |
100 | case PCA953X_TYPE: | |
101 | ret = i2c_smbus_write_word_data(chip->client, | |
102 | reg << 1, val); | |
103 | break; | |
104 | case PCA957X_TYPE: | |
105 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
106 | val & 0xff); | |
107 | if (ret < 0) | |
108 | break; | |
109 | ret = i2c_smbus_write_byte_data(chip->client, | |
110 | (reg << 1) + 1, | |
111 | (val & 0xff00) >> 8); | |
112 | break; | |
113 | } | |
114 | } | |
f5e8ff48 GL |
115 | |
116 | if (ret < 0) { | |
117 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 118 | return ret; |
f5e8ff48 GL |
119 | } |
120 | ||
121 | return 0; | |
9e60fdcf | 122 | } |
123 | ||
f3dc3630 | 124 | static int pca953x_read_reg(struct pca953x_chip *chip, int reg, uint16_t *val) |
9e60fdcf | 125 | { |
126 | int ret; | |
127 | ||
f5e8ff48 GL |
128 | if (chip->gpio_chip.ngpio <= 8) |
129 | ret = i2c_smbus_read_byte_data(chip->client, reg); | |
130 | else | |
131 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); | |
132 | ||
9e60fdcf | 133 | if (ret < 0) { |
134 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 135 | return ret; |
9e60fdcf | 136 | } |
137 | ||
138 | *val = (uint16_t)ret; | |
139 | return 0; | |
140 | } | |
141 | ||
f3dc3630 | 142 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 143 | { |
f3dc3630 | 144 | struct pca953x_chip *chip; |
9e60fdcf | 145 | uint16_t reg_val; |
33226ffd | 146 | int ret, offset = 0; |
9e60fdcf | 147 | |
f3dc3630 | 148 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 149 | |
6e20fb18 | 150 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 151 | reg_val = chip->reg_direction | (1u << off); |
33226ffd HZ |
152 | |
153 | switch (chip->chip_type) { | |
154 | case PCA953X_TYPE: | |
155 | offset = PCA953X_DIRECTION; | |
156 | break; | |
157 | case PCA957X_TYPE: | |
158 | offset = PCA957X_CFG; | |
159 | break; | |
160 | } | |
161 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 162 | if (ret) |
6e20fb18 | 163 | goto exit; |
9e60fdcf | 164 | |
165 | chip->reg_direction = reg_val; | |
6e20fb18 RS |
166 | ret = 0; |
167 | exit: | |
168 | mutex_unlock(&chip->i2c_lock); | |
169 | return ret; | |
9e60fdcf | 170 | } |
171 | ||
f3dc3630 | 172 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 173 | unsigned off, int val) |
174 | { | |
f3dc3630 | 175 | struct pca953x_chip *chip; |
9e60fdcf | 176 | uint16_t reg_val; |
33226ffd | 177 | int ret, offset = 0; |
9e60fdcf | 178 | |
f3dc3630 | 179 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 180 | |
6e20fb18 | 181 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 182 | /* set output level */ |
183 | if (val) | |
184 | reg_val = chip->reg_output | (1u << off); | |
185 | else | |
186 | reg_val = chip->reg_output & ~(1u << off); | |
187 | ||
33226ffd HZ |
188 | switch (chip->chip_type) { |
189 | case PCA953X_TYPE: | |
190 | offset = PCA953X_OUTPUT; | |
191 | break; | |
192 | case PCA957X_TYPE: | |
193 | offset = PCA957X_OUT; | |
194 | break; | |
195 | } | |
196 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 197 | if (ret) |
6e20fb18 | 198 | goto exit; |
9e60fdcf | 199 | |
200 | chip->reg_output = reg_val; | |
201 | ||
202 | /* then direction */ | |
203 | reg_val = chip->reg_direction & ~(1u << off); | |
33226ffd HZ |
204 | switch (chip->chip_type) { |
205 | case PCA953X_TYPE: | |
206 | offset = PCA953X_DIRECTION; | |
207 | break; | |
208 | case PCA957X_TYPE: | |
209 | offset = PCA957X_CFG; | |
210 | break; | |
211 | } | |
212 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 213 | if (ret) |
6e20fb18 | 214 | goto exit; |
9e60fdcf | 215 | |
216 | chip->reg_direction = reg_val; | |
6e20fb18 RS |
217 | ret = 0; |
218 | exit: | |
219 | mutex_unlock(&chip->i2c_lock); | |
220 | return ret; | |
9e60fdcf | 221 | } |
222 | ||
f3dc3630 | 223 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 224 | { |
f3dc3630 | 225 | struct pca953x_chip *chip; |
9e60fdcf | 226 | uint16_t reg_val; |
33226ffd | 227 | int ret, offset = 0; |
9e60fdcf | 228 | |
f3dc3630 | 229 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 230 | |
6e20fb18 | 231 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
232 | switch (chip->chip_type) { |
233 | case PCA953X_TYPE: | |
234 | offset = PCA953X_INPUT; | |
235 | break; | |
236 | case PCA957X_TYPE: | |
237 | offset = PCA957X_IN; | |
238 | break; | |
239 | } | |
240 | ret = pca953x_read_reg(chip, offset, ®_val); | |
6e20fb18 | 241 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 242 | if (ret < 0) { |
243 | /* NOTE: diagnostic already emitted; that's all we should | |
244 | * do unless gpio_*_value_cansleep() calls become different | |
245 | * from their nonsleeping siblings (and report faults). | |
246 | */ | |
247 | return 0; | |
248 | } | |
249 | ||
250 | return (reg_val & (1u << off)) ? 1 : 0; | |
251 | } | |
252 | ||
f3dc3630 | 253 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 254 | { |
f3dc3630 | 255 | struct pca953x_chip *chip; |
9e60fdcf | 256 | uint16_t reg_val; |
33226ffd | 257 | int ret, offset = 0; |
9e60fdcf | 258 | |
f3dc3630 | 259 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 260 | |
6e20fb18 | 261 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 262 | if (val) |
263 | reg_val = chip->reg_output | (1u << off); | |
264 | else | |
265 | reg_val = chip->reg_output & ~(1u << off); | |
266 | ||
33226ffd HZ |
267 | switch (chip->chip_type) { |
268 | case PCA953X_TYPE: | |
269 | offset = PCA953X_OUTPUT; | |
270 | break; | |
271 | case PCA957X_TYPE: | |
272 | offset = PCA957X_OUT; | |
273 | break; | |
274 | } | |
275 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 276 | if (ret) |
6e20fb18 | 277 | goto exit; |
9e60fdcf | 278 | |
279 | chip->reg_output = reg_val; | |
6e20fb18 RS |
280 | exit: |
281 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 282 | } |
283 | ||
f5e8ff48 | 284 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 285 | { |
286 | struct gpio_chip *gc; | |
287 | ||
288 | gc = &chip->gpio_chip; | |
289 | ||
f3dc3630 GL |
290 | gc->direction_input = pca953x_gpio_direction_input; |
291 | gc->direction_output = pca953x_gpio_direction_output; | |
292 | gc->get = pca953x_gpio_get_value; | |
293 | gc->set = pca953x_gpio_set_value; | |
84207805 | 294 | gc->can_sleep = 1; |
9e60fdcf | 295 | |
296 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
297 | gc->ngpio = gpios; |
298 | gc->label = chip->client->name; | |
d8f388d8 | 299 | gc->dev = &chip->client->dev; |
d72cbed0 | 300 | gc->owner = THIS_MODULE; |
77906a54 | 301 | gc->names = chip->names; |
9e60fdcf | 302 | } |
303 | ||
89ea8bbe MZ |
304 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
305 | static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off) | |
306 | { | |
307 | struct pca953x_chip *chip; | |
308 | ||
309 | chip = container_of(gc, struct pca953x_chip, gpio_chip); | |
310 | return chip->irq_base + off; | |
311 | } | |
312 | ||
6f5cfc0e | 313 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 314 | { |
6f5cfc0e | 315 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
89ea8bbe | 316 | |
6f5cfc0e | 317 | chip->irq_mask &= ~(1 << (d->irq - chip->irq_base)); |
89ea8bbe MZ |
318 | } |
319 | ||
6f5cfc0e | 320 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 321 | { |
6f5cfc0e | 322 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
89ea8bbe | 323 | |
6f5cfc0e | 324 | chip->irq_mask |= 1 << (d->irq - chip->irq_base); |
89ea8bbe MZ |
325 | } |
326 | ||
6f5cfc0e | 327 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 328 | { |
6f5cfc0e | 329 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
89ea8bbe MZ |
330 | |
331 | mutex_lock(&chip->irq_lock); | |
332 | } | |
333 | ||
6f5cfc0e | 334 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 335 | { |
6f5cfc0e | 336 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
a2cb9aeb MZ |
337 | uint16_t new_irqs; |
338 | uint16_t level; | |
339 | ||
340 | /* Look for any newly setup interrupt */ | |
341 | new_irqs = chip->irq_trig_fall | chip->irq_trig_raise; | |
342 | new_irqs &= ~chip->reg_direction; | |
343 | ||
344 | while (new_irqs) { | |
345 | level = __ffs(new_irqs); | |
346 | pca953x_gpio_direction_input(&chip->gpio_chip, level); | |
347 | new_irqs &= ~(1 << level); | |
348 | } | |
89ea8bbe MZ |
349 | |
350 | mutex_unlock(&chip->irq_lock); | |
351 | } | |
352 | ||
6f5cfc0e | 353 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 354 | { |
6f5cfc0e LB |
355 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
356 | uint16_t level = d->irq - chip->irq_base; | |
89ea8bbe MZ |
357 | uint16_t mask = 1 << level; |
358 | ||
359 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
360 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 361 | d->irq, type); |
89ea8bbe MZ |
362 | return -EINVAL; |
363 | } | |
364 | ||
365 | if (type & IRQ_TYPE_EDGE_FALLING) | |
366 | chip->irq_trig_fall |= mask; | |
367 | else | |
368 | chip->irq_trig_fall &= ~mask; | |
369 | ||
370 | if (type & IRQ_TYPE_EDGE_RISING) | |
371 | chip->irq_trig_raise |= mask; | |
372 | else | |
373 | chip->irq_trig_raise &= ~mask; | |
374 | ||
a2cb9aeb | 375 | return 0; |
89ea8bbe MZ |
376 | } |
377 | ||
378 | static struct irq_chip pca953x_irq_chip = { | |
379 | .name = "pca953x", | |
6f5cfc0e LB |
380 | .irq_mask = pca953x_irq_mask, |
381 | .irq_unmask = pca953x_irq_unmask, | |
382 | .irq_bus_lock = pca953x_irq_bus_lock, | |
383 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
384 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
385 | }; |
386 | ||
387 | static uint16_t pca953x_irq_pending(struct pca953x_chip *chip) | |
388 | { | |
389 | uint16_t cur_stat; | |
390 | uint16_t old_stat; | |
391 | uint16_t pending; | |
392 | uint16_t trigger; | |
33226ffd HZ |
393 | int ret, offset = 0; |
394 | ||
395 | switch (chip->chip_type) { | |
396 | case PCA953X_TYPE: | |
397 | offset = PCA953X_INPUT; | |
398 | break; | |
399 | case PCA957X_TYPE: | |
400 | offset = PCA957X_IN; | |
401 | break; | |
402 | } | |
403 | ret = pca953x_read_reg(chip, offset, &cur_stat); | |
89ea8bbe MZ |
404 | if (ret) |
405 | return 0; | |
406 | ||
407 | /* Remove output pins from the equation */ | |
408 | cur_stat &= chip->reg_direction; | |
409 | ||
410 | old_stat = chip->irq_stat; | |
411 | trigger = (cur_stat ^ old_stat) & chip->irq_mask; | |
412 | ||
413 | if (!trigger) | |
414 | return 0; | |
415 | ||
416 | chip->irq_stat = cur_stat; | |
417 | ||
418 | pending = (old_stat & chip->irq_trig_fall) | | |
419 | (cur_stat & chip->irq_trig_raise); | |
420 | pending &= trigger; | |
421 | ||
422 | return pending; | |
423 | } | |
424 | ||
425 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
426 | { | |
427 | struct pca953x_chip *chip = devid; | |
428 | uint16_t pending; | |
429 | uint16_t level; | |
430 | ||
431 | pending = pca953x_irq_pending(chip); | |
432 | ||
433 | if (!pending) | |
434 | return IRQ_HANDLED; | |
435 | ||
436 | do { | |
437 | level = __ffs(pending); | |
6dd599f8 | 438 | handle_nested_irq(level + chip->irq_base); |
89ea8bbe MZ |
439 | |
440 | pending &= ~(1 << level); | |
441 | } while (pending); | |
442 | ||
443 | return IRQ_HANDLED; | |
444 | } | |
445 | ||
446 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 DJ |
447 | const struct i2c_device_id *id, |
448 | int irq_base) | |
89ea8bbe MZ |
449 | { |
450 | struct i2c_client *client = chip->client; | |
33226ffd | 451 | int ret, offset = 0; |
89ea8bbe | 452 | |
c6dcf592 | 453 | if (irq_base != -1 |
33226ffd | 454 | && (id->driver_data & PCA_INT)) { |
89ea8bbe MZ |
455 | int lvl; |
456 | ||
33226ffd HZ |
457 | switch (chip->chip_type) { |
458 | case PCA953X_TYPE: | |
459 | offset = PCA953X_INPUT; | |
460 | break; | |
461 | case PCA957X_TYPE: | |
462 | offset = PCA957X_IN; | |
463 | break; | |
464 | } | |
465 | ret = pca953x_read_reg(chip, offset, &chip->irq_stat); | |
89ea8bbe MZ |
466 | if (ret) |
467 | goto out_failed; | |
468 | ||
469 | /* | |
470 | * There is no way to know which GPIO line generated the | |
471 | * interrupt. We have to rely on the previous read for | |
472 | * this purpose. | |
473 | */ | |
474 | chip->irq_stat &= chip->reg_direction; | |
89ea8bbe MZ |
475 | mutex_init(&chip->irq_lock); |
476 | ||
c6dcf592 | 477 | chip->irq_base = irq_alloc_descs(-1, irq_base, chip->gpio_chip.ngpio, -1); |
910c8fb6 DJ |
478 | if (chip->irq_base < 0) |
479 | goto out_failed; | |
480 | ||
89ea8bbe MZ |
481 | for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { |
482 | int irq = lvl + chip->irq_base; | |
483 | ||
910c8fb6 | 484 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
b51804bc | 485 | irq_set_chip_data(irq, chip); |
6dd599f8 DJ |
486 | irq_set_chip(irq, &pca953x_irq_chip); |
487 | irq_set_nested_thread(irq, true); | |
89ea8bbe MZ |
488 | #ifdef CONFIG_ARM |
489 | set_irq_flags(irq, IRQF_VALID); | |
490 | #else | |
b51804bc | 491 | irq_set_noprobe(irq); |
89ea8bbe MZ |
492 | #endif |
493 | } | |
494 | ||
495 | ret = request_threaded_irq(client->irq, | |
496 | NULL, | |
497 | pca953x_irq_handler, | |
17e8b42c | 498 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, |
89ea8bbe MZ |
499 | dev_name(&client->dev), chip); |
500 | if (ret) { | |
501 | dev_err(&client->dev, "failed to request irq %d\n", | |
502 | client->irq); | |
503 | goto out_failed; | |
504 | } | |
505 | ||
506 | chip->gpio_chip.to_irq = pca953x_gpio_to_irq; | |
507 | } | |
508 | ||
509 | return 0; | |
510 | ||
511 | out_failed: | |
8a233f01 | 512 | chip->irq_base = -1; |
89ea8bbe MZ |
513 | return ret; |
514 | } | |
515 | ||
516 | static void pca953x_irq_teardown(struct pca953x_chip *chip) | |
517 | { | |
c609c05d DJ |
518 | if (chip->irq_base != -1) { |
519 | irq_free_descs(chip->irq_base, chip->gpio_chip.ngpio); | |
89ea8bbe | 520 | free_irq(chip->client->irq, chip); |
c609c05d | 521 | } |
89ea8bbe MZ |
522 | } |
523 | #else /* CONFIG_GPIO_PCA953X_IRQ */ | |
524 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 DJ |
525 | const struct i2c_device_id *id, |
526 | int irq_base) | |
89ea8bbe MZ |
527 | { |
528 | struct i2c_client *client = chip->client; | |
89ea8bbe | 529 | |
c6dcf592 | 530 | if (irq_base != -1 && (id->driver_data & PCA_INT)) |
89ea8bbe MZ |
531 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static void pca953x_irq_teardown(struct pca953x_chip *chip) | |
537 | { | |
538 | } | |
539 | #endif | |
540 | ||
1965d303 NC |
541 | /* |
542 | * Handlers for alternative sources of platform_data | |
543 | */ | |
544 | #ifdef CONFIG_OF_GPIO | |
545 | /* | |
546 | * Translate OpenFirmware node properties into platform_data | |
a57339b4 | 547 | * WARNING: This is DEPRECATED and will be removed eventually! |
1965d303 | 548 | */ |
404ba2b8 | 549 | static void |
c6dcf592 | 550 | pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert) |
1965d303 | 551 | { |
1965d303 | 552 | struct device_node *node; |
1648237d DE |
553 | const __be32 *val; |
554 | int size; | |
1965d303 | 555 | |
61c7a080 | 556 | node = client->dev.of_node; |
1965d303 | 557 | if (node == NULL) |
c6dcf592 | 558 | return; |
1965d303 | 559 | |
c6dcf592 | 560 | *gpio_base = -1; |
1648237d | 561 | val = of_get_property(node, "linux,gpio-base", &size); |
a57339b4 | 562 | WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__); |
1965d303 | 563 | if (val) { |
1648237d DE |
564 | if (size != sizeof(*val)) |
565 | dev_warn(&client->dev, "%s: wrong linux,gpio-base\n", | |
566 | node->full_name); | |
1965d303 | 567 | else |
c6dcf592 | 568 | *gpio_base = be32_to_cpup(val); |
1965d303 NC |
569 | } |
570 | ||
571 | val = of_get_property(node, "polarity", NULL); | |
a57339b4 | 572 | WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__); |
1965d303 | 573 | if (val) |
c6dcf592 | 574 | *invert = *val; |
1965d303 NC |
575 | } |
576 | #else | |
404ba2b8 | 577 | static void |
c6dcf592 | 578 | pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert) |
1965d303 | 579 | { |
25fcf2b7 | 580 | *gpio_base = -1; |
1965d303 NC |
581 | } |
582 | #endif | |
583 | ||
33226ffd HZ |
584 | static int __devinit device_pca953x_init(struct pca953x_chip *chip, int invert) |
585 | { | |
586 | int ret; | |
587 | ||
588 | ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); | |
589 | if (ret) | |
590 | goto out; | |
591 | ||
592 | ret = pca953x_read_reg(chip, PCA953X_DIRECTION, | |
593 | &chip->reg_direction); | |
594 | if (ret) | |
595 | goto out; | |
596 | ||
597 | /* set platform specific polarity inversion */ | |
598 | ret = pca953x_write_reg(chip, PCA953X_INVERT, invert); | |
33226ffd HZ |
599 | out: |
600 | return ret; | |
601 | } | |
602 | ||
603 | static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert) | |
604 | { | |
605 | int ret; | |
606 | uint16_t val = 0; | |
607 | ||
608 | /* Let every port in proper state, that could save power */ | |
609 | pca953x_write_reg(chip, PCA957X_PUPD, 0x0); | |
610 | pca953x_write_reg(chip, PCA957X_CFG, 0xffff); | |
611 | pca953x_write_reg(chip, PCA957X_OUT, 0x0); | |
612 | ||
613 | ret = pca953x_read_reg(chip, PCA957X_IN, &val); | |
614 | if (ret) | |
615 | goto out; | |
616 | ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output); | |
617 | if (ret) | |
618 | goto out; | |
619 | ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction); | |
620 | if (ret) | |
621 | goto out; | |
622 | ||
623 | /* set platform specific polarity inversion */ | |
624 | pca953x_write_reg(chip, PCA957X_INVRT, invert); | |
625 | ||
626 | /* To enable register 6, 7 to controll pull up and pull down */ | |
627 | pca953x_write_reg(chip, PCA957X_BKEN, 0x202); | |
628 | ||
629 | return 0; | |
630 | out: | |
631 | return ret; | |
632 | } | |
633 | ||
d2653e92 | 634 | static int __devinit pca953x_probe(struct i2c_client *client, |
3760f736 | 635 | const struct i2c_device_id *id) |
9e60fdcf | 636 | { |
f3dc3630 GL |
637 | struct pca953x_platform_data *pdata; |
638 | struct pca953x_chip *chip; | |
a57339b4 | 639 | int irq_base=0, invert=0; |
7ea2aa20 | 640 | int ret; |
9e60fdcf | 641 | |
1965d303 NC |
642 | chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL); |
643 | if (chip == NULL) | |
644 | return -ENOMEM; | |
645 | ||
9e60fdcf | 646 | pdata = client->dev.platform_data; |
c6dcf592 DJ |
647 | if (pdata) { |
648 | irq_base = pdata->irq_base; | |
649 | chip->gpio_start = pdata->gpio_base; | |
650 | invert = pdata->invert; | |
651 | chip->names = pdata->names; | |
652 | } else { | |
653 | pca953x_get_alt_pdata(client, &chip->gpio_start, &invert); | |
a57339b4 DJ |
654 | #ifdef CONFIG_OF_GPIO |
655 | /* If I2C node has no interrupts property, disable GPIO interrupts */ | |
656 | if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL) | |
657 | irq_base = -1; | |
658 | #endif | |
1965d303 | 659 | } |
9e60fdcf | 660 | |
661 | chip->client = client; | |
662 | ||
33226ffd | 663 | chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE); |
77906a54 | 664 | |
6e20fb18 RS |
665 | mutex_init(&chip->i2c_lock); |
666 | ||
9e60fdcf | 667 | /* initialize cached registers from their original values. |
668 | * we can't share this chip with another i2c master. | |
669 | */ | |
33226ffd | 670 | pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 671 | |
33226ffd | 672 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 673 | ret = device_pca953x_init(chip, invert); |
33226ffd | 674 | else |
7ea2aa20 WS |
675 | ret = device_pca957x_init(chip, invert); |
676 | if (ret) | |
9e60fdcf | 677 | goto out_failed; |
678 | ||
c6dcf592 | 679 | ret = pca953x_irq_setup(chip, id, irq_base); |
89ea8bbe MZ |
680 | if (ret) |
681 | goto out_failed; | |
f5e8ff48 GL |
682 | |
683 | ret = gpiochip_add(&chip->gpio_chip); | |
9e60fdcf | 684 | if (ret) |
272df502 | 685 | goto out_failed_irq; |
9e60fdcf | 686 | |
c6dcf592 | 687 | if (pdata && pdata->setup) { |
9e60fdcf | 688 | ret = pdata->setup(client, chip->gpio_chip.base, |
689 | chip->gpio_chip.ngpio, pdata->context); | |
690 | if (ret < 0) | |
691 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
692 | } | |
693 | ||
694 | i2c_set_clientdata(client, chip); | |
695 | return 0; | |
696 | ||
272df502 | 697 | out_failed_irq: |
89ea8bbe | 698 | pca953x_irq_teardown(chip); |
272df502 | 699 | out_failed: |
9e60fdcf | 700 | kfree(chip); |
701 | return ret; | |
702 | } | |
703 | ||
f3dc3630 | 704 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 705 | { |
f3dc3630 GL |
706 | struct pca953x_platform_data *pdata = client->dev.platform_data; |
707 | struct pca953x_chip *chip = i2c_get_clientdata(client); | |
9e60fdcf | 708 | int ret = 0; |
709 | ||
c6dcf592 | 710 | if (pdata && pdata->teardown) { |
9e60fdcf | 711 | ret = pdata->teardown(client, chip->gpio_chip.base, |
712 | chip->gpio_chip.ngpio, pdata->context); | |
713 | if (ret < 0) { | |
714 | dev_err(&client->dev, "%s failed, %d\n", | |
715 | "teardown", ret); | |
716 | return ret; | |
717 | } | |
718 | } | |
719 | ||
720 | ret = gpiochip_remove(&chip->gpio_chip); | |
721 | if (ret) { | |
722 | dev_err(&client->dev, "%s failed, %d\n", | |
723 | "gpiochip_remove()", ret); | |
724 | return ret; | |
725 | } | |
726 | ||
89ea8bbe | 727 | pca953x_irq_teardown(chip); |
9e60fdcf | 728 | kfree(chip); |
729 | return 0; | |
730 | } | |
731 | ||
f3dc3630 | 732 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 733 | .driver = { |
f3dc3630 | 734 | .name = "pca953x", |
9e60fdcf | 735 | }, |
f3dc3630 GL |
736 | .probe = pca953x_probe, |
737 | .remove = pca953x_remove, | |
3760f736 | 738 | .id_table = pca953x_id, |
9e60fdcf | 739 | }; |
740 | ||
f3dc3630 | 741 | static int __init pca953x_init(void) |
9e60fdcf | 742 | { |
f3dc3630 | 743 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 744 | } |
2f8d1197 DB |
745 | /* register after i2c postcore initcall and before |
746 | * subsys initcalls that may rely on these GPIOs | |
747 | */ | |
748 | subsys_initcall(pca953x_init); | |
9e60fdcf | 749 | |
f3dc3630 | 750 | static void __exit pca953x_exit(void) |
9e60fdcf | 751 | { |
f3dc3630 | 752 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 753 | } |
f3dc3630 | 754 | module_exit(pca953x_exit); |
9e60fdcf | 755 | |
756 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 757 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 758 | MODULE_LICENSE("GPL"); |