Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1965d303 | 21 | #include <linux/of_platform.h> |
f32517bf | 22 | #include <linux/acpi.h> |
9e60fdcf | 23 | |
33226ffd HZ |
24 | #define PCA953X_INPUT 0 |
25 | #define PCA953X_OUTPUT 1 | |
26 | #define PCA953X_INVERT 2 | |
27 | #define PCA953X_DIRECTION 3 | |
28 | ||
ae79c190 AS |
29 | #define REG_ADDR_AI 0x80 |
30 | ||
33226ffd HZ |
31 | #define PCA957X_IN 0 |
32 | #define PCA957X_INVRT 1 | |
33 | #define PCA957X_BKEN 2 | |
34 | #define PCA957X_PUPD 3 | |
35 | #define PCA957X_CFG 4 | |
36 | #define PCA957X_OUT 5 | |
37 | #define PCA957X_MSK 6 | |
38 | #define PCA957X_INTS 7 | |
39 | ||
40 | #define PCA_GPIO_MASK 0x00FF | |
41 | #define PCA_INT 0x0100 | |
42 | #define PCA953X_TYPE 0x1000 | |
43 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
44 | #define PCA_TYPE_MASK 0xF000 |
45 | ||
46 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 47 | |
3760f736 | 48 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 49 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
50 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
51 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
52 | { "pca9536", 4 | PCA953X_TYPE, }, | |
53 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
54 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
55 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
56 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
57 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
58 | { "pca9556", 8 | PCA953X_TYPE, }, | |
59 | { "pca9557", 8 | PCA953X_TYPE, }, | |
60 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
61 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 62 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd HZ |
63 | |
64 | { "max7310", 8 | PCA953X_TYPE, }, | |
65 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
66 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
67 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
68 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
69 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
70 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 71 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 72 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 73 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 74 | { } |
f5e8ff48 | 75 | }; |
3760f736 | 76 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 77 | |
f32517bf AS |
78 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
79 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT, }, | |
80 | { } | |
81 | }; | |
82 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
83 | ||
f5f0b7aa GC |
84 | #define MAX_BANK 5 |
85 | #define BANK_SZ 8 | |
86 | ||
87 | #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ) | |
88 | ||
f3dc3630 | 89 | struct pca953x_chip { |
9e60fdcf | 90 | unsigned gpio_start; |
f5f0b7aa GC |
91 | u8 reg_output[MAX_BANK]; |
92 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 93 | struct mutex i2c_lock; |
9e60fdcf | 94 | |
89ea8bbe MZ |
95 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
96 | struct mutex irq_lock; | |
f5f0b7aa GC |
97 | u8 irq_mask[MAX_BANK]; |
98 | u8 irq_stat[MAX_BANK]; | |
99 | u8 irq_trig_raise[MAX_BANK]; | |
100 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
101 | #endif |
102 | ||
9e60fdcf | 103 | struct i2c_client *client; |
104 | struct gpio_chip gpio_chip; | |
62154991 | 105 | const char *const *names; |
33226ffd | 106 | int chip_type; |
c6664149 | 107 | unsigned long driver_data; |
9e60fdcf | 108 | }; |
109 | ||
7bcbce55 LW |
110 | static inline struct pca953x_chip *to_pca(struct gpio_chip *gc) |
111 | { | |
112 | return container_of(gc, struct pca953x_chip, gpio_chip); | |
113 | } | |
114 | ||
f5f0b7aa GC |
115 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
116 | int off) | |
117 | { | |
118 | int ret; | |
119 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
120 | int offset = off / BANK_SZ; | |
121 | ||
122 | ret = i2c_smbus_read_byte_data(chip->client, | |
123 | (reg << bank_shift) + offset); | |
124 | *val = ret; | |
125 | ||
126 | if (ret < 0) { | |
127 | dev_err(&chip->client->dev, "failed reading register\n"); | |
128 | return ret; | |
129 | } | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
135 | int off) | |
136 | { | |
137 | int ret = 0; | |
138 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
139 | int offset = off / BANK_SZ; | |
140 | ||
141 | ret = i2c_smbus_write_byte_data(chip->client, | |
142 | (reg << bank_shift) + offset, val); | |
143 | ||
144 | if (ret < 0) { | |
145 | dev_err(&chip->client->dev, "failed writing register\n"); | |
146 | return ret; | |
147 | } | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
9e60fdcf | 153 | { |
33226ffd | 154 | int ret = 0; |
f5e8ff48 GL |
155 | |
156 | if (chip->gpio_chip.ngpio <= 8) | |
f5f0b7aa GC |
157 | ret = i2c_smbus_write_byte_data(chip->client, reg, *val); |
158 | else if (chip->gpio_chip.ngpio >= 24) { | |
159 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
96b70641 | 160 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
f5f0b7aa GC |
161 | (reg << bank_shift) | REG_ADDR_AI, |
162 | NBANK(chip), val); | |
50e44430 | 163 | } else { |
33226ffd HZ |
164 | switch (chip->chip_type) { |
165 | case PCA953X_TYPE: | |
166 | ret = i2c_smbus_write_word_data(chip->client, | |
f5f0b7aa | 167 | reg << 1, (u16) *val); |
33226ffd HZ |
168 | break; |
169 | case PCA957X_TYPE: | |
170 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
f5f0b7aa | 171 | val[0]); |
33226ffd HZ |
172 | if (ret < 0) |
173 | break; | |
174 | ret = i2c_smbus_write_byte_data(chip->client, | |
175 | (reg << 1) + 1, | |
f5f0b7aa | 176 | val[1]); |
33226ffd HZ |
177 | break; |
178 | } | |
179 | } | |
f5e8ff48 GL |
180 | |
181 | if (ret < 0) { | |
182 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 183 | return ret; |
f5e8ff48 GL |
184 | } |
185 | ||
186 | return 0; | |
9e60fdcf | 187 | } |
188 | ||
f5f0b7aa | 189 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 190 | { |
191 | int ret; | |
192 | ||
96b70641 | 193 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 194 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 195 | *val = ret; |
f5f0b7aa GC |
196 | } else if (chip->gpio_chip.ngpio >= 24) { |
197 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
198 | ||
96b70641 | 199 | ret = i2c_smbus_read_i2c_block_data(chip->client, |
f5f0b7aa GC |
200 | (reg << bank_shift) | REG_ADDR_AI, |
201 | NBANK(chip), val); | |
96b70641 | 202 | } else { |
f5e8ff48 | 203 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
f5f0b7aa GC |
204 | val[0] = (u16)ret & 0xFF; |
205 | val[1] = (u16)ret >> 8; | |
96b70641 | 206 | } |
9e60fdcf | 207 | if (ret < 0) { |
208 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 209 | return ret; |
9e60fdcf | 210 | } |
211 | ||
9e60fdcf | 212 | return 0; |
213 | } | |
214 | ||
f3dc3630 | 215 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 216 | { |
7bcbce55 | 217 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 218 | u8 reg_val; |
33226ffd | 219 | int ret, offset = 0; |
9e60fdcf | 220 | |
6e20fb18 | 221 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 222 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd HZ |
223 | |
224 | switch (chip->chip_type) { | |
225 | case PCA953X_TYPE: | |
226 | offset = PCA953X_DIRECTION; | |
227 | break; | |
228 | case PCA957X_TYPE: | |
229 | offset = PCA957X_CFG; | |
230 | break; | |
231 | } | |
f5f0b7aa | 232 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 233 | if (ret) |
6e20fb18 | 234 | goto exit; |
9e60fdcf | 235 | |
f5f0b7aa | 236 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
237 | ret = 0; |
238 | exit: | |
239 | mutex_unlock(&chip->i2c_lock); | |
240 | return ret; | |
9e60fdcf | 241 | } |
242 | ||
f3dc3630 | 243 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 244 | unsigned off, int val) |
245 | { | |
7bcbce55 | 246 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 247 | u8 reg_val; |
33226ffd | 248 | int ret, offset = 0; |
9e60fdcf | 249 | |
6e20fb18 | 250 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 251 | /* set output level */ |
252 | if (val) | |
f5f0b7aa GC |
253 | reg_val = chip->reg_output[off / BANK_SZ] |
254 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 255 | else |
f5f0b7aa GC |
256 | reg_val = chip->reg_output[off / BANK_SZ] |
257 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 258 | |
33226ffd HZ |
259 | switch (chip->chip_type) { |
260 | case PCA953X_TYPE: | |
261 | offset = PCA953X_OUTPUT; | |
262 | break; | |
263 | case PCA957X_TYPE: | |
264 | offset = PCA957X_OUT; | |
265 | break; | |
266 | } | |
f5f0b7aa | 267 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 268 | if (ret) |
6e20fb18 | 269 | goto exit; |
9e60fdcf | 270 | |
f5f0b7aa | 271 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 272 | |
273 | /* then direction */ | |
f5f0b7aa | 274 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
33226ffd HZ |
275 | switch (chip->chip_type) { |
276 | case PCA953X_TYPE: | |
277 | offset = PCA953X_DIRECTION; | |
278 | break; | |
279 | case PCA957X_TYPE: | |
280 | offset = PCA957X_CFG; | |
281 | break; | |
282 | } | |
f5f0b7aa | 283 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 284 | if (ret) |
6e20fb18 | 285 | goto exit; |
9e60fdcf | 286 | |
f5f0b7aa | 287 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
288 | ret = 0; |
289 | exit: | |
290 | mutex_unlock(&chip->i2c_lock); | |
291 | return ret; | |
9e60fdcf | 292 | } |
293 | ||
f3dc3630 | 294 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 295 | { |
7bcbce55 | 296 | struct pca953x_chip *chip = to_pca(gc); |
ae79c190 | 297 | u32 reg_val; |
33226ffd | 298 | int ret, offset = 0; |
9e60fdcf | 299 | |
6e20fb18 | 300 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
301 | switch (chip->chip_type) { |
302 | case PCA953X_TYPE: | |
303 | offset = PCA953X_INPUT; | |
304 | break; | |
305 | case PCA957X_TYPE: | |
306 | offset = PCA957X_IN; | |
307 | break; | |
308 | } | |
f5f0b7aa | 309 | ret = pca953x_read_single(chip, offset, ®_val, off); |
6e20fb18 | 310 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 311 | if (ret < 0) { |
312 | /* NOTE: diagnostic already emitted; that's all we should | |
313 | * do unless gpio_*_value_cansleep() calls become different | |
314 | * from their nonsleeping siblings (and report faults). | |
315 | */ | |
316 | return 0; | |
317 | } | |
318 | ||
40a625da | 319 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 320 | } |
321 | ||
f3dc3630 | 322 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 323 | { |
7bcbce55 | 324 | struct pca953x_chip *chip = to_pca(gc); |
f5f0b7aa | 325 | u8 reg_val; |
33226ffd | 326 | int ret, offset = 0; |
9e60fdcf | 327 | |
6e20fb18 | 328 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 329 | if (val) |
f5f0b7aa GC |
330 | reg_val = chip->reg_output[off / BANK_SZ] |
331 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 332 | else |
f5f0b7aa GC |
333 | reg_val = chip->reg_output[off / BANK_SZ] |
334 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 335 | |
33226ffd HZ |
336 | switch (chip->chip_type) { |
337 | case PCA953X_TYPE: | |
338 | offset = PCA953X_OUTPUT; | |
339 | break; | |
340 | case PCA957X_TYPE: | |
341 | offset = PCA957X_OUT; | |
342 | break; | |
343 | } | |
f5f0b7aa | 344 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 345 | if (ret) |
6e20fb18 | 346 | goto exit; |
9e60fdcf | 347 | |
f5f0b7aa | 348 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
349 | exit: |
350 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 351 | } |
352 | ||
b4818afe PR |
353 | |
354 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, | |
355 | unsigned long *mask, unsigned long *bits) | |
356 | { | |
357 | struct pca953x_chip *chip = to_pca(gc); | |
358 | u8 reg_val[MAX_BANK]; | |
359 | int ret, offset = 0; | |
360 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
361 | int bank; | |
362 | ||
363 | switch (chip->chip_type) { | |
364 | case PCA953X_TYPE: | |
365 | offset = PCA953X_OUTPUT; | |
366 | break; | |
367 | case PCA957X_TYPE: | |
368 | offset = PCA957X_OUT; | |
369 | break; | |
370 | } | |
371 | ||
372 | memcpy(reg_val, chip->reg_output, NBANK(chip)); | |
373 | mutex_lock(&chip->i2c_lock); | |
374 | for(bank=0; bank<NBANK(chip); bank++) { | |
375 | unsigned bankmask = mask[bank/4] >> ((bank % 4) * 8); | |
376 | if(bankmask) { | |
377 | unsigned bankval = bits[bank/4] >> ((bank % 4) * 8); | |
378 | reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval; | |
379 | } | |
380 | } | |
381 | ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val); | |
382 | if (ret) | |
383 | goto exit; | |
384 | ||
385 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
386 | exit: | |
387 | mutex_unlock(&chip->i2c_lock); | |
388 | } | |
389 | ||
f5e8ff48 | 390 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 391 | { |
392 | struct gpio_chip *gc; | |
393 | ||
394 | gc = &chip->gpio_chip; | |
395 | ||
f3dc3630 GL |
396 | gc->direction_input = pca953x_gpio_direction_input; |
397 | gc->direction_output = pca953x_gpio_direction_output; | |
398 | gc->get = pca953x_gpio_get_value; | |
399 | gc->set = pca953x_gpio_set_value; | |
b4818afe | 400 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 401 | gc->can_sleep = true; |
9e60fdcf | 402 | |
403 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
404 | gc->ngpio = gpios; |
405 | gc->label = chip->client->name; | |
58383c78 | 406 | gc->parent = &chip->client->dev; |
d72cbed0 | 407 | gc->owner = THIS_MODULE; |
77906a54 | 408 | gc->names = chip->names; |
9e60fdcf | 409 | } |
410 | ||
89ea8bbe | 411 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 412 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 413 | { |
7bcbce55 LW |
414 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
415 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe | 416 | |
f5f0b7aa | 417 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
418 | } |
419 | ||
6f5cfc0e | 420 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 421 | { |
7bcbce55 LW |
422 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
423 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe | 424 | |
f5f0b7aa | 425 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
426 | } |
427 | ||
6f5cfc0e | 428 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 429 | { |
7bcbce55 LW |
430 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
431 | struct pca953x_chip *chip = to_pca(gc); | |
89ea8bbe MZ |
432 | |
433 | mutex_lock(&chip->irq_lock); | |
434 | } | |
435 | ||
6f5cfc0e | 436 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 437 | { |
7bcbce55 LW |
438 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
439 | struct pca953x_chip *chip = to_pca(gc); | |
f5f0b7aa GC |
440 | u8 new_irqs; |
441 | int level, i; | |
a2cb9aeb MZ |
442 | |
443 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
444 | for (i = 0; i < NBANK(chip); i++) { |
445 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
446 | new_irqs &= ~chip->reg_direction[i]; | |
447 | ||
448 | while (new_irqs) { | |
449 | level = __ffs(new_irqs); | |
450 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
451 | level + (BANK_SZ * i)); | |
452 | new_irqs &= ~(1 << level); | |
453 | } | |
a2cb9aeb | 454 | } |
89ea8bbe MZ |
455 | |
456 | mutex_unlock(&chip->irq_lock); | |
457 | } | |
458 | ||
6f5cfc0e | 459 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 460 | { |
7bcbce55 LW |
461 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
462 | struct pca953x_chip *chip = to_pca(gc); | |
f5f0b7aa GC |
463 | int bank_nb = d->hwirq / BANK_SZ; |
464 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
465 | |
466 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
467 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 468 | d->irq, type); |
89ea8bbe MZ |
469 | return -EINVAL; |
470 | } | |
471 | ||
472 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 473 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 474 | else |
f5f0b7aa | 475 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
476 | |
477 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 478 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 479 | else |
f5f0b7aa | 480 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 481 | |
a2cb9aeb | 482 | return 0; |
89ea8bbe MZ |
483 | } |
484 | ||
485 | static struct irq_chip pca953x_irq_chip = { | |
486 | .name = "pca953x", | |
6f5cfc0e LB |
487 | .irq_mask = pca953x_irq_mask, |
488 | .irq_unmask = pca953x_irq_unmask, | |
489 | .irq_bus_lock = pca953x_irq_bus_lock, | |
490 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
491 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
492 | }; |
493 | ||
b6ac1280 | 494 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 495 | { |
f5f0b7aa GC |
496 | u8 cur_stat[MAX_BANK]; |
497 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
498 | bool pending_seen = false; |
499 | bool trigger_seen = false; | |
500 | u8 trigger[MAX_BANK]; | |
f5f0b7aa | 501 | int ret, i, offset = 0; |
33226ffd HZ |
502 | |
503 | switch (chip->chip_type) { | |
504 | case PCA953X_TYPE: | |
505 | offset = PCA953X_INPUT; | |
506 | break; | |
507 | case PCA957X_TYPE: | |
508 | offset = PCA957X_IN; | |
509 | break; | |
510 | } | |
f5f0b7aa | 511 | ret = pca953x_read_regs(chip, offset, cur_stat); |
89ea8bbe | 512 | if (ret) |
b6ac1280 | 513 | return false; |
89ea8bbe MZ |
514 | |
515 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
516 | for (i = 0; i < NBANK(chip); i++) |
517 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 518 | |
f5f0b7aa | 519 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 520 | |
f5f0b7aa GC |
521 | for (i = 0; i < NBANK(chip); i++) { |
522 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
523 | if (trigger[i]) |
524 | trigger_seen = true; | |
f5f0b7aa GC |
525 | } |
526 | ||
b6ac1280 JS |
527 | if (!trigger_seen) |
528 | return false; | |
89ea8bbe | 529 | |
f5f0b7aa | 530 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 531 | |
f5f0b7aa GC |
532 | for (i = 0; i < NBANK(chip); i++) { |
533 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
534 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
535 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
536 | if (pending[i]) |
537 | pending_seen = true; | |
f5f0b7aa | 538 | } |
89ea8bbe | 539 | |
b6ac1280 | 540 | return pending_seen; |
89ea8bbe MZ |
541 | } |
542 | ||
543 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
544 | { | |
545 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
546 | u8 pending[MAX_BANK]; |
547 | u8 level; | |
3275d072 | 548 | unsigned nhandled = 0; |
f5f0b7aa | 549 | int i; |
89ea8bbe | 550 | |
f5f0b7aa | 551 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 552 | return IRQ_NONE; |
89ea8bbe | 553 | |
f5f0b7aa GC |
554 | for (i = 0; i < NBANK(chip); i++) { |
555 | while (pending[i]) { | |
556 | level = __ffs(pending[i]); | |
7bcbce55 | 557 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
558 | level + (BANK_SZ * i))); |
559 | pending[i] &= ~(1 << level); | |
3275d072 | 560 | nhandled++; |
f5f0b7aa GC |
561 | } |
562 | } | |
89ea8bbe | 563 | |
3275d072 | 564 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
565 | } |
566 | ||
567 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 568 | int irq_base) |
89ea8bbe MZ |
569 | { |
570 | struct i2c_client *client = chip->client; | |
f5f0b7aa | 571 | int ret, i, offset = 0; |
89ea8bbe | 572 | |
4bb93349 | 573 | if (client->irq && irq_base != -1 |
c6664149 | 574 | && (chip->driver_data & PCA_INT)) { |
89ea8bbe | 575 | |
33226ffd HZ |
576 | switch (chip->chip_type) { |
577 | case PCA953X_TYPE: | |
578 | offset = PCA953X_INPUT; | |
579 | break; | |
580 | case PCA957X_TYPE: | |
581 | offset = PCA957X_IN; | |
582 | break; | |
583 | } | |
f5f0b7aa | 584 | ret = pca953x_read_regs(chip, offset, chip->irq_stat); |
89ea8bbe | 585 | if (ret) |
b42748c9 | 586 | return ret; |
89ea8bbe MZ |
587 | |
588 | /* | |
589 | * There is no way to know which GPIO line generated the | |
590 | * interrupt. We have to rely on the previous read for | |
591 | * this purpose. | |
592 | */ | |
f5f0b7aa GC |
593 | for (i = 0; i < NBANK(chip); i++) |
594 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
595 | mutex_init(&chip->irq_lock); |
596 | ||
b42748c9 LW |
597 | ret = devm_request_threaded_irq(&client->dev, |
598 | client->irq, | |
89ea8bbe MZ |
599 | NULL, |
600 | pca953x_irq_handler, | |
91329132 TS |
601 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
602 | IRQF_SHARED, | |
89ea8bbe MZ |
603 | dev_name(&client->dev), chip); |
604 | if (ret) { | |
605 | dev_err(&client->dev, "failed to request irq %d\n", | |
606 | client->irq); | |
0e8f2fda | 607 | return ret; |
89ea8bbe MZ |
608 | } |
609 | ||
7bcbce55 LW |
610 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
611 | &pca953x_irq_chip, | |
612 | irq_base, | |
613 | handle_simple_irq, | |
614 | IRQ_TYPE_NONE); | |
615 | if (ret) { | |
616 | dev_err(&client->dev, | |
617 | "could not connect irqchip to gpiochip\n"); | |
618 | return ret; | |
619 | } | |
fdd50409 GS |
620 | |
621 | gpiochip_set_chained_irqchip(&chip->gpio_chip, | |
622 | &pca953x_irq_chip, | |
623 | client->irq, NULL); | |
89ea8bbe MZ |
624 | } |
625 | ||
626 | return 0; | |
89ea8bbe MZ |
627 | } |
628 | ||
89ea8bbe MZ |
629 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
630 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 631 | int irq_base) |
89ea8bbe MZ |
632 | { |
633 | struct i2c_client *client = chip->client; | |
89ea8bbe | 634 | |
c6664149 | 635 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
636 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
637 | ||
638 | return 0; | |
639 | } | |
89ea8bbe MZ |
640 | #endif |
641 | ||
3836309d | 642 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
643 | { |
644 | int ret; | |
f5f0b7aa | 645 | u8 val[MAX_BANK]; |
33226ffd | 646 | |
f5f0b7aa | 647 | ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output); |
33226ffd HZ |
648 | if (ret) |
649 | goto out; | |
650 | ||
f5f0b7aa GC |
651 | ret = pca953x_read_regs(chip, PCA953X_DIRECTION, |
652 | chip->reg_direction); | |
33226ffd HZ |
653 | if (ret) |
654 | goto out; | |
655 | ||
656 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
657 | if (invert) |
658 | memset(val, 0xFF, NBANK(chip)); | |
659 | else | |
660 | memset(val, 0, NBANK(chip)); | |
661 | ||
662 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
663 | out: |
664 | return ret; | |
665 | } | |
666 | ||
3836309d | 667 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
668 | { |
669 | int ret; | |
f5f0b7aa | 670 | u8 val[MAX_BANK]; |
33226ffd | 671 | |
f5f0b7aa | 672 | ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output); |
33226ffd HZ |
673 | if (ret) |
674 | goto out; | |
f5f0b7aa | 675 | ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction); |
33226ffd HZ |
676 | if (ret) |
677 | goto out; | |
678 | ||
679 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
680 | if (invert) |
681 | memset(val, 0xFF, NBANK(chip)); | |
682 | else | |
683 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
684 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
685 | if (ret) | |
686 | goto out; | |
33226ffd | 687 | |
20a8a968 | 688 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 689 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
690 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
691 | if (ret) | |
692 | goto out; | |
33226ffd HZ |
693 | |
694 | return 0; | |
695 | out: | |
696 | return ret; | |
697 | } | |
698 | ||
6f29c9af BD |
699 | static const struct of_device_id pca953x_dt_ids[]; |
700 | ||
3836309d | 701 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 702 | const struct i2c_device_id *id) |
9e60fdcf | 703 | { |
f3dc3630 GL |
704 | struct pca953x_platform_data *pdata; |
705 | struct pca953x_chip *chip; | |
6a7b36aa | 706 | int irq_base = 0; |
7ea2aa20 | 707 | int ret; |
6a7b36aa | 708 | u32 invert = 0; |
9e60fdcf | 709 | |
b42748c9 LW |
710 | chip = devm_kzalloc(&client->dev, |
711 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
712 | if (chip == NULL) |
713 | return -ENOMEM; | |
714 | ||
e56aee18 | 715 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
716 | if (pdata) { |
717 | irq_base = pdata->irq_base; | |
718 | chip->gpio_start = pdata->gpio_base; | |
719 | invert = pdata->invert; | |
720 | chip->names = pdata->names; | |
721 | } else { | |
4bb93349 MP |
722 | chip->gpio_start = -1; |
723 | irq_base = 0; | |
1965d303 | 724 | } |
9e60fdcf | 725 | |
726 | chip->client = client; | |
727 | ||
f32517bf AS |
728 | if (id) { |
729 | chip->driver_data = id->driver_data; | |
730 | } else { | |
731 | const struct acpi_device_id *id; | |
6f29c9af | 732 | const struct of_device_id *match; |
f32517bf | 733 | |
6f29c9af BD |
734 | match = of_match_device(pca953x_dt_ids, &client->dev); |
735 | if (match) { | |
736 | chip->driver_data = (int)(uintptr_t)match->data; | |
737 | } else { | |
738 | id = acpi_match_device(pca953x_acpi_ids, &client->dev); | |
739 | if (!id) | |
740 | return -ENODEV; | |
f32517bf | 741 | |
6f29c9af BD |
742 | chip->driver_data = id->driver_data; |
743 | } | |
f32517bf AS |
744 | } |
745 | ||
c6664149 | 746 | chip->chip_type = PCA_CHIP_TYPE(chip->driver_data); |
77906a54 | 747 | |
6e20fb18 RS |
748 | mutex_init(&chip->i2c_lock); |
749 | ||
9e60fdcf | 750 | /* initialize cached registers from their original values. |
751 | * we can't share this chip with another i2c master. | |
752 | */ | |
c6664149 | 753 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 754 | |
33226ffd | 755 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 756 | ret = device_pca953x_init(chip, invert); |
33226ffd | 757 | else |
7ea2aa20 WS |
758 | ret = device_pca957x_init(chip, invert); |
759 | if (ret) | |
b42748c9 | 760 | return ret; |
9e60fdcf | 761 | |
7bcbce55 | 762 | ret = gpiochip_add(&chip->gpio_chip); |
89ea8bbe | 763 | if (ret) |
b42748c9 | 764 | return ret; |
f5e8ff48 | 765 | |
c6664149 | 766 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 767 | if (ret) |
b42748c9 | 768 | return ret; |
9e60fdcf | 769 | |
c6dcf592 | 770 | if (pdata && pdata->setup) { |
9e60fdcf | 771 | ret = pdata->setup(client, chip->gpio_chip.base, |
772 | chip->gpio_chip.ngpio, pdata->context); | |
773 | if (ret < 0) | |
774 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
775 | } | |
776 | ||
777 | i2c_set_clientdata(client, chip); | |
778 | return 0; | |
9e60fdcf | 779 | } |
780 | ||
f3dc3630 | 781 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 782 | { |
e56aee18 | 783 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 784 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
9e60fdcf | 785 | int ret = 0; |
786 | ||
c6dcf592 | 787 | if (pdata && pdata->teardown) { |
9e60fdcf | 788 | ret = pdata->teardown(client, chip->gpio_chip.base, |
789 | chip->gpio_chip.ngpio, pdata->context); | |
790 | if (ret < 0) { | |
791 | dev_err(&client->dev, "%s failed, %d\n", | |
792 | "teardown", ret); | |
793 | return ret; | |
794 | } | |
795 | } | |
796 | ||
9f5132ae | 797 | gpiochip_remove(&chip->gpio_chip); |
9e60fdcf | 798 | |
9e60fdcf | 799 | return 0; |
800 | } | |
801 | ||
6f29c9af BD |
802 | /* convenience to stop overlong match-table lines */ |
803 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
804 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
805 | ||
ed32620e | 806 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
807 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
808 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
809 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
810 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
811 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
812 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
813 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
814 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
815 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
816 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
817 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
818 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
819 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
820 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
821 | ||
822 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, | |
823 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
824 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
825 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
826 | ||
827 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
828 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, | |
829 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
830 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
831 | ||
832 | { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, | |
833 | ||
834 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
835 | { } |
836 | }; | |
837 | ||
838 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
839 | ||
f3dc3630 | 840 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 841 | .driver = { |
f3dc3630 | 842 | .name = "pca953x", |
ed32620e | 843 | .of_match_table = pca953x_dt_ids, |
f32517bf | 844 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 845 | }, |
f3dc3630 GL |
846 | .probe = pca953x_probe, |
847 | .remove = pca953x_remove, | |
3760f736 | 848 | .id_table = pca953x_id, |
9e60fdcf | 849 | }; |
850 | ||
f3dc3630 | 851 | static int __init pca953x_init(void) |
9e60fdcf | 852 | { |
f3dc3630 | 853 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 854 | } |
2f8d1197 DB |
855 | /* register after i2c postcore initcall and before |
856 | * subsys initcalls that may rely on these GPIOs | |
857 | */ | |
858 | subsys_initcall(pca953x_init); | |
9e60fdcf | 859 | |
f3dc3630 | 860 | static void __exit pca953x_exit(void) |
9e60fdcf | 861 | { |
f3dc3630 | 862 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 863 | } |
f3dc3630 | 864 | module_exit(pca953x_exit); |
9e60fdcf | 865 | |
866 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 867 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 868 | MODULE_LICENSE("GPL"); |