Commit | Line | Data |
---|---|---|
9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1965d303 | 21 | #include <linux/of_platform.h> |
f32517bf | 22 | #include <linux/acpi.h> |
9e60fdcf | 23 | |
33226ffd HZ |
24 | #define PCA953X_INPUT 0 |
25 | #define PCA953X_OUTPUT 1 | |
26 | #define PCA953X_INVERT 2 | |
27 | #define PCA953X_DIRECTION 3 | |
28 | ||
ae79c190 AS |
29 | #define REG_ADDR_AI 0x80 |
30 | ||
33226ffd HZ |
31 | #define PCA957X_IN 0 |
32 | #define PCA957X_INVRT 1 | |
33 | #define PCA957X_BKEN 2 | |
34 | #define PCA957X_PUPD 3 | |
35 | #define PCA957X_CFG 4 | |
36 | #define PCA957X_OUT 5 | |
37 | #define PCA957X_MSK 6 | |
38 | #define PCA957X_INTS 7 | |
39 | ||
40 | #define PCA_GPIO_MASK 0x00FF | |
41 | #define PCA_INT 0x0100 | |
42 | #define PCA953X_TYPE 0x1000 | |
43 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
44 | #define PCA_TYPE_MASK 0xF000 |
45 | ||
46 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 47 | |
3760f736 | 48 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 49 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
50 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
51 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
52 | { "pca9536", 4 | PCA953X_TYPE, }, | |
53 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
54 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
55 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
56 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
57 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
58 | { "pca9556", 8 | PCA953X_TYPE, }, | |
59 | { "pca9557", 8 | PCA953X_TYPE, }, | |
60 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
61 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 62 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd HZ |
63 | |
64 | { "max7310", 8 | PCA953X_TYPE, }, | |
65 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
66 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
67 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
68 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
69 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
70 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 71 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 72 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 73 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 74 | { } |
f5e8ff48 | 75 | }; |
3760f736 | 76 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 77 | |
f32517bf AS |
78 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
79 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT, }, | |
80 | { } | |
81 | }; | |
82 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
83 | ||
f5f0b7aa GC |
84 | #define MAX_BANK 5 |
85 | #define BANK_SZ 8 | |
86 | ||
87 | #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ) | |
88 | ||
f3dc3630 | 89 | struct pca953x_chip { |
9e60fdcf | 90 | unsigned gpio_start; |
f5f0b7aa GC |
91 | u8 reg_output[MAX_BANK]; |
92 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 93 | struct mutex i2c_lock; |
9e60fdcf | 94 | |
89ea8bbe MZ |
95 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
96 | struct mutex irq_lock; | |
f5f0b7aa GC |
97 | u8 irq_mask[MAX_BANK]; |
98 | u8 irq_stat[MAX_BANK]; | |
99 | u8 irq_trig_raise[MAX_BANK]; | |
100 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
101 | #endif |
102 | ||
9e60fdcf | 103 | struct i2c_client *client; |
104 | struct gpio_chip gpio_chip; | |
62154991 | 105 | const char *const *names; |
33226ffd | 106 | int chip_type; |
c6664149 | 107 | unsigned long driver_data; |
9e60fdcf | 108 | }; |
109 | ||
f5f0b7aa GC |
110 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
111 | int off) | |
112 | { | |
113 | int ret; | |
114 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
115 | int offset = off / BANK_SZ; | |
116 | ||
117 | ret = i2c_smbus_read_byte_data(chip->client, | |
118 | (reg << bank_shift) + offset); | |
119 | *val = ret; | |
120 | ||
121 | if (ret < 0) { | |
122 | dev_err(&chip->client->dev, "failed reading register\n"); | |
123 | return ret; | |
124 | } | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
129 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
130 | int off) | |
131 | { | |
132 | int ret = 0; | |
133 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
134 | int offset = off / BANK_SZ; | |
135 | ||
136 | ret = i2c_smbus_write_byte_data(chip->client, | |
137 | (reg << bank_shift) + offset, val); | |
138 | ||
139 | if (ret < 0) { | |
140 | dev_err(&chip->client->dev, "failed writing register\n"); | |
141 | return ret; | |
142 | } | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
9e60fdcf | 148 | { |
33226ffd | 149 | int ret = 0; |
f5e8ff48 GL |
150 | |
151 | if (chip->gpio_chip.ngpio <= 8) | |
f5f0b7aa GC |
152 | ret = i2c_smbus_write_byte_data(chip->client, reg, *val); |
153 | else if (chip->gpio_chip.ngpio >= 24) { | |
154 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
96b70641 | 155 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
f5f0b7aa GC |
156 | (reg << bank_shift) | REG_ADDR_AI, |
157 | NBANK(chip), val); | |
50e44430 | 158 | } else { |
33226ffd HZ |
159 | switch (chip->chip_type) { |
160 | case PCA953X_TYPE: | |
161 | ret = i2c_smbus_write_word_data(chip->client, | |
f5f0b7aa | 162 | reg << 1, (u16) *val); |
33226ffd HZ |
163 | break; |
164 | case PCA957X_TYPE: | |
165 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
f5f0b7aa | 166 | val[0]); |
33226ffd HZ |
167 | if (ret < 0) |
168 | break; | |
169 | ret = i2c_smbus_write_byte_data(chip->client, | |
170 | (reg << 1) + 1, | |
f5f0b7aa | 171 | val[1]); |
33226ffd HZ |
172 | break; |
173 | } | |
174 | } | |
f5e8ff48 GL |
175 | |
176 | if (ret < 0) { | |
177 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 178 | return ret; |
f5e8ff48 GL |
179 | } |
180 | ||
181 | return 0; | |
9e60fdcf | 182 | } |
183 | ||
f5f0b7aa | 184 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 185 | { |
186 | int ret; | |
187 | ||
96b70641 | 188 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 189 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 190 | *val = ret; |
f5f0b7aa GC |
191 | } else if (chip->gpio_chip.ngpio >= 24) { |
192 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
193 | ||
96b70641 | 194 | ret = i2c_smbus_read_i2c_block_data(chip->client, |
f5f0b7aa GC |
195 | (reg << bank_shift) | REG_ADDR_AI, |
196 | NBANK(chip), val); | |
96b70641 | 197 | } else { |
f5e8ff48 | 198 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
f5f0b7aa GC |
199 | val[0] = (u16)ret & 0xFF; |
200 | val[1] = (u16)ret >> 8; | |
96b70641 | 201 | } |
9e60fdcf | 202 | if (ret < 0) { |
203 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 204 | return ret; |
9e60fdcf | 205 | } |
206 | ||
9e60fdcf | 207 | return 0; |
208 | } | |
209 | ||
f3dc3630 | 210 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 211 | { |
468e67f6 | 212 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 213 | u8 reg_val; |
33226ffd | 214 | int ret, offset = 0; |
9e60fdcf | 215 | |
6e20fb18 | 216 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 217 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd HZ |
218 | |
219 | switch (chip->chip_type) { | |
220 | case PCA953X_TYPE: | |
221 | offset = PCA953X_DIRECTION; | |
222 | break; | |
223 | case PCA957X_TYPE: | |
224 | offset = PCA957X_CFG; | |
225 | break; | |
226 | } | |
f5f0b7aa | 227 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 228 | if (ret) |
6e20fb18 | 229 | goto exit; |
9e60fdcf | 230 | |
f5f0b7aa | 231 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
232 | ret = 0; |
233 | exit: | |
234 | mutex_unlock(&chip->i2c_lock); | |
235 | return ret; | |
9e60fdcf | 236 | } |
237 | ||
f3dc3630 | 238 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 239 | unsigned off, int val) |
240 | { | |
468e67f6 | 241 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 242 | u8 reg_val; |
33226ffd | 243 | int ret, offset = 0; |
9e60fdcf | 244 | |
6e20fb18 | 245 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 246 | /* set output level */ |
247 | if (val) | |
f5f0b7aa GC |
248 | reg_val = chip->reg_output[off / BANK_SZ] |
249 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 250 | else |
f5f0b7aa GC |
251 | reg_val = chip->reg_output[off / BANK_SZ] |
252 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 253 | |
33226ffd HZ |
254 | switch (chip->chip_type) { |
255 | case PCA953X_TYPE: | |
256 | offset = PCA953X_OUTPUT; | |
257 | break; | |
258 | case PCA957X_TYPE: | |
259 | offset = PCA957X_OUT; | |
260 | break; | |
261 | } | |
f5f0b7aa | 262 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 263 | if (ret) |
6e20fb18 | 264 | goto exit; |
9e60fdcf | 265 | |
f5f0b7aa | 266 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 267 | |
268 | /* then direction */ | |
f5f0b7aa | 269 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
33226ffd HZ |
270 | switch (chip->chip_type) { |
271 | case PCA953X_TYPE: | |
272 | offset = PCA953X_DIRECTION; | |
273 | break; | |
274 | case PCA957X_TYPE: | |
275 | offset = PCA957X_CFG; | |
276 | break; | |
277 | } | |
f5f0b7aa | 278 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 279 | if (ret) |
6e20fb18 | 280 | goto exit; |
9e60fdcf | 281 | |
f5f0b7aa | 282 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
283 | ret = 0; |
284 | exit: | |
285 | mutex_unlock(&chip->i2c_lock); | |
286 | return ret; | |
9e60fdcf | 287 | } |
288 | ||
f3dc3630 | 289 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 290 | { |
468e67f6 | 291 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 292 | u32 reg_val; |
33226ffd | 293 | int ret, offset = 0; |
9e60fdcf | 294 | |
6e20fb18 | 295 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
296 | switch (chip->chip_type) { |
297 | case PCA953X_TYPE: | |
298 | offset = PCA953X_INPUT; | |
299 | break; | |
300 | case PCA957X_TYPE: | |
301 | offset = PCA957X_IN; | |
302 | break; | |
303 | } | |
f5f0b7aa | 304 | ret = pca953x_read_single(chip, offset, ®_val, off); |
6e20fb18 | 305 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 306 | if (ret < 0) { |
307 | /* NOTE: diagnostic already emitted; that's all we should | |
308 | * do unless gpio_*_value_cansleep() calls become different | |
309 | * from their nonsleeping siblings (and report faults). | |
310 | */ | |
311 | return 0; | |
312 | } | |
313 | ||
40a625da | 314 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 315 | } |
316 | ||
f3dc3630 | 317 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 318 | { |
468e67f6 | 319 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 320 | u8 reg_val; |
33226ffd | 321 | int ret, offset = 0; |
9e60fdcf | 322 | |
6e20fb18 | 323 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 324 | if (val) |
f5f0b7aa GC |
325 | reg_val = chip->reg_output[off / BANK_SZ] |
326 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 327 | else |
f5f0b7aa GC |
328 | reg_val = chip->reg_output[off / BANK_SZ] |
329 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 330 | |
33226ffd HZ |
331 | switch (chip->chip_type) { |
332 | case PCA953X_TYPE: | |
333 | offset = PCA953X_OUTPUT; | |
334 | break; | |
335 | case PCA957X_TYPE: | |
336 | offset = PCA957X_OUT; | |
337 | break; | |
338 | } | |
f5f0b7aa | 339 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 340 | if (ret) |
6e20fb18 | 341 | goto exit; |
9e60fdcf | 342 | |
f5f0b7aa | 343 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
344 | exit: |
345 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 346 | } |
347 | ||
b4818afe PR |
348 | |
349 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, | |
350 | unsigned long *mask, unsigned long *bits) | |
351 | { | |
468e67f6 | 352 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
b4818afe PR |
353 | u8 reg_val[MAX_BANK]; |
354 | int ret, offset = 0; | |
355 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
356 | int bank; | |
357 | ||
358 | switch (chip->chip_type) { | |
359 | case PCA953X_TYPE: | |
360 | offset = PCA953X_OUTPUT; | |
361 | break; | |
362 | case PCA957X_TYPE: | |
363 | offset = PCA957X_OUT; | |
364 | break; | |
365 | } | |
366 | ||
367 | memcpy(reg_val, chip->reg_output, NBANK(chip)); | |
368 | mutex_lock(&chip->i2c_lock); | |
369 | for(bank=0; bank<NBANK(chip); bank++) { | |
370 | unsigned bankmask = mask[bank/4] >> ((bank % 4) * 8); | |
371 | if(bankmask) { | |
372 | unsigned bankval = bits[bank/4] >> ((bank % 4) * 8); | |
373 | reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval; | |
374 | } | |
375 | } | |
376 | ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val); | |
377 | if (ret) | |
378 | goto exit; | |
379 | ||
380 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
381 | exit: | |
382 | mutex_unlock(&chip->i2c_lock); | |
383 | } | |
384 | ||
f5e8ff48 | 385 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 386 | { |
387 | struct gpio_chip *gc; | |
388 | ||
389 | gc = &chip->gpio_chip; | |
390 | ||
f3dc3630 GL |
391 | gc->direction_input = pca953x_gpio_direction_input; |
392 | gc->direction_output = pca953x_gpio_direction_output; | |
393 | gc->get = pca953x_gpio_get_value; | |
394 | gc->set = pca953x_gpio_set_value; | |
b4818afe | 395 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 396 | gc->can_sleep = true; |
9e60fdcf | 397 | |
398 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
399 | gc->ngpio = gpios; |
400 | gc->label = chip->client->name; | |
58383c78 | 401 | gc->parent = &chip->client->dev; |
d72cbed0 | 402 | gc->owner = THIS_MODULE; |
77906a54 | 403 | gc->names = chip->names; |
9e60fdcf | 404 | } |
405 | ||
89ea8bbe | 406 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 407 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 408 | { |
7bcbce55 | 409 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 410 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 411 | |
f5f0b7aa | 412 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
413 | } |
414 | ||
6f5cfc0e | 415 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 416 | { |
7bcbce55 | 417 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 418 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 419 | |
f5f0b7aa | 420 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
421 | } |
422 | ||
6f5cfc0e | 423 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 424 | { |
7bcbce55 | 425 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 426 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
427 | |
428 | mutex_lock(&chip->irq_lock); | |
429 | } | |
430 | ||
6f5cfc0e | 431 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 432 | { |
7bcbce55 | 433 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 434 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
435 | u8 new_irqs; |
436 | int level, i; | |
a2cb9aeb MZ |
437 | |
438 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
439 | for (i = 0; i < NBANK(chip); i++) { |
440 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
441 | new_irqs &= ~chip->reg_direction[i]; | |
442 | ||
443 | while (new_irqs) { | |
444 | level = __ffs(new_irqs); | |
445 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
446 | level + (BANK_SZ * i)); | |
447 | new_irqs &= ~(1 << level); | |
448 | } | |
a2cb9aeb | 449 | } |
89ea8bbe MZ |
450 | |
451 | mutex_unlock(&chip->irq_lock); | |
452 | } | |
453 | ||
6f5cfc0e | 454 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 455 | { |
7bcbce55 | 456 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 457 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
458 | int bank_nb = d->hwirq / BANK_SZ; |
459 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
460 | |
461 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
462 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 463 | d->irq, type); |
89ea8bbe MZ |
464 | return -EINVAL; |
465 | } | |
466 | ||
467 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 468 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 469 | else |
f5f0b7aa | 470 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
471 | |
472 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 473 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 474 | else |
f5f0b7aa | 475 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 476 | |
a2cb9aeb | 477 | return 0; |
89ea8bbe MZ |
478 | } |
479 | ||
480 | static struct irq_chip pca953x_irq_chip = { | |
481 | .name = "pca953x", | |
6f5cfc0e LB |
482 | .irq_mask = pca953x_irq_mask, |
483 | .irq_unmask = pca953x_irq_unmask, | |
484 | .irq_bus_lock = pca953x_irq_bus_lock, | |
485 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
486 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
487 | }; |
488 | ||
b6ac1280 | 489 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 490 | { |
f5f0b7aa GC |
491 | u8 cur_stat[MAX_BANK]; |
492 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
493 | bool pending_seen = false; |
494 | bool trigger_seen = false; | |
495 | u8 trigger[MAX_BANK]; | |
f5f0b7aa | 496 | int ret, i, offset = 0; |
33226ffd HZ |
497 | |
498 | switch (chip->chip_type) { | |
499 | case PCA953X_TYPE: | |
500 | offset = PCA953X_INPUT; | |
501 | break; | |
502 | case PCA957X_TYPE: | |
503 | offset = PCA957X_IN; | |
504 | break; | |
505 | } | |
f5f0b7aa | 506 | ret = pca953x_read_regs(chip, offset, cur_stat); |
89ea8bbe | 507 | if (ret) |
b6ac1280 | 508 | return false; |
89ea8bbe MZ |
509 | |
510 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
511 | for (i = 0; i < NBANK(chip); i++) |
512 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 513 | |
f5f0b7aa | 514 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 515 | |
f5f0b7aa GC |
516 | for (i = 0; i < NBANK(chip); i++) { |
517 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
518 | if (trigger[i]) |
519 | trigger_seen = true; | |
f5f0b7aa GC |
520 | } |
521 | ||
b6ac1280 JS |
522 | if (!trigger_seen) |
523 | return false; | |
89ea8bbe | 524 | |
f5f0b7aa | 525 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 526 | |
f5f0b7aa GC |
527 | for (i = 0; i < NBANK(chip); i++) { |
528 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
529 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
530 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
531 | if (pending[i]) |
532 | pending_seen = true; | |
f5f0b7aa | 533 | } |
89ea8bbe | 534 | |
b6ac1280 | 535 | return pending_seen; |
89ea8bbe MZ |
536 | } |
537 | ||
538 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
539 | { | |
540 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
541 | u8 pending[MAX_BANK]; |
542 | u8 level; | |
3275d072 | 543 | unsigned nhandled = 0; |
f5f0b7aa | 544 | int i; |
89ea8bbe | 545 | |
f5f0b7aa | 546 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 547 | return IRQ_NONE; |
89ea8bbe | 548 | |
f5f0b7aa GC |
549 | for (i = 0; i < NBANK(chip); i++) { |
550 | while (pending[i]) { | |
551 | level = __ffs(pending[i]); | |
7bcbce55 | 552 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
553 | level + (BANK_SZ * i))); |
554 | pending[i] &= ~(1 << level); | |
3275d072 | 555 | nhandled++; |
f5f0b7aa GC |
556 | } |
557 | } | |
89ea8bbe | 558 | |
3275d072 | 559 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
560 | } |
561 | ||
562 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 563 | int irq_base) |
89ea8bbe MZ |
564 | { |
565 | struct i2c_client *client = chip->client; | |
f5f0b7aa | 566 | int ret, i, offset = 0; |
89ea8bbe | 567 | |
4bb93349 | 568 | if (client->irq && irq_base != -1 |
c6664149 | 569 | && (chip->driver_data & PCA_INT)) { |
89ea8bbe | 570 | |
33226ffd HZ |
571 | switch (chip->chip_type) { |
572 | case PCA953X_TYPE: | |
573 | offset = PCA953X_INPUT; | |
574 | break; | |
575 | case PCA957X_TYPE: | |
576 | offset = PCA957X_IN; | |
577 | break; | |
578 | } | |
f5f0b7aa | 579 | ret = pca953x_read_regs(chip, offset, chip->irq_stat); |
89ea8bbe | 580 | if (ret) |
b42748c9 | 581 | return ret; |
89ea8bbe MZ |
582 | |
583 | /* | |
584 | * There is no way to know which GPIO line generated the | |
585 | * interrupt. We have to rely on the previous read for | |
586 | * this purpose. | |
587 | */ | |
f5f0b7aa GC |
588 | for (i = 0; i < NBANK(chip); i++) |
589 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
590 | mutex_init(&chip->irq_lock); |
591 | ||
b42748c9 LW |
592 | ret = devm_request_threaded_irq(&client->dev, |
593 | client->irq, | |
89ea8bbe MZ |
594 | NULL, |
595 | pca953x_irq_handler, | |
91329132 TS |
596 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
597 | IRQF_SHARED, | |
89ea8bbe MZ |
598 | dev_name(&client->dev), chip); |
599 | if (ret) { | |
600 | dev_err(&client->dev, "failed to request irq %d\n", | |
601 | client->irq); | |
0e8f2fda | 602 | return ret; |
89ea8bbe MZ |
603 | } |
604 | ||
7bcbce55 LW |
605 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
606 | &pca953x_irq_chip, | |
607 | irq_base, | |
608 | handle_simple_irq, | |
609 | IRQ_TYPE_NONE); | |
610 | if (ret) { | |
611 | dev_err(&client->dev, | |
612 | "could not connect irqchip to gpiochip\n"); | |
613 | return ret; | |
614 | } | |
fdd50409 GS |
615 | |
616 | gpiochip_set_chained_irqchip(&chip->gpio_chip, | |
617 | &pca953x_irq_chip, | |
618 | client->irq, NULL); | |
89ea8bbe MZ |
619 | } |
620 | ||
621 | return 0; | |
89ea8bbe MZ |
622 | } |
623 | ||
89ea8bbe MZ |
624 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
625 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 626 | int irq_base) |
89ea8bbe MZ |
627 | { |
628 | struct i2c_client *client = chip->client; | |
89ea8bbe | 629 | |
c6664149 | 630 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
631 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
632 | ||
633 | return 0; | |
634 | } | |
89ea8bbe MZ |
635 | #endif |
636 | ||
3836309d | 637 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
638 | { |
639 | int ret; | |
f5f0b7aa | 640 | u8 val[MAX_BANK]; |
33226ffd | 641 | |
f5f0b7aa | 642 | ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output); |
33226ffd HZ |
643 | if (ret) |
644 | goto out; | |
645 | ||
f5f0b7aa GC |
646 | ret = pca953x_read_regs(chip, PCA953X_DIRECTION, |
647 | chip->reg_direction); | |
33226ffd HZ |
648 | if (ret) |
649 | goto out; | |
650 | ||
651 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
652 | if (invert) |
653 | memset(val, 0xFF, NBANK(chip)); | |
654 | else | |
655 | memset(val, 0, NBANK(chip)); | |
656 | ||
657 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
658 | out: |
659 | return ret; | |
660 | } | |
661 | ||
3836309d | 662 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
663 | { |
664 | int ret; | |
f5f0b7aa | 665 | u8 val[MAX_BANK]; |
33226ffd | 666 | |
f5f0b7aa | 667 | ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output); |
33226ffd HZ |
668 | if (ret) |
669 | goto out; | |
f5f0b7aa | 670 | ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction); |
33226ffd HZ |
671 | if (ret) |
672 | goto out; | |
673 | ||
674 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
675 | if (invert) |
676 | memset(val, 0xFF, NBANK(chip)); | |
677 | else | |
678 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
679 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
680 | if (ret) | |
681 | goto out; | |
33226ffd | 682 | |
20a8a968 | 683 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 684 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
685 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
686 | if (ret) | |
687 | goto out; | |
33226ffd HZ |
688 | |
689 | return 0; | |
690 | out: | |
691 | return ret; | |
692 | } | |
693 | ||
6f29c9af BD |
694 | static const struct of_device_id pca953x_dt_ids[]; |
695 | ||
3836309d | 696 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 697 | const struct i2c_device_id *id) |
9e60fdcf | 698 | { |
f3dc3630 GL |
699 | struct pca953x_platform_data *pdata; |
700 | struct pca953x_chip *chip; | |
6a7b36aa | 701 | int irq_base = 0; |
7ea2aa20 | 702 | int ret; |
6a7b36aa | 703 | u32 invert = 0; |
9e60fdcf | 704 | |
b42748c9 LW |
705 | chip = devm_kzalloc(&client->dev, |
706 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
707 | if (chip == NULL) |
708 | return -ENOMEM; | |
709 | ||
e56aee18 | 710 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
711 | if (pdata) { |
712 | irq_base = pdata->irq_base; | |
713 | chip->gpio_start = pdata->gpio_base; | |
714 | invert = pdata->invert; | |
715 | chip->names = pdata->names; | |
716 | } else { | |
4bb93349 MP |
717 | chip->gpio_start = -1; |
718 | irq_base = 0; | |
1965d303 | 719 | } |
9e60fdcf | 720 | |
721 | chip->client = client; | |
722 | ||
f32517bf AS |
723 | if (id) { |
724 | chip->driver_data = id->driver_data; | |
725 | } else { | |
726 | const struct acpi_device_id *id; | |
6f29c9af | 727 | const struct of_device_id *match; |
f32517bf | 728 | |
6f29c9af BD |
729 | match = of_match_device(pca953x_dt_ids, &client->dev); |
730 | if (match) { | |
731 | chip->driver_data = (int)(uintptr_t)match->data; | |
732 | } else { | |
733 | id = acpi_match_device(pca953x_acpi_ids, &client->dev); | |
734 | if (!id) | |
735 | return -ENODEV; | |
f32517bf | 736 | |
6f29c9af BD |
737 | chip->driver_data = id->driver_data; |
738 | } | |
f32517bf AS |
739 | } |
740 | ||
c6664149 | 741 | chip->chip_type = PCA_CHIP_TYPE(chip->driver_data); |
77906a54 | 742 | |
6e20fb18 RS |
743 | mutex_init(&chip->i2c_lock); |
744 | ||
9e60fdcf | 745 | /* initialize cached registers from their original values. |
746 | * we can't share this chip with another i2c master. | |
747 | */ | |
c6664149 | 748 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 749 | |
33226ffd | 750 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 751 | ret = device_pca953x_init(chip, invert); |
33226ffd | 752 | else |
7ea2aa20 WS |
753 | ret = device_pca957x_init(chip, invert); |
754 | if (ret) | |
b42748c9 | 755 | return ret; |
9e60fdcf | 756 | |
0ece84f5 | 757 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 758 | if (ret) |
b42748c9 | 759 | return ret; |
f5e8ff48 | 760 | |
c6664149 | 761 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 762 | if (ret) |
b42748c9 | 763 | return ret; |
9e60fdcf | 764 | |
c6dcf592 | 765 | if (pdata && pdata->setup) { |
9e60fdcf | 766 | ret = pdata->setup(client, chip->gpio_chip.base, |
767 | chip->gpio_chip.ngpio, pdata->context); | |
768 | if (ret < 0) | |
769 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
770 | } | |
771 | ||
772 | i2c_set_clientdata(client, chip); | |
773 | return 0; | |
9e60fdcf | 774 | } |
775 | ||
f3dc3630 | 776 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 777 | { |
e56aee18 | 778 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 779 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
9e60fdcf | 780 | int ret = 0; |
781 | ||
c6dcf592 | 782 | if (pdata && pdata->teardown) { |
9e60fdcf | 783 | ret = pdata->teardown(client, chip->gpio_chip.base, |
784 | chip->gpio_chip.ngpio, pdata->context); | |
785 | if (ret < 0) { | |
786 | dev_err(&client->dev, "%s failed, %d\n", | |
787 | "teardown", ret); | |
788 | return ret; | |
789 | } | |
790 | } | |
791 | ||
9e60fdcf | 792 | return 0; |
793 | } | |
794 | ||
6f29c9af BD |
795 | /* convenience to stop overlong match-table lines */ |
796 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
797 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
798 | ||
ed32620e | 799 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
800 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
801 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
802 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
803 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
804 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
805 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
806 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
807 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
808 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
809 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
810 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
811 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
812 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
813 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
814 | ||
815 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, | |
816 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
817 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
818 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
819 | ||
820 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
821 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, | |
822 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
823 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
824 | ||
825 | { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, | |
826 | ||
827 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
828 | { } |
829 | }; | |
830 | ||
831 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
832 | ||
f3dc3630 | 833 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 834 | .driver = { |
f3dc3630 | 835 | .name = "pca953x", |
ed32620e | 836 | .of_match_table = pca953x_dt_ids, |
f32517bf | 837 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 838 | }, |
f3dc3630 GL |
839 | .probe = pca953x_probe, |
840 | .remove = pca953x_remove, | |
3760f736 | 841 | .id_table = pca953x_id, |
9e60fdcf | 842 | }; |
843 | ||
f3dc3630 | 844 | static int __init pca953x_init(void) |
9e60fdcf | 845 | { |
f3dc3630 | 846 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 847 | } |
2f8d1197 DB |
848 | /* register after i2c postcore initcall and before |
849 | * subsys initcalls that may rely on these GPIOs | |
850 | */ | |
851 | subsys_initcall(pca953x_init); | |
9e60fdcf | 852 | |
f3dc3630 | 853 | static void __exit pca953x_exit(void) |
9e60fdcf | 854 | { |
f3dc3630 | 855 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 856 | } |
f3dc3630 | 857 | module_exit(pca953x_exit); |
9e60fdcf | 858 | |
859 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 860 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 861 | MODULE_LICENSE("GPL"); |