Commit | Line | Data |
---|---|---|
15fae37d | 1 | /* |
c103de24 | 2 | * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders |
15fae37d DB |
3 | * |
4 | * Copyright (C) 2007 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
d120c17f | 21 | #include <linux/gpio.h> |
15fae37d DB |
22 | #include <linux/i2c.h> |
23 | #include <linux/i2c/pcf857x.h> | |
6e20a0a4 KM |
24 | #include <linux/interrupt.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/irqdomain.h> | |
c990d6cb | 27 | #include <linux/kernel.h> |
bb207ef1 | 28 | #include <linux/module.h> |
63f57cd4 LP |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
c990d6cb | 31 | #include <linux/slab.h> |
6e20a0a4 | 32 | #include <linux/spinlock.h> |
15fae37d | 33 | |
15fae37d | 34 | |
3760f736 JD |
35 | static const struct i2c_device_id pcf857x_id[] = { |
36 | { "pcf8574", 8 }, | |
4ba2ccb8 | 37 | { "pcf8574a", 8 }, |
3760f736 JD |
38 | { "pca8574", 8 }, |
39 | { "pca9670", 8 }, | |
40 | { "pca9672", 8 }, | |
41 | { "pca9674", 8 }, | |
42 | { "pcf8575", 16 }, | |
43 | { "pca8575", 16 }, | |
44 | { "pca9671", 16 }, | |
45 | { "pca9673", 16 }, | |
46 | { "pca9675", 16 }, | |
1673ad52 DB |
47 | { "max7328", 8 }, |
48 | { "max7329", 8 }, | |
02130490 | 49 | { "tca9554", 8 }, |
3760f736 JD |
50 | { } |
51 | }; | |
52 | MODULE_DEVICE_TABLE(i2c, pcf857x_id); | |
53 | ||
63f57cd4 LP |
54 | #ifdef CONFIG_OF |
55 | static const struct of_device_id pcf857x_of_table[] = { | |
56 | { .compatible = "nxp,pcf8574" }, | |
57 | { .compatible = "nxp,pcf8574a" }, | |
58 | { .compatible = "nxp,pca8574" }, | |
59 | { .compatible = "nxp,pca9670" }, | |
60 | { .compatible = "nxp,pca9672" }, | |
61 | { .compatible = "nxp,pca9674" }, | |
62 | { .compatible = "nxp,pcf8575" }, | |
63 | { .compatible = "nxp,pca8575" }, | |
64 | { .compatible = "nxp,pca9671" }, | |
65 | { .compatible = "nxp,pca9673" }, | |
66 | { .compatible = "nxp,pca9675" }, | |
67 | { .compatible = "maxim,max7328" }, | |
68 | { .compatible = "maxim,max7329" }, | |
69 | { .compatible = "ti,tca9554" }, | |
70 | { } | |
71 | }; | |
72 | MODULE_DEVICE_TABLE(of, pcf857x_of_table); | |
73 | #endif | |
74 | ||
15fae37d DB |
75 | /* |
76 | * The pcf857x, pca857x, and pca967x chips only expose one read and one | |
77 | * write register. Writing a "one" bit (to match the reset state) lets | |
78 | * that pin be used as an input; it's not an open-drain model, but acts | |
79 | * a bit like one. This is described as "quasi-bidirectional"; read the | |
80 | * chip documentation for details. | |
81 | * | |
82 | * Many other I2C GPIO expander chips (like the pca953x models) have | |
83 | * more complex register models and more conventional circuitry using | |
84 | * push/pull drivers. They often use the same 0x20..0x27 addresses as | |
85 | * pcf857x parts, making the "legacy" I2C driver model problematic. | |
86 | */ | |
87 | struct pcf857x { | |
88 | struct gpio_chip chip; | |
89 | struct i2c_client *client; | |
1673ad52 | 90 | struct mutex lock; /* protect 'out' */ |
6e20a0a4 KM |
91 | struct irq_domain *irq_domain; /* for irq demux */ |
92 | spinlock_t slock; /* protect irq demux */ | |
15fae37d | 93 | unsigned out; /* software latch */ |
6e20a0a4 | 94 | unsigned status; /* current status */ |
21fd3cd1 | 95 | unsigned irq_mapped; /* mapped gpio irqs */ |
0c65ddd4 KM |
96 | |
97 | int (*write)(struct i2c_client *client, unsigned data); | |
98 | int (*read)(struct i2c_client *client); | |
15fae37d DB |
99 | }; |
100 | ||
101 | /*-------------------------------------------------------------------------*/ | |
102 | ||
103 | /* Talk to 8-bit I/O expander */ | |
104 | ||
0c65ddd4 | 105 | static int i2c_write_le8(struct i2c_client *client, unsigned data) |
15fae37d | 106 | { |
0c65ddd4 | 107 | return i2c_smbus_write_byte(client, data); |
15fae37d DB |
108 | } |
109 | ||
0c65ddd4 | 110 | static int i2c_read_le8(struct i2c_client *client) |
15fae37d | 111 | { |
0c65ddd4 | 112 | return (int)i2c_smbus_read_byte(client); |
15fae37d DB |
113 | } |
114 | ||
15fae37d DB |
115 | /* Talk to 16-bit I/O expander */ |
116 | ||
0c65ddd4 | 117 | static int i2c_write_le16(struct i2c_client *client, unsigned word) |
15fae37d DB |
118 | { |
119 | u8 buf[2] = { word & 0xff, word >> 8, }; | |
120 | int status; | |
121 | ||
122 | status = i2c_master_send(client, buf, 2); | |
123 | return (status < 0) ? status : 0; | |
124 | } | |
125 | ||
126 | static int i2c_read_le16(struct i2c_client *client) | |
127 | { | |
128 | u8 buf[2]; | |
129 | int status; | |
130 | ||
131 | status = i2c_master_recv(client, buf, 2); | |
132 | if (status < 0) | |
133 | return status; | |
134 | return (buf[1] << 8) | buf[0]; | |
135 | } | |
136 | ||
0c65ddd4 KM |
137 | /*-------------------------------------------------------------------------*/ |
138 | ||
139 | static int pcf857x_input(struct gpio_chip *chip, unsigned offset) | |
15fae37d DB |
140 | { |
141 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
1673ad52 | 142 | int status; |
15fae37d | 143 | |
1673ad52 | 144 | mutex_lock(&gpio->lock); |
15fae37d | 145 | gpio->out |= (1 << offset); |
0c65ddd4 | 146 | status = gpio->write(gpio->client, gpio->out); |
1673ad52 DB |
147 | mutex_unlock(&gpio->lock); |
148 | ||
149 | return status; | |
15fae37d DB |
150 | } |
151 | ||
0c65ddd4 | 152 | static int pcf857x_get(struct gpio_chip *chip, unsigned offset) |
15fae37d DB |
153 | { |
154 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
155 | int value; | |
156 | ||
0c65ddd4 | 157 | value = gpio->read(gpio->client); |
15fae37d DB |
158 | return (value < 0) ? 0 : (value & (1 << offset)); |
159 | } | |
160 | ||
0c65ddd4 | 161 | static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value) |
15fae37d DB |
162 | { |
163 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
164 | unsigned bit = 1 << offset; | |
1673ad52 | 165 | int status; |
15fae37d | 166 | |
1673ad52 | 167 | mutex_lock(&gpio->lock); |
15fae37d DB |
168 | if (value) |
169 | gpio->out |= bit; | |
170 | else | |
171 | gpio->out &= ~bit; | |
0c65ddd4 | 172 | status = gpio->write(gpio->client, gpio->out); |
1673ad52 DB |
173 | mutex_unlock(&gpio->lock); |
174 | ||
175 | return status; | |
15fae37d DB |
176 | } |
177 | ||
0c65ddd4 | 178 | static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value) |
15fae37d | 179 | { |
0c65ddd4 | 180 | pcf857x_output(chip, offset, value); |
15fae37d DB |
181 | } |
182 | ||
183 | /*-------------------------------------------------------------------------*/ | |
184 | ||
6e20a0a4 KM |
185 | static int pcf857x_to_irq(struct gpio_chip *chip, unsigned offset) |
186 | { | |
187 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
21fd3cd1 | 188 | int ret; |
6e20a0a4 | 189 | |
21fd3cd1 GC |
190 | ret = irq_create_mapping(gpio->irq_domain, offset); |
191 | if (ret > 0) | |
192 | gpio->irq_mapped |= (1 << offset); | |
193 | ||
194 | return ret; | |
6e20a0a4 KM |
195 | } |
196 | ||
5c21d008 GC |
197 | static irqreturn_t pcf857x_irq(int irq, void *data) |
198 | { | |
199 | struct pcf857x *gpio = data; | |
200 | unsigned long change, i, status, flags; | |
201 | ||
202 | status = gpio->read(gpio->client); | |
203 | ||
204 | spin_lock_irqsave(&gpio->slock, flags); | |
205 | ||
21fd3cd1 GC |
206 | /* |
207 | * call the interrupt handler iff gpio is used as | |
208 | * interrupt source, just to avoid bad irqs | |
209 | */ | |
210 | ||
211 | change = ((gpio->status ^ status) & gpio->irq_mapped); | |
5c21d008 GC |
212 | for_each_set_bit(i, &change, gpio->chip.ngpio) |
213 | generic_handle_irq(irq_find_mapping(gpio->irq_domain, i)); | |
214 | gpio->status = status; | |
215 | ||
216 | spin_unlock_irqrestore(&gpio->slock, flags); | |
217 | ||
218 | return IRQ_HANDLED; | |
219 | } | |
220 | ||
c27769ef | 221 | static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int irq, |
6e20a0a4 KM |
222 | irq_hw_number_t hw) |
223 | { | |
21fd3cd1 GC |
224 | struct pcf857x *gpio = domain->host_data; |
225 | ||
c27769ef | 226 | irq_set_chip_and_handler(irq, |
6e20a0a4 KM |
227 | &dummy_irq_chip, |
228 | handle_level_irq); | |
c27769ef LW |
229 | #ifdef CONFIG_ARM |
230 | set_irq_flags(irq, IRQF_VALID); | |
231 | #else | |
232 | irq_set_noprobe(irq); | |
233 | #endif | |
21fd3cd1 GC |
234 | gpio->irq_mapped |= (1 << hw); |
235 | ||
6e20a0a4 KM |
236 | return 0; |
237 | } | |
238 | ||
239 | static struct irq_domain_ops pcf857x_irq_domain_ops = { | |
240 | .map = pcf857x_irq_domain_map, | |
241 | }; | |
242 | ||
243 | static void pcf857x_irq_domain_cleanup(struct pcf857x *gpio) | |
244 | { | |
245 | if (gpio->irq_domain) | |
246 | irq_domain_remove(gpio->irq_domain); | |
247 | ||
6e20a0a4 KM |
248 | } |
249 | ||
250 | static int pcf857x_irq_domain_init(struct pcf857x *gpio, | |
805f864e | 251 | struct i2c_client *client) |
6e20a0a4 KM |
252 | { |
253 | int status; | |
254 | ||
805f864e | 255 | gpio->irq_domain = irq_domain_add_linear(client->dev.of_node, |
6e20a0a4 KM |
256 | gpio->chip.ngpio, |
257 | &pcf857x_irq_domain_ops, | |
21fd3cd1 | 258 | gpio); |
6e20a0a4 KM |
259 | if (!gpio->irq_domain) |
260 | goto fail; | |
261 | ||
262 | /* enable real irq */ | |
5c21d008 GC |
263 | status = devm_request_threaded_irq(&client->dev, client->irq, |
264 | NULL, pcf857x_irq, IRQF_ONESHOT | | |
5795cf35 | 265 | IRQF_TRIGGER_FALLING | IRQF_SHARED, |
5c21d008 GC |
266 | dev_name(&client->dev), gpio); |
267 | ||
6e20a0a4 KM |
268 | if (status) |
269 | goto fail; | |
270 | ||
271 | /* enable gpio_to_irq() */ | |
6e20a0a4 | 272 | gpio->chip.to_irq = pcf857x_to_irq; |
6e20a0a4 KM |
273 | |
274 | return 0; | |
275 | ||
276 | fail: | |
277 | pcf857x_irq_domain_cleanup(gpio); | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | /*-------------------------------------------------------------------------*/ | |
282 | ||
d2653e92 JD |
283 | static int pcf857x_probe(struct i2c_client *client, |
284 | const struct i2c_device_id *id) | |
15fae37d | 285 | { |
63f57cd4 LP |
286 | struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev); |
287 | struct device_node *np = client->dev.of_node; | |
15fae37d | 288 | struct pcf857x *gpio; |
63f57cd4 | 289 | unsigned int n_latch = 0; |
15fae37d DB |
290 | int status; |
291 | ||
63f57cd4 LP |
292 | if (IS_ENABLED(CONFIG_OF) && np) |
293 | of_property_read_u32(np, "lines-initial-states", &n_latch); | |
294 | else if (pdata) | |
295 | n_latch = pdata->n_latch; | |
296 | else | |
a342d215 | 297 | dev_dbg(&client->dev, "no platform data\n"); |
15fae37d DB |
298 | |
299 | /* Allocate, initialize, and register this gpio_chip. */ | |
f39f54af | 300 | gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); |
15fae37d DB |
301 | if (!gpio) |
302 | return -ENOMEM; | |
303 | ||
1673ad52 | 304 | mutex_init(&gpio->lock); |
6e20a0a4 | 305 | spin_lock_init(&gpio->slock); |
1673ad52 | 306 | |
0c65ddd4 | 307 | gpio->chip.base = pdata ? pdata->gpio_base : -1; |
9fb1f39e | 308 | gpio->chip.can_sleep = true; |
0c65ddd4 KM |
309 | gpio->chip.dev = &client->dev; |
310 | gpio->chip.owner = THIS_MODULE; | |
311 | gpio->chip.get = pcf857x_get; | |
312 | gpio->chip.set = pcf857x_set; | |
313 | gpio->chip.direction_input = pcf857x_input; | |
314 | gpio->chip.direction_output = pcf857x_output; | |
315 | gpio->chip.ngpio = id->driver_data; | |
15fae37d | 316 | |
6e20a0a4 | 317 | /* enable gpio_to_irq() if platform has settings */ |
655c4e79 LP |
318 | if (client->irq) { |
319 | status = pcf857x_irq_domain_init(gpio, client); | |
6e20a0a4 KM |
320 | if (status < 0) { |
321 | dev_err(&client->dev, "irq_domain init failed\n"); | |
e6b698f6 | 322 | goto fail_irq_domain; |
6e20a0a4 KM |
323 | } |
324 | } | |
325 | ||
15fae37d DB |
326 | /* NOTE: the OnSemi jlc1562b is also largely compatible with |
327 | * these parts, notably for output. It has a low-resolution | |
328 | * DAC instead of pin change IRQs; and its inputs can be the | |
329 | * result of comparators. | |
330 | */ | |
331 | ||
332 | /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f; | |
333 | * 9670, 9672, 9764, and 9764a use quite a variety. | |
334 | * | |
335 | * NOTE: we don't distinguish here between *4 and *4a parts. | |
336 | */ | |
3760f736 | 337 | if (gpio->chip.ngpio == 8) { |
0c65ddd4 KM |
338 | gpio->write = i2c_write_le8; |
339 | gpio->read = i2c_read_le8; | |
15fae37d DB |
340 | |
341 | if (!i2c_check_functionality(client->adapter, | |
342 | I2C_FUNC_SMBUS_BYTE)) | |
343 | status = -EIO; | |
344 | ||
345 | /* fail if there's no chip present */ | |
346 | else | |
347 | status = i2c_smbus_read_byte(client); | |
348 | ||
349 | /* '75/'75c addresses are 0x20..0x27, just like the '74; | |
350 | * the '75c doesn't have a current source pulling high. | |
351 | * 9671, 9673, and 9765 use quite a variety of addresses. | |
352 | * | |
353 | * NOTE: we don't distinguish here between '75 and '75c parts. | |
354 | */ | |
3760f736 | 355 | } else if (gpio->chip.ngpio == 16) { |
0c65ddd4 KM |
356 | gpio->write = i2c_write_le16; |
357 | gpio->read = i2c_read_le16; | |
15fae37d DB |
358 | |
359 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) | |
360 | status = -EIO; | |
361 | ||
362 | /* fail if there's no chip present */ | |
363 | else | |
364 | status = i2c_read_le16(client); | |
365 | ||
a342d215 BD |
366 | } else { |
367 | dev_dbg(&client->dev, "unsupported number of gpios\n"); | |
368 | status = -EINVAL; | |
369 | } | |
15fae37d DB |
370 | |
371 | if (status < 0) | |
372 | goto fail; | |
373 | ||
374 | gpio->chip.label = client->name; | |
375 | ||
376 | gpio->client = client; | |
377 | i2c_set_clientdata(client, gpio); | |
378 | ||
379 | /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. | |
380 | * We can't actually know whether a pin is configured (a) as output | |
381 | * and driving the signal low, or (b) as input and reporting a low | |
382 | * value ... without knowing the last value written since the chip | |
383 | * came out of reset (if any). We can't read the latched output. | |
384 | * | |
385 | * In short, the only reliable solution for setting up pin direction | |
386 | * is to do it explicitly. The setup() method can do that, but it | |
387 | * may cause transient glitching since it can't know the last value | |
388 | * written (some pins may need to be driven low). | |
389 | * | |
63f57cd4 LP |
390 | * Using n_latch avoids that trouble. When left initialized to zero, |
391 | * our software copy of the "latch" then matches the chip's all-ones | |
392 | * reset state. Otherwise it flags pins to be driven low. | |
15fae37d | 393 | */ |
63f57cd4 | 394 | gpio->out = ~n_latch; |
6e20a0a4 | 395 | gpio->status = gpio->out; |
15fae37d DB |
396 | |
397 | status = gpiochip_add(&gpio->chip); | |
398 | if (status < 0) | |
399 | goto fail; | |
400 | ||
15fae37d DB |
401 | /* Let platform code set up the GPIOs and their users. |
402 | * Now is the first time anyone could use them. | |
403 | */ | |
49946f68 | 404 | if (pdata && pdata->setup) { |
15fae37d DB |
405 | status = pdata->setup(client, |
406 | gpio->chip.base, gpio->chip.ngpio, | |
407 | pdata->context); | |
408 | if (status < 0) | |
409 | dev_warn(&client->dev, "setup --> %d\n", status); | |
410 | } | |
411 | ||
805f864e KM |
412 | dev_info(&client->dev, "probed\n"); |
413 | ||
15fae37d DB |
414 | return 0; |
415 | ||
416 | fail: | |
655c4e79 | 417 | if (client->irq) |
6e20a0a4 KM |
418 | pcf857x_irq_domain_cleanup(gpio); |
419 | ||
e6b698f6 GC |
420 | fail_irq_domain: |
421 | dev_dbg(&client->dev, "probe error %d for '%s'\n", | |
422 | status, client->name); | |
423 | ||
15fae37d DB |
424 | return status; |
425 | } | |
426 | ||
427 | static int pcf857x_remove(struct i2c_client *client) | |
428 | { | |
e56aee18 | 429 | struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev); |
15fae37d DB |
430 | struct pcf857x *gpio = i2c_get_clientdata(client); |
431 | int status = 0; | |
432 | ||
49946f68 | 433 | if (pdata && pdata->teardown) { |
15fae37d DB |
434 | status = pdata->teardown(client, |
435 | gpio->chip.base, gpio->chip.ngpio, | |
436 | pdata->context); | |
437 | if (status < 0) { | |
438 | dev_err(&client->dev, "%s --> %d\n", | |
439 | "teardown", status); | |
440 | return status; | |
441 | } | |
442 | } | |
443 | ||
655c4e79 | 444 | if (client->irq) |
6e20a0a4 KM |
445 | pcf857x_irq_domain_cleanup(gpio); |
446 | ||
9f5132ae | 447 | gpiochip_remove(&gpio->chip); |
15fae37d DB |
448 | return status; |
449 | } | |
450 | ||
451 | static struct i2c_driver pcf857x_driver = { | |
452 | .driver = { | |
453 | .name = "pcf857x", | |
454 | .owner = THIS_MODULE, | |
63f57cd4 | 455 | .of_match_table = of_match_ptr(pcf857x_of_table), |
15fae37d DB |
456 | }, |
457 | .probe = pcf857x_probe, | |
458 | .remove = pcf857x_remove, | |
3760f736 | 459 | .id_table = pcf857x_id, |
15fae37d DB |
460 | }; |
461 | ||
462 | static int __init pcf857x_init(void) | |
463 | { | |
464 | return i2c_add_driver(&pcf857x_driver); | |
465 | } | |
2f8d1197 DB |
466 | /* register after i2c postcore initcall and before |
467 | * subsys initcalls that may rely on these GPIOs | |
468 | */ | |
469 | subsys_initcall(pcf857x_init); | |
15fae37d DB |
470 | |
471 | static void __exit pcf857x_exit(void) | |
472 | { | |
473 | i2c_del_driver(&pcf857x_driver); | |
474 | } | |
475 | module_exit(pcf857x_exit); | |
476 | ||
477 | MODULE_LICENSE("GPL"); | |
478 | MODULE_AUTHOR("David Brownell"); |