[deliverable/linux.git] / drivers / gpio / gpio-pch.c

/*
 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#define PCH_EDGE_FALLING	0
#define PCH_EDGE_RISING		BIT(0)
#define PCH_LEVEL_L		BIT(1)
#define PCH_LEVEL_H		(BIT(0) | BIT(1))
#define PCH_EDGE_BOTH		BIT(2)
#define PCH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))

#define PCH_IRQ_BASE		24

struct pch_regs {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im0;
	u32	im1;
	u32	reserved[3];
	u32	gpio_use_sel;
	u32	reset;
};

enum pch_type_t {
	INTEL_EG20T_PCH,
	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
	OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
};

/* Specifies number of GPIO PINS */
static int gpio_pins[] = {
	[INTEL_EG20T_PCH] = 12,
	[OKISEMI_ML7223m_IOH] = 8,
	[OKISEMI_ML7223n_IOH] = 8,
};

/**
 * struct pch_gpio_reg_data - The register store data.
 * @ien_reg:	To store contents of IEN register.
 * @imask_reg:	To store contents of IMASK register.
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of IM0 register.
 * @im1_reg:	To store contents of IM1 register.
 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
 *		       (Only ML7223 Bus-n)
 */
struct pch_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 gpio_use_sel_reg;
};

/**
 * struct pch_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped PCH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @pch_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @lock:			Used for register access protection
 * @irq_base:		Save base of IRQ number for interrupt
 * @ioh:		IOH ID
 * @spinlock:		Used for register access protection
 */
struct pch_gpio {
	void __iomem *base;
	struct pch_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct pch_gpio_reg_data pch_gpio_reg;
	int irq_base;
	enum pch_type_t ioh;
	spinlock_t spinlock;
};

static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	u32 reg_val;
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);

	iowrite32(reg_val, &chip->reg->po);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);

	return ioread32(&chip->reg->pi) & (1 << nr);
}

static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				     int val)
{
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);
	u32 pm;
	u32 reg_val;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);

	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);
	iowrite32(reg_val, &chip->reg->po);

	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	pm |= (1 << nr);
	iowrite32(pm, &chip->reg->pm);

	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);
	u32 pm;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	pm &= ~(1 << nr);
	iowrite32(pm, &chip->reg->pm);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

/*
 * Save register configuration and disable interrupts.
 */
static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
{
	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		chip->pch_gpio_reg.gpio_use_sel_reg =\
					    ioread32(&chip->reg->gpio_use_sel);
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
{
	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
	/* to store contents of PO register */
	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	/* to store contents of PM register */
	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
			  &chip->reg->gpio_use_sel);
}

static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	return chip->irq_base + offset;
}

static void pch_gpio_setup(struct pch_gpio *chip)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->dev = chip->dev;
	gpio->owner = THIS_MODULE;
	gpio->direction_input = pch_gpio_direction_input;
	gpio->get = pch_gpio_get;
	gpio->direction_output = pch_gpio_direction_output;
	gpio->set = pch_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = -1;
	gpio->ngpio = gpio_pins[chip->ioh];
	gpio->can_sleep = false;
	gpio->to_irq = pch_gpio_to_irq;
}

static int pch_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;
	u32 im, im_pos, val;
	u32 __iomem *im_reg;
	unsigned long flags;
	int ch, irq = d->irq;

	ch = irq - chip->irq_base;
	if (irq <= chip->irq_base + 7) {
		im_reg = &chip->reg->im0;
		im_pos = ch;
	} else {
		im_reg = &chip->reg->im1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
		__func__, irq, type, ch, im_pos);

	spin_lock_irqsave(&chip->spinlock, flags);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = PCH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = PCH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = PCH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = PCH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = PCH_LEVEL_L;
		break;
	default:
		goto unlock;
	}

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* And the handler */
	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

unlock:
	spin_unlock_irqrestore(&chip->spinlock, flags);
	return 0;
}

static void pch_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
}

static void pch_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
}

static void pch_irq_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
}

static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
{
	struct pch_gpio *chip = dev_id;
	u32 reg_val = ioread32(&chip->reg->istatus);
	int i, ret = IRQ_NONE;

	for (i = 0; i < gpio_pins[chip->ioh]; i++) {
		if (reg_val & BIT(i)) {
			dev_dbg(chip->dev, "%s:[%d]:irq=%d  status=0x%x\n",
				__func__, i, irq, reg_val);
			generic_handle_irq(chip->irq_base + i);
			ret = IRQ_HANDLED;
		}
	}
	return ret;
}

static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
				unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
				    handle_simple_irq);
	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_ack = pch_irq_ack;
	ct->chip.irq_mask = pch_irq_mask;
	ct->chip.irq_unmask = pch_irq_unmask;
	ct->chip.irq_set_type = pch_irq_type;

	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int pch_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	s32 ret;
	struct pch_gpio *chip;
	int irq_base;
	u32 msk;

	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	chip->dev = &pdev->dev;
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
		goto err_pci_enable;
	}

	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
		goto err_request_regions;
	}

	chip->base = pci_iomap(pdev, 1, 0);
	if (!chip->base) {
		dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
		ret = -ENOMEM;
		goto err_iomap;
	}

	if (pdev->device == 0x8803)
		chip->ioh = INTEL_EG20T_PCH;
	else if (pdev->device == 0x8014)
		chip->ioh = OKISEMI_ML7223m_IOH;
	else if (pdev->device == 0x8043)
		chip->ioh = OKISEMI_ML7223n_IOH;

	chip->reg = chip->base;
	pci_set_drvdata(pdev, chip);
	spin_lock_init(&chip->spinlock);
	pch_gpio_setup(chip);
	ret = gpiochip_add(&chip->gpio);
	if (ret) {
		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
		goto err_gpiochip_add;
	}

	irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
	if (irq_base < 0) {
		dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
		chip->irq_base = -1;
		goto end;
	}
	chip->irq_base = irq_base;

	/* Mask all interrupts, but enable them */
	msk = (1 << gpio_pins[chip->ioh]) - 1;
	iowrite32(msk, &chip->reg->imask);
	iowrite32(msk, &chip->reg->ien);

	ret = request_irq(pdev->irq, pch_gpio_handler,
			  IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev,
			"%s request_irq failed\n", __func__);
		goto err_request_irq;
	}

	pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);

end:
	return 0;

err_request_irq:
	irq_free_descs(irq_base, gpio_pins[chip->ioh]);

	if (gpiochip_remove(&chip->gpio))
		dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);

err_gpiochip_add:
	pci_iounmap(pdev, chip->base);

err_iomap:
	pci_release_regions(pdev);

err_request_regions:
	pci_disable_device(pdev);

err_pci_enable:
	kfree(chip);
	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	return ret;
}

static void pch_gpio_remove(struct pci_dev *pdev)
{
	int err;
	struct pch_gpio *chip = pci_get_drvdata(pdev);

	if (chip->irq_base != -1) {
		free_irq(pdev->irq, chip);

		irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
	}

	err = gpiochip_remove(&chip->gpio);
	if (err)
		dev_err(&pdev->dev, "Failed gpiochip_remove\n");

	pci_iounmap(pdev, chip->base);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	kfree(chip);
}

#ifdef CONFIG_PM
static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
{
	s32 ret;
	struct pch_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pch_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	ret = pci_save_state(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
		return ret;
	}
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_wake(pdev, PCI_D0, 1);
	if (ret)
		dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);

	return 0;
}

static int pch_gpio_resume(struct pci_dev *pdev)
{
	s32 ret;
	struct pch_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	ret = pci_enable_wake(pdev, PCI_D0, 0);

	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
		return ret;
	}
	pci_restore_state(pdev);

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->reset);
	iowrite32(0x00, &chip->reg->reset);
	pch_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}
#else
#define pch_gpio_suspend NULL
#define pch_gpio_resume NULL
#endif

#define PCI_VENDOR_ID_ROHM             0x10DB
static const struct pci_device_id pch_gpio_pcidev_id[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

static struct pci_driver pch_gpio_driver = {
	.name = "pch_gpio",
	.id_table = pch_gpio_pcidev_id,
	.probe = pch_gpio_probe,
	.remove = pch_gpio_remove,
	.suspend = pch_gpio_suspend,
	.resume = pch_gpio_resume
};

module_pci_driver(pch_gpio_driver);

MODULE_DESCRIPTION("PCH GPIO PCI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
04c17aa8	1	/*
f4574beb	2	* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
04c17aa8 TM	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2 of the License.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
	16	*/
bb207ef1	17	#include <linux/module.h>
04c17aa8 TM	18	#include <linux/kernel.h>
	19	#include <linux/pci.h>
	20	#include <linux/gpio.h>
38eb18a6 TM	21	#include <linux/interrupt.h>
	22	#include <linux/irq.h>
	23
	24	#define PCH_EDGE_FALLING 0
	25	#define PCH_EDGE_RISING BIT(0)
	26	#define PCH_LEVEL_L BIT(1)
	27	#define PCH_LEVEL_H (BIT(0) \| BIT(1))
	28	#define PCH_EDGE_BOTH BIT(2)
	29	#define PCH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
	30
	31	#define PCH_IRQ_BASE 24
04c17aa8	32
04c17aa8 TM	33	struct pch_regs {
	34	u32 ien;
	35	u32 istatus;
	36	u32 idisp;
	37	u32 iclr;
	38	u32 imask;
	39	u32 imaskclr;
	40	u32 po;
	41	u32 pi;
	42	u32 pm;
	43	u32 im0;
	44	u32 im1;
e98bed7f TM	45	u32 reserved[3];
e98bed7f TM	46	u32 gpio_use_sel;
04c17aa8 TM	47	u32 reset;
	48	};
	49
d4260e6d TM	50	enum pch_type_t {
d4260e6d TM	51	INTEL_EG20T_PCH,
f4574beb TM	52	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
f4574beb TM	53	OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
d4260e6d TM	54	};
	55
	56	/* Specifies number of GPIO PINS */
	57	static int gpio_pins[] = {
	58	[INTEL_EG20T_PCH] = 12,
	59	[OKISEMI_ML7223m_IOH] = 8,
	60	[OKISEMI_ML7223n_IOH] = 8,
	61	};
	62
04c17aa8 TM	63	/**
04c17aa8 TM	64	* struct pch_gpio_reg_data - The register store data.
38eb18a6 TM	65	* @ien_reg: To store contents of IEN register.
38eb18a6 TM	66	* @imask_reg: To store contents of IMASK register.
04c17aa8 TM	67	* @po_reg: To store contents of PO register.
04c17aa8 TM	68	* @pm_reg: To store contents of PM register.
e98bed7f TM	69	* @im0_reg: To store contents of IM0 register.
	70	* @im1_reg: To store contents of IM1 register.
	71	* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
	72	* (Only ML7223 Bus-n)
04c17aa8 TM	73	*/
04c17aa8 TM	74	struct pch_gpio_reg_data {
38eb18a6 TM	75	u32 ien_reg;
38eb18a6 TM	76	u32 imask_reg;
04c17aa8 TM	77	u32 po_reg;
04c17aa8 TM	78	u32 pm_reg;
e98bed7f TM	79	u32 im0_reg;
	80	u32 im1_reg;
	81	u32 gpio_use_sel_reg;
04c17aa8 TM	82	};
	83
	84	/**
	85	* struct pch_gpio - GPIO private data structure.
	86	* @base: PCI base address of Memory mapped I/O register.
	87	* @reg: Memory mapped PCH GPIO register list.
	88	* @dev: Pointer to device structure.
	89	* @gpio: Data for GPIO infrastructure.
	90	* @pch_gpio_reg: Memory mapped Register data is saved here
	91	* when suspend.
38eb18a6 TM	92	* @lock: Used for register access protection
38eb18a6 TM	93	* @irq_base: Save base of IRQ number for interrupt
d4260e6d	94	* @ioh: IOH ID
7cb6580c	95	* @spinlock: Used for register access protection
04c17aa8 TM	96	*/
	97	struct pch_gpio {
	98	void __iomem *base;
	99	struct pch_regs __iomem *reg;
	100	struct device *dev;
	101	struct gpio_chip gpio;
	102	struct pch_gpio_reg_data pch_gpio_reg;
38eb18a6	103	int irq_base;
d4260e6d	104	enum pch_type_t ioh;
d568a681	105	spinlock_t spinlock;
04c17aa8 TM	106	};
	107
	108	static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	109	{
	110	u32 reg_val;
	111	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
7cb6580c	112	unsigned long flags;
04c17aa8	113
7cb6580c	114	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	115	reg_val = ioread32(&chip->reg->po);
	116	if (val)
	117	reg_val \|= (1 << nr);
	118	else
	119	reg_val &= ~(1 << nr);
	120
	121	iowrite32(reg_val, &chip->reg->po);
7cb6580c	122	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	123	}
	124
	125	static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
	126	{
	127	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	128
	129	return ioread32(&chip->reg->pi) & (1 << nr);
	130	}
	131
	132	static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	133	int val)
	134	{
	135	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	136	u32 pm;
	137	u32 reg_val;
7cb6580c	138	unsigned long flags;
04c17aa8	139
7cb6580c	140	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	141
	142	reg_val = ioread32(&chip->reg->po);
	143	if (val)
	144	reg_val \|= (1 << nr);
	145	else
	146	reg_val &= ~(1 << nr);
88aab934	147	iowrite32(reg_val, &chip->reg->po);
2ddf6cd6 DK	148
	149	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	150	pm \|= (1 << nr);
	151	iowrite32(pm, &chip->reg->pm);
	152
7cb6580c	153	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	154
	155	return 0;
	156	}
	157
	158	static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	159	{
	160	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	161	u32 pm;
7cb6580c	162	unsigned long flags;
04c17aa8	163
7cb6580c	164	spin_lock_irqsave(&chip->spinlock, flags);
d4260e6d	165	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
04c17aa8 TM	166	pm &= ~(1 << nr);
04c17aa8 TM	167	iowrite32(pm, &chip->reg->pm);
7cb6580c	168	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	169
	170	return 0;
	171	}
	172
	173	/*
	174	* Save register configuration and disable interrupts.
	175	*/
	176	static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
	177	{
38eb18a6 TM	178	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
38eb18a6 TM	179	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
04c17aa8 TM	180	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
04c17aa8 TM	181	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
e98bed7f TM	182	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	183	if (chip->ioh == INTEL_EG20T_PCH)
	184	chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	185	if (chip->ioh == OKISEMI_ML7223n_IOH)
	186	chip->pch_gpio_reg.gpio_use_sel_reg =\
	187	ioread32(&chip->reg->gpio_use_sel);
04c17aa8 TM	188	}
	189
	190	/*
	191	* This function restores the register configuration of the GPIO device.
	192	*/
	193	static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
	194	{
38eb18a6 TM	195	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
38eb18a6 TM	196	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
04c17aa8 TM	197	/* to store contents of PO register */
	198	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	199	/* to store contents of PM register */
	200	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
e98bed7f TM	201	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	202	if (chip->ioh == INTEL_EG20T_PCH)
	203	iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	204	if (chip->ioh == OKISEMI_ML7223n_IOH)
	205	iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
	206	&chip->reg->gpio_use_sel);
04c17aa8 TM	207	}
04c17aa8 TM	208
38eb18a6 TM	209	static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	210	{
	211	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	212	return chip->irq_base + offset;
	213	}
	214
04c17aa8 TM	215	static void pch_gpio_setup(struct pch_gpio *chip)
	216	{
	217	struct gpio_chip *gpio = &chip->gpio;
	218
	219	gpio->label = dev_name(chip->dev);
5c868fc6	220	gpio->dev = chip->dev;
04c17aa8 TM	221	gpio->owner = THIS_MODULE;
	222	gpio->direction_input = pch_gpio_direction_input;
	223	gpio->get = pch_gpio_get;
	224	gpio->direction_output = pch_gpio_direction_output;
	225	gpio->set = pch_gpio_set;
	226	gpio->dbg_show = NULL;
	227	gpio->base = -1;
d4260e6d	228	gpio->ngpio = gpio_pins[chip->ioh];
9fb1f39e	229	gpio->can_sleep = false;
38eb18a6 TM	230	gpio->to_irq = pch_gpio_to_irq;
	231	}
	232
	233	static int pch_irq_type(struct irq_data *d, unsigned int type)
	234	{
38eb18a6 TM	235	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38eb18a6 TM	236	struct pch_gpio *chip = gc->private;
df9541a6 TG	237	u32 im, im_pos, val;
	238	u32 __iomem *im_reg;
	239	unsigned long flags;
	240	int ch, irq = d->irq;
38eb18a6 TM	241
	242	ch = irq - chip->irq_base;
	243	if (irq <= chip->irq_base + 7) {
	244	im_reg = &chip->reg->im0;
	245	im_pos = ch;
	246	} else {
	247	im_reg = &chip->reg->im1;
	248	im_pos = ch - 8;
	249	}
	250	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
	251	__func__, irq, type, ch, im_pos);
	252
	253	spin_lock_irqsave(&chip->spinlock, flags);
	254
	255	switch (type) {
	256	case IRQ_TYPE_EDGE_RISING:
	257	val = PCH_EDGE_RISING;
	258	break;
	259	case IRQ_TYPE_EDGE_FALLING:
	260	val = PCH_EDGE_FALLING;
	261	break;
	262	case IRQ_TYPE_EDGE_BOTH:
	263	val = PCH_EDGE_BOTH;
	264	break;
	265	case IRQ_TYPE_LEVEL_HIGH:
	266	val = PCH_LEVEL_H;
	267	break;
	268	case IRQ_TYPE_LEVEL_LOW:
	269	val = PCH_LEVEL_L;
	270	break;
38eb18a6	271	default:
df9541a6	272	goto unlock;
38eb18a6 TM	273	}
	274
	275	/* Set interrupt mode */
	276	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	277	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	278
df9541a6 TG	279	/* And the handler */
	280	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
	281	__irq_set_handler_locked(d->irq, handle_level_irq);
	282	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	283	__irq_set_handler_locked(d->irq, handle_edge_irq);
38eb18a6	284
df9541a6	285	unlock:
38eb18a6	286	spin_unlock_irqrestore(&chip->spinlock, flags);
38eb18a6 TM	287	return 0;
	288	}
	289
	290	static void pch_irq_unmask(struct irq_data *d)
	291	{
	292	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	293	struct pch_gpio *chip = gc->private;
	294
	295	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
	296	}
	297
	298	static void pch_irq_mask(struct irq_data *d)
	299	{
	300	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	301	struct pch_gpio *chip = gc->private;
	302
	303	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
	304	}
	305
df9541a6 TG	306	static void pch_irq_ack(struct irq_data *d)
	307	{
	308	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	309	struct pch_gpio *chip = gc->private;
	310
	311	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
	312	}
	313
38eb18a6 TM	314	static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
	315	{
	316	struct pch_gpio *chip = dev_id;
	317	u32 reg_val = ioread32(&chip->reg->istatus);
df9541a6	318	int i, ret = IRQ_NONE;
38eb18a6 TM	319
	320	for (i = 0; i < gpio_pins[chip->ioh]; i++) {
	321	if (reg_val & BIT(i)) {
	322	dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
	323	__func__, i, irq, reg_val);
38eb18a6 TM	324	generic_handle_irq(chip->irq_base + i);
	325	ret = IRQ_HANDLED;
	326	}
	327	}
	328	return ret;
	329	}
	330
3836309d	331	static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
38eb18a6 TM	332	unsigned int irq_start, unsigned int num)
	333	{
	334	struct irq_chip_generic *gc;
	335	struct irq_chip_type *ct;
	336
	337	gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
	338	handle_simple_irq);
	339	gc->private = chip;
	340	ct = gc->chip_types;
	341
df9541a6	342	ct->chip.irq_ack = pch_irq_ack;
38eb18a6 TM	343	ct->chip.irq_mask = pch_irq_mask;
	344	ct->chip.irq_unmask = pch_irq_unmask;
	345	ct->chip.irq_set_type = pch_irq_type;
	346
	347	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	348	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
04c17aa8 TM	349	}
04c17aa8 TM	350
3836309d	351	static int pch_gpio_probe(struct pci_dev *pdev,
04c17aa8 TM	352	const struct pci_device_id *id)
	353	{
	354	s32 ret;
	355	struct pch_gpio *chip;
38eb18a6	356	int irq_base;
df9541a6	357	u32 msk;
04c17aa8 TM	358
	359	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	360	if (chip == NULL)
	361	return -ENOMEM;
	362
	363	chip->dev = &pdev->dev;
	364	ret = pci_enable_device(pdev);
	365	if (ret) {
	366	dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
	367	goto err_pci_enable;
	368	}
	369
	370	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	371	if (ret) {
	372	dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
	373	goto err_request_regions;
	374	}
	375
	376	chip->base = pci_iomap(pdev, 1, 0);
c4addcb5	377	if (!chip->base) {
04c17aa8 TM	378	dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
	379	ret = -ENOMEM;
	380	goto err_iomap;
	381	}
	382
d4260e6d TM	383	if (pdev->device == 0x8803)
	384	chip->ioh = INTEL_EG20T_PCH;
	385	else if (pdev->device == 0x8014)
	386	chip->ioh = OKISEMI_ML7223m_IOH;
	387	else if (pdev->device == 0x8043)
	388	chip->ioh = OKISEMI_ML7223n_IOH;
	389
04c17aa8 TM	390	chip->reg = chip->base;
04c17aa8 TM	391	pci_set_drvdata(pdev, chip);
d166370a	392	spin_lock_init(&chip->spinlock);
04c17aa8 TM	393	pch_gpio_setup(chip);
	394	ret = gpiochip_add(&chip->gpio);
	395	if (ret) {
	396	dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
	397	goto err_gpiochip_add;
	398	}
	399
2824bc9c	400	irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
38eb18a6 TM	401	if (irq_base < 0) {
	402	dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
	403	chip->irq_base = -1;
	404	goto end;
	405	}
	406	chip->irq_base = irq_base;
	407
df9541a6 TG	408	/* Mask all interrupts, but enable them */
	409	msk = (1 << gpio_pins[chip->ioh]) - 1;
	410	iowrite32(msk, &chip->reg->imask);
	411	iowrite32(msk, &chip->reg->ien);
	412
38eb18a6	413	ret = request_irq(pdev->irq, pch_gpio_handler,
df9541a6	414	IRQF_SHARED, KBUILD_MODNAME, chip);
38eb18a6 TM	415	if (ret != 0) {
	416	dev_err(&pdev->dev,
	417	"%s request_irq failed\n", __func__);
	418	goto err_request_irq;
	419	}
	420
	421	pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
	422
38eb18a6	423	end:
04c17aa8 TM	424	return 0;
04c17aa8 TM	425
38eb18a6 TM	426	err_request_irq:
	427	irq_free_descs(irq_base, gpio_pins[chip->ioh]);
	428
cfb10898	429	if (gpiochip_remove(&chip->gpio))
38eb18a6 TM	430	dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
38eb18a6 TM	431
04c17aa8 TM	432	err_gpiochip_add:
	433	pci_iounmap(pdev, chip->base);
	434
	435	err_iomap:
	436	pci_release_regions(pdev);
	437
	438	err_request_regions:
	439	pci_disable_device(pdev);
	440
	441	err_pci_enable:
	442	kfree(chip);
	443	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	444	return ret;
	445	}
	446
206210ce	447	static void pch_gpio_remove(struct pci_dev *pdev)
04c17aa8 TM	448	{
	449	int err;
	450	struct pch_gpio *chip = pci_get_drvdata(pdev);
	451
38eb18a6 TM	452	if (chip->irq_base != -1) {
	453	free_irq(pdev->irq, chip);
	454
	455	irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
	456	}
	457
04c17aa8 TM	458	err = gpiochip_remove(&chip->gpio);
	459	if (err)
	460	dev_err(&pdev->dev, "Failed gpiochip_remove\n");
	461
	462	pci_iounmap(pdev, chip->base);
	463	pci_release_regions(pdev);
	464	pci_disable_device(pdev);
	465	kfree(chip);
	466	}
	467
	468	#ifdef CONFIG_PM
	469	static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
	470	{
	471	s32 ret;
	472	struct pch_gpio *chip = pci_get_drvdata(pdev);
d568a681	473	unsigned long flags;
04c17aa8	474
d568a681	475	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8	476	pch_gpio_save_reg_conf(chip);
d568a681	477	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	478
	479	ret = pci_save_state(pdev);
	480	if (ret) {
	481	dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
	482	return ret;
	483	}
	484	pci_disable_device(pdev);
	485	pci_set_power_state(pdev, PCI_D0);
	486	ret = pci_enable_wake(pdev, PCI_D0, 1);
	487	if (ret)
	488	dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
	489
	490	return 0;
	491	}
	492
	493	static int pch_gpio_resume(struct pci_dev *pdev)
	494	{
	495	s32 ret;
	496	struct pch_gpio *chip = pci_get_drvdata(pdev);
d568a681	497	unsigned long flags;
04c17aa8 TM	498
	499	ret = pci_enable_wake(pdev, PCI_D0, 0);
	500
	501	pci_set_power_state(pdev, PCI_D0);
	502	ret = pci_enable_device(pdev);
	503	if (ret) {
	504	dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
	505	return ret;
	506	}
	507	pci_restore_state(pdev);
	508
d568a681	509	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	510	iowrite32(0x01, &chip->reg->reset);
	511	iowrite32(0x00, &chip->reg->reset);
	512	pch_gpio_restore_reg_conf(chip);
d568a681	513	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	514
	515	return 0;
	516	}
	517	#else
	518	#define pch_gpio_suspend NULL
	519	#define pch_gpio_resume NULL
	520	#endif
	521
bc786cce	522	#define PCI_VENDOR_ID_ROHM 0x10DB
14f4a883	523	static const struct pci_device_id pch_gpio_pcidev_id[] = {
04c17aa8	524	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
bc786cce	525	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
c3520a1a	526	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
868fea05	527	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
04c17aa8 TM	528	{ 0, }
04c17aa8 TM	529	};
19234cdd	530	MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
04c17aa8 TM	531
	532	static struct pci_driver pch_gpio_driver = {
	533	.name = "pch_gpio",
	534	.id_table = pch_gpio_pcidev_id,
	535	.probe = pch_gpio_probe,
8283c4ff	536	.remove = pch_gpio_remove,
04c17aa8 TM	537	.suspend = pch_gpio_suspend,
	538	.resume = pch_gpio_resume
	539	};
	540
93baa65f	541	module_pci_driver(pch_gpio_driver);
04c17aa8 TM	542
	543	MODULE_DESCRIPTION("PCH GPIO PCI Driver");
	544	MODULE_LICENSE("GPL");