[deliverable/linux.git] / drivers / gpio / gpio-pch.c

/*
 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>

#define PCH_EDGE_FALLING	0
#define PCH_EDGE_RISING		BIT(0)
#define PCH_LEVEL_L		BIT(1)
#define PCH_LEVEL_H		(BIT(0) | BIT(1))
#define PCH_EDGE_BOTH		BIT(2)
#define PCH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))

#define PCH_IRQ_BASE		24

struct pch_regs {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im0;
	u32	im1;
	u32	reserved[3];
	u32	gpio_use_sel;
	u32	reset;
};

enum pch_type_t {
	INTEL_EG20T_PCH,
	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
	OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
};

/* Specifies number of GPIO PINS */
static int gpio_pins[] = {
	[INTEL_EG20T_PCH] = 12,
	[OKISEMI_ML7223m_IOH] = 8,
	[OKISEMI_ML7223n_IOH] = 8,
};

/**
 * struct pch_gpio_reg_data - The register store data.
 * @ien_reg:	To store contents of IEN register.
 * @imask_reg:	To store contents of IMASK register.
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of IM0 register.
 * @im1_reg:	To store contents of IM1 register.
 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
 *		       (Only ML7223 Bus-n)
 */
struct pch_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 gpio_use_sel_reg;
};

/**
 * struct pch_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped PCH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @pch_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @lock:			Used for register access protection
 * @irq_base:		Save base of IRQ number for interrupt
 * @ioh:		IOH ID
 * @spinlock:		Used for register access protection
 */
struct pch_gpio {
	void __iomem *base;
	struct pch_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct pch_gpio_reg_data pch_gpio_reg;
	int irq_base;
	enum pch_type_t ioh;
	spinlock_t spinlock;
};

static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	u32 reg_val;
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);

	iowrite32(reg_val, &chip->reg->po);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);

	return ioread32(&chip->reg->pi) & (1 << nr);
}

static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				     int val)
{
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);
	u32 pm;
	u32 reg_val;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);

	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);
	iowrite32(reg_val, &chip->reg->po);

	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	pm |= (1 << nr);
	iowrite32(pm, &chip->reg->pm);

	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct pch_gpio *chip =	container_of(gpio, struct pch_gpio, gpio);
	u32 pm;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	pm &= ~(1 << nr);
	iowrite32(pm, &chip->reg->pm);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

/*
 * Save register configuration and disable interrupts.
 */
static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
{
	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		chip->pch_gpio_reg.gpio_use_sel_reg =\
					    ioread32(&chip->reg->gpio_use_sel);
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
{
	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
	/* to store contents of PO register */
	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	/* to store contents of PM register */
	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
			  &chip->reg->gpio_use_sel);
}

static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	return chip->irq_base + offset;
}

static void pch_gpio_setup(struct pch_gpio *chip)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->dev = chip->dev;
	gpio->owner = THIS_MODULE;
	gpio->direction_input = pch_gpio_direction_input;
	gpio->get = pch_gpio_get;
	gpio->direction_output = pch_gpio_direction_output;
	gpio->set = pch_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = -1;
	gpio->ngpio = gpio_pins[chip->ioh];
	gpio->can_sleep = false;
	gpio->to_irq = pch_gpio_to_irq;
}

static int pch_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;
	u32 im, im_pos, val;
	u32 __iomem *im_reg;
	unsigned long flags;
	int ch, irq = d->irq;

	ch = irq - chip->irq_base;
	if (irq <= chip->irq_base + 7) {
		im_reg = &chip->reg->im0;
		im_pos = ch;
	} else {
		im_reg = &chip->reg->im1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
		__func__, irq, type, ch, im_pos);

	spin_lock_irqsave(&chip->spinlock, flags);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = PCH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = PCH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = PCH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = PCH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = PCH_LEVEL_L;
		break;
	default:
		goto unlock;
	}

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* And the handler */
	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

unlock:
	spin_unlock_irqrestore(&chip->spinlock, flags);
	return 0;
}

static void pch_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
}

static void pch_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
}

static void pch_irq_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
}

static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
{
	struct pch_gpio *chip = dev_id;
	u32 reg_val = ioread32(&chip->reg->istatus);
	int i, ret = IRQ_NONE;

	for (i = 0; i < gpio_pins[chip->ioh]; i++) {
		if (reg_val & BIT(i)) {
			dev_dbg(chip->dev, "%s:[%d]:irq=%d  status=0x%x\n",
				__func__, i, irq, reg_val);
			generic_handle_irq(chip->irq_base + i);
			ret = IRQ_HANDLED;
		}
	}
	return ret;
}

static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
				unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
				    handle_simple_irq);
	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_ack = pch_irq_ack;
	ct->chip.irq_mask = pch_irq_mask;
	ct->chip.irq_unmask = pch_irq_unmask;
	ct->chip.irq_set_type = pch_irq_type;

	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int pch_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	s32 ret;
	struct pch_gpio *chip;
	int irq_base;
	u32 msk;

	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	chip->dev = &pdev->dev;
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
		goto err_pci_enable;
	}

	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
		goto err_request_regions;
	}

	chip->base = pci_iomap(pdev, 1, 0);
	if (!chip->base) {
		dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
		ret = -ENOMEM;
		goto err_iomap;
	}

	if (pdev->device == 0x8803)
		chip->ioh = INTEL_EG20T_PCH;
	else if (pdev->device == 0x8014)
		chip->ioh = OKISEMI_ML7223m_IOH;
	else if (pdev->device == 0x8043)
		chip->ioh = OKISEMI_ML7223n_IOH;

	chip->reg = chip->base;
	pci_set_drvdata(pdev, chip);
	spin_lock_init(&chip->spinlock);
	pch_gpio_setup(chip);
	ret = gpiochip_add(&chip->gpio);
	if (ret) {
		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
		goto err_gpiochip_add;
	}

	irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
	if (irq_base < 0) {
		dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
		chip->irq_base = -1;
		goto end;
	}
	chip->irq_base = irq_base;

	/* Mask all interrupts, but enable them */
	msk = (1 << gpio_pins[chip->ioh]) - 1;
	iowrite32(msk, &chip->reg->imask);
	iowrite32(msk, &chip->reg->ien);

	ret = request_irq(pdev->irq, pch_gpio_handler,
			  IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev,
			"%s request_irq failed\n", __func__);
		goto err_request_irq;
	}

	pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);

end:
	return 0;

err_request_irq:
	irq_free_descs(irq_base, gpio_pins[chip->ioh]);
	gpiochip_remove(&chip->gpio);

err_gpiochip_add:
	pci_iounmap(pdev, chip->base);

err_iomap:
	pci_release_regions(pdev);

err_request_regions:
	pci_disable_device(pdev);

err_pci_enable:
	kfree(chip);
	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	return ret;
}

static void pch_gpio_remove(struct pci_dev *pdev)
{
	struct pch_gpio *chip = pci_get_drvdata(pdev);

	if (chip->irq_base != -1) {
		free_irq(pdev->irq, chip);

		irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
	}

	gpiochip_remove(&chip->gpio);
	pci_iounmap(pdev, chip->base);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	kfree(chip);
}

#ifdef CONFIG_PM
static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
{
	s32 ret;
	struct pch_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pch_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	ret = pci_save_state(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
		return ret;
	}
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_wake(pdev, PCI_D0, 1);
	if (ret)
		dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);

	return 0;
}

static int pch_gpio_resume(struct pci_dev *pdev)
{
	s32 ret;
	struct pch_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	ret = pci_enable_wake(pdev, PCI_D0, 0);

	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
		return ret;
	}
	pci_restore_state(pdev);

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->reset);
	iowrite32(0x00, &chip->reg->reset);
	pch_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}
#else
#define pch_gpio_suspend NULL
#define pch_gpio_resume NULL
#endif

#define PCI_VENDOR_ID_ROHM             0x10DB
static const struct pci_device_id pch_gpio_pcidev_id[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

static struct pci_driver pch_gpio_driver = {
	.name = "pch_gpio",
	.id_table = pch_gpio_pcidev_id,
	.probe = pch_gpio_probe,
	.remove = pch_gpio_remove,
	.suspend = pch_gpio_suspend,
	.resume = pch_gpio_resume
};

module_pci_driver(pch_gpio_driver);

MODULE_DESCRIPTION("PCH GPIO PCI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
04c17aa8	1	/*
f4574beb	2	* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
04c17aa8 TM	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2 of the License.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
	16	*/
bb207ef1	17	#include <linux/module.h>
04c17aa8 TM	18	#include <linux/kernel.h>
	19	#include <linux/pci.h>
	20	#include <linux/gpio.h>
38eb18a6 TM	21	#include <linux/interrupt.h>
38eb18a6 TM	22	#include <linux/irq.h>
349b6c53	23	#include <linux/slab.h>
38eb18a6 TM	24
	25	#define PCH_EDGE_FALLING 0
	26	#define PCH_EDGE_RISING BIT(0)
	27	#define PCH_LEVEL_L BIT(1)
	28	#define PCH_LEVEL_H (BIT(0) \| BIT(1))
	29	#define PCH_EDGE_BOTH BIT(2)
	30	#define PCH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
	31
	32	#define PCH_IRQ_BASE 24
04c17aa8	33
04c17aa8 TM	34	struct pch_regs {
	35	u32 ien;
	36	u32 istatus;
	37	u32 idisp;
	38	u32 iclr;
	39	u32 imask;
	40	u32 imaskclr;
	41	u32 po;
	42	u32 pi;
	43	u32 pm;
	44	u32 im0;
	45	u32 im1;
e98bed7f TM	46	u32 reserved[3];
e98bed7f TM	47	u32 gpio_use_sel;
04c17aa8 TM	48	u32 reset;
	49	};
	50
d4260e6d TM	51	enum pch_type_t {
d4260e6d TM	52	INTEL_EG20T_PCH,
f4574beb TM	53	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
f4574beb TM	54	OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
d4260e6d TM	55	};
	56
	57	/* Specifies number of GPIO PINS */
	58	static int gpio_pins[] = {
	59	[INTEL_EG20T_PCH] = 12,
	60	[OKISEMI_ML7223m_IOH] = 8,
	61	[OKISEMI_ML7223n_IOH] = 8,
	62	};
	63
04c17aa8 TM	64	/**
04c17aa8 TM	65	* struct pch_gpio_reg_data - The register store data.
38eb18a6 TM	66	* @ien_reg: To store contents of IEN register.
38eb18a6 TM	67	* @imask_reg: To store contents of IMASK register.
04c17aa8 TM	68	* @po_reg: To store contents of PO register.
04c17aa8 TM	69	* @pm_reg: To store contents of PM register.
e98bed7f TM	70	* @im0_reg: To store contents of IM0 register.
	71	* @im1_reg: To store contents of IM1 register.
	72	* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
	73	* (Only ML7223 Bus-n)
04c17aa8 TM	74	*/
04c17aa8 TM	75	struct pch_gpio_reg_data {
38eb18a6 TM	76	u32 ien_reg;
38eb18a6 TM	77	u32 imask_reg;
04c17aa8 TM	78	u32 po_reg;
04c17aa8 TM	79	u32 pm_reg;
e98bed7f TM	80	u32 im0_reg;
	81	u32 im1_reg;
	82	u32 gpio_use_sel_reg;
04c17aa8 TM	83	};
	84
	85	/**
	86	* struct pch_gpio - GPIO private data structure.
	87	* @base: PCI base address of Memory mapped I/O register.
	88	* @reg: Memory mapped PCH GPIO register list.
	89	* @dev: Pointer to device structure.
	90	* @gpio: Data for GPIO infrastructure.
	91	* @pch_gpio_reg: Memory mapped Register data is saved here
	92	* when suspend.
38eb18a6 TM	93	* @lock: Used for register access protection
38eb18a6 TM	94	* @irq_base: Save base of IRQ number for interrupt
d4260e6d	95	* @ioh: IOH ID
7cb6580c	96	* @spinlock: Used for register access protection
04c17aa8 TM	97	*/
	98	struct pch_gpio {
	99	void __iomem *base;
	100	struct pch_regs __iomem *reg;
	101	struct device *dev;
	102	struct gpio_chip gpio;
	103	struct pch_gpio_reg_data pch_gpio_reg;
38eb18a6	104	int irq_base;
d4260e6d	105	enum pch_type_t ioh;
d568a681	106	spinlock_t spinlock;
04c17aa8 TM	107	};
	108
	109	static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	110	{
	111	u32 reg_val;
	112	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
7cb6580c	113	unsigned long flags;
04c17aa8	114
7cb6580c	115	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	116	reg_val = ioread32(&chip->reg->po);
	117	if (val)
	118	reg_val \|= (1 << nr);
	119	else
	120	reg_val &= ~(1 << nr);
	121
	122	iowrite32(reg_val, &chip->reg->po);
7cb6580c	123	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	124	}
	125
	126	static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
	127	{
	128	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	129
	130	return ioread32(&chip->reg->pi) & (1 << nr);
	131	}
	132
	133	static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	134	int val)
	135	{
	136	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	137	u32 pm;
	138	u32 reg_val;
7cb6580c	139	unsigned long flags;
04c17aa8	140
7cb6580c	141	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	142
	143	reg_val = ioread32(&chip->reg->po);
	144	if (val)
	145	reg_val \|= (1 << nr);
	146	else
	147	reg_val &= ~(1 << nr);
88aab934	148	iowrite32(reg_val, &chip->reg->po);
2ddf6cd6 DK	149
	150	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	151	pm \|= (1 << nr);
	152	iowrite32(pm, &chip->reg->pm);
	153
7cb6580c	154	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	155
	156	return 0;
	157	}
	158
	159	static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	160	{
	161	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	162	u32 pm;
7cb6580c	163	unsigned long flags;
04c17aa8	164
7cb6580c	165	spin_lock_irqsave(&chip->spinlock, flags);
d4260e6d	166	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
04c17aa8 TM	167	pm &= ~(1 << nr);
04c17aa8 TM	168	iowrite32(pm, &chip->reg->pm);
7cb6580c	169	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	170
	171	return 0;
	172	}
	173
	174	/*
	175	* Save register configuration and disable interrupts.
	176	*/
	177	static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
	178	{
38eb18a6 TM	179	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
38eb18a6 TM	180	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
04c17aa8 TM	181	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
04c17aa8 TM	182	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
e98bed7f TM	183	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	184	if (chip->ioh == INTEL_EG20T_PCH)
	185	chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	186	if (chip->ioh == OKISEMI_ML7223n_IOH)
	187	chip->pch_gpio_reg.gpio_use_sel_reg =\
	188	ioread32(&chip->reg->gpio_use_sel);
04c17aa8 TM	189	}
	190
	191	/*
	192	* This function restores the register configuration of the GPIO device.
	193	*/
	194	static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
	195	{
38eb18a6 TM	196	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
38eb18a6 TM	197	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
04c17aa8 TM	198	/* to store contents of PO register */
	199	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	200	/* to store contents of PM register */
	201	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
e98bed7f TM	202	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	203	if (chip->ioh == INTEL_EG20T_PCH)
	204	iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	205	if (chip->ioh == OKISEMI_ML7223n_IOH)
	206	iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
	207	&chip->reg->gpio_use_sel);
04c17aa8 TM	208	}
04c17aa8 TM	209
38eb18a6 TM	210	static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	211	{
	212	struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
	213	return chip->irq_base + offset;
	214	}
	215
04c17aa8 TM	216	static void pch_gpio_setup(struct pch_gpio *chip)
	217	{
	218	struct gpio_chip *gpio = &chip->gpio;
	219
	220	gpio->label = dev_name(chip->dev);
5c868fc6	221	gpio->dev = chip->dev;
04c17aa8 TM	222	gpio->owner = THIS_MODULE;
	223	gpio->direction_input = pch_gpio_direction_input;
	224	gpio->get = pch_gpio_get;
	225	gpio->direction_output = pch_gpio_direction_output;
	226	gpio->set = pch_gpio_set;
	227	gpio->dbg_show = NULL;
	228	gpio->base = -1;
d4260e6d	229	gpio->ngpio = gpio_pins[chip->ioh];
9fb1f39e	230	gpio->can_sleep = false;
38eb18a6 TM	231	gpio->to_irq = pch_gpio_to_irq;
	232	}
	233
	234	static int pch_irq_type(struct irq_data *d, unsigned int type)
	235	{
38eb18a6 TM	236	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38eb18a6 TM	237	struct pch_gpio *chip = gc->private;
df9541a6 TG	238	u32 im, im_pos, val;
	239	u32 __iomem *im_reg;
	240	unsigned long flags;
	241	int ch, irq = d->irq;
38eb18a6 TM	242
	243	ch = irq - chip->irq_base;
	244	if (irq <= chip->irq_base + 7) {
	245	im_reg = &chip->reg->im0;
	246	im_pos = ch;
	247	} else {
	248	im_reg = &chip->reg->im1;
	249	im_pos = ch - 8;
	250	}
	251	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
	252	__func__, irq, type, ch, im_pos);
	253
	254	spin_lock_irqsave(&chip->spinlock, flags);
	255
	256	switch (type) {
	257	case IRQ_TYPE_EDGE_RISING:
	258	val = PCH_EDGE_RISING;
	259	break;
	260	case IRQ_TYPE_EDGE_FALLING:
	261	val = PCH_EDGE_FALLING;
	262	break;
	263	case IRQ_TYPE_EDGE_BOTH:
	264	val = PCH_EDGE_BOTH;
	265	break;
	266	case IRQ_TYPE_LEVEL_HIGH:
	267	val = PCH_LEVEL_H;
	268	break;
	269	case IRQ_TYPE_LEVEL_LOW:
	270	val = PCH_LEVEL_L;
	271	break;
38eb18a6	272	default:
df9541a6	273	goto unlock;
38eb18a6 TM	274	}
	275
	276	/* Set interrupt mode */
	277	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	278	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	279
df9541a6 TG	280	/* And the handler */
	281	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
	282	__irq_set_handler_locked(d->irq, handle_level_irq);
	283	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	284	__irq_set_handler_locked(d->irq, handle_edge_irq);
38eb18a6	285
df9541a6	286	unlock:
38eb18a6	287	spin_unlock_irqrestore(&chip->spinlock, flags);
38eb18a6 TM	288	return 0;
	289	}
	290
	291	static void pch_irq_unmask(struct irq_data *d)
	292	{
	293	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	294	struct pch_gpio *chip = gc->private;
	295
	296	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
	297	}
	298
	299	static void pch_irq_mask(struct irq_data *d)
	300	{
	301	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	302	struct pch_gpio *chip = gc->private;
	303
	304	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
	305	}
	306
df9541a6 TG	307	static void pch_irq_ack(struct irq_data *d)
	308	{
	309	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	310	struct pch_gpio *chip = gc->private;
	311
	312	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
	313	}
	314
38eb18a6 TM	315	static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
	316	{
	317	struct pch_gpio *chip = dev_id;
	318	u32 reg_val = ioread32(&chip->reg->istatus);
df9541a6	319	int i, ret = IRQ_NONE;
38eb18a6 TM	320
	321	for (i = 0; i < gpio_pins[chip->ioh]; i++) {
	322	if (reg_val & BIT(i)) {
	323	dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
	324	__func__, i, irq, reg_val);
38eb18a6 TM	325	generic_handle_irq(chip->irq_base + i);
	326	ret = IRQ_HANDLED;
	327	}
	328	}
	329	return ret;
	330	}
	331
3836309d	332	static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
38eb18a6 TM	333	unsigned int irq_start, unsigned int num)
	334	{
	335	struct irq_chip_generic *gc;
	336	struct irq_chip_type *ct;
	337
	338	gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
	339	handle_simple_irq);
	340	gc->private = chip;
	341	ct = gc->chip_types;
	342
df9541a6	343	ct->chip.irq_ack = pch_irq_ack;
38eb18a6 TM	344	ct->chip.irq_mask = pch_irq_mask;
	345	ct->chip.irq_unmask = pch_irq_unmask;
	346	ct->chip.irq_set_type = pch_irq_type;
	347
	348	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	349	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
04c17aa8 TM	350	}
04c17aa8 TM	351
3836309d	352	static int pch_gpio_probe(struct pci_dev *pdev,
04c17aa8 TM	353	const struct pci_device_id *id)
	354	{
	355	s32 ret;
	356	struct pch_gpio *chip;
38eb18a6	357	int irq_base;
df9541a6	358	u32 msk;
04c17aa8 TM	359
	360	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	361	if (chip == NULL)
	362	return -ENOMEM;
	363
	364	chip->dev = &pdev->dev;
	365	ret = pci_enable_device(pdev);
	366	if (ret) {
	367	dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
	368	goto err_pci_enable;
	369	}
	370
	371	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	372	if (ret) {
	373	dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
	374	goto err_request_regions;
	375	}
	376
	377	chip->base = pci_iomap(pdev, 1, 0);
c4addcb5	378	if (!chip->base) {
04c17aa8 TM	379	dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
	380	ret = -ENOMEM;
	381	goto err_iomap;
	382	}
	383
d4260e6d TM	384	if (pdev->device == 0x8803)
	385	chip->ioh = INTEL_EG20T_PCH;
	386	else if (pdev->device == 0x8014)
	387	chip->ioh = OKISEMI_ML7223m_IOH;
	388	else if (pdev->device == 0x8043)
	389	chip->ioh = OKISEMI_ML7223n_IOH;
	390
04c17aa8 TM	391	chip->reg = chip->base;
04c17aa8 TM	392	pci_set_drvdata(pdev, chip);
d166370a	393	spin_lock_init(&chip->spinlock);
04c17aa8 TM	394	pch_gpio_setup(chip);
	395	ret = gpiochip_add(&chip->gpio);
	396	if (ret) {
	397	dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
	398	goto err_gpiochip_add;
	399	}
	400
2824bc9c	401	irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
38eb18a6 TM	402	if (irq_base < 0) {
	403	dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
	404	chip->irq_base = -1;
	405	goto end;
	406	}
	407	chip->irq_base = irq_base;
	408
df9541a6 TG	409	/* Mask all interrupts, but enable them */
	410	msk = (1 << gpio_pins[chip->ioh]) - 1;
	411	iowrite32(msk, &chip->reg->imask);
	412	iowrite32(msk, &chip->reg->ien);
	413
38eb18a6	414	ret = request_irq(pdev->irq, pch_gpio_handler,
df9541a6	415	IRQF_SHARED, KBUILD_MODNAME, chip);
38eb18a6 TM	416	if (ret != 0) {
	417	dev_err(&pdev->dev,
	418	"%s request_irq failed\n", __func__);
	419	goto err_request_irq;
	420	}
	421
	422	pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
	423
38eb18a6	424	end:
04c17aa8 TM	425	return 0;
04c17aa8 TM	426
38eb18a6 TM	427	err_request_irq:
38eb18a6 TM	428	irq_free_descs(irq_base, gpio_pins[chip->ioh]);
9f5132ae	429	gpiochip_remove(&chip->gpio);
38eb18a6	430
04c17aa8 TM	431	err_gpiochip_add:
	432	pci_iounmap(pdev, chip->base);
	433
	434	err_iomap:
	435	pci_release_regions(pdev);
	436
	437	err_request_regions:
	438	pci_disable_device(pdev);
	439
	440	err_pci_enable:
	441	kfree(chip);
	442	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	443	return ret;
	444	}
	445
206210ce	446	static void pch_gpio_remove(struct pci_dev *pdev)
04c17aa8	447	{
04c17aa8 TM	448	struct pch_gpio *chip = pci_get_drvdata(pdev);
04c17aa8 TM	449
38eb18a6 TM	450	if (chip->irq_base != -1) {
	451	free_irq(pdev->irq, chip);
	452
	453	irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
	454	}
	455
9f5132ae	456	gpiochip_remove(&chip->gpio);
04c17aa8 TM	457	pci_iounmap(pdev, chip->base);
	458	pci_release_regions(pdev);
	459	pci_disable_device(pdev);
	460	kfree(chip);
	461	}
	462
	463	#ifdef CONFIG_PM
	464	static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
	465	{
	466	s32 ret;
	467	struct pch_gpio *chip = pci_get_drvdata(pdev);
d568a681	468	unsigned long flags;
04c17aa8	469
d568a681	470	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8	471	pch_gpio_save_reg_conf(chip);
d568a681	472	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	473
	474	ret = pci_save_state(pdev);
	475	if (ret) {
	476	dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
	477	return ret;
	478	}
	479	pci_disable_device(pdev);
	480	pci_set_power_state(pdev, PCI_D0);
	481	ret = pci_enable_wake(pdev, PCI_D0, 1);
	482	if (ret)
	483	dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
	484
	485	return 0;
	486	}
	487
	488	static int pch_gpio_resume(struct pci_dev *pdev)
	489	{
	490	s32 ret;
	491	struct pch_gpio *chip = pci_get_drvdata(pdev);
d568a681	492	unsigned long flags;
04c17aa8 TM	493
	494	ret = pci_enable_wake(pdev, PCI_D0, 0);
	495
	496	pci_set_power_state(pdev, PCI_D0);
	497	ret = pci_enable_device(pdev);
	498	if (ret) {
	499	dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
	500	return ret;
	501	}
	502	pci_restore_state(pdev);
	503
d568a681	504	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	505	iowrite32(0x01, &chip->reg->reset);
	506	iowrite32(0x00, &chip->reg->reset);
	507	pch_gpio_restore_reg_conf(chip);
d568a681	508	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	509
	510	return 0;
	511	}
	512	#else
	513	#define pch_gpio_suspend NULL
	514	#define pch_gpio_resume NULL
	515	#endif
	516
bc786cce	517	#define PCI_VENDOR_ID_ROHM 0x10DB
14f4a883	518	static const struct pci_device_id pch_gpio_pcidev_id[] = {
04c17aa8	519	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
bc786cce	520	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
c3520a1a	521	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
868fea05	522	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
04c17aa8 TM	523	{ 0, }
04c17aa8 TM	524	};
19234cdd	525	MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
04c17aa8 TM	526
	527	static struct pci_driver pch_gpio_driver = {
	528	.name = "pch_gpio",
	529	.id_table = pch_gpio_pcidev_id,
	530	.probe = pch_gpio_probe,
8283c4ff	531	.remove = pch_gpio_remove,
04c17aa8 TM	532	.suspend = pch_gpio_suspend,
	533	.resume = pch_gpio_resume
	534	};
	535
93baa65f	536	module_pci_driver(pch_gpio_driver);
04c17aa8 TM	537
	538	MODULE_DESCRIPTION("PCH GPIO PCI Driver");
	539	MODULE_LICENSE("GPL");