[deliverable/linux.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061_gpio {
	spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	/*
	 * Map back to global GPIO space and request muxing, the direction
	 * parameter does not matter for this controller.
	 */
	int gpio = chip->base + offset;

	return pinctrl_request_gpio(gpio);
}

static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	int gpio = chip->base + offset;

	pinctrl_free_gpio(gpio);
}

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir &= ~(BIT(offset));
	writeb(gpiodir, chip->base + GPIODIR);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir |= BIT(offset);
	writeb(gpiodir, chip->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	return !!readb(chip->base + (BIT(offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;
	u8 bit = BIT(offset);

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);

	gpioiev = readb(chip->base + GPIOIEV);
	gpiois = readb(chip->base + GPIOIS);
	gpioibe = readb(chip->base + GPIOIBE);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		gpiois |= bit;
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
	} else
		gpiois &= ~bit;

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		/* Setting this makes GPIOEV be ignored */
		gpioibe |= bit;
	else {
		gpioibe &= ~bit;
		if (trigger & IRQ_TYPE_EDGE_RISING)
			gpioiev |= bit;
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
			gpioiev &= ~bit;
	}

	writeb(gpiois, chip->base + GPIOIS);
	writeb(gpioibe, chip->base + GPIOIBE);
	writeb(gpioiev, chip->base + GPIOIEV);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(chip->base + GPIOMIS);
	writeb(pending, chip->base + GPIOIC);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irqdomain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) & ~mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) | mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static struct irq_chip pl061_irqchip = {
	.name		= "pl061",
	.irq_mask	= pl061_irq_mask,
	.irq_unmask	= pl061_irq_unmask,
	.irq_set_type	= pl061_irq_type,
};

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061_platform_data *pdata = dev_get_platdata(dev);
	struct pl061_gpio *chip;
	int ret, irq, i, irq_base;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	if (pdata) {
		chip->gc.base = pdata->gpio_base;
		irq_base = pdata->irq_base;
		if (irq_base <= 0) {
			dev_err(&adev->dev, "invalid IRQ base in pdata\n");
			return -ENODEV;
		}
	} else {
		chip->gc.base = -1;
		irq_base = 0;
	}

	chip->base = devm_ioremap_resource(dev, &adev->res);
	if (IS_ERR(chip->base))
		return PTR_ERR(chip->base);

	spin_lock_init(&chip->lock);

	chip->gc.request = pl061_gpio_request;
	chip->gc.free = pl061_gpio_free;
	chip->gc.direction_input = pl061_direction_input;
	chip->gc.direction_output = pl061_direction_output;
	chip->gc.get = pl061_get_value;
	chip->gc.set = pl061_set_value;
	chip->gc.ngpio = PL061_GPIO_NR;
	chip->gc.label = dev_name(dev);
	chip->gc.dev = dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add(&chip->gc);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writeb(0, chip->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0) {
		dev_err(&adev->dev, "invalid IRQ\n");
		return -ENODEV;
	}

	ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
				   irq_base, handle_simple_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_info(&adev->dev, "could not add irqchip\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
				     irq, pl061_irq_handler);

	for (i = 0; i < PL061_GPIO_NR; i++) {
		if (pdata) {
			if (pdata->directions & (BIT(i)))
				pl061_direction_output(&chip->gc, i,
						pdata->values & (BIT(i)));
			else
				pl061_direction_input(&chip->gc, i);
		}
	}

	amba_set_drvdata(adev, chip);
	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
		 &adev->res.start);

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	chip->csave_regs.gpio_data = 0;
	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (BIT(offset)))
			chip->csave_regs.gpio_data |=
				pl061_get_value(&chip->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (BIT(offset)))
			pl061_direction_output(&chip->gc, offset,
					chip->csave_regs.gpio_data &
					(BIT(offset)));
		else
			pl061_direction_input(&chip->gc, offset);
	}

	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

MODULE_DEVICE_TABLE(amba, pl061_ids);

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
module_init(pl061_gpio_init);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("PL061 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859 BS	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	9	*
	10	* Data sheet: ARM DDI 0190B, September 2000
	11	*/
	12	#include <linux/spinlock.h>
	13	#include <linux/errno.h>
	14	#include <linux/module.h>
1e9c2859 BS	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
de88cbb7	18	#include <linux/irqchip/chained_irq.h>
1e9c2859	19	#include <linux/bitops.h>
1e9c2859 BS	20	#include <linux/gpio.h>
	21	#include <linux/device.h>
	22	#include <linux/amba/bus.h>
	23	#include <linux/amba/pl061.h>
5a0e3ad6	24	#include <linux/slab.h>
39b70ee0	25	#include <linux/pinctrl/consumer.h>
e198a8de	26	#include <linux/pm.h>
1e9c2859 BS	27
	28	#define GPIODIR 0x400
	29	#define GPIOIS 0x404
	30	#define GPIOIBE 0x408
	31	#define GPIOIEV 0x40C
	32	#define GPIOIE 0x410
	33	#define GPIORIS 0x414
	34	#define GPIOMIS 0x418
	35	#define GPIOIC 0x41C
	36
	37	#define PL061_GPIO_NR 8
	38
e198a8de DS	39	#ifdef CONFIG_PM
	40	struct pl061_context_save_regs {
	41	u8 gpio_data;
	42	u8 gpio_dir;
	43	u8 gpio_is;
	44	u8 gpio_ibe;
	45	u8 gpio_iev;
	46	u8 gpio_ie;
	47	};
	48	#endif
1e9c2859	49
1e9c2859	50	struct pl061_gpio {
835c192f	51	spinlock_t lock;
1e9c2859 BS	52
1e9c2859 BS	53	void __iomem *base;
1e9c2859	54	struct gpio_chip gc;
e198a8de DS	55
	56	#ifdef CONFIG_PM
	57	struct pl061_context_save_regs csave_regs;
	58	#endif
1e9c2859 BS	59	};
1e9c2859 BS	60
39b70ee0 HZ	61	static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
	62	{
	63	/*
	64	* Map back to global GPIO space and request muxing, the direction
	65	* parameter does not matter for this controller.
	66	*/
	67	int gpio = chip->base + offset;
	68
	69	return pinctrl_request_gpio(gpio);
	70	}
	71
22ce4464 AL	72	static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
	73	{
	74	int gpio = chip->base + offset;
	75
	76	pinctrl_free_gpio(gpio);
	77	}
	78
1e9c2859 BS	79	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
	80	{
	81	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	82	unsigned long flags;
	83	unsigned char gpiodir;
	84
	85	if (offset >= gc->ngpio)
	86	return -EINVAL;
	87
	88	spin_lock_irqsave(&chip->lock, flags);
	89	gpiodir = readb(chip->base + GPIODIR);
bea41504	90	gpiodir &= ~(BIT(offset));
1e9c2859 BS	91	writeb(gpiodir, chip->base + GPIODIR);
	92	spin_unlock_irqrestore(&chip->lock, flags);
	93
	94	return 0;
	95	}
	96
	97	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	98	int value)
	99	{
	100	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	101	unsigned long flags;
	102	unsigned char gpiodir;
	103
	104	if (offset >= gc->ngpio)
	105	return -EINVAL;
	106
	107	spin_lock_irqsave(&chip->lock, flags);
bea41504	108	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
1e9c2859	109	gpiodir = readb(chip->base + GPIODIR);
bea41504	110	gpiodir \|= BIT(offset);
1e9c2859	111	writeb(gpiodir, chip->base + GPIODIR);
64b997c5	112
	113	/*
	114	* gpio value is set again, because pl061 doesn't allow to set value of
	115	* a gpio pin before configuring it in OUT mode.
	116	*/
bea41504	117	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
1e9c2859 BS	118	spin_unlock_irqrestore(&chip->lock, flags);
	119
	120	return 0;
	121	}
	122
	123	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	124	{
	125	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	126
bea41504	127	return !!readb(chip->base + (BIT(offset + 2)));
1e9c2859 BS	128	}
	129
	130	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	131	{
	132	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	133
bea41504	134	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
1e9c2859 BS	135	}
1e9c2859 BS	136
b2221869	137	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	138	{
8d5b24bd LW	139	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
8d5b24bd LW	140	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
f1f70479	141	int offset = irqd_to_hwirq(d);
1e9c2859 BS	142	unsigned long flags;
1e9c2859 BS	143	u8 gpiois, gpioibe, gpioiev;
438a2c9a	144	u8 bit = BIT(offset);
1e9c2859	145
c1cc9b97	146	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	147	return -EINVAL;
1e9c2859 BS	148
f1f70479	149	spin_lock_irqsave(&chip->lock, flags);
1e9c2859 BS	150
1e9c2859 BS	151	gpioiev = readb(chip->base + GPIOIEV);
1e9c2859	152	gpiois = readb(chip->base + GPIOIS);
438a2c9a LW	153	gpioibe = readb(chip->base + GPIOIBE);
438a2c9a LW	154
1e9c2859	155	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
438a2c9a	156	gpiois \|= bit;
1e9c2859	157	if (trigger & IRQ_TYPE_LEVEL_HIGH)
438a2c9a	158	gpioiev \|= bit;
1e9c2859	159	else
438a2c9a	160	gpioiev &= ~bit;
1e9c2859	161	} else
438a2c9a	162	gpiois &= ~bit;
1e9c2859	163
1e9c2859	164	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
438a2c9a LW	165	/* Setting this makes GPIOEV be ignored */
438a2c9a LW	166	gpioibe \|= bit;
1e9c2859	167	else {
438a2c9a	168	gpioibe &= ~bit;
1e9c2859	169	if (trigger & IRQ_TYPE_EDGE_RISING)
438a2c9a	170	gpioiev \|= bit;
db7e1bc4	171	else if (trigger & IRQ_TYPE_EDGE_FALLING)
438a2c9a	172	gpioiev &= ~bit;
1e9c2859	173	}
1e9c2859	174
438a2c9a LW	175	writeb(gpiois, chip->base + GPIOIS);
438a2c9a LW	176	writeb(gpioibe, chip->base + GPIOIBE);
1e9c2859 BS	177	writeb(gpioiev, chip->base + GPIOIEV);
1e9c2859 BS	178
f1f70479	179	spin_unlock_irqrestore(&chip->lock, flags);
1e9c2859 BS	180
	181	return 0;
	182	}
	183
1e9c2859 BS	184	static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
1e9c2859 BS	185	{
2de0dbc5 RH	186	unsigned long pending;
2de0dbc5 RH	187	int offset;
8d5b24bd LW	188	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
8d5b24bd LW	189	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
dece904d	190	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	191
dece904d	192	chained_irq_enter(irqchip, desc);
1e9c2859	193
2de0dbc5 RH	194	pending = readb(chip->base + GPIOMIS);
	195	writeb(pending, chip->base + GPIOIC);
	196	if (pending) {
984b3f57	197	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
8d5b24bd LW	198	generic_handle_irq(irq_find_mapping(gc->irqdomain,
8d5b24bd LW	199	offset));
1e9c2859	200	}
2de0dbc5	201
dece904d	202	chained_irq_exit(irqchip, desc);
1e9c2859 BS	203	}
1e9c2859 BS	204
f1f70479	205	static void pl061_irq_mask(struct irq_data *d)
3ab52475	206	{
8d5b24bd LW	207	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
8d5b24bd LW	208	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
bea41504	209	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	210	u8 gpioie;
	211
	212	spin_lock(&chip->lock);
	213	gpioie = readb(chip->base + GPIOIE) & ~mask;
	214	writeb(gpioie, chip->base + GPIOIE);
	215	spin_unlock(&chip->lock);
	216	}
3ab52475	217
f1f70479 HZ	218	static void pl061_irq_unmask(struct irq_data *d)
f1f70479 HZ	219	{
8d5b24bd LW	220	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
8d5b24bd LW	221	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
bea41504	222	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	223	u8 gpioie;
	224
	225	spin_lock(&chip->lock);
	226	gpioie = readb(chip->base + GPIOIE) \| mask;
	227	writeb(gpioie, chip->base + GPIOIE);
	228	spin_unlock(&chip->lock);
	229	}
	230
	231	static struct irq_chip pl061_irqchip = {
9ae7e9e3	232	.name = "pl061",
f1f70479 HZ	233	.irq_mask = pl061_irq_mask,
	234	.irq_unmask = pl061_irq_unmask,
	235	.irq_set_type = pl061_irq_type,
f1f70479 HZ	236	};
f1f70479 HZ	237
8944df72	238	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	239	{
8944df72	240	struct device *dev = &adev->dev;
e56aee18	241	struct pl061_platform_data *pdata = dev_get_platdata(dev);
1e9c2859	242	struct pl061_gpio *chip;
f1f70479	243	int ret, irq, i, irq_base;
1e9c2859	244
8944df72	245	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1e9c2859 BS	246	if (chip == NULL)
	247	return -ENOMEM;
	248
76c05c8a RH	249	if (pdata) {
76c05c8a RH	250	chip->gc.base = pdata->gpio_base;
f1f70479	251	irq_base = pdata->irq_base;
7808755d LW	252	if (irq_base <= 0) {
7808755d LW	253	dev_err(&adev->dev, "invalid IRQ base in pdata\n");
f1f70479	254	return -ENODEV;
7808755d	255	}
f1f70479	256	} else {
76c05c8a	257	chip->gc.base = -1;
f1f70479 HZ	258	irq_base = 0;
f1f70479 HZ	259	}
76c05c8a	260
09bafc30 JH	261	chip->base = devm_ioremap_resource(dev, &adev->res);
	262	if (IS_ERR(chip->base))
	263	return PTR_ERR(chip->base);
1e9c2859 BS	264
1e9c2859 BS	265	spin_lock_init(&chip->lock);
1e9c2859	266
39b70ee0	267	chip->gc.request = pl061_gpio_request;
22ce4464	268	chip->gc.free = pl061_gpio_free;
1e9c2859 BS	269	chip->gc.direction_input = pl061_direction_input;
	270	chip->gc.direction_output = pl061_direction_output;
	271	chip->gc.get = pl061_get_value;
	272	chip->gc.set = pl061_set_value;
1e9c2859	273	chip->gc.ngpio = PL061_GPIO_NR;
8944df72 TK	274	chip->gc.label = dev_name(dev);
8944df72 TK	275	chip->gc.dev = dev;
1e9c2859 BS	276	chip->gc.owner = THIS_MODULE;
1e9c2859 BS	277
1e9c2859 BS	278	ret = gpiochip_add(&chip->gc);
1e9c2859 BS	279	if (ret)
8944df72	280	return ret;
1e9c2859 BS	281
	282	/*
	283	* irq_chip support
	284	*/
1e9c2859	285	writeb(0, chip->base + GPIOIE); /* disable irqs */
8944df72	286	irq = adev->irq[0];
7808755d LW	287	if (irq < 0) {
7808755d LW	288	dev_err(&adev->dev, "invalid IRQ\n");
8944df72	289	return -ENODEV;
7808755d	290	}
8944df72	291
8d5b24bd LW	292	ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
	293	irq_base, handle_simple_irq,
	294	IRQ_TYPE_NONE);
	295	if (ret) {
	296	dev_info(&adev->dev, "could not add irqchip\n");
	297	return ret;
7808755d	298	}
8d5b24bd LW	299	gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
8d5b24bd LW	300	irq, pl061_irq_handler);
2ba3154d	301
1e9c2859	302	for (i = 0; i < PL061_GPIO_NR; i++) {
76c05c8a	303	if (pdata) {
bea41504	304	if (pdata->directions & (BIT(i)))
76c05c8a	305	pl061_direction_output(&chip->gc, i,
bea41504	306	pdata->values & (BIT(i)));
76c05c8a RH	307	else
	308	pl061_direction_input(&chip->gc, i);
	309	}
1e9c2859 BS	310	}
1e9c2859 BS	311
8944df72	312	amba_set_drvdata(adev, chip);
76b3627e FE	313	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
76b3627e FE	314	&adev->res.start);
e198a8de	315
1e9c2859	316	return 0;
1e9c2859 BS	317	}
1e9c2859 BS	318
e198a8de DS	319	#ifdef CONFIG_PM
	320	static int pl061_suspend(struct device *dev)
	321	{
	322	struct pl061_gpio *chip = dev_get_drvdata(dev);
	323	int offset;
	324
	325	chip->csave_regs.gpio_data = 0;
	326	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	327	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	328	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	329	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	330	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
	331
	332	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
bea41504	333	if (chip->csave_regs.gpio_dir & (BIT(offset)))
e198a8de DS	334	chip->csave_regs.gpio_data \|=
	335	pl061_get_value(&chip->gc, offset) << offset;
	336	}
	337
	338	return 0;
	339	}
	340
	341	static int pl061_resume(struct device *dev)
	342	{
	343	struct pl061_gpio *chip = dev_get_drvdata(dev);
	344	int offset;
	345
	346	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
bea41504	347	if (chip->csave_regs.gpio_dir & (BIT(offset)))
e198a8de DS	348	pl061_direction_output(&chip->gc, offset,
e198a8de DS	349	chip->csave_regs.gpio_data &
bea41504	350	(BIT(offset)));
e198a8de DS	351	else
	352	pl061_direction_input(&chip->gc, offset);
	353	}
	354
	355	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	356	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	357	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	358	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
	359
	360	return 0;
	361	}
	362
6e33aced VK	363	static const struct dev_pm_ops pl061_dev_pm_ops = {
	364	.suspend = pl061_suspend,
	365	.resume = pl061_resume,
	366	.freeze = pl061_suspend,
	367	.restore = pl061_resume,
	368	};
e198a8de DS	369	#endif
e198a8de DS	370
2c39c9e1	371	static struct amba_id pl061_ids[] = {
1e9c2859 BS	372	{
	373	.id = 0x00041061,
	374	.mask = 0x000fffff,
	375	},
	376	{ 0, 0 },
	377	};
	378
955b678c DM	379	MODULE_DEVICE_TABLE(amba, pl061_ids);
955b678c DM	380
1e9c2859 BS	381	static struct amba_driver pl061_gpio_driver = {
	382	.drv = {
	383	.name = "pl061_gpio",
e198a8de DS	384	#ifdef CONFIG_PM
	385	.pm = &pl061_dev_pm_ops,
	386	#endif
1e9c2859 BS	387	},
	388	.id_table = pl061_ids,
	389	.probe = pl061_probe,
	390	};
	391
	392	static int __init pl061_gpio_init(void)
	393	{
	394	return amba_driver_register(&pl061_gpio_driver);
	395	}
5985d76c	396	module_init(pl061_gpio_init);
1e9c2859 BS	397
	398	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	399	MODULE_DESCRIPTION("PL061 GPIO driver");
	400	MODULE_LICENSE("GPL");